Display device

Abstract

A display device is provided. The display device includes a pixel circuit of a first pixel disposed in a first metal layer on a substrate, an active layer on the first metal layer, and a second metal layer on the active layer; a first electrode disposed in the third metal layer on the second metal layer and overlapping the pixel circuit of the first pixel; a pixel circuit of a second pixel disposed in the first metal layer, the active layer, and the second metal layer, and spaced apart from the pixel circuit of the first pixel in the first direction; a second electrode disposed in the third metal layer and overlapping a pixel circuit of the second pixel; an alignment line disposed in the third metal layer and extending in the first direction; and a plurality of light emitting elements aligned between the alignment line and the first electrode and between the alignment line and the second electrode on the third metal layer.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the progress of the information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device and an organic light emitting display device. Among the flat panel display devices, in the light emitting display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, an image can be displayed without a backlight unit that provides light to the display panel. The light emitting element can be an organic light emitting diode using an organic material as a fluorescent material and an inorganic light emitting diode using an inorganic material as a fluorescent material. Summary of the invention

[0003] Technical issues

[0004] A problem to be solved by the present disclosure is to provide a display device capable of improving image quality by reducing coupling capacitance between pixel circuits and preventing horizontal crosstalk.

[0005] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure for solving the problem includes: a pixel circuit of a first pixel, which is arranged in a first metal layer on a substrate, an active layer on the first metal layer, and a second metal layer on the active layer; a first electrode, which is arranged in a third metal layer on the second metal layer to overlap with the pixel circuit of the first pixel; a pixel circuit of a second pixel, which is arranged in the first metal layer, the active layer, and the second metal layer, and is spaced apart from the pixel circuit of the first pixel in a first direction; a second electrode, which is arranged in the third metal layer to overlap with the pixel circuit of the second pixel; an alignment line, which is arranged in the third metal layer to extend in the first direction; and a plurality of light-emitting elements, which are aligned on the third metal layer between the alignment line and the first electrode and between the alignment line and the second electrode.

[0008] The pixel circuit of the first pixel may include a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer. The first electrode may overlap the first capacitor electrode of the first pixel and may be electrically connected to the second capacitor electrode of the first pixel.

[0009] The display device may also include: a low potential line, arranged in the second metal layer to extend in a second direction intersecting the first direction; a first contact electrode, arranged in a fourth metal layer on the third metal layer to connect between the first electrode and a plurality of light-emitting elements; and a second contact electrode, arranged in the fourth metal layer to connect between the plurality of light-emitting elements and the low potential line.

[0010] The display device may also include: a pixel circuit of a third pixel, arranged in the first metal layer, the active layer and the second metal layer, and arranged between the pixel circuit of the first pixel and the pixel circuit of the second pixel; and a third electrode, arranged in the third metal layer to overlap with the pixel circuit of the third pixel.

[0011] The display device may further include a fourth electrode provided in the third metal layer to be spaced apart from the third electrode and connected to a pixel circuit of a third pixel, the alignment line being interposed between the fourth electrode and the third electrode.

[0012] The pixel circuit of the second pixel may include a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer. The second electrode may overlap the first capacitor electrode of the second pixel and may be electrically connected to the second capacitor electrode of the second pixel.

[0013] The display device may further include a bank disposed on the first electrode and the second electrode to include an opening portion disposed between the first electrode and the second electrode.

[0014] The bank may further include a light emitting portion extending in the first direction. A plurality of light emitting elements may be provided in the light emitting portion.

[0015] The display device may further include a gate line disposed in the second metal layer to extend in a second direction intersecting the first direction and supplying a gate signal to a pixel circuit of the first pixel and a pixel circuit of the second pixel. The gate line may be disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel.

[0016] A display device according to an embodiment of the present disclosure for solving the problem includes: a pixel circuit of a first pixel, which is arranged in a first metal layer on a substrate, an active layer on the first metal layer, and a second metal layer on the active layer; a first electrode, which is arranged in a third metal layer on the second metal layer to overlap with the pixel circuit of the first pixel; a pixel circuit of a second pixel, which is arranged in the first metal layer, the active layer, and the second metal layer, and is spaced apart from the pixel circuit of the first pixel in a first direction; a second electrode, which is arranged in the third metal layer to overlap with the pixel circuit of the second pixel; and a dam, which is arranged on the first electrode and the second electrode to include an opening portion arranged between the first electrode and the second electrode.

[0017] The display device may further include: an alignment line provided in the third metal layer to be spaced apart from the first electrode and the second electrode in a second direction crossing the first direction; and a plurality of light emitting elements aligned between the alignment line and the first electrode.

[0018] The bank may further include a light emitting portion overlapping the alignment line and a region between the first electrode. A plurality of light emitting elements may be provided in the light emitting portion.

[0019] The display device may also include: a low potential line, arranged in the second metal layer to extend in a second direction intersecting the first direction; a first contact electrode, arranged in a fourth metal layer on the third metal layer to connect between the first electrode and a plurality of light-emitting elements; and a second contact electrode, arranged in the fourth metal layer to connect between the plurality of light-emitting elements and the low potential line.

[0020] The display device may further include: an alignment line provided in the third metal layer to be spaced apart from the first electrode and the second electrode in a second direction crossing the first direction; and a plurality of light emitting elements aligned between the alignment line and the second electrode.

[0021] The display device may also include: a low potential line, arranged in the second metal layer to extend in a second direction intersecting the first direction; a first contact electrode, arranged in a fourth metal layer on the third metal layer to connect between the second electrode and a plurality of light-emitting elements; and a second contact electrode, arranged in the fourth metal layer to connect between the plurality of light-emitting elements and the low potential line.

[0022] The pixel circuit of the first pixel may include a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer. The first electrode may overlap the first capacitor electrode of the first pixel and may be electrically connected to the second capacitor electrode of the first pixel.

[0023] The pixel circuit of the second pixel may include a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer. The second electrode may overlap the first capacitor electrode of the second pixel and may be electrically connected to the second capacitor electrode of the second pixel.

[0024] A display device according to an embodiment of the present disclosure for solving the problem includes: a first voltage line, which is arranged in a first metal layer on a substrate; a first transistor, including a drain electrode arranged in an active layer on the first metal layer to be electrically connected to the first voltage line, a source electrode arranged in the active layer, and a gate electrode arranged in a second metal layer on the active layer; a first capacitor electrode, which is arranged in the active layer to be electrically connected to the gate electrode of the first transistor; a second capacitor electrode, which is arranged in the first metal layer to overlap with the first capacitor electrode; a first electrode, which is arranged in a third metal layer on the second metal layer to overlap with the first capacitor electrode and be electrically connected to the second capacitor electrode; an alignment line, which is arranged in the third metal layer to extend in a first direction; and a plurality of light-emitting elements, which are aligned between the alignment line and the first electrode on the third metal layer.

[0025] The display device may further include: a data line provided in the first metal layer to extend in the first direction; and a second transistor electrically connecting the data line and the first capacitor electrode.

[0026] The display device may further include: an initialization voltage line provided in the first metal layer to extend in the first direction; and a third transistor electrically connecting the initialization voltage line and the second capacitor electrode.

[0027] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0028] Beneficial Effects

[0029] According to the display device according to the embodiment, by forming a double capacitor between the gate electrode and the source electrode of the first transistor, the display device can ensure capacitance to reduce coupling capacitance between pixel circuits and prevent horizontal crosstalk to improve image quality.

[0030] The effects according to the embodiments are not limited to the contents exemplified above, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a plan view showing a display device according to an embodiment.

[0032] Figure 2 is a plan view showing a contact portion of a vertical gate line and a horizontal gate line in a display device according to one embodiment.

[0033] Figure 3 is a diagram showing pixels and lines of a display device according to one embodiment.

[0034] Figure 4 is a circuit diagram showing a pixel of a display device according to an embodiment.

[0035] Figure 5 and Figure 6 is a plan view showing a part of a display area in a display device according to an embodiment.

[0036] Figure 7 It is along Figure 5 and Figure 6 A cross-sectional view taken along line II'.

[0037] Figure 8 It is along Figure 5 and Figure 6 A cross-sectional view taken along line II-II'.

[0038] Fig. 9 is a plan view showing a first metal layer, an active layer, a second metal layer, a third metal layer, and a bank in a display device according to one embodiment.

[0039] Figures 10 to 13 1 is a diagram showing a process of manufacturing a light emitting element layer in the display device according to the embodiment.

[0040] Fig.14 It is along Fig. 9 and Fig.13 A cross-sectional view taken along line III-III'.

[0041] Fig.15 It is along Fig. 9 and Fig.13 A cross-sectional view taken along line IV-IV'.

[0042] Fig.16 is a plan view showing a third metal layer, a bank, a light emitting element, a fourth metal layer, and a separation portion in a display device according to another embodiment. DETAILED DESCRIPTION

[0043] The advantages and features of the present invention and the methods for achieving them will become clear with reference to the embodiments described in detail below using the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and fully inform the technical personnel in the field of the present invention of the scope of the present invention, and the present invention is limited only by the scope of the claims.

[0044] When an element or layer is referred to as being "on" another element or layer, this includes all cases where the layer or element is directly placed on the other element or layer or other elements or layers are between the element or layer and the other element or layer. Throughout the specification, the same reference numerals represent the same components. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for illustrating the embodiments are examples, and thus the present invention is not limited to the matters shown.

[0045] Although the terms "first", "second", etc. are used to describe various components, these components are certainly not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, it goes without saying that the first component mentioned below can also be a second component within the technical concept of the present invention.

[0046] Each of the features of the various embodiments of the present invention may be partially or entirely combined or combined with each other, and various technical connections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0047] Specific embodiments will be described below with reference to the accompanying drawings.

[0048] Figure 1 is a plan view showing a display device according to an embodiment.

[0049] The terms "above", "top" and "top surface" as used herein refer to the upward direction (i.e., the Z-axis direction) relative to the display device 10. The terms "below", "bottom" and "bottom surface" as used herein refer to the downward direction (i.e., the direction opposite to the Z-axis direction) relative to the display device 10. In addition, the terms "left", "right", "upper" and "lower" respectively refer to corresponding directions on the surface of the display device 10. For example, the term "left" refers to the direction opposite to the X-axis direction, the term "right" refers to the X-axis direction, the term "upper" refers to the Y-axis direction, and the term "lower" refers to the direction opposite to the Y-axis direction.

[0050] Reference Figure 1 The display device 10, which is a device for displaying moving images or still images, can be used as a display screen for various large-sized products (such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs)).

[0051] The display device 10 may include a display panel 100 , a flexible film 210 , a display driver 220 , a circuit board 230 , a timing controller 240 , and a power supply unit 250 .

[0052] The display panel 100 may have a rectangular shape in a plan view. For example, the display panel 100 may have a rectangular shape in a plan view, the rectangular shape having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction). The angle formed by the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be formed into another polygonal shape, a circular shape, or an elliptical shape. For example, the display panel 100 may be formed to be flat, but is not limited thereto. In another example, the display panel 100 may be curved with a predetermined curvature.

[0053] The display panel 100 may include a display area DA and a non-display area NDA.

[0054] The display area DA as an area for displaying an image may be defined as a central area of ​​the display panel 100. The display area DA may include a pixel SP, a gate line GL, a data line DL, an initialization voltage line VIL, a first voltage line VDL, a horizontal voltage line HVDL, a vertical voltage line VVSL, and a second voltage line VSL. A pixel SP may be formed for each pixel area crossed by a plurality of data lines DL and a plurality of gate lines GL. The pixel SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be connected to one gate line GL and one data line DL. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be defined as a minimum unit area for outputting light.

[0055] The first pixel SP1 may emit light of a first color such as red light, the second pixel SP2 may emit light of a second color such as green light, and the third pixel SP3 may emit light of a third color such as blue light. The pixel circuits of the first pixel SP1, the third pixel SP3, and the second pixel SP2 may be arranged in opposite directions of the second direction (Y-axis direction), but the arrangement direction of the pixel circuits is not limited thereto.

[0056] The gate lines GL may include a vertical gate line VGL, a horizontal gate line HGL, and an auxiliary gate line BGL.

[0057] A plurality of vertical gate lines VGL may be connected to the display driver 220 to extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The vertical gate lines VGL may be arranged in parallel with the data lines DL. A plurality of horizontal gate lines HGL may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). A plurality of horizontal gate lines HGL may intersect with a plurality of vertical gate lines VGL. For example, a horizontal gate line HGL may be connected to one of the plurality of vertical gate lines VGL through a contact portion MDC. The contact portion MDC may correspond to a portion of the horizontal gate line HGL inserted into the contact hole and contacting the vertical gate line VGL. An auxiliary gate line BGL may extend from the horizontal gate line HGL to supply gate signals to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0058] The plurality of data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The plurality of data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. Each of the first data line DL1, the second data line DL2, and the third data line DL3 may supply a data voltage to each of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0059] A plurality of initialization voltage lines VIL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The initialization voltage line VIL may supply an initialization voltage received from the display driver 220 to a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage line VIL may receive a sensing signal from a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 to supply the sensing signal to the display driver 220.

[0060] A plurality of first voltage lines VDL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The first voltage lines VDL may supply a driving voltage or a high potential voltage received from the power supply unit 250 to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0061] A plurality of horizontal voltage lines HVDL may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction). The horizontal voltage lines HVDL may be connected to the first voltage lines VDL. The horizontal voltage lines HVDL may supply a driving voltage or a high potential voltage to the first voltage lines VDL.

[0062] A plurality of vertical voltage lines VVSL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The vertical voltage line VVSL may be connected to the second voltage line VSL. The vertical voltage line VVSL may supply the second voltage line VSL with a low potential voltage received from the power supply unit 250.

[0063] A plurality of second voltage lines VSL may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). The second voltage lines VSL may supply a low potential voltage. Therefore, the second voltage lines VSL may be low potential lines.

[0064] The connection relationship among the pixels SP, the gate lines GL, the data lines DL, the initialization voltage line VIL, the first voltage line VDL, and the second voltage line VSL may be changed in design according to the number and arrangement of the pixels SP.

[0065] The non-display area NDA may be defined as a remaining area of ​​the display panel 100 except for the display area DA. For example, the non-display area NDA may include a fan-out line connecting the vertical gate line VGL, the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driver 220, and a pad (also referred to as a "pad" or "pad") portion connected to the flexible film 210.

[0066] The input terminal disposed on one side of the flexible film 210 may be attached to the circuit board 230 by a film attachment process, and the output terminal disposed at the other side of the flexible film 210 may be attached to the pad portion by a film attachment process. For example, the flexible film 210 may be bent, such as a tape carrier package or a chip on a film. The flexible film 210 may be bent toward the lower portion of the display panel 100 to reduce the border area of ​​the display device 10. The display driver 220 may be mounted on the flexible film 210. For example, the display driver 220 may be implemented as an integrated circuit (IC). The display driver 220 may receive digital video data and a data control signal from the timing controller 240, and according to the data control signal, convert the digital video data into an analog data voltage to supply it to the data line DL through a fan-out line. The display driver 220 may generate a gate signal according to a gate control signal supplied from the timing controller 240, and sequentially supply the gate signal to a plurality of vertical gate lines VGL in a set order. Therefore, the display driver 220 may be used as a data driver and a gate driver at the same time. Since the display device 10 includes the display driver 220 disposed at the lower side of the non-display area NDA, the sizes of the left, right, and upper sides of the non-display area NDA may be minimized.

[0067] The circuit board 230 may support the timing controller 240 and the power supply unit 250, and supply signals and power to the display driver 220. For example, the circuit board 230 may supply the display driver 220 with a signal supplied from the timing controller 240 and a power voltage supplied from the power supply unit 250 to display an image on each pixel. To this end, a signal transmission line and a power line may be provided on the circuit board 230.

[0068] The timing controller 240 may be mounted on the circuit board 230, and receive image data and a timing synchronization signal supplied from a display driving system or a graphic device through a user connector provided on the circuit board 230. The timing controller 240 may generate digital video data by arranging the image data to fit a pixel arrangement structure based on the timing synchronization signal, and may supply the generated digital video data to the display driver 220. The timing controller 240 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 240 may control the data voltage supply timing of the display driver 220 based on the data control signal, and may control the gate signal supply timing of the display driver 220 based on the gate control signal.

[0069] The power supply unit 250 may be disposed on the circuit board 230 to supply power voltage to the display driver 220 and the display panel 100. For example, the power supply unit 250 may generate a driving voltage or a high potential voltage and supply it to the first voltage line VDL, may generate a low potential voltage and supply it to the vertical voltage line VVSL, and may generate an initialization voltage and supply it to the initialization voltage line VIL.

[0070] Figure 2 is a plan view showing a contact portion of a vertical gate line and a horizontal gate line in a display device according to one embodiment.

[0071] Reference Figure 2 , the display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3.

[0072] Each of the horizontal gate lines HGL may cross the vertical gate line VGL. The horizontal gate line HGL may cross the vertical gate line VGL in the contact portion MDC and the non-contact portion NMC. For example, one horizontal gate line HGL may be connected to one of the vertical gate lines VGL through the contact portion MDC. One horizontal gate line HGL may be insulated from other vertical gate lines VGL in the non-contact portion NMC.

[0073] The contact portion MDC of the first display area DA1 may be disposed on an extension line extending from the upper left end of the first display area DA1 to the lower right end of the first display area DA1. The contact portion MDC of the second display area DA2 may be disposed on an extension line extending from the upper left end of the second display area DA2 to the lower right end of the second display area DA2. The contact portion MDC of the third display area DA3 may be disposed on an extension line extending from the upper left end of the third display area DA3 to the lower right end of the third display area DA3. Therefore, the contact portion MDC may be arranged in each of the first display area DA1, the second display area DA2, and the third display area DA3 along an oblique direction between the opposite direction of the first direction (X-axis direction) and the second direction (Y-axis direction).

[0074] The display device 10 may include a display driver 220 serving as a data driver and a gate driver. Therefore, since the data lines DL receive data voltages from the display driver 220 disposed at the lower side of the non-display area NDA, and the vertical gate lines VGL receive gate signals from the display driver 220 disposed at the lower side of the non-display area NDA, the display device 10 may minimize the sizes of the left side, the right side, and the upper side of the non-display area NDA.

[0075] Figure 3 is a diagram showing pixels and lines of a display device according to one embodiment.

[0076] Reference Figure 3 , the pixel SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuits of the first pixel SP1, the third pixel SP3, and the second pixel SP2 may be arranged in opposite directions of the second direction (Y-axis direction), but the arrangement direction of the pixel circuits is not limited thereto.

[0077] Each of the first pixel SP1 , the second pixel SP2 , and the third pixel SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a gate line GL, and a data line DL.

[0078] The first voltage line VDL may extend in the second direction (Y-axis direction). The first voltage line VDL may be disposed on the left side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The first voltage line VDL may supply a driving voltage or a high potential voltage to the transistor of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0079] The horizontal voltage line HVDL may extend in the first direction (X-axis direction). The horizontal voltage line HVDL may be disposed on the upper side of the pixel circuit of the first pixel SP1. The horizontal voltage line HVDL may be connected to the first voltage line VDL. The horizontal voltage line HVDL may supply a driving voltage or a high potential voltage to the first voltage line VDL.

[0080] The initialization voltage line VIL may extend in the second direction (Y-axis direction). The initialization voltage line VIL may be disposed on the right side of the auxiliary gate line BGL. The initialization voltage line VIL may be disposed between the auxiliary gate line BGL and the data line DL. The initialization voltage line VIL may supply an initialization voltage to a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage line VIL may receive a sensing signal from a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 to supply a sensing signal to the display driver 220.

[0081] The gate lines GL may include a vertical gate line VGL, a horizontal gate line HGL, and an auxiliary gate line BGL.

[0082] The vertical gate line VGL may extend in the second direction (Y-axis direction). The vertical gate line VGL may be connected between the display driver 220 and the horizontal gate line HGL. Each of the vertical gate lines VGL may cross the horizontal gate line HGL. The vertical gate line VGL may supply a gate signal received from the display driver 220 to the horizontal gate line HGL.

[0083] For example, the n-3rd vertical gate line VGLn-3 (n is a positive integer) and the n-2nd vertical gate line VGLn-2 may be disposed on the left side of the pixel SP disposed in the jth column COLj (j is a positive integer). The vertical gate line VGL may be disposed in parallel with the left side of the first voltage line VDL. The n-1st vertical gate line VGLn-1 and the nth vertical gate line VGLn may be disposed between the data line DL connected to the pixel SP disposed in the jth column COLj and the first voltage line VDL connected to the pixel SP disposed in the j+1st column COLj+1. The n-1st vertical gate line VGLn-1 may be connected to the n-1st horizontal gate line HGLn-1 through the contact portion MDC and may be insulated from the remaining horizontal gate lines HGL. The nth vertical gate line VGLn may be connected to the nth horizontal gate line HGLn through the contact portion MDC and may be insulated from the remaining horizontal gate lines HGL. The (n-1)th vertical gate line VGLn-1 and the (n)th vertical gate line VGLn may be disposed on the left side of the first voltage line VDL connected to the pixel SP disposed in the (j+1)th column COLj+1.

[0084] The horizontal gate line HGL may extend in the first direction (X-axis direction). The horizontal gate line HGL may be disposed between the pixel circuit of the first pixel SP1 and the pixel circuit of the third pixel SP3. The horizontal gate line HGL may be disposed below the pixel circuit of the first pixel SP1 and above the pixel circuit of the third pixel SP3. The horizontal gate line HGL may be connected between the vertical gate line VGL and the auxiliary gate line BGL. The horizontal gate line HGL may supply the auxiliary gate line BGL with a gate signal received from the vertical gate line VGL.

[0085] For example, the n-1th horizontal gate line HGLn-1 may be disposed at the lower side of the pixel circuit of the first pixel SP1 disposed in the k-th row ROWk (k is a positive integer). The n-1th horizontal gate line HGLn-1 may be connected to the n-1th vertical gate line VGLn-1 through the contact portion MDC, and may be insulated from the remaining vertical gate lines VGL. The n-th horizontal gate line HGLn may be disposed at the lower side of the pixel circuit of the first pixel SP1 disposed in the k+1th row ROWk+1. The n-th horizontal gate line HGLn may be connected to the n-th vertical gate line VGLn through the contact portion MDC, and may be insulated from the remaining vertical gate lines VGL.

[0086] The auxiliary gate line BGL may extend from the horizontal gate line HGL in the second direction (Y-axis direction) and in the opposite direction of the second direction (Y-axis direction). The auxiliary gate line BGL may be disposed on the right side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The auxiliary gate line BGL may supply the gate signal received from the horizontal gate line HGL to the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0087] The data lines DL may extend in the second direction (Y-axis direction). The data lines DL may supply data voltages to the pixels SP. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3.

[0088] The first data line DL1 may extend in the second direction (Y-axis direction). The first data line DL1 may be disposed on the right side of the second data line DL2. The first data line DL1 may supply a data voltage received from the display driver 220 to a pixel circuit of the first pixel SP1.

[0089] The second data line DL2 may extend in the second direction (Y-axis direction). The second data line DL2 may be disposed on the right side of the initialization voltage line VIL. The second data line DL2 may supply a data voltage received from the display driver 220 to a pixel circuit of the second pixel SP2.

[0090] The third data line DL3 may extend in the second direction (Y-axis direction). The third data line DL3 may be disposed on the right side of the first data line DL1. The third data line DL3 may supply a data voltage received from the display driver 220 to a pixel circuit of a third pixel SP3.

[0091] The vertical voltage line VVSL may extend in the second direction (Y-axis direction). The vertical voltage line VVSL may be disposed on the right side of the third data line DL3. The vertical voltage line VVSL may be connected between the power supply unit 250 and the second voltage line VSL. The vertical voltage line VVSL may supply the low potential voltage supplied from the power supply unit 250 to the second voltage line VSL.

[0092] The second voltage line VSL may extend in the first direction (X-axis direction). The second voltage line VSL may be disposed at the lower side of the pixel circuit of the second pixel SP2. The second voltage line VSL may supply the light emitting element layers of the first pixel SP1, the second pixel SP2, and the third pixel SP3 with a low potential voltage received from the vertical voltage line VVSL. Figures 9 to 15 The light emitting element layers of the first pixel SP1, the second pixel SP2, and the third pixel SP3 are described in detail.

[0093] Figure 4 is a circuit diagram showing a pixel of a display device according to an embodiment.

[0094] Reference Figure 4 , each of the pixels SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a gate line GL, and a second voltage line VSL.

[0095] Each of the first pixel SP1 , the second pixel SP2 , and the third pixel SP3 may include first, second, and third transistors ST1 , ST2 , and ST3 , a first capacitor C1 , and a plurality of light emitting elements ED.

[0096] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 may be connected to the first node N1, the drain electrode of the first transistor ST1 may be connected to the first voltage line VDL, and the source electrode of the first transistor ST1 may be connected to the second node N2. The first transistor ST1 may control a drain-source current (or a driving current) based on a data voltage applied to the gate electrode.

[0097] The light emitting element ED may include a first light emitting element ED1 and a second light emitting element ED2. The first light emitting element ED1 and the second light emitting element ED2 may be connected in series. The first light emitting element ED1 and the second light emitting element ED2 may receive a driving current to emit light. The amount of light emitted or the brightness of the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an inorganic light emitting element including an inorganic semiconductor, but is not limited thereto.

[0098] A first electrode of the first light emitting element ED1 may be connected to the second node N2, and a second electrode of the first light emitting element ED1 may be connected to the third node N3. The first electrode of the first light emitting element ED1 may be connected to the source electrode of the first transistor ST1, the drain electrode of the third transistor ST3, and the second capacitor electrode of the first capacitor C1 through the second node N2. The second electrode of the first light emitting element ED1 may be connected to the first electrode of the second light emitting element ED2 through the third node N3.

[0099] A first electrode of the second light emitting element ED2 may be connected to the third node N3, and a second electrode of the second light emitting element ED2 may be connected to the second voltage line VSL. The second electrode of the second light emitting element ED2 may receive a low potential voltage from the second voltage line VSL.

[0100] The second transistor ST2 may be turned on by a gate signal of the gate line GL to connect the data line DL to the first node N1 which is the gate electrode of the first transistor ST1. The second transistor ST2 may be turned on according to the gate signal to supply a data voltage to the first node N1. The gate electrode of the second transistor ST2 may be connected to the gate line GL, the drain electrode of the second transistor ST2 may be connected to the data line DL, and the source electrode of the second transistor ST2 may be connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the gate electrode of the first transistor ST1 and the first capacitor electrode of the first capacitor C1 through the first node N1.

[0101] The third transistor ST3 may be turned on by a gate signal of the gate line GL to connect the initialization voltage line VIL to the second node N2 as the source electrode of the first transistor ST1. The third transistor ST3 may be turned on according to the gate signal to supply the initialization voltage to the second node N2. The third transistor ST3 may be turned on according to the gate signal to supply the sensing signal to the initialization voltage line VIL. The gate electrode of the third transistor ST3 may be connected to the gate line GL, the drain electrode of the third transistor ST3 may be connected to the second node N2, and the source electrode of the third transistor ST3 may be connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode of the first transistor ST1, the second capacitor electrode of the first capacitor C1, and the first electrode of the first light emitting element ED1 through the second node N2.

[0102] Figure 5 and Figure 6 is a plan view showing a part of a display area in a display device according to an embodiment. Figure 5 and Figure 6 Description is made by dividing the same views by reference numerals. Figure 7 It is along Figure 5 and Figure 6 A cross-sectional view taken along line II' of Figure 8 It is along Figure 5 and Figure 6 A cross-sectional view taken along line II-II'.

[0103] Reference Figures 5 to 8 The display area DA may include a pixel SP, a first voltage line VDL, a horizontal voltage line HVDL, an initialization voltage line VIL, an n-1th vertical gate line VGLn-1, an nth vertical gate line VGLn, an nth horizontal gate line HGLn, an auxiliary gate line BGL, a data line DL, a vertical voltage line VVSL and a second voltage line VSL.

[0104] The pixel SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuit of the first pixel SP1, the pixel circuit of the third pixel SP3, and the pixel circuit of the second pixel SP2 may be arranged in opposite directions of the second direction (Y-axis direction). The pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be set in a pixel area.

[0105] The first voltage line VDL may be provided in the first metal layer MTL1 on the substrate SUB. The first voltage line VDL may be provided to the left side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The fifth connection electrode CE5 of the second metal layer MTL2 may electrically connect the first voltage line VDL and the drain electrode DE1 of the first transistor ST1 of the first pixel SP1 through the first contact hole CNT1. The eleventh connection electrode CE11 of the second metal layer MTL2 may electrically connect the first voltage line VDL and the drain electrode DE1 of the first transistor ST1 of the second pixel SP2 through the ninth contact hole CNT9. The sixteenth connection electrode CE16 of the second metal layer MTL2 may electrically connect the first voltage line VDL and the drain electrode DE1 of the first transistor ST1 of the third pixel SP3 through the sixteenth contact hole CNT16. Therefore, the first voltage line VDL may supply a driving voltage or a high potential voltage to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0106] The horizontal voltage line HVDL may be disposed in the second metal layer MTL2. The second metal layer MTL2 may be disposed on the gate insulating layer GI covering the active layer ACTL. The horizontal voltage line HVDL may be disposed on the upper side of the pixel circuit of the first pixel SP1. The horizontal voltage line HVDL may be connected to the first voltage line VDL through the twenty-fourth contact hole CNT24 to supply a driving voltage or a high potential voltage. The horizontal voltage line HVDL may supply a first alignment signal to the first alignment line. Here, the first alignment line may be disposed in the third metal layer on the second metal layer MTL2, and a plurality of twenty-sixth contact holes CNT26 may be formed to penetrate the via layer VIA and the passivation layer PV. Reference will be made to Figures 9 to 15 The first alignment line and the third metal layer are described in detail. A passivation layer PV may be disposed on the second metal layer MTL2 and the gate insulating layer GI, and a via layer VIA may be disposed on the passivation layer PV.

[0107] The initialization voltage line VIL may be disposed in the first metal layer MTL1. The initialization voltage line VIL may be disposed on the right side of the auxiliary gate line BGL. The third connection electrode CE3 of the second metal layer MTL2 may electrically connect the initialization voltage line VIL to the source electrode SE3 of the third transistor ST3 of the first pixel SP1 through the fifth contact hole CNT5. The ninth connection electrode CE9 of the second metal layer MTL2 may electrically connect the initialization voltage line VIL to the source electrode SE3 of the third transistor ST3 of the second pixel SP2 through the thirteenth contact hole CNT13. The ninth connection electrode CE9 may electrically connect the initialization voltage line VIL to the source electrode SE3 of the third transistor ST3 of the third pixel SP3 through the thirteenth contact hole CNT13. The source electrode SE3 of the third transistor ST3 of the second pixel SP2 and the source electrode SE3 of the third transistor ST3 of the third pixel SP3 may be integrally formed, but are not limited thereto. Therefore, the initialization voltage line VIL may supply an initialization voltage to the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3, and receive a sensing signal from the third transistor ST3.

[0108] A plurality of vertical gate lines VGL may be disposed in the first metal layer MTL1. An n-1th vertical gate line VGLn-1 and an nth vertical gate line VGLn may be disposed on the left side of the first voltage line VDL. The nth vertical gate line VGLn may be connected to an nth horizontal gate line HGLn of the second metal layer MTL2 through a contact portion MDC. The nth vertical gate line VGLn may supply a gate signal to the nth horizontal gate line HGLn.

[0109] The nth horizontal gate line HGLn may be disposed in the second metal layer MTL2. The nth horizontal gate line HGLn may be disposed between the pixel circuit of the first pixel SP1 and the pixel circuit of the third pixel SP3. The pixel circuit of the first pixel SP1 and the pixel circuit of the third pixel SP3 may be spaced apart by the width of the nth horizontal gate line HGLn. The nth horizontal gate line HGLn may be connected to the nth vertical gate line VGLn disposed in the first metal layer MTL1 through the contact portion MDC. The nth horizontal gate line HGLn may supply the gate signal received from the nth vertical gate line VGLn to the auxiliary gate line BGL.

[0110] The auxiliary gate line BGL may be disposed in the second metal layer MTL2. A first portion of the auxiliary gate line BGL may protrude from the nth horizontal gate line HGLn in the second direction (Y-axis direction), and a second portion of the auxiliary gate line BGL may protrude from the nth horizontal gate line HGLn in a direction opposite to the second direction (Y-axis direction). The auxiliary gate line BGL may be formed integrally with the nth horizontal gate line HGLn, but is not limited thereto. A first portion of the auxiliary gate line BGL may be disposed on the right side of the pixel circuit of the first pixel SP1, and a second portion of the auxiliary gate line BGL may be disposed on the right side of the pixel circuit of the second pixel SP2 and the third pixel SP3. The auxiliary gate line BGL may supply a gate signal received from the nth horizontal gate line HGLn to the second transistor ST2 and the third transistor ST3 of the first pixel SP1, the second pixel SP2, and the third pixel SP3, respectively.

[0111] The first data line DL1 may be disposed in the first metal layer MTL1. The first data line DL1 may be disposed on the right side of the second data line DL2. The second connection electrode CE2 of the second metal layer MTL2 may electrically connect the first data line DL1 to the drain electrode DE2 of the second transistor ST2 of the first pixel SP1 through the fourth contact hole CNT4. The first data line DL1 may supply a data voltage to the second transistor ST2 of the first pixel SP1.

[0112] The second data line DL2 may be disposed in the first metal layer MTL1. The second data line DL2 may be disposed on the right side of the initialization voltage line VIL. The eighth connection electrode CE8 of the second metal layer MTL2 may electrically connect the second data line DL2 to the drain electrode DE2 of the second transistor ST2 of the second pixel SP2 through the twelfth contact hole CNT12. The second data line DL2 may supply a data voltage to the second transistor ST2 of the second pixel SP2.

[0113] The third data line DL3 may be disposed in the first metal layer MTL1. The third data line DL3 may be disposed on the right side of the first data line DL1. The fourteenth connection electrode CE14 of the second metal layer MTL2 may electrically connect the third data line DL3 to the drain electrode DE2 of the second transistor ST2 of the third pixel SP3 through the nineteenth contact hole CNT19. The third data line DL3 may supply a data voltage to the second transistor ST2 of the third pixel SP3.

[0114] The vertical voltage line VVSL may be disposed in the first metal layer MTL1. The vertical voltage line VVSL may be disposed on the right side of the third data line DL3. The vertical voltage line VVSL may be connected to the second voltage line VSL of the second metal layer MTL2 through the twenty-fifth contact hole CNT25. The vertical voltage line VVSL may supply a low potential voltage to the second voltage line VSL.

[0115] The second voltage line VSL may be disposed in the second metal layer MTL2. The second voltage line VSL may be disposed at the lower side of the pixel circuit of the second pixel SP2. The second voltage line VSL may supply a low potential voltage received from the vertical voltage line VVSL to each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. For example, the second voltage line VSL may be connected to the contact electrode of the first pixel SP1 through the thirty-first contact hole CNT31. The second voltage line VSL may be connected to the contact electrode of the second pixel SP2 through the thirty-third contact hole CNT33. The second voltage line VSL may be connected to the contact electrode of the third pixel SP3 through the thirty-fifth contact hole CNT35. Here, the contact electrode may be disposed in the fourth metal layer on the third metal layer. Reference will be made to Figures 9 to 15 The fourth metal layer is described in detail.

[0116] The second voltage line VSL can supply a second alignment signal to the second alignment line of the third metal layer. For example, the second voltage line VSL can be connected to the second alignment line of the first pixel SP1 through the twenty-seventh contact hole CNT27. The second voltage line VSL can be connected to the second alignment line of the second pixel SP2 through the twenty-eighth contact hole CNT28. The second voltage line VSL can be connected to the second alignment line of the third pixel SP3 through the twenty-ninth contact hole CNT29. Here, the second alignment line can be set in the third metal layer, and the twenty-seventh contact hole CNT27, the twenty-eighth contact hole CNT28 and the twenty-ninth contact hole CNT29 can be formed to penetrate the via layer VIA and the passivation layer PV. Reference will be made to Figures 9 to 15 The second alignment line is described in detail.

[0117] The pixel circuit of the first pixel SP1 may include a first transistor ST1, a second transistor ST2, and a third transistor ST3 and a first capacitor C1. The first transistor ST1 of the first pixel SP1 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap with the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction). The active layer ACTL may be disposed on the buffer layer BF covering the first metal layer MTL1.

[0118] The gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The gate electrode GE1 of the first transistor ST1 may be integrally formed with the first connection electrode CE1. The first connection electrode CE1 may be connected to the first capacitor electrode CPE1 of the first capacitor C1 disposed in the active layer ACTL through the third contact hole CNT3. The first capacitor electrode CPE1 of the first capacitor C1 may be made conductive by heat treatment of the active layer ACTL. The first capacitor electrode CPE1 of the first capacitor C1 may be integrally formed with the source electrode SE2 of the second transistor ST2, but is not limited thereto.

[0119] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE1 and the source electrode SE1 may be formed as an N-type semiconductor, but the disclosure is not limited thereto. The fifth connection electrode CE5 may electrically connect the first voltage line VDL to the drain electrode DE1 of the first transistor ST1 of the first pixel SP1 through the first contact hole CNT1. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0120] The fourth connection electrode CE4 of the second metal layer MTL2 may electrically connect the source electrode SE1 of the first transistor ST1, the drain electrode DE3 of the third transistor ST3, and the second capacitor electrode CPE2 of the first metal layer MTL1 through the second contact hole CNT2. The first capacitor C1 may be formed between the first capacitor electrode CPE1 of the active layer ACTL and the second capacitor electrode CPE2 of the first metal layer MTL1.

[0121] The sixth connection electrode CE6 of the second metal layer MTL2 may be connected to the second capacitor electrode CPE2 through the sixth contact hole CNT6. The sixth connection electrode CE6 may be connected to the first electrode of the third metal layer through the seventh contact hole CNT7, and may be connected to the fifth electrode of the third metal layer through the eighth contact hole CNT8. Figures 9 to 15 The first electrode and the fifth electrode of the third metal layer are described in detail.

[0122] The second transistor ST2 of the first pixel SP1 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the gate electrode GE2 of the second transistor ST2 in the thickness direction (Z-axis direction).

[0123] The gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The gate electrode GE2 of the second transistor ST2 may be a portion of the auxiliary gate line BGL.

[0124] The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The second connection electrode CE2 may electrically connect the drain electrode DE2 of the second transistor ST2 to the first data line DL1 through the fourth contact hole CNT4. The drain electrode DE2 of the second transistor ST2 may receive the data voltage of the first pixel SP1 from the first data line DL1.

[0125] The source electrode SE2 of the second transistor ST2 may be integrally formed with the first capacitor electrode CPE1 of the first capacitor C1. The source electrode SE2 of the second transistor ST2 may be electrically connected to the gate electrode GE1 of the first transistor ST1 through the first capacitor electrode CPE1 and the first connection electrode CE1.

[0126] The third transistor ST3 of the first pixel SP1 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0127] The gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The gate electrode GE3 of the third transistor ST3 may be a portion of the auxiliary gate line BGL.

[0128] The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE3 of the third transistor ST3 may be electrically connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2 through the fourth connection electrode CE4.

[0129] The source electrode SE3 of the third transistor ST3 may be connected to the third connection electrode CE3 of the second metal layer MTL2 through the fifth contact hole CNT5. The third connection electrode CE3 may electrically connect the source electrode SE3 of the third transistor ST3 to the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0130] The pixel circuit of the second pixel SP2 may include a first transistor ST1, a second transistor ST2, and a third transistor ST3 and a first capacitor C1. The first transistor ST1 of the second pixel SP2 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap with the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction).

[0131] The gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The gate electrode GE1 of the first transistor ST1 may be integrally formed with the seventh connection electrode CE7. The seventh connection electrode CE7 may be connected to the first capacitor electrode CPE1 of the first capacitor C1 disposed in the active layer ACTL through the eleventh contact hole CNT11. The first capacitor electrode CPE1 of the first capacitor C1 may be made conductive by heat treatment of the active layer ACTL. The first capacitor electrode CPE1 of the first capacitor C1 may be integrally formed with the source electrode SE2 of the second transistor ST2, but is not limited thereto.

[0132] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE1 and the source electrode SE1 may be formed as an N-type semiconductor, but the disclosure is not limited thereto. The eleventh connection electrode CE11 may electrically connect the first voltage line VDL to the drain electrode DE1 of the first transistor ST1 of the second pixel SP2 through the ninth contact hole CNT9. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0133] The tenth connection electrode CE10 of the second metal layer MTL2 may electrically connect the source electrode SE1 of the first transistor ST1, the drain electrode DE3 of the third transistor ST3, and the second capacitor electrode CPE2 of the first metal layer MTL1 through the tenth contact hole CNT10. The first capacitor C1 may be formed between the first capacitor electrode CPE1 of the active layer ACTL and the second capacitor electrode CPE2 of the first metal layer MTL1.

[0134] The twelfth connection electrode CE12 of the second metal layer MTL2 may be connected to the second capacitor electrode CPE2 through the fourteenth contact hole CNT14. The twelfth connection electrode CE12 may be connected to the second electrode of the third metal layer through the fifteenth contact hole CNT15. Figures 9 to 15 The second electrode of the third metal layer is described in detail.

[0135] The second transistor ST2 of the second pixel SP2 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the gate electrode GE2 of the second transistor ST2 in the thickness direction (Z-axis direction).

[0136] The gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The gate electrode GE2 of the second transistor ST2 may be a portion of the auxiliary gate line BGL.

[0137] The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The eighth connection electrode CE8 may electrically connect the drain electrode DE2 of the second transistor ST2 to the second data line DL2 through the twelfth contact hole CNT12. The drain electrode DE2 of the second transistor ST2 may receive the data voltage of the second pixel SP2 from the second data line DL2.

[0138] The source electrode SE2 of the second transistor ST2 may be integrally formed with the first capacitor electrode CPE1 of the first capacitor C1. The source electrode SE2 of the second transistor ST2 may be electrically connected to the gate electrode GE1 of the first transistor ST1 through the first capacitor electrode CPE1 and the seventh connection electrode CE7.

[0139] The third transistor ST3 of the second pixel SP2 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0140] The gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The gate electrode GE3 of the third transistor ST3 may be a portion of the auxiliary gate line BGL.

[0141] The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE3 of the third transistor ST3 may be connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2.

[0142] The source electrode SE3 of the third transistor ST3 may be connected to the ninth connection electrode CE9 of the second metal layer MTL2 through the thirteenth contact hole CNT13. The ninth connection electrode CE9 may electrically connect the source electrode SE3 of the third transistor ST3 to the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0143] The pixel circuit of the third pixel SP3 may include a first transistor ST1, a second transistor ST2, and a third transistor ST3, and a first capacitor C1. The first transistor ST1 of the third pixel SP3 may include an active area ACT1, a gate electrode GE1, a drain electrode DE1, and a source electrode SE1. The active area ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap with the gate electrode GE1 of the first transistor ST1 in the thickness direction (Z-axis direction).

[0144] The gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The gate electrode GE1 of the first transistor ST1 may be integrally formed with the thirteenth connection electrode CE13. The thirteenth connection electrode CE13 may be connected to the first capacitor electrode CPE1 of the first capacitor C1 disposed in the active layer ACTL through the eighteenth contact hole CNT18. The first capacitor electrode CPE1 of the first capacitor C1 may be made conductive by heat treatment of the active layer ACTL. The first capacitor electrode CPE1 of the first capacitor C1 may be integrally formed with the source electrode SE2 of the second transistor ST2, but is not limited thereto.

[0145] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE1 and the source electrode SE1 may be made of an N-type semiconductor, but are not limited thereto. The sixteenth connection electrode CE16 may electrically connect the first voltage line VDL and the drain electrode DE1 of the first transistor ST1 of the third pixel SP3 through the sixteenth contact hole CNT16. The drain electrode DE1 of the first transistor ST1 may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0146] The fifteenth connection electrode CE15 of the second metal layer MTL2 may electrically connect the source electrode SE1 of the first transistor ST1, the drain electrode DE3 of the third transistor ST3, and the second capacitor electrode CPE2 of the first metal layer MTL1 through the seventeenth contact hole CNT17. The first capacitor C1 may be formed between the first capacitor electrode CPE1 of the active layer ACTL and the second capacitor electrode CPE2 of the first metal layer MTL1.

[0147] The seventeenth connection electrode CE17 of the second metal layer MTL2 may be connected to the second capacitor electrode CPE2 through the twentieth contact hole CNT20. The seventeenth connection electrode CE17 may be connected to the third electrode of the third metal layer through the twenty-first contact hole CNT21. Figures 9 to 15 The third electrode of the third metal layer is described in detail.

[0148] The eighteenth connection electrode CE18 of the second metal layer MTL2 may be connected to the second capacitor electrode CPE2 through the twenty-second contact hole CNT22. The eighteenth connection electrode CE18 may be connected to the fourth electrode of the third metal layer through the twenty-third contact hole CNT23. Figures 9 to 15 The fourth electrode of the third metal layer is described in detail.

[0149] The second transistor ST2 of the third pixel SP3 may include an active region ACT2, a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the gate electrode GE2 of the second transistor ST2 in the thickness direction (Z-axis direction).

[0150] The gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The gate electrode GE2 of the second transistor ST2 may be a portion of the auxiliary gate line BGL.

[0151] The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The fourteenth connection electrode CE14 may electrically connect the drain electrode DE2 of the second transistor ST2 and the third data line DL3 through the nineteenth contact hole CNT19. The drain electrode DE2 of the second transistor ST2 may receive the data voltage of the third pixel SP3 from the third data line DL3.

[0152] The source electrode SE2 of the second transistor ST2 may be integrally formed with the first capacitor electrode CPE1 of the first capacitor C1. The source electrode SE2 of the second transistor ST2 may be electrically connected to the gate electrode GE1 of the first transistor ST1 through the first capacitor electrode CPE1 and the thirteenth connection electrode CE13.

[0153] The third transistor ST3 of the third pixel SP3 may include an active region ACT3, a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the gate electrode GE3 of the third transistor ST3 in the thickness direction (Z-axis direction).

[0154] The gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The gate electrode GE3 of the third transistor ST3 may be a portion of the auxiliary gate line BGL.

[0155] The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The drain electrode DE3 of the third transistor ST3 may be connected to the source electrode SE1 of the first transistor ST1 and the second capacitor electrode CPE2 through the fifteenth connection electrode CE15.

[0156] The source electrode SE3 of the third transistor ST3 may be connected to the ninth connection electrode CE9 through the thirteenth contact hole CNT13. The ninth connection electrode CE9 may electrically connect the source electrode SE3 of the third transistor ST3 to the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0157] Fig. 9 is a plan view showing a first metal layer, an active layer, a second metal layer, a third metal layer, and a bank in a display device according to one embodiment. Fig. 9 is to add a third metal layer and dam to Figure 5 and Figure 6 . Figures 10 to 13 1 is a diagram showing a process of manufacturing a light emitting element layer in the display device according to the embodiment. Fig.14 It is along Fig. 9 and Fig.13 A cross-sectional view taken along line III-III', and Fig.15 It is along Fig. 9 and Fig.13 The same elements as those described above will be briefly described below or will not be described.

[0158] Reference Figures 9 to 15 , the light emitting element layer EML of the display device 10 may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first and second alignment lines AL1 and AL2, first electrodes RME1, second electrodes RME2, third electrodes RME3, fourth electrodes RME4, and fifth electrodes RME5, a bank BNK, a first insulating layer PAS1, first and second light emitting elements ED1 and ED2, a second insulating layer PAS2, first contact electrodes CTE1, second and third contact electrodes CTE2, and a third insulating layer PAS3. Here, the first electrode RME1, the second electrode RME2, the third electrode RME3, the fourth electrode RME4, and the fifth electrode RME5 may be formed by separating the second alignment line AL2.

[0159] exist Fig.10 In the embodiment, first alignment lines AL1 may be provided in the third metal layer MTL3 on the via layer VIA. A plurality of first alignment lines AL1 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The first alignment lines AL1 may be provided between the second alignment lines AL2. Each of the first alignment lines AL1 may be provided by Figure 6 The twenty-sixth contact hole CNT26 is connected to the horizontal voltage line HVDL. The first alignment line AL1 may receive a high potential voltage or a first alignment signal from the horizontal voltage line HVDL. The width of the first alignment line AL1 may be smaller than that of the second alignment line AL2, but is not limited thereto.

[0160] Second alignment lines AL2 may be provided in the third metal layer MTL3. A plurality of second alignment lines AL2 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The second alignment lines AL2 may be provided between the first alignment lines AL1. Each of the second alignment lines AL2 may be provided by Figure 6 The twenty-seventh to twenty-ninth contact holes CNT27 to CNT29 are connected to the second voltage line VSL. The second alignment line AL2 may receive a low potential voltage or a second alignment signal from the second voltage line VSL.

[0161] At least one of the second alignment lines AL2 may include a first portion AL2a, a second portion AL2b, and a third portion AL2c. The first portion AL2a of the second alignment line AL2 may overlap with the pixel circuit of the first pixel SP1, the second portion AL2b of the second alignment line AL2 may overlap with the pixel circuit of the second pixel SP2, and the third portion AL2c of the second alignment line AL2 may overlap with the pixel circuit of the third pixel SP3. The third portion AL2c of the second alignment line AL2 may be disposed between the first portion AL2a and the second portion AL2b. The first portion AL2a and the third portion AL2c of the second alignment line AL2 may be adjacent to each other in the second direction (Y-axis direction) and may be connected to each other through a connecting portion CNP. The third portion AL2c and the second portion AL2b of the second alignment line AL2 may be adjacent to each other in the second direction (Y-axis direction) and may be connected to each other through a connecting portion CNP. The width of the connecting portion CNP in the first direction (X-axis direction) may be smaller than the width of each of the first portion AL2a, the second portion AL2b, and the third portion AL2c in the first direction (X-axis direction). The connection portion CNP may be exposed through the opening portion OPN of the bank BNK.

[0162] A bank BNK may be provided on the via layer VIA and the first and second alignment lines AL1 and AL2. The bank BNK may include a first light emitting unit (or referred to as a "first light emitting portion") LOP1, a second light emitting unit (or referred to as a "second light emitting portion") LOP2, and a third light emitting unit (or referred to as a "third light emitting portion") LOP3 and an opening portion OPN.

[0163] A plurality of first light emitting cells LOP1 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). Each of the first light emitting cells LOP1 may overlap a region between the first alignment line AL1 and the second alignment line AL2. The first light emitting cells LOP1 may expose edges of the first alignment line AL1 and the second alignment line AL2.

[0164] A plurality of second light emitting cells LOP2 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). Each of the second light emitting cells LOP2 may overlap a region between the first alignment line AL1 and the second alignment line AL2. The second light emitting cells LOP2 may expose edges of the first alignment line AL1 and the second alignment line AL2.

[0165] A plurality of third light emitting cells LOP3 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). Each of the third light emitting cells LOP3 may overlap a region between the first alignment line AL1 and the second alignment line AL2. The third light emitting cells LOP3 may expose edges of the first alignment line AL1 and the second alignment line AL2.

[0166] An opening portion OPN may be provided between the first light emitting unit LOP1 and the second light emitting unit LOP2. The opening portion OPN may expose the connection portion CNP of the second alignment line AL2. The opening portion OPN may be provided between the pixel circuit of the first pixel SP1 and the pixel circuit of the third pixel SP3 and between the pixel circuit of the third pixel SP3 and the pixel circuit of the second pixel SP2 on a plane. The opening portion OPN may be provided between the first portion AL2a and the third portion AL2c of the second alignment line AL2 and between the third portion AL2c and the second portion AL2b of the second alignment line AL2.

[0167] exist Fig.11In the embodiment, a plurality of light emitting elements ED may be provided in the first light emitting part LOP1, the second light emitting part LOP2, and the third light emitting part LOP3. The light emitting elements ED may be aligned between the first alignment line AL1 and the second alignment line AL2. The first alignment line AL1 may receive a first alignment signal, the second alignment line AL2 may receive a second alignment signal, and an electric field may be formed between the first alignment line AL1 and the second alignment line AL2. For example, ink including a plurality of light emitting elements ED may be sprayed onto the first alignment line AL1 and the second alignment line AL2 by an inkjet printing process, and the plurality of light emitting elements ED dispersed in the ink may receive a dielectrophoretic force for alignment due to the electric field formed between the first alignment line AL1 and the second alignment line AL2. Therefore, the plurality of light emitting elements ED may be aligned along the second direction (Y-axis direction) between the first alignment line AL1 and the second alignment line AL2.

[0168] The light emitting element ED of the first pixel SP1 may be disposed in the first light emitting portion LOP1. A plurality of first light emitting elements ED1 of the first pixel SP1 may be disposed in the left first light emitting portion LOP1, and a plurality of second light emitting elements ED2 of the first pixel SP1 may be disposed in the right first light emitting portion LOP1.

[0169] The light emitting element ED of the second pixel SP2 may be disposed in the second light emitting portion LOP2. The plurality of first light emitting elements ED1 of the second pixel SP2 may be disposed in the left second light emitting portion LOP2, and the plurality of second light emitting elements ED2 of the second pixel SP2 may be disposed in the right second light emitting portion LOP2.

[0170] The light emitting element ED of the third pixel SP3 may be disposed in the third light emitting portion LOP3. The plurality of first light emitting elements ED1 of the third pixel SP3 may be disposed in the third light emitting portion LOP3 on the left, and the plurality of second light emitting elements ED2 of the third pixel SP3 may be disposed in the third light emitting portion LOP3 on the right.

[0171] exist Fig.12 In the embodiment, the first, second, and third contact electrodes CTE1, CTE2, and CTE3 of each of the first, second, and third pixels SP1, SP2, and SP3 may be disposed in the fourth metal layer MTL4.

[0172] The first pixel SP1 may include a first contact electrode CTE1, a second contact electrode CTE2, and a third contact electrode CTE3. The first contact electrode CTE1 of the first pixel SP1 may be connected to the first portion AL2a of the second alignment line AL2 through a thirtieth contact hole CNT30. The first contact electrode CTE1 may extend in the second direction (Y-axis direction) while overlapping the first alignment line AL1. The first contact electrode CTE1 may be connected between the first portion AL2a of the second alignment line AL2 and one end of the first light emitting element ED1. The first contact electrode CTE1 may correspond to an anode electrode of the first light emitting element ED1, but is not limited thereto.

[0173] The second contact electrode CTE2 of the first pixel SP1 may be insulated from the first alignment line AL1 and the second alignment line AL2. A first portion of the second contact electrode CTE2 may be disposed on the second alignment line AL2 to extend in the second direction (Y-axis direction). A second portion of the second contact electrode CTE2 may be disposed on the first alignment line AL1 to extend in the second direction (Y-axis direction). The second contact electrode CTE2 may be connected between the other end of the first light emitting element ED1 and one end of the second light emitting element ED2. The second contact electrode CTE2 may correspond to Figure 4 The second contact electrode CTE2 may correspond to the cathode electrode of the first light emitting element ED1, but is not limited thereto. The second contact electrode CTE2 may correspond to the anode electrode of the second light emitting element ED2, but is not limited thereto.

[0174] The third contact electrode CTE3 may be connected to the second voltage line VSL through the thirty-first contact hole CNT31. The third contact electrode CTE3 may extend in the second direction (Y-axis direction) while overlapping the second alignment line AL2. The third contact electrode CTE3 may be connected between the other end of the second light emitting element ED2 and the second voltage line VSL. The third contact electrode CTE3 may correspond to the cathode electrode of the second light emitting element ED2, but is not limited thereto. The third contact electrode CTE3 may receive a low potential voltage through the second voltage line VSL.

[0175] The second pixel SP2 may include a first contact electrode CTE1, a second contact electrode CTE2, and a third contact electrode CTE3. The first contact electrode CTE1 of the second pixel SP2 may be connected to the second portion AL2b of the second alignment line AL2 through a thirty-second contact hole CNT32. The first contact electrode CTE1 may be connected between the second portion AL2b of the second alignment line AL2 and one end of the first light emitting element ED1. The second contact electrode CTE2 may be connected between the other end of the first light emitting element ED1 and one end of the second light emitting element ED2. The third contact electrode CTE3 may be connected to the second voltage line VSL through a thirty-third contact hole CNT33. The third contact electrode CTE3 may be connected between the other end of the second light emitting element ED2 and the second voltage line VSL.

[0176] The third pixel SP3 may include a first contact electrode CTE1, a second contact electrode CTE2, and a third contact electrode CTE3. The first contact electrode CTE1 of the third pixel SP3 may be connected to the second alignment line AL2 through a thirty-fourth contact hole CNT34. The first contact electrode CTE1 may be connected between the second alignment line AL2 and one end of the first light emitting element ED1. The second contact electrode CTE2 may be connected between the other end of the first light emitting element ED1 and one end of the second light emitting element ED2. The third contact electrode CTE3 may be connected to the second voltage line VSL through a thirty-fifth contact hole CNT35. The third contact electrode CTE3 may be connected between the other end of the second light emitting element ED2 and the second voltage line VSL.

[0177] exist Fig.13 In the embodiment, the plurality of second alignment lines AL2 may be separated in row units by the separation portion ROP.

[0178] The connection portion CNP of the second alignment line AL2 may be exposed by the opening portion OPN of the bank BNK and may be removed after the alignment process of the light emitting element ED is completed. Therefore, the first portion AL2a, the second portion AL2b, and the third portion AL2c of the second alignment line AL2 may be separated from each other.

[0179] The first portion AL2a of the second alignment line AL2 may be separated to become a first electrode RME1. The first electrode RME1 may overlap with the pixel circuit of the first pixel SP1. The first electrode RME1 may be connected to the sixth connection electrode CE6 through the seventh contact hole CNT7, and the sixth connection electrode CE6 may be connected to the second capacitor electrode CPE2 through the sixth contact hole CNT6. The first electrode RME1 may be connected to the first contact electrode CTE1 through the thirtieth contact hole CNT30. The first electrode RME1 may supply the first contact electrode CTE1 with a driving current received from the pixel circuit of the first pixel SP1.

[0180] The first electrode RME1 may face the first capacitor electrode CPE1 of the active layer ACTL. The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, and may also be formed between the first capacitor electrode CPE1 and the first electrode RME1. Therefore, the display device 10 may overlap the first electrode RME1 of the third metal layer MTL3 with the first capacitor electrode CPE1 of the active layer ACTL, and electrically connect the first electrode RME1 of the third metal layer MTL3 to the second capacitor electrode CPE2 of the first metal layer MTL1, thereby forming the first capacitor C1 double to ensure capacitance and reduce coupling capacitance between pixel circuits. The display device 10 may cover the first capacitor electrode CPE1 of the first pixel SP1 with the first electrode RME1, thereby minimizing changes due to coupling capacitance of the first capacitor electrode CPE1 and preventing horizontal crosstalk to improve image quality.

[0181] The second portion AL2b of the second alignment line AL2 may be separated to become a second electrode RME2. The second electrode RME2 may overlap with the pixel circuit of the second pixel SP2. The second electrode RME2 may be connected to the twelfth connection electrode CE12 through the fifteenth contact hole CNT15, and the twelfth connection electrode CE12 may be connected to the second capacitor electrode CPE2 through the fourteenth contact hole CNT14. The second electrode RME2 may be connected to the first contact electrode CTE1 through the thirty-second contact hole CNT32. The second electrode RME2 may supply the first contact electrode CTE1 with a driving current received from the pixel circuit of the second pixel SP2.

[0182] The second electrode RME2 may face the first capacitor electrode CPE1 of the active layer ACTL. The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, and may also be formed between the first capacitor electrode CPE1 and the second electrode RME2. Therefore, the display device 10 may overlap the second electrode RME2 of the third metal layer MTL3 with the first capacitor electrode CPE1 of the active layer ACTL, and electrically connect the second electrode RME2 of the third metal layer MTL3 to the second capacitor electrode CPE2 of the first metal layer MTL1, thereby forming the first capacitor C1 double to ensure capacitance and reduce coupling capacitance between pixel circuits. The display device 10 may cover the first capacitor electrode CPE1 of the second pixel SP2 with the second electrode RME2, thereby minimizing changes due to coupling capacitance of the first capacitor electrode CPE1 and preventing horizontal crosstalk to improve image quality.

[0183] The third portion AL2c of the second alignment line AL2 may be separated to become a third electrode RME3. The third electrode RME3 may overlap with the pixel circuit of the third pixel SP3. The third electrode RME3 may be connected to the seventeenth connection electrode CE17 through the twenty-first contact hole CNT21, and the seventeenth connection electrode CE17 may be connected to the second capacitor electrode CPE2 through the twentieth contact hole CNT20.

[0184] The third electrode RME3 may face the first capacitor electrode CPE1 of the active layer ACTL. The first capacitor C1 may be formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2, and may also be formed between the first capacitor electrode CPE1 and the third electrode RME3. Therefore, the display device 10 may overlap the third electrode RME3 of the third metal layer MTL3 with the first capacitor electrode CPE1 of the active layer ACTL, and electrically connect the third electrode RME3 of the third metal layer MTL3 to the second capacitor electrode CPE2 of the first metal layer MTL1, thereby forming the first capacitor C1 double to ensure capacitance and reduce coupling capacitance between pixel circuits. The display device 10 may cover the first capacitor electrode CPE1 of the third pixel SP3 with the third electrode RME3, thereby minimizing changes due to coupling capacitance of the first capacitor electrode CPE1 and preventing horizontal crosstalk to improve image quality.

[0185] The second alignment line AL2 may be separated to become a fourth electrode RME4. The fourth electrode RME4 may overlap with the initialization voltage line VIL and the first, second, and third data lines DL1, DL2, and DL3. The fourth electrode RME4 may be connected to the eighteenth connection electrode CE18 through the twenty-third contact hole CNT23, and the eighteenth connection electrode CE18 may be connected to the second capacitor electrode CPE2 through the twenty-second contact hole CNT22. The fourth electrode RME4 may be connected to the first contact electrode CTE1 of the third pixel SP3 through the thirty-fourth contact hole CNT34. The fourth electrode RME4 may supply the first contact electrode CTE1 with a driving current received from the pixel circuit of the third pixel SP3.

[0186] The second alignment line AL2 may be separated to become a fifth electrode RME5. The fifth electrode RME5 may overlap the n-1th vertical gate line VGLn-1 and the nth vertical gate line VGLn. The fifth electrode RME5 may be connected to the sixth connection electrode CE6 through the eighth contact hole CNT8, and the sixth connection electrode CE6 may be connected to the second capacitor electrode CPE2 through the sixth contact hole CNT6.

[0187] exist Fig.14 and Fig.15In the embodiment, the first insulating layer PAS1 may be disposed on the via layer VIA, the third metal layer MTL3, and the bank BNK. The first insulating layer PAS1 may insulate the third metal layer MTL3 from the light emitting element ED. The second insulating layer PAS2 may be disposed on the top portion of the light emitting element ED and the first insulating layer PAS1. The third insulating layer PAS3 may be disposed on the second insulating layer PAS2 and the fourth metal layer MTL4. The second insulating layer PAS2 and the third insulating layer PAS3 may insulate each of the first contact electrode CTE1, the second contact electrode CTE2, and the third contact electrode CTE3.

[0188] Fig.16 is a plan view showing a third metal layer, a bank, a light emitting element, a fourth metal layer, and a separation portion in a display device according to another embodiment. Fig.16 The display device is similar to the one in the configuration of the separation portion ROP of the first alignment line AL1. Fig.13 The display device is different, and the same configuration as that described above will be briefly described, or the description thereof will be omitted.

[0189] Reference Fig.16 , the first alignment line AL1 and the second alignment line AL2 may be disposed in the third metal layer MTL3 on the via layer VIA. The first alignment line AL1 and the second alignment line AL2 may be separated in row units by a separation portion ROP.

[0190] The first alignment lines AL1 may be separated in row units to become anode electrodes of the light emitting elements ED, but are not limited thereto.

[0191] The second alignment line AL2 may become the first electrode RME1, the second electrode RME2, the third electrode RME3, the fourth electrode RME4, and the fifth electrode RME5 by separating in row units and removing the connection portion CNP.

[0192] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that the present invention may be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are examples in all aspects and are not restrictive.

Claims

1. A display device, comprising: A pixel circuit of a first pixel is arranged in a first metal layer on a substrate, an active layer on the first metal layer, and a second metal layer on the active layer; a first electrode disposed in a third metal layer on the second metal layer to overlap the pixel circuit of the first pixel; a pixel circuit of a second pixel, disposed in the first metal layer, the active layer, and the second metal layer, and spaced apart from the pixel circuit of the first pixel in a first direction; a second electrode, disposed in the third metal layer to overlap with the pixel circuit of the second pixel; an alignment line disposed in the third metal layer to extend in the first direction; as well as A plurality of light emitting elements are aligned on the third metal layer between the alignment line and the first electrode and between the alignment line and the second electrode.

2. The display device according to claim 1, in, The pixel circuit of the first pixel includes a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer, and The first electrode overlaps the first capacitor electrode of the first pixel and is electrically connected to the second capacitor electrode of the first pixel.

3. The display device according to claim 1, further comprising: a low potential line, disposed in the second metal layer to extend in a second direction intersecting the first direction; a first contact electrode, disposed in a fourth metal layer on the third metal layer, so as to be connected between the first electrode and the plurality of light emitting elements; as well as The second contact electrode is arranged in the fourth metal layer to connect between the plurality of light emitting elements and the low potential line.

4. The display device according to claim 1, further comprising: a pixel circuit of a third pixel, disposed in the first metal layer, the active layer, and the second metal layer, and disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel; as well as A third electrode is disposed in the third metal layer to overlap with the pixel circuit of the third pixel.

5. The display device according to claim 4, further comprising a fourth electrode, the fourth electrode being arranged in the third metal layer to be spaced apart from the third electrode and connected to the pixel circuit of the third pixel, the alignment line being placed between the fourth electrode and the third electrode.

6. The display device according to claim 1, in, The pixel circuit of the second pixel includes a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer, and The second electrode overlaps the first capacitor electrode of the second pixel and is electrically connected to the second capacitor electrode of the second pixel. 7 . The display device according to claim 1 , further comprising a bank provided on the first electrode and the second electrode to include an opening portion provided between the first electrode and the second electrode.

8. The display device according to claim 7, wherein: The bank further includes a light emitting portion extending in the first direction, and Wherein, the plurality of light emitting elements are arranged in the light emitting part.

9. The display device according to claim 1, further comprising a gate line provided in the second metal layer to extend in a second direction intersecting the first direction and supplying a gate signal to the pixel circuit of the first pixel and the pixel circuit of the second pixel, in, The gate line is disposed between the pixel circuit of the first pixel and the pixel circuit of the second pixel.

10. A display device, comprising: A pixel circuit of a first pixel is arranged in a first metal layer on a substrate, an active layer on the first metal layer, and a second metal layer on the active layer; a first electrode disposed in a third metal layer on the second metal layer to overlap the pixel circuit of the first pixel; a pixel circuit of a second pixel, disposed in the first metal layer, the active layer, and the second metal layer, and spaced apart from the pixel circuit of the first pixel in a first direction; a second electrode, disposed in the third metal layer to overlap with the pixel circuit of the second pixel; as well as A bank is provided on the first electrode and the second electrode to include an opening portion provided between the first electrode and the second electrode.

11. The display device according to claim 10, further comprising: an alignment line disposed in the third metal layer to be spaced apart from the first electrode and the second electrode in a second direction intersecting the first direction; as well as A plurality of light emitting elements are aligned between the alignment line and the first electrode.

12. The display device according to claim 11, in, The bank further includes a light emitting portion overlapping a region between the alignment line and the first electrode, and Wherein, the plurality of light emitting elements are arranged in the light emitting part.

13. The display device according to claim 11, further comprising: a low potential line, provided in the second metal layer to extend in the second direction intersecting the first direction; a first contact electrode, disposed in a fourth metal layer on the third metal layer, so as to be connected between the first electrode and the plurality of light emitting elements; as well as The second contact electrode is arranged in the fourth metal layer to connect between the plurality of light emitting elements and the low potential line.

14. The display device according to claim 10, further comprising: an alignment line disposed in the third metal layer to be spaced apart from the first electrode and the second electrode in a second direction intersecting the first direction; as well as A plurality of light emitting elements are aligned between the alignment line and the second electrode.

15. The display device according to claim 14, further comprising: a low potential line, provided in the second metal layer to extend in the second direction intersecting the first direction; a first contact electrode, disposed in a fourth metal layer on the third metal layer, so as to be connected between the second electrode and the plurality of light emitting elements; as well as The second contact electrode is arranged in the fourth metal layer to connect between the plurality of light emitting elements and the low potential line.

16. The display device according to claim 10, in, The pixel circuit of the first pixel includes a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer, and The first electrode overlaps the first capacitor electrode of the first pixel and is electrically connected to the second capacitor electrode of the first pixel.

17. The display device according to claim 10, in, The pixel circuit of the second pixel includes a first capacitor electrode disposed in the active layer and a second capacitor electrode disposed in the first metal layer, and The second electrode overlaps the first capacitor electrode of the second pixel and is electrically connected to the second capacitor electrode of the second pixel.

18. A display device, comprising: A first voltage line is disposed in a first metal layer on the substrate; a first transistor including a drain electrode disposed in an active layer on the first metal layer to be electrically connected to the first voltage line, a source electrode disposed in the active layer, and a gate electrode disposed in a second metal layer on the active layer; a first capacitor electrode disposed in the active layer to be electrically connected to the gate electrode of the first transistor; a second capacitor electrode disposed in the first metal layer to overlap with the first capacitor electrode; a first electrode disposed in a third metal layer on the second metal layer to overlap the first capacitor electrode and to be electrically connected to the second capacitor electrode; an alignment line disposed in the third metal layer to extend in a first direction; as well as A plurality of light emitting elements are aligned on the third metal layer between the alignment line and the first electrode.

19. The display device according to claim 18, further comprising: a data line, disposed in the first metal layer to extend in the first direction; as well as The second transistor electrically connects the data line and the first capacitor electrode.

20. The display device according to claim 18, further comprising: an initialization voltage line, disposed in the first metal layer to extend in the first direction; as well as The third transistor electrically connects the initialization voltage line and the second capacitor electrode.

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