Sub-EUV Patterned Heater For A Bar-Strip Mushroom-Shaped Cell PCM

Abstract

A phase change material (PCM) memory cell has a sub-EUV sized metal heater element. The PCM memory cell comprises a bottom electrode comprising a metallic material, a memory cell structure comprising a phase change material; and a sub-extreme ultraviolet (sub-EUV) sized metal heater element between and electrically connecting the bottom electrode and the PCM memory cell structure. The metal heater element is formed from a sub-EUV-sized circular via structure and has a seamless metal nitride fill material. The sub-extreme ultraviolet (sub-EUV) sized circular via structure also includes a sub-EUV sized metal nitride liner, the sub-EUV sized metal nitride liner including a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion. The thicker metal nitride liner bottom surface portion improves thermal insulation and provides high resistance / low power switching and reduced amorphous phase change material volume.

Description

Background Art

[0001] The present disclosure relates to mushroom-shaped cell phase change devices, and more particularly, to an integration and patterning method to implement a sub-EUV bottom electrode heater that can be metallized for use with mushroom-shaped cell phase change devices.

[0002] Even with the advent of extreme ultraviolet (EUV) lithography enabling sub-40 nm pitch printing resolution, the lack of robustness of organic materials and integration schemes, pattern transfer suffers from mask erosion, resulting in pattern collapse and poor line edge roughness.

[0003] In mushroom-cell phase-change devices, the "mushroom size" (and therefore the energy required to switch) is determined by the bottom electrode (heater) area. Various sublithographic techniques have been proposed for defining the heater, including sidewall spacer methods, using carbon nanotubes as heaters, and forming nanoscale conductive filaments in the oxide layer atop the heater via electrical breakdown (breaking the oxide).

[0004] EUV limitations prevent effective ultra-small heater sizes and require multi-layer ALD / CVD deposition to create thin heater filaments. Summary of the invention

[0005] In one aspect, an integration and semiconductor device patterning method is provided to realize a sub-EUV bottom electrode heater that can be simply metallized with CVD metals and metal nitrides to achieve high resistance / low power switching and reduced amorphous volume.

[0006] On the other hand, a multi-mushroom crossbar array implemented by a sub-EUV heater is provided.

[0007] By minimizing the heater size, the amorphous switching volume of the PCM cell is minimized, and the reduced contact area more effectively reduces the PCM cell programming current. This provides an undamaged GST volume, reduces current draw (lower power), and increases device density.

[0008] According to a first embodiment, a phase change material (PCM) memory cell is provided. The PCM memory cell includes: a bottom electrode including a metal material; a memory cell structure including a phase change material; and a sub-extreme ultraviolet (sub-EUV) sized metal heater element located between and electrically connecting the bottom electrode and the PCM memory cell structure, the metal heater element including a sub-EUV sized circular via structure having a seamless filling material.

[0009] In one embodiment, the seamless fill material includes a metal nitride fill material.

[0010] In one embodiment, the sub-extreme ultraviolet (sub-EUV) sized circular via structure further includes a sub-EUV sized metal nitride liner.

[0011] In one embodiment, the sub-EUV sized metal nitride liner includes a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion. The thicker metal nitride liner bottom surface portion improves thermal insulation, i.e., better blocks heat. In addition, the metal heater element including the sub-EUV sized circular via structure provides high resistance / low power switching and reduced amorphous phase change material volume.

[0012] In one embodiment, a metal heater element including a sub-EUV sized circular via structure includes an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

[0013] According to another embodiment, a phase change material (PCM) memory cell array is provided. The PCM memory cell array includes: a first insulating material layer including a plurality of bottom electrodes containing a metal material; a plurality of phase change material memory cell structures, each memory cell structure being aligned with a corresponding bottom electrode; and a plurality of sub-extreme ultraviolet (sub-EUV) sized metal heater elements, a corresponding metal heater element being located between a corresponding bottom electrode and a corresponding PCM memory cell structure and electrically connecting the corresponding bottom electrode and the corresponding PCM memory cell structure, each corresponding metal heater element including a sub-EUV sized circular via structure having a seamless filling material.

[0014] In the PCM memory cell array, the seamless filling material includes a metal nitride filling material.

[0015] In another embodiment, a metal heater element including a sub-extreme ultraviolet (sub-EUV) sized circular via structure further includes a sub-EUV sized metal nitride liner. The sub-EUV sized metal nitride liner includes a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion. The thicker metal nitride liner bottom surface portion improves thermal insulation, i.e., better blocks heat. The metal heater element including the sub-EUV sized circular via structure provides high resistance / low power switching and reduced amorphous phase change material volume.

[0016] In another embodiment, each metal heater element comprises a sub-EUV sized circular via structure comprising an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

[0017] According to one aspect of the present invention, a method for forming a phase change material (PCM) memory cell is provided. The method comprises a multi-step integrated method, including at least one tapered reactive ion etching (RIE) process, for achieving an insulating layer with a certain topography profile and aspect ratio, so that the metal material can be filled into a circular via hole of sub-EUV size with minimal or no voids / gaps / seams at sub-EUV size, which results in a unique structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A-1G An embodiment of a method for fabricating a PCM memory cell device in a manner that produces sub-EUV via features in one aspect of the present disclosure is depicted;

[0019] Figure 2A-2C An alternative embodiment of method steps for fabricating a PCM memory device in a manner that produces sub-EUV via features according to another aspect of the present disclosure is depicted.

[0020] Figure 3 depicts a memory cell structure having a bottom heater electrode structure formed according to embodiments described herein;

[0021] Figure 4A-4C Various views showing a 2-D or 3-D PCM cell memory array including a template structure with bottom lined heater metal structure with sub-EUV dimensions according to embodiments herein; and

[0022] Figure 5A-Figure 5C Various views showing a 2-D or 3-D PCM cell memory array including PCM memory cells formed on a template structure having a bottom heater metal structure with sub-EUV dimensions according to another embodiment. DETAILED DESCRIPTION

[0023] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0024] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0025] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0026] In one embodiment, the present disclosure provides a method and structure for forming a PCM memory cell on a semiconductor wafer.

[0027] In particular, an integration and patterning method is provided to realize sub-EUV (ie, critical dimension <25 nm) bottom electrode heaters that can be simply metallized with CVD metals and metal nitrides for high resistance / low power switching and reduced amorphous volume.

[0028] The present disclosure relates to a multi-mushroom crossbar array implemented by a sub-EUV heater and a manufacturing method. By minimizing the heater size, the amorphous switching volume is minimized, and the reduced contact area more effectively reduces the PCM cell programming current.

[0029] This approach advantageously provides an undamaged GST volume in the PCM cell, reduces current draw (lower power), and increases device density.

[0030] Figures 1A to 1G One embodiment of a method for fabricating a memory device in a manner that produces sub-EUV via features in one aspect of the present invention is described.

[0031] like Figure 1A , which depicts a cross-sectional view of an initial semiconductor structure 100. Initial structure 10 is formed after performing MOL or BEOL semiconductor manufacturing processes for fabricating conductive wiring, contacts, insulating material layers, metal levels, etc. that interconnect already formed individual devices such as transistors, capacitors, resistors, etc. (not shown). Figure 1AAs shown, the exemplary structure 100 includes, from bottom to top: a first inter-level dielectric layer 12 of a low-k dielectric material (e.g., SiN); a capping dielectric material cap layer 15 formed on the inter-level dielectric material layer 12, e.g., TiN; a second inter-level dielectric material layer 20, e.g., a low-k dielectric material such as an oxide dielectric material, e.g., SiO2, or a silicon-doped oxide formed above the dielectric material cap layer 15; and a capping developable OPL (organic planarization material) layer 25. In an embodiment, the first inter-level dielectric layer 12 of SiN dielectric material is formed to a thickness of about 75 nm. The capping TiN cap layer 15 formed on the inter-level dielectric material layer 12 and used as a hard mask is formed to a thickness of about 10 nm-30 nm. The SiO 2 covering second inter-level dielectric material layer 20 formed on the dielectric material cap layer 15 may also be a tetraethyl orthosilicate (TEOS) dielectric material layer formed to a thickness in the range of about 100 nm to 300 nm.

[0032] A capping top anti-reflective coating 30, such as a silicon-containing anti-reflective coating (SiARC), is also provided on top of the inter-level dielectric material layer 20. A patterned mask layer, such as a photoresist material layer 40, is further formed on the top SiARC layer 30, which is formed as a result of applying photolithography imaging and development processes to produce a formed mask pattern 35.

[0033] That is to say, Figure 1A The initial structure 100 is obtained by exposing the formed mask layer 40 to an image pattern (not shown) using a photolithography system, and thereafter Figure 1A In the embodiment, the image pattern is developed in a developing solvent to form a pattern 35 in the photoresist layer 40, the resist pattern 35 including a series of openings, wherein the resist structure 38 is formed as a periodic pattern. In one embodiment, the periodicity calculated as the distance d between adjacent resist pattern layer structures 38 is in the range of about 32nm-40nm.

[0034] Figure 1B shows that by using a dry etching process Figure 1A1 is a cross-sectional view of a structure 101 obtained by transferring a pattern 35 in a photoresist layer 40 in a structure 100 to an underlying OPL layer 25. That is, as a result of a reactive ion etching (RIE) step selectively performed on the surface of the dielectric layer level 20, there is an etch through the SiARC layer 38 and the OPL layer 25 to form a pattern 55 in the OPL layer defined by the resist structure 38, which includes a series of slightly tapered openings 56, and the remaining OPL structure 58 has a periodicity comparable to the periodic distance d of the structure 38 and the original resist layer pattern 35. In one embodiment, the etching is performed to form a structure 58 with a defined aspect ratio, that is, the structure 58 has edges that form an angle of <90 degrees relative to the vertical direction, for example, an angle ranging between 86 degrees and 89.5 degrees. Figure 1B The resulting structure 101 depicts the result of further removing any remaining resist layer 35 and removing the SiARC layer 30 .

[0035] Figure 1C 1 shows a cross-sectional view of a structure 102 produced by performing a first RIE etch to remove the Figure 1B The invention relates to a method for transferring a pattern 55 in the OPL layer 25 in the structure 101 of the resist layer 101 to the underlying hard mask layer 15, and a second pattern transfer through the hard mask layer 15 using a hard mask (HM) metal RIE, i.e., etching through the SiO2 layer 20 as a result of an additional tapered RIE etching step selective to the surface of the hard mask layer 15, resulting in a formed pattern 65 of funnel-shaped vias 66 in the dielectric material (e.g., SiO2 layer 20), as defined by the overlying tapered openings 56 between the OPL layer structures 58, the formed pattern 65 comprising a series of funnel-shaped via openings 66, leaving a residual dielectric layer structure 68 having a periodicity comparable to the periodicity distance d of the structure 38 of the original resist layer pattern 35. In one embodiment, the first tapered RIE etching is performed so that each of the residual dielectric layer structures 68 in the pattern 65 has an inclined sidewall 67 with an increased slope relative to the sidewall 57 of the overlying structure 58 in the OPL patterned layer 55. In one embodiment, a capacitively coupled plasma chamber using a polymerized plasma chemistry of N2 / H2 can be adjusted to achieve a desired contour opening 56 in the patterned layer 55. In one embodiment, a tapered etch using a polymerized plasma chemistry of C4F8 / O2 / Ar in a capacitively coupled plasma chamber can be adjusted to achieve a sloped sidewall structure 68 with a defined aspect ratio, that is, the angle formed by the edge of the structure 68 with the vertical direction is less than (<) 90°, for example, between 86° and 89.5°, thereby forming a desired contour opening 66 in the patterned layer 65. Figure 1CAs shown, the funnel-shaped via opening 66 formed exposes a portion of the top surface of the hard mask layer 15 between the inclined sidewall structures 68 having a length l. In one embodiment, the exposed hard mask top surface length l is about 10nm to 20nm. By using two consecutive plasma RIE conditions, the initially defined critical dimension (CD) can be reduced by 20nm to 30nm, thereby defining the final critical dimension to be less than 20nm (a highly shrink RIE process).

[0036] Figure 1C Also shown is the resulting structure 102 formed after performing an additional isotropic etch selective to the bottom inter-level dielectric layer 12 to transfer the dielectric material layer pattern 65 to the hard mask layer 15 using a standard hard mask metal RIE etch. This results in a hard mask layer pattern 75 having periodic vertical circular vias or openings 76 between the remaining hard mask structures 78, wherein each vertical circular via opening 76 has a diameter length l, for example, a diameter of about 8 nm. The resulting hard mask structure 78 has straight sidewalls and a length of about 28+ / -0.1 nm.

[0037] Figure 1D shows that by using a dry etching process Figure 1C 102 is transferred to the underlying dielectric layer 12 by transferring the pattern 75 defined in the hard mask layer 15 in the structure 102. That is, as a result of the additional RIE step and the etch bias technique performed through the defined circular via openings 76, a final pattern 85 is produced in the dielectric layer 12, which includes a series of vertically oriented circular via openings 86 aligned with the circular via openings 76 in the hard mask layer 15. In one embodiment, an etch bias of -10 nm (etch bias) produces sub-EUV feature size openings 86 of approximately 8 nm. The resulting pattern 85 includes a remaining SiN layer structure 88 having a periodicity comparable to the period distance d of the structure 38 and the original resist layer pattern 35, Figure 1D The resulting structure 103 shows the result of further removing any remaining overlying OPL layer structure 58. In one embodiment, the etching bias is applied according to:

[0038] DCD(LTH)-FCD(SiN)=10nm

[0039] Where DCD represents developed critical dimension, LTH represents lithographic printing, and FCD(ILD) represents final critical dimension (e.g., final CD printed in SiN or any inter-level dielectric). As an example, given a starting pitch of d=36nm, the achieved lithographic printing CD is 18nm, and the highly shrunk RIE CD is further shrunk to 10nm, and the final CD of opening 76 in layer 75 is 8nm, while maintaining a pitch of d=36nm consistent with the initial pitch.

[0040] Figure 1E When formed on a bottom electrode layer (not shown), the Figure 1D 104 is a cross-sectional view of a structure 104 obtained by a metallization step of depositing a metal material on the structure 103. In particular, the heater metal material, such as but not limited to TiN, W, TaN, Al or AlN, is deposited using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. The deposition process results in the formation of a resulting thin heater metal material layer 89 that conforms to the top surface and the inclined sidewall edge surface of the patterned dielectric material layer 65, and results in the heater electrode or heater filament structure 95 of the heater metal material seamlessly filling the aligned vertically oriented circular via openings 76, 86 defined in the hard mask and dielectric material patterns 75, 85, respectively.

[0041] Figure 1F A close-up view of an alternative structure is shown in which a liner material 92 is first deposited on the core prior to filling the core with the heater metal material. Figure 1D The funnel-shaped via opening 66 and the aligned vertical circular via openings 76, 86 in the structure 103. That is, Figure 1D As shown, as a result of using tapered RIE, a patterned dielectric material layer 65 is achieved with a surface structure 68 that defines a funnel-shaped via opening 66 having an aspect ratio that allows for material fill with minimal or no seams. Figure 1F As shown, at sub-EUV dimensions, Figure 1D The defined surface topology of the first implements PVD of a metal nitride material liner 89, which has a via bottom liner portion 93 thicker than a sidewall metal nitride liner portion 94 without a seam. In one embodiment, the PVD deposition process can deposit a liner 89 of a liner material including, but not limited to, TaN, TiN, AlN, WN, amorphous carbon (α-C), Cobolt, ruthenium, etc. Figure 1FAs shown, the funnel-shaped via opening 66 enables the deposition of the metal nitride liner and the core fill material, thereby avoiding pinch-off. The PVD metal nitride material deposition performed first can provide a continuous layer of a thick bottom liner 93 with less sidewall deposition 94 due to the straight sidewalls. This resulting structure 90 results in the formation of a heater structure 90 with a thicker TaN liner bottom 93, which improves thermal insulation, i.e., better blocks heat. In addition, due to the tapered RIE profile achieved at the patterned dielectric material layer 65 and the aspect ratio of the funnel-shaped opening 66, the final PVD deposited metal nitride heater core fill material 95 (e.g., TaN) does not have any voids / gaps / seams.

[0042] Figure 1G shows a cross-sectional view of a template structure 105, which is formed by applying a Figure 1E The structure 104 is produced by a chemical mechanical planarization (CMP) step for removing the remaining patterned dielectric material layer 65 and removing the remaining patterned hard mask metal layer 75, thereby producing a patterned dielectric layer 85 having formed metal heater features 95 with sub-EUV pads without voids / seams / gaps. Each formed sub-EUV metal heater structure 95 has a width l1 of approximately 8nm and is spaced apart by a distance l2 of approximately 28nm, for example, as determined by the DCD(LTH)-FCD(SiN) formula. In a non-limiting example, this results in a pitch range of approximately 32nm-40nm. The resulting patterned dielectric layer 85 of the resulting structure 105 including the formed sub-EUV lined metal heater features 95 can be a precursor or template for further patterning. For example, each of these formed sub-EUV sized lined metal heater structures 95 is aligned with a subsequently formed memory cell (i.e., a phase change memory cell) that is formed aligned therewith in a subsequent process step (not shown).

[0043] Figure 2A-2C Alternative embodiments of method steps for fabricating a PCM memory device in a manner that produces sub-EUV via features according to another aspect of the present disclosure are described.

[0044] In particular, Figure 2A Another cross-sectional view of a structure 204 of a second embodiment is shown, the structure 204 resulting from a metallization step for forming a metallization layer when formed over a bottom electrode layer (not shown). Figure 1DA metal material liner 189 is deposited on the structure 103. In particular, a heater metal material such as TiN, W, TaN, Al or AlN is deposited using a CVD or PVD process in such a way as to line the surface of the inclined sidewalls 67 of the funnel-shaped opening 66 defined in the patterned dielectric layer 65 and form a liner at the inner surface of the aligned etched holes 76, 86 of the corresponding patterned hard mask 75 and the patterned first dielectric layer 85. Figure 1F In the embodiment of the present invention, the funnel-shaped via opening 66 enables the deposition of the metal nitride liner and the core fill material, thereby avoiding pinch-off. The CVD or PVD deposition of the metal nitride liner material results in the formation of a heater metal material liner 189 that is approximately 2-3 nm thick. There is also an optional etch bias (e.g., an in-situ sputter etch bias) and a dielectric fill step that can be performed after the formation of the liner 189. Figure 2A A lined tapered opening 66 lined with a metal nitride liner material in the patterned dielectric layer 65 is shown, and corresponding lined etched circular vias 76 , 86 of the patterned hard mask layer 75 and the patterned dielectric layer 85 are shown.

[0045] In an alternative embodiment, Figure 2B The resulting structure 190 shown depicts Figure 2A The result of depositing the first liner material 189 in the funnel-shaped via opening 66 and the aligned vertical circular via openings 76, 86 in the structure 204, and depositing the core heater metal material 195 in the vertically oriented circular via opening 86. That is, as formed using tapered RIE Figure 1D As a result of the funnel-shaped via opening 66, a patterned dielectric material layer 65 of a surface structure 68 is achieved, which defines a funnel-shaped opening 66 with an aspect ratio that allows for minimal or no seams in the metal fill. At sub-EUV dimensions, Figure 1D The defined surface topology of first enables PVD of a metal material outer liner 189, such as TaN, with a continuous thick bottom liner portion 193 thicker than the sidewall liner portion 194 without a seam. Other metal material liners may include TiN, AlN, WN, α-C, etc. Figure 2BAs shown, the funnel-shaped via opening 66 enables the deposition of a metal nitride material liner 189 (e.g., TaN) and a core fill material 195 that avoids pinching off. The PVD metal nitride material deposition performed first can provide a continuous outer layer of a thick bottom liner 193 with less metal nitride material deposition sidewall deposition 194 due to the straight sidewalls. The resulting heater structure 190 has a thicker metal nitride material liner bottom 193, which improves thermal insulation, i.e., better blocks heat. Another deposition step of a metal nitride material (such as TiN) can result in the formation of another inner metal nitride filament layer 192 that conforms to the inner surface of the outer liner portion 193, 194. The filament layer can be a TiN layer deposited by an atomic layer deposition (ALD) process. Furthermore, a final PVD deposition step is performed to deposit a metal nitride core fill material 195 (eg, TaN) without any voids / gaps / seams due to the tapered RIE profile and the aspect ratio achieved by the funnel-shaped opening 66 , avoiding pinch-off at the patterned dielectric material layer 65 .

[0046] Alternatively, instead of depositing a metal nitride core fill material 195 , an inter-level dielectric material fill 195 may be deposited in a final PVD deposition step, which may include, but is not limited to, SiO 2 or SiN, for example, deposited by an ALD / CVD process.

[0047] Figure 2C A cross-sectional view of the resulting template structure 205 of the second embodiment is shown, the structure 204 being formed by applying Figure 2A The structure 204 is obtained by a CMP step for removing the remaining patterned dielectric material layer 65 and removing the remaining patterned hard mask metal layer 75, thereby obtaining a patterned dielectric layer 85 having spaced-apart sub-EUV metal heater structures 190. Each formed sub-EUV metal heater structure 190 includes a circular via opening with a diameter l1 of approximately 8 nm having a pad 189 and is filled with a metal nitride or dielectric material 195. Adjacent sub-EUV metal heater pad structures 190 are spaced apart by a distance l2 of approximately 28 nm. In one embodiment, the opening diameter l1 ranges between 6 nm and 10 nm, and the distance l2 can range between 26 nm and 30 nm. The resulting patterned dielectric layer 85 of the resulting template structure 205 including the formed sub-EUV metal heater structures 190 can be a precursor or template for further patterning. For example, each of these sub-EUV sized metal heater structures 190 may be formed in alignment with a memory cell (ie, a phase change memory cell) to be formed in alignment therewith in a subsequent process step (not shown).

[0048] Figure 3A memory cell structure 200 having a bottom heater electrode structure 300 formed according to embodiments described herein is depicted. For example, in one embodiment, a PCM mushroom-shaped cell memory element 150 comprising an active volume of Ge2Sb2Te5 (GST) material is formed at Figure 1G In another design, a PCM mushroom-shaped unit memory element 150 including an active volume of GST material is formed on a corresponding sub-EUV size heater metal filament of the template structure 105. Figure 2B The template structure 205 is disposed on a corresponding sub-EUV sized heater filament.

[0049] That is to say, Figure 3 As shown, the PCM cell memory element 150 is formed as an electrically contact aligned photolithographically defined bottom heater metal electrode 300, whether formed by e.g. Figure 1G The sub-EUV sized bottom heater metal filament structure 95 shown in FIG. 1 is composed of, for example, Figure 2B The sub-EUV sized metal heater pad features 190 shown in FIG. Electrical connections are shown between corresponding aligned active amorphous GST (α-GST) phase change material portions 151 of the memory element 150. Figure 1G The sub-EUV sized bottom heater wire structure 95 shown or such Figure 2B The defined dimensions of the sub-EUV metal heater pad features 190 shown determine the size of the switching volume of the α-GST material portion 151 of the cell 150. The sub-EUV sized bottom heater electrode 300 causes the PCM cell 200 to undergo an amorphous to crystalline state transition as a function of the voltage and current applied to the bottom electrode 300.

[0050] Figure 4A-4C Various views showing a 2-D or 3-D PCM cell memory array including a template structure with bottom lined heater metal structure with sub-EUV dimensions according to one embodiment herein.

[0051] In particular, Figure 4A-4C Various views showing a 2-D or 3-D PCM cell memory array 400, including having a plurality of Figure 1F The template structure 105 of the bottom lined heater metal structure 95 of the sub-EUV size shown, or having a Figure 2B A template structure 205 of the lined heater metal structure 190 is shown with sub-EUV dimensions.

[0052] Figure 4AA cross-sectional view of a 2-D or 3-DPCM cell memory array 400 is shown having a series of multiple memory elements 410 formed on a template formed, the template being formed having Figure 1G The dielectric layer template 105 of the bottom heater wire 95 of the sub-EUV size shown, or having a dielectric layer template such as Figure 2B Template 205 of sub-EUV sized metal heater pad features 190 is shown. Figure 4A As shown in FIG. 1 , aligned with the corresponding bottom heater wire 95 or metal heater pad feature 190 are corresponding PCM mushroom-shaped cell memory elements 410, each cell having a GST material (e.g., crystalline GST or c-GST) and a corresponding α-GST switching material portion 411. Figure 4A As shown, in one embodiment, the memory cell array 400 is formed on an inter-level low-k dielectric (ILD) or tetraethyl orthosilicate (TEOS) material layer 415, which has a surface on which a Figure 1G The dielectric layer template 105 of the bottom heater metal wire 95 of the sub-EUV size shown, or having a dielectric layer template 105 of the bottom heater metal wire 95 of the sub-EUV size shown Figure 2B The template 205 of the sub-EUV sized metal heater pad features 190 is shown. Formed in the patterned TEOS material layer 415 are corresponding metal conductors (metal wires or conductive lines) 420, each of which is electrically connected to Figure 1G or alternatively connected to a corresponding separate sub-EUV sized bottom heater wire 95 as shown in FIG. Figure 2B 4. The corresponding individual sub-EUV sized metal heater pad features 190 are shown in FIG. In an embodiment, individual metal conductor lines or wires 420 receive voltage or current signals for programming the resistance states of individual PCM memory cells 410. Figure 4A As further shown in , each PCM memory cell is electrically connected to a single top metal electrode 425 formed in an upper inter-level dielectric layer and aligned with the line or memory cells 410 to electrically connect to each cell 410 .

[0053] In one embodiment, each line or conductor is formed of a metallic material such as copper, tungsten, copper alloy, cobalt, or any suitable conductive metal, and may be lined with a barrier layer, for example, Ta, TaN, Ti, TiN, or any suitable liner material (not shown).

[0054] Figure 4B Depicted Figure 4A FIG. 4 is a cross-sectional view of a 2-D or 3-D PCM cell memory array 400 , however showing the array structure rotated 90 degrees. Figure 4BThe cross-sectional view of a 90° rotated 2-D or 3-D PCM cell memory array structure depicts a series of memory elements 410, wherein each memory cell element has a corresponding respectively aligned top electrode 425 formed in a top inter-level dielectric layer 435 of a dielectric material such as TEOS. Figure 4B The cross-sectional view of the rotated 2-D or 3-D PCM cell memory array structure also depicts a series of memory elements 410 in a rotated orientation electrically connected to a single individual metal conductor line or wire 420 that receives a voltage or current signal for programming the individual memory cells 410. Although not shown, an exemplary current applied from the bottom individual metal conductor line or wire 420 passes through the sub-EUV sized bottom heater metal filaments 95 of the template 105, the sub-EUV sized metal heater pad features 190, and through the corresponding memory cell elements, which current can be read or sensed via the top metal electrode 425.

[0055] Figure 4C Depicted Figure 4A and Figure 4B A top view 450 of a 2-D or 3-D PCM cell cross-strip memory array 400 depicts the cross-strip memory array 400 formed in the embodiment of the present invention. Figure 1G The template 105 with sub-EUV sized bottom heater wire 95 as shown or Figure 2C A linear series of PCM memory cells 410 on a template 205 is shown having metal heater pad features 190 of sub-EUV dimensions. Figure 4A In particular, the image taken along line Y-Y' is shown. Figure 4C 4 is a cross-sectional view of a structure 450 in which a linear series of cells 410 of a 2D array are connected to corresponding top conductors 425. Figure 4B Shows a view taken along line X-X' Figure 4C 4 is a cross-sectional view of a structure 450 in which a linear series of cells 410 of a 2D array are connected to corresponding bottom metal conductors 420.

[0056] Figure 5A-Figure 5C Various views showing a 2-D or 3-D PCM cell memory array including PCM memory cells formed on a template structure having a sub-EUV sized bottom heater metal structure according to another embodiment.

[0057] In particular, Figure 5A-Figure 5C Various views showing another embodiment of a 2-D or 3-D PCM cell memory array 500 including a 2-D or 3-D PCM cell memory array formed on a substrate having a structure such as Figure 1GThe bottom heater metal filament structure 95 of the sub-EUV size shown is formed on a template structure 105 or on a substrate having a structure such as Figure 2C A PCM memory cell on a template structure 205 with sub-EUV sized metal heater pad features 190 is shown.

[0058] Figure 5A A cross-sectional view of a 2-D or 3-D PCM cell memory array 500 is shown having a series of multiple individual memory elements 410 formed on a template formed, the template having Figure 1G The dielectric layer template 105 of the bottom heater metal wire 95 of the sub-EUV size shown, or having a dielectric layer template 105 of the bottom heater metal wire 95 of the sub-EUV size shown Figure 2C Template 205 of sub-EUV sized metal heater pad features 190 is shown. Figure 5A The memory cell array 500 is Figure 4A The difference between the memory cell array 400 embodiments is that Figure 5A Each PCM memory cell in the embodiment of the PCM memory array 500 is isolated and separated from adjacent PCM memory cells 510 by dielectric material spacers 512. That is, in one embodiment, spacers are formed between each memory cell during the fabrication of the PCM memory cell elements 510, and each spacer includes a SiO2 or similar dielectric material spacer filler 512.

[0059] like Figure 5A As shown in FIG. 1 , aligned with the corresponding bottom heater wire 95 or metal heater pad feature 190 are corresponding PCM mushroom-shaped cell memory elements 510, each cell having a GST material (e.g., polyester-GST or c-GST) and a corresponding α-GST switching material portion 511. Figure 5A As shown, in one embodiment, the memory cell array 500 is formed on an inter-level low-k dielectric (ILD) or tetraethyl orthosilicate (TEOS) material layer 515, which has a surface on which a Figure 1G The dielectric layer template 105 of the bottom heater wire 95 of the sub-EUV size shown, or having a dielectric layer template such as Figure 2C The template 205 of the sub-EUV sized metal heater pad features 190 is shown. Formed in the patterned TEOS material layer 515 are corresponding metal conductors (metal wires or conductive lines) 520, each of which is electrically connected to Figure 1G or alternatively connected to a corresponding separate sub-EUV sized bottom heater wire 95 as shown in FIG. Figure 2C, and the corresponding individual sub-EUV sized metal heater pad features 190 shown in FIG. In an embodiment, individual metal conductor lines or wires 520 receive voltage or current signals for programming the resistance states of individual PCM memory cells 510. Figure 5A As further shown in , each PCM memory cell is electrically connected to a single top metal electrode 525 formed in an upper inter-level dielectric layer and aligned with the line or memory cells 510 for electrical connection to each cell 510 .

[0060] In one embodiment, each line or conductor is formed of a metallic material such as copper, tungsten, copper alloy, cobalt, or any suitable conductive metal, and may be lined with a barrier layer, for example, Ta, TaN, Ti, TiN, or any suitable liner material (not shown).

[0061] Figure 5B Depicted Figure 5A FIG. 5 is a cross-sectional view of a 2-D or 3-D PCM cell memory array 500 , however showing the array structure rotated 90 degrees. Figure 5B The cross-sectional view of a 90° rotated 2-D or 3-D PCM cell memory array structure shows a series of individual and isolated memory elements 510 separated by spacers 512, wherein each memory cell element has a corresponding respectively aligned top electrode 525 formed in a top inter-level dielectric layer 535 of a dielectric material such as TEOS. Figure 5B The cross-sectional view of the rotated 2-D or 3-D PCM cell memory array structure also depicts a series of memory elements 510 in a rotated orientation electrically connected to a single individual metal conductor line or wire 520 receiving a voltage or current signal for programming the individual memory cells 510. Although not shown, an exemplary current applied from the bottom individual metal conductor line or wire 520 passes through the sub-EUV sized bottom heater metal filaments 95 of the template 105, the sub-EUV sized metal heater pad features 190, and through the corresponding memory cell elements, which current can be read or sensed via the top metal electrode 525.

[0062] Figure 5C Depicted Figure 5A and Figure 5B A top view 550 of a 2-D or 3-D PCM cell crossbar memory array 500 depicts a linear series of individual and isolated PCM memory cells 510, each separated by a dielectric material spacer 512, formed in a manner having Figure 1G The bottom heater wire 95 of the sub-EUV size shown in FIG. 1 is formed on a template 105, or on a bottom heater wire 95 having a sub-EUV size shown in FIG. Figure 2CSub-EUV sized metal heater pad features 190 are shown on template 205 . Figure 5A In particular, the image taken along line Y-Y' is shown. Figure 5C 5 is a cross-sectional view of a structure 550 in which a linear series of cells 510 of a 2D array are connected to corresponding top conductors 525. Figure 5B Shows a view taken along line X-X' Figure 5C 5 is a cross-sectional view of a structure 550 in which a linear series of cells 510 of a 2D array are connected to corresponding bottom metal conductors 520.

[0063] Figure 1A-1G and Figure 2A-2C The method proposes a new integration and patterning method to realize PCM cell sub-EUV bottom electrode heater, which can be simply metalized with CVD metals and metal nitrides for high resistance / low power switching and reduced amorphous volume. That is, EUV lithography process and etch bias it are used to further reduce the via size while achieving a large top CD aperture to enable metallization with PVD / ALD. These methods enable more vertical heater via size walls. Additional embodiments include multi-mushroom shaped cross-strip PCM cell arrays realized by sub-EUV heaters. By minimizing the heater size, the PCM cell amorphous switching volume is minimized and an undamaged GST volume is provided, reducing current draw (operating at lower power) and increasing device density. The smaller the heater size, the more efficient the PCM device performance.

[0064] Figure 1A-1G and Figure 2A-2C The method can be applied to PCM device technology at the heater module, and the method is scalable to achieve higher density PCM architectures.

[0065] Although the present disclosure has been described in terms of specific embodiments, it is apparent that many alternatives, modifications, and variations will be apparent to those skilled in the art in view of the foregoing description. The various embodiments of the present disclosure may be used alone or in combination with any other embodiment, unless otherwise expressly stated or clearly incompatible with each other. Therefore, the present disclosure is intended to encompass all such alternatives, modifications, and variations that fall within the scope of the present disclosure and the appended claims.

Claims

1. A phase change material PCM memory cell, comprising: a bottom electrode comprising a metallic material; A memory cell structure including a phase change material; as well as A sub-EUV-sized metal heater element is located between and electrically connects the bottom electrode and the PCM memory cell structure, the metal heater element comprising a sub-EUV-sized vertical circular via structure with a seamless filling material.

2. The PCM memory cell of claim 1, wherein the seamless fill material comprises a metal nitride fill material.

3. The PCM memory cell of claim 2, wherein the sub-EUV-sized vertical circular via structure further comprises a sub-EUV-sized metal nitride liner.

4. The PCM memory cell of claim 3, wherein the metal nitride liner of sub-EUV size comprises a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion.

5. The PCM memory cell of claim 1, wherein the metal heater element comprising a sub-EUV sized vertical circular via structure comprises an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

6. The PCM memory cell of claim 5, wherein the outer metal nitride liner of sub-EUV dimensions comprises a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion.

7. The PCM memory cell of claim 6, wherein the seamless filling material comprises a material selected from the group consisting of: a metal nitride filling material or a dielectric filling material.

8. The PCM memory cell of claim 1 , wherein the sub-EUV sized metal heater element via structure is formed in a first dielectric material layer directly below the PCM memory cell structure, and the bottom electrode is formed in a second dielectric layer below the first dielectric material layer.

9. A phase change material PCM memory cell array, comprising: a first insulating material layer including a plurality of bottom electrodes comprising a metallic material; a plurality of memory cell structures of phase change material, each memory cell structure being aligned with a corresponding bottom electrode; as well as A plurality of sub-EUV sized metal heater elements, each of the respective metal heater elements being located between and electrically connecting a respective bottom electrode and a respective PCM memory cell structure, each respective metal heater element comprising a sub-EUV sized vertical circular via structure having a seamless filling material.

10. The PCM memory cell array of claim 9, wherein the seamless filling material comprises a metal nitride filling material.

11. The PCM memory cell array of claim 10, wherein the sub-EUV-sub-EUV sized vertical circular via structure further comprises a sub-EUV sized metal nitride liner.

12. The PCM memory cell array of claim 11, wherein the sub-EUV sized metal nitride liner comprises a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion.

13. The PCM memory cell array of claim 9, wherein each metal heater element comprising a sub-EUV sized vertical circular via structure comprises an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

14. The PCM memory cell array of claim 13, wherein the outer metal nitride liner of sub-EUV size comprises a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion.

15. The PCM memory cell array of claim 14, wherein the seamless filling material comprises a material selected from the group consisting of: a metal nitride filling material or a dielectric filling material.

16. The PCM memory cell array of claim 9, wherein the plurality of metal heater elements of sub-EUV size are formed in a first dielectric material layer directly below the PCM memory cell structure, and the plurality of bottom electrodes are formed in a second dielectric layer below the first dielectric material layer.

17. A method of forming a phase change material (PCM) memory cell, comprising: forming a first insulating material layer having a bottom electrode containing a metal material; forming a second insulating material layer having a sub-EUV sized metal heater element, the sub-EUV sized metal heater element comprising a sub-EUV sized vertical circular via structure aligned with and electrically connected to the bottom electrode, the vertical circular via structure having a seamless filling material; and A PCM memory cell structure electrically connected to the metal heater element is formed over the sub-EUV sized metal heater element.

18. The method of claim 17, wherein said forming said second insulating material layer to have a metal heater element having sub-EUV dimensions comprises: forming the second insulating material layer above the first insulating material layer; forming a hard mask dielectric material layer over the second insulating material layer; forming an intermediate dielectric material layer over the hard mask dielectric material layer; etching the intermediate dielectric material layer using a tapered etching process to achieve a topographic profile defining one or more funnel-shaped openings; performing an additional etching process within the defined funnel-shaped opening to form a circular via opening aligned with the funnel-shaped opening and extending through the hard mask dielectric material layer and the second insulating material layer; performing a vapor deposition process to seamlessly deposit the fill material in the vertical circular via opening; as well as The intermediate dielectric material layer is removed, and the hard mask dielectric material layer is removed.

19. The method of claim 18, wherein the fill material seamlessly deposited in the vertical circular via opening comprises a metal nitride fill material.

20. The method of claim 19, wherein before performing a vapor deposition process to seamlessly deposit the filling material, an additional step is: A sub-EUV sized metal nitride liner is deposited in the vertical circular via opening, the sub-EUV sized metal nitride liner comprising a thicker metal nitride liner bottom surface portion and a thinner sidewall metal nitride portion.

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