Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and aims to solve the problem that the on-state current of a high-brush product or a product with a high charging rate requirement is difficult to increase. The array substrate comprises a first substrate body, a transistor located on one side of the first substrate body and a first electrode. The transistor comprises a first grid electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the side, away from the first substrate, of the first grid electrode. The first electrode is located on the side, away from the first substrate, of the source electrode, and the orthographic projection of the first electrode on the first substrate covers at least part of the orthographic projection of the source electrode on the first substrate and covers at least part of the orthographic projection of the drain electrode on the first substrate. And the first electrode is insulated from the first grid electrode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In order to improve the viewing angle, brightness, contrast and response speed of display devices, existing LCDs use high aperture advanced super dimensional switching (HADS) technology. With the development of the times, consumers have higher and higher requirements for screen image display, from 60Hz at the beginning to 120Hz, 144Hz, 165Hz, 288Hz, 330Hz and even 450Hz. However, as the refresh rate increases, the pixel charging time decreases, resulting in blackening defects in the product, such as Figure 1 As shown. In order to improve the product charging rate, the storage capacitance is reduced by increasing the thickness of the passivation layer, but this design will lead to a decrease in the on-state current of the transistor device, and the corresponding product charging rate will be reduced. Therefore, the liquid crystal display of the prior art cannot take into account both the higher on-state current and the smaller pixel storage capacitance, and the on-state current is difficult to increase. Summary of the invention

[0003] The present invention provides an array substrate, a display panel and a display device to improve the problem that it is difficult to increase the on-state current of high-refresh products or products with high charging rate requirements.

[0004] An embodiment of the present invention provides an array substrate, comprising: a first substrate, a transistor located on one side of the first substrate, and a first electrode; wherein the transistor comprises: a first gate, a source and a drain located on a side of the first gate away from the first substrate;

[0005] The first electrode is located on the side of the source away from the first substrate, and the first electrode's projection on the first substrate covers at least part of the source's projection on the first substrate and covers at least part of the drain's projection on the first substrate, and the first electrode is insulated from the first gate.

[0006] In a possible implementation manner, the array substrate further includes: a pixel electrode; the first electrode and the pixel electrode are made of the same layer and material, and the first electrode and the pixel electrode are integrally connected.

[0007] In a possible implementation, the array substrate includes: a plurality of gate lines extending along a first direction; the first electrode includes: a first electrode portion and a second electrode portion arranged along a second direction; the second direction is perpendicular to the first direction;

[0008] The array substrate comprises: a passivation layer located between a layer where the pixel electrode is located and a layer where the drain electrode is located; the passivation layer has a first via hole exposing a portion of the drain electrode;

[0009] The first electrode portion covers the first via hole and overlaps with the drain electrode; the second electrode portion overlaps with the orthographic projection of the gate line on the first substrate.

[0010] In a possible implementation, the array substrate further includes: a first active pattern located on a side of the drain electrode facing the first substrate and in contact with the drain electrode; the first active pattern includes a first active portion overlapping the drain electrode, and a second active portion extending from the first active portion;

[0011] The first via hole exposes a portion of the drain electrode away from a surface of one side of the first substrate, a side surface of the drain electrode, a portion of the second active portion away from a surface of one side of the first substrate, and a portion of the side surface of the second active portion, and exposes a portion of the passivation layer adjacent to the second active portion.

[0012] In a possible implementation manner, the source includes: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion along the second direction;

[0013] An orthographic projection of the second electrode portion on the first substrate covers the first source branch, the second source branch, and an area between the first source branch and the second source branch.

[0014] In a possible implementation manner, the maximum depth of the first via hole is less than the maximum thickness of the passivation layer.

[0015] In a possible implementation manner, the array substrate further includes: a pixel electrode; the first electrode and the pixel electrode are made of the same layer and material, and the first electrode and the pixel electrode are insulated from each other.

[0016] In a possible implementation, the array substrate includes: a plurality of gate lines extending along a first direction; the first electrode includes: a third electrode portion, a fourth electrode portion, and a fifth electrode portion extending along a third direction and connecting the third electrode portion and the fourth electrode portion; the third direction intersects both the first direction and the second direction;

[0017] The third electrode portion and the pixel electrode are located on the same side of the gate line; the orthographic projection of the fourth electrode portion on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

[0018] In a possible implementation, the array substrate further includes: a passivation layer located between the layer where the pixel electrode is located and the layer where the drain electrode is located, a switching electrode located in the layer where the drain electrode is located, a second active pattern located on a side of the switching electrode facing the first substrate and in contact with the switching electrode, a gate insulating layer located on a side of the second active pattern facing the first substrate, a common electrode layer located on a side of the gate insulating layer facing the first substrate, and a second via hole penetrating the passivation layer and the gate insulating layer; the second active pattern has a third active portion overlapping the switching electrode, and a fourth active portion extending from the third active portion; the common electrode layer includes: a plurality of common electrode strips extending along the first direction;

[0019] The second via hole exposes a portion of the transfer electrode facing away from a surface of one side of the first substrate, a side surface of the transfer electrode, a portion of the fourth active portion facing away from a surface of one side of the first substrate and a portion of the side surface of the fourth active portion, and a portion of the common electrode strip facing away from a surface of one side of the first substrate; the third electrode portion covers the second via hole and overlaps at least the transfer electrode and the common electrode strip.

[0020] In a possible implementation manner, the source includes: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion along the second direction;

[0021] The orthographic projection of the fourth electrode portion on the first substrate covers the first source branch, the second source branch, and an area between the first source branch and the second source branch.

[0022] In a possible embodiment, the passivation layer further has a first groove which is recessed from a surface facing away from a side of the first substrate toward a side of the first substrate; an orthographic projection of the first groove on the first substrate covers at least a portion of an orthographic projection of the source on the first substrate, and covers at least a portion of an orthographic projection of the drain on the first substrate.

[0023] In a possible implementation manner, the second electrode portion is located in the first groove; or the fourth electrode portion is located in the first groove.

[0024] An embodiment of the present invention further provides a display panel, comprising the array substrate provided in the embodiment of the present invention, and further comprising an opposite substrate arranged opposite to the array substrate.

[0025] In a possible embodiment, the array substrate has a first groove; the opposing substrate includes: a second substrate, and a spacer located on the side of the second substrate facing the array substrate, the orthographic projection of the spacer on the first substrate overlaps with the orthographic projection of the first groove on the first substrate; the surface of the spacer facing the array substrate is covered with a conductive part; the conductive part is in contact with the first electrode.

[0026] In a possible implementation manner, the conductive portion is a whole layer of transparent planar electrode.

[0027] In a possible implementation, the counter substrate further includes: a black matrix layer located on the side of the spacer facing the second substrate; the black matrix layer includes: a plurality of first sub-black matrix portions extending along the first direction, and a plurality of second sub-black matrix portions extending along the second direction;

[0028] The conductive part includes: a plurality of first sub-conductive parts extending along the first direction, and a plurality of second sub-conductive parts extending along the second direction; the orthographic projection of the first sub-black matrix part on the second substrate covers the orthographic projection of the first sub-conductive part on the second substrate; the orthographic projection of the second sub-black matrix part on the second substrate covers the orthographic projection of the second sub-conductive part on the second substrate.

[0029] In a possible implementation manner, the material of the conductive part includes: transparent metal oxide or metal.

[0030] In a possible implementation, the array substrate further includes: a common electrode layer; the voltage loaded on the conductive portion is different from the voltage loaded on the common electrode layer; or the voltage loaded on the conductive portion is the same as the voltage loaded on the common electrode layer.

[0031] An embodiment of the present invention further provides a display device, comprising the display panel provided by the embodiment of the present invention.

[0032] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present invention, the array substrate further comprises a first electrode, the first electrode is located on a side of the source electrode away from the first substrate, and the orthographic projection of the first electrode on the first substrate covers at least a portion of the orthographic projection of the source electrode on the first substrate, and covers at least a portion of the orthographic projection of the drain electrode on the first substrate, so that the first electrode can be formed as a top gate of the transistor, so that the transistor has a dual-gate structure, which is beneficial to improving the on-state current, that is, because the orthographic projection of the first electrode partially or completely overlaps with the orthographic projection of the source electrode and / or the drain electrode, the edge electric field can be enhanced, so that the lateral electric field strength is enhanced, which is beneficial to increase the carrier concentration of the active layer, thereby increasing the on-state current; in addition, the orthographic projection of the first electrode partially or completely overlaps with the orthographic projection of the source electrode and / or the drain electrode, and because the first electrode exists above the channel, the channel can be protected from the influence of the external environment, isolating the risk of external water vapor penetrating from the passivation layer into the channel to corrode the active layer channel; moreover, the first electrode is insulated from the first gate, that is, the voltage of the first electrode as the top gate can be flexibly adjusted to obtain the required on-state current, realize the digital on-state current, and meet the charging rate of broadband products. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a display panel having poor blackening;

[0034] Figure 2 Schematic diagram of the relationship between the on-state current coefficient of the transistor and the thickness of the passivation layer;

[0035] Figure 3 It is a schematic diagram of the principle of the on-state current coefficient of the transistor and the thickness of the passivation layer;

[0036] Figure 4A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure;

[0037] Figure 4B for Figure 4A Schematic diagram of the film layers of the common electrode layer;

[0038] Figure 4C for Figure 4A Schematic diagram of the film layer of the middle gate line layer;

[0039] Figure 4D for Figure 4A Schematic diagram of the film layer of the data line layer;

[0040] Figure 4E for Figure 4A Schematic diagram of a single film layer of the pixel electrode layer;

[0041] Figure 5 for Figure 4A A schematic cross-sectional view along the dotted line e1 in FIG.

[0042] Figure 6for Figure 4A A schematic cross-sectional view along the dotted line e2;

[0043] Fig. 7A A second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0044] Figure 7B for Fig. 7A Schematic diagram of the film layers of the common electrode layer;

[0045] Figure 7C for Fig. 7A Schematic diagram of the film layer of the middle gate line layer;

[0046] Fig.7D for Fig. 7A Schematic diagram of the film layer of the data line layer;

[0047] Fig. 7E for Figure 4A Schematic diagram of a single film layer of the pixel electrode layer;

[0048] Figure 8 for Fig. 7A A schematic cross-sectional view at the dotted line e1;

[0049] Fig. 9 for Fig. 7A A schematic cross-sectional view at the dotted line e2;

[0050] Fig.10 One of the cross-sectional schematic diagrams of a display panel provided by an embodiment of the present invention;

[0051] Fig.11 is a schematic diagram of a black matrix and a conductive part;

[0052] Fig.12 The second cross-sectional schematic diagram of the display panel provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0055] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0056] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0057] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0058] like Figure 2 As shown, the abscissa represents the thickness of the passivation layer in the display product (in angstroms), the ordinate represents the on-state current coefficient of the transistor, the solid line represents the connection line of the on-state current coefficient corresponding to different thicknesses of the passivation layer, and the dotted line represents the fitting line of the passivation layer thickness and the on-state current coefficient. Figure 2It can be seen that the on-state current coefficient of the transistor in the display product decreases with the increase of the thickness of the passivation layer, which is close to a linear relationship. When the thickness of the passivation layer of the display product is greater than 3000 angstroms, the on-state current coefficient of the transistor decreases significantly and can no longer meet the design requirements of the display product (design requirement: on-state current coefficient ≥ 0.8). In order to reduce the pixel storage capacitance, the passivation layer thickness of the high refresh product can reach ≥ 7000 angstroms. According to experimental results, the on-state current coefficient is much smaller than the design requirement. A small on-state current coefficient indicates that the on-state current of the product's transistor device is too low, that is, the transistor device cannot fully charge the pixel storage capacitance within a fixed time, which will cause the product to have a blackened moire (Mura) defect.

[0059] like Figure 3 As shown in (a), the transistor device is composed of a gate, a gate insulating layer (Gate Insulator, GI), an active layer (Active, a-Si), a source and drain (Source and Drain, referred to as SD electrodes), a passivation layer (Passivation, PVX), a pixel electrode (PXL ITO) and a common electrode (Com ITO); the mechanism by which the thickness of the passivation layer affects the on-state current of the product may include: when a positive voltage is applied to the gate, generally 15V, and a voltage is applied to the source and drain electrodes, generally 15V, the transistor device is in the on state, the current in the transistor is the on-state current, the pixel electrode obtains an electrical signal, and begins to charge the pixel storage capacitor. Due to the potential difference between the source and drain, the surface of the passivation layer is induced with charge, that is, a top-gate transistor device is formed, the induced charge acts as the gate, and the passivation layer acts as the gate insulation layer; when the bottom-gate / top-gate transistor devices are turned on at the same time, it is equivalent to applying two electric fields to the active layer at the same time, and the energy band of the active layer is effectively reduced, so that the gate insulation layer / active layer and active layer / passivation layer interface electrons are filled more quickly to achieve conduction, such as Figure 3 In addition, from the on-state current and capacitance formula, we know that: As the thickness of the passivation layer increases (d), the capacitance per unit area decreases (C), and the electron concentration at the active layer / passivation layer interface decreases, which reduces the on-state current of the top-gate transistor device. That is, for high-refresh products or products with high charging rate requirements, increasing the thickness of the passivation layer can reduce the pixel capacitance, but it cannot take into account the higher on-state current.

[0060] In view of this, see FIG. 4A to FIG. 4E , Figure 5 , Figure 6 As shown, Figure 4B for Figure 4A Schematic diagram of the film layer of the common electrode layer, Figure 4C for Figure 4A Schematic diagram of the film layer of the middle gate line layer. Figure 4D for Figure 4ASchematic diagram of the film layer of the data line layer. Figure 4E for Figure 4A Schematic diagram of a single film layer of the pixel electrode layer. Figure 5 for Figure 4A Schematic diagram of the cross section along the dotted line e1, Figure 6 for Figure 4A , a cross-sectional schematic diagram along the dotted line e2 in FIG. 1 , an embodiment of the present invention provides an array substrate, comprising: a first substrate 11, a transistor T located on one side of the first substrate 11, and a first electrode 12; wherein the transistor T comprises: a first gate TA, a source TB and a drain TC located on a side of the first gate TA away from the first substrate 11;

[0061] The first electrode 12 is located on the side of the source TB away from the first substrate 11, and the first electrode 12 covers at least part of the positive projection of the source TB on the first substrate 11, and covers at least part of the positive projection of the drain 12 on the first substrate 11, and the first electrode 12 is insulated from the first gate TA.

[0062] In the embodiment of the present invention, the array substrate further includes a first electrode 12, the first electrode 12 is located on the side of the source electrode TB away from the first substrate 11, and the orthographic projection of the first electrode 12 on the first substrate 11 covers at least part of the orthographic projection of the source electrode TB on the first substrate 11, and covers at least part of the orthographic projection of the drain electrode TC on the first substrate 11, so that the first electrode 12 can be formed as the top gate of the transistor T, so that the transistor T has a double-gate structure. Since the orthographic projection of the first electrode 12 partially or completely overlaps with the orthographic projection of the source electrode TB and / or the drain electrode TC, the edge electric field can be enhanced, so that the lateral electric field strength The degree is enhanced, which is beneficial to increase the carrier concentration of the active layer, thereby increasing the on-state current; in addition, the orthographic projection of the first electrode 12 partially or completely overlaps with the orthographic projection of the source TB and / or the drain TC. Due to the presence of the first electrode 12 above the channel, the channel can be protected from the influence of the external environment, and the risk of external water vapor penetrating from the passivation layer into the channel to corrode the active layer channel is isolated; moreover, the first electrode 12 is insulated from the first gate TA, that is, the voltage of the first electrode 12 as the top gate can be flexibly adjusted to obtain the required on-state current, realize the digital on-state current, and meet the charging rate of broadband products.

[0063] In one possible implementation, see Figure 4A-4E , Figure 5 , Figure 6As shown, the array substrate further includes: a common electrode layer located on one side of the first substrate 11, a plurality of gate lines 14 located on a side of the common electrode layer away from the first substrate 11 and extending along a first direction X, a gate insulating layer 141 located on a layer of the gate line 14 away from the common electrode layer, an active layer and a data line layer located on a side of the gate insulating layer 141 away from the gate line 14 (the data line layer may include a plurality of data lines 15 extending along a second direction Y), a passivation layer 142 located on a side of the data line 15 away from the active layer, and a pixel electrode 13 located on a side of the passivation layer 142 away from the data line 15; wherein,

[0064] The common electrode layer may include: a plurality of common electrode strips 16 extending along the first direction X, and a first auxiliary wiring 162; wherein the common electrode strips 16 may include: a plurality of common electrode blocks 160 arranged along one side of the first direction X, and a second auxiliary wiring 161 located at one end of the common electrode block 160 and connecting the common electrode blocks 160;

[0065] The layer where the gate line 14 is located may further include: a plurality of first common wirings 141 extending along the first direction X; wherein the orthographic projection of the gate line 14 on the first substrate 11 may coincide with the first auxiliary wiring 162; the orthographic projection of the first common wiring 141 on the first substrate 11 may coincide with the second auxiliary wiring 161; the layer where the gate line 14 is located may be in direct contact with the common electrode layer, and no insulating layer may be provided between the two, and may be formed by a mask process, thereby saving the manufacturing cost of the array substrate; the first common wiring 141 may form at least part of the pixel storage capacitor with the pixel electrode 13;

[0066] The active layer and the layer where the data line is located may be in direct contact, and an insulating layer may not be provided between the two, and they may be formed by a mask process, thereby saving the manufacturing cost of the array substrate; the film layer patterns of at least some regions of the two are the same; the active layer may include: a transistor active pattern TD0, a first active pattern TD1, and a second active pattern TD2; the layer where the data line 15 is located may include: a source electrode TB, a drain electrode TC, and a switching electrode 151; the switching electrode 151 may be used to conduct two adjacent rows of common electrodes 16;

[0067] The layer where the pixel electrode 13 is located may also have a lap electrode 131 , and the orthographic projection of the lap electrode 131 on the first substrate 11 may overlap with the orthographic projection of the switching electrode 151 on the first substrate 11 . The lap electrode 131 and the switching electrode 151 together connect two adjacent rows of common electrodes 16 .

[0068] In one possible implementation, see Figure 4A-4E , Figure 5 , Figure 6As shown, the first electrode 12 and the pixel electrode 13 are in the same layer and material, and the first electrode 12 and the pixel electrode 13 are connected as one body. In the embodiment of the present invention, the first electrode 12 and the pixel electrode 13 are connected as one body, so that the voltage of the first electrode 12 as the top gate can change with the pixel voltage, or the top gate voltage can be changed by adjusting the pixel voltage to obtain the required on-state current; and the first electrode 12 can be formed at the same time as the pixel electrode 13 is formed, without increasing the process cost.

[0069] In one possible implementation, see Figure 4E As shown, the first electrode 12 includes: a first electrode portion 121 and a second electrode portion 122 arranged along a second direction Y; the second direction Y is perpendicular to the first direction X; see Figure 6 As shown, the passivation layer 142 has a first via hole K1 exposing a portion of the drain electrode TC; the first electrode portion 121 covers the first via hole K1 and overlaps the drain electrode TC; Figure 4A As shown, the second electrode portion 122 overlaps with the orthographic projection of the gate line 14 on the first substrate 11 .

[0070] In the embodiment of the present invention, the first electrode 12 includes: a first electrode portion 121 arranged along the second direction Y, and a second electrode portion 122, the first electrode portion 121 covers the first via K1 and overlaps with the drain TC; the second electrode portion 122 overlaps with the gate line 14 on the orthographic projection of the first substrate 11, and the first electrode 12 covers the channel region of the transistor T and forms the top gate of the transistor T by extending and covering the portion where the pixel electrode 13 overlaps with the drain TC; moreover, the integrated connection between the first electrode 12 and the pixel electrode 13 can optimize the number of vias of the array substrate without the need to add additional deep holes (such as deep holes formed by etching from the passivation layer to the gate insulating layer and then etching to the gate scanning line), thereby avoiding via-type defects.

[0071] In a possible implementation, the first electrode 12 may be in a block shape, a strip shape, or have a hollow structure.

[0072] In one possible implementation, see Figure 6 As shown, the array substrate further includes: a first active pattern TD1 located on the side of the drain electrode TC facing the first substrate 11 and contacting the drain electrode TC; the first active pattern TD1 has a first active portion TD11 overlapping the drain electrode TC, and a second active portion TD12 extending from the first active portion TD11;

[0073] The first via K1 exposes a portion of the drain electrode TC away from the surface of one side of the first substrate 11, a side of the drain electrode TC, a portion of the second active portion TD12 away from the surface of one side of the first substrate 11, and a portion of the side of the second active portion TD12, and exposes a portion of the passivation layer 142 adjacent to the second active portion TD12, so that a gap J is formed between the exposed side of the second active portion TD12 and the side of the passivation layer 142 facing the second active portion TD12.

[0074] In the embodiment of the present invention, the first via hole K1 exposes a portion of the surface of the drain electrode TC away from the side of the first substrate 11, a side of the drain electrode TC, a portion of the surface of the second active portion TD12 away from the side of the first substrate 11, and a portion of the side of the second active portion TD12. That is, the first via hole K1 is a shallow hole, which can avoid the difficulty in etching and forming a deep hole and the risk of poor contact that may exist in the deep hole.

[0075] In one possible implementation, see Figure 6 As shown, the maximum depth d1 of the first via hole K1 is less than the maximum thickness d2 of the passivation layer 142. In the embodiment of the present invention, the first via hole K1 only etches a portion of the passivation layer 142, which can reduce channel water stains or stripping solution residues and improve via hole corrosion defects.

[0076] In one possible implementation, combining Figure 4A and Figure 4D As shown, the source TB includes: a source main portion TB0, and a first source branch TB1 and a second source branch TB2 extending from the source main portion TB0 along the second direction Y; the second electrode portion 122 covers the first source branch TB1, the second source branch TB2, and the area between the first source branch TB1 and the second source branch TB2 in the orthographic projection of the first substrate 11.

[0077] In one possible implementation, combining Figure 7A-7E , Figure 8 and Fig. 9 As shown, Figure 7B for Fig. 7A Schematic diagram of a single film layer where the pixel electrode is located. Figure 8 for Fig. 7A Schematic diagram of the cross section at the dotted line e1, Fig. 9 for Fig. 7A In the cross-sectional diagram at the dotted line e2, the array substrate further includes: a pixel electrode 13; a first electrode 12 and the pixel electrode 13 are made of the same layer and material, and the first electrode 12 and the pixel electrode 13 are insulated from each other. In the embodiment of the present invention, the first electrode 12 and the pixel electrode 13 are made of the same layer and material, and the first electrode 12 can be formed at the same time as the pixel electrode 13 is formed, without increasing the process cost.

[0078] In one possible implementation, combining Figure 7A-7E , Figure 8 and Fig. 9 As shown, the first electrode 12 includes: a third electrode portion 123, a fourth electrode portion 124, and a fifth electrode portion 125 extending along a third direction Z and connecting the third electrode portion 123 and the fourth electrode portion 124; the third direction Z intersects with both the first direction X and the second direction Y; the third electrode portion 123 and the pixel electrode 13 are located on the same side of the gate line 14; the orthographic projection of the fourth electrode portion 124 on the first substrate 11 overlaps with the orthographic projection of the gate line 14 on the first substrate 11.

[0079] It should be noted that the third electrode portion 123 and the pixel electrode 13 are located on the same side of the gate line 14 , and may be in the same pixel region. The third electrode portion 123 and the pixel electrode 13 are located on the same side of the gate line 14 .

[0080] In one possible implementation, combining Figure 7A-7E , Figure 8 and Fig. 9 As shown, the array substrate further includes: a transfer electrode 151 located at the layer where the drain electrode TC is located, a second active pattern TD2 located at the side of the transfer electrode 151 facing the first substrate 11 and in contact with the transfer electrode 151, a gate insulating layer 141 located at the side of the second active pattern TD2 facing the first substrate 11, a common electrode layer located at the side of the gate insulating layer 141 facing the first substrate 11, and a second via K2 penetrating the passivation layer 142 and the gate insulating layer 141; the second active pattern TD2 has a third active portion TD21 overlapping with the transfer electrode 151, and a fourth active portion TD22 extended from the third active portion TD21; the common electrode layer includes: a plurality of common electrode strips 16 extending along the first direction X;

[0081] The second via hole K2 exposes a portion of the surface of the transfer electrode 151 that is away from one side of the first substrate 11, a side surface of the transfer electrode 151, a portion of the surface of the fourth active portion TD22 that is away from one side of the first substrate 11 and a portion of the side surface of the fourth active portion TD22, as well as a portion of the surface of the common electrode strip 16 that is away from one side of the first substrate 11; the third electrode portion 123 covers the second via hole K2 and overlaps at least the transfer electrode 151 and the common electrode strip 16.

[0082] In the embodiment of the present invention, the first electrode 12 is overlapped with the common electrode strip 16 through the third electrode portion 123, so that the voltage of the first electrode 12 serving as the top gate can change with the common voltage, or the required on-state current can be obtained by adjusting the common voltage to change the top gate voltage; and when the first electrode 12 is electrically connected to the common electrode 16, the second via K2 when two adjacent rows of common electrodes 16 are electrically connected is reused, so the number of vias of the array substrate can be optimized, and there is no need to add additional deep holes (such as deep holes formed by first etching from the passivation layer to the gate insulating layer and then etching to the gate scanning line), thereby avoiding via-type defects.

[0083] In one possible implementation, combining Figure 7A-7E , Figure 8 and Fig. 9 As shown, the source TB includes: a source main portion TB0, and a first source branch TB2 and a second source branch TB2 extending from the source main portion TB0 along the second direction Y; the fourth electrode portion 124 covers the first source branch TB1, the second source branch TB2, and the area between the first source branch TB1 and the second source branch TB2 in the orthographic projection of the first substrate 11.

[0084] In one possible implementation, combining Fig. 7A As shown, the switching electrode 151 and the first electrode 12 may be set at only some of the sub-pixels. For example, the switching electrode 151 and the first electrode 12 may be set at one of the sub-pixels in each pixel (a pixel may include three sub-pixels), and the switching electrode 151 and the first electrode 12 may not be set at the remaining two sub-pixels. In another possible implementation, the switching electrode 151 and the first electrode 12 may also be set at each sub-pixel.

[0085] In one possible implementation, combining Figure 5 and Figure 8 As shown, the passivation layer 142 also has a first groove Q which is recessed toward the first substrate 11 from the surface on the side facing away from the first substrate 11; the first groove Q is an orthographic projection of the first substrate 11, covering at least a portion of the orthographic projection of the source TB on the first substrate 11, and covering at least a portion of the orthographic projection of the drain TC on the first substrate 11.

[0086] In the embodiment of the present invention, the first groove Q is an orthographic projection of the first substrate 11, covering at least a portion of the orthographic projection of the source TB on the first substrate 11, and covering at least a portion of the orthographic projection of the drain TC on the first substrate 11, that is, a portion of the passivation layer 141 at the position of the transistor T is removed, thereby reducing the thickness of the passivation layer 141 at the top of the transistor T, while retaining the film thickness of the passivation layer 141 in the pixel area, thereby taking into account the technical problems of increasing the on-state current of the transistor T and reducing the pixel storage capacitance (the capacitance formed by the pixel electrode and the common wiring).

[0087] In a possible implementation, the size of the first groove Q can be determined based on the gate size and the transistor T size of the actual display product. For example, the orthographic projection of the first groove Q on the first substrate 11 can coincide with the orthographic projection of the overlapping area formed by the gate line 14 and the transistor T. Optionally, the length of the first groove Q in the first direction X can range from 14 microns to 17 microns, and the length of the first groove Q in the second direction Y can range from 35 microns to 50 microns.

[0088] In a possible embodiment, in a direction perpendicular to the first substrate 11, the depth d2 of the first groove Q may be in a range of 0.5 microns to 2 microns; in a possible embodiment, the top passivation layer 141 at the position of the transistor T is partially etched and partially retained, and the thickness d3 of the retained passivation layer 141 may be in a range of 500 angstroms to 1000 angstroms to ensure that there is still an insulating layer between the source TB (and / or the drain TC) and the first electrode 12.

[0089] In one possible implementation, combining Figure 5 As shown, the second electrode 122 is partially located in the first groove Q; in a possible implementation, combined with Figure 8 As shown, the second electrode 122 (or the fourth electrode portion 124) is located in the first groove Q. In the embodiment of the present invention, the second electrode 122 (or the fourth electrode portion 124) is located in the first groove Q, and the first groove Q is an orthographic projection of the first substrate 11, covering at least a portion of the orthographic projection of the source TB on the first substrate 11, and covering at least a portion of the orthographic projection of the drain TC on the first substrate 11, that is, the lateral electric field strength between the second electrode 122 (or the fourth electrode portion 124) and the source TB (and / or the drain TC) can be enhanced, which is beneficial to increase the carrier concentration of the active layer of the transistor, thereby increasing the on-state current; and, due to the presence of the second electrode 122 (or the fourth electrode portion 124) above the channel, the channel is protected from the influence of the external environment, isolating the risk of external water vapor penetrating from the passivation layer to the channel corrosion.

[0090] Based on the same inventive concept, see Fig.10 As shown, an embodiment of the present invention further provides a display panel, comprising the array substrate 1 provided in the embodiment of the present invention, and further comprising an opposite substrate 2 arranged opposite to the array substrate 1 .

[0091] In one possible implementation, see Fig.10As shown, the array substrate has a first groove Q; the opposing substrate 2 includes: a second substrate 21, and a spacer PS located on the side of the second substrate 21 facing the array substrate 1, the orthographic projection of the spacer PS on the first substrate 11 overlaps with the orthographic projection of the first groove Q on the first substrate; the surface of the spacer PS on the side facing the array substrate 1 is covered with a conductive part 22; the conductive part 22 is in contact with the first electrode 12.

[0092] In the embodiment of the present invention, the opposing substrate 2 includes a conductive portion 22 covering the surface of the spacer PS; the conductive portion 22 is in contact with the first electrode 12, that is, a layer of conductive film (as the conductive portion 22) is sputtered on the surface of the spacer PS of the opposing substrate 2. When the array substrate 1 and the opposing substrate 2 are assembled, the conductive portion 22 on the surface of the spacer PS is in contact with the first electrode 12 above the transistor T of the array substrate 1 to form conduction, that is, the voltage of the top gate (first electrode 12) of the transistor T is flexibly adjusted through the conductive portion 22 of the opposing substrate 2 to obtain the required on-state current.

[0093] In the embodiment of the present invention, the top gate first electrode 12 of the transistor T can have many beneficial effects, including: ① The number of vias can be optimized, and there is no need to add additional deep holes or shallow holes to conduct with the bottom gate, thereby avoiding via-type defects; ② Intelligent top gate, since the top gate is not connected to the bottom gate, the top gate is connected to the conductive portion 22 of the opposite substrate 2, and the voltage can be flexibly adjusted to obtain the required on-state current, realize digital on-state current, and meet the charging rate of broadband products; ③ Edge electric field enhancement, since the top gate fully overlaps or partially overlaps with the source / drain, the lateral electric field strength is enhanced, which is beneficial to increase the carrier concentration of the active layer, thereby increasing the on-state current; ④ Protect the channel from the influence of the external environment, because the channel The presence of the first electrode 12 on the top isolates the risk of external moisture penetrating from the passivation layer to the channel corrosion; ⑤ Improvement of alignment film scratches. In the original design, the spacer PS is on the surface of the passivation layer 142. When the display panel surface is pressed, the spacer PS will be displaced, scratching the alignment film layer, resulting in poor bright spots. However, due to the design of the first groove Q in the present invention, the displacement range of the spacer PS is within the first groove Q, that is, the first groove Q design can clamp the spacer PS inside the first groove Q to avoid scratches on the alignment film. At the same time, the first groove Q design provides a reference for the alignment of the array substrate 1 and the opposing substrate 2, thereby improving the box alignment accuracy, thereby avoiding poor screen light leakage due to alignment accuracy.

[0094] In one possible implementation, combining Fig.10 As shown, on the array substrate 1 side, the first electrode 12 can be in an isolated state, and the first electrode 12 can be flexibly adjusted by the conductive portion 22 of the opposite substrate 2 .

[0095] For example, in one possible implementation, see Fig.12As shown, the conductive part 22 is a whole layer of transparent planar electrode, and a dynamic voltage can be provided by an external driving circuit to charge the conductive part 22 and act as a top gate signal to control the top gate voltage of the transistor T on the array substrate 1 side.

[0096] For example, in one possible implementation, see Fig.10 and Fig.11 As shown, the counter substrate 2 further includes: a black matrix layer BM located on the side of the spacer PS facing the second substrate 21; the black matrix layer BM includes: a plurality of first sub-black matrix parts BM1 extending along the first direction X, and a plurality of second sub-black matrix parts BM2 extending along the second direction Y; the conductive part 22 includes: a plurality of first sub-conductive parts 221 extending along the first direction X, and a plurality of second sub-conductive parts 222 extending along the second direction Y; the orthographic projection of the first sub-black matrix part BM on the second substrate 21 covers the orthographic projection of the first sub-conductive part 221 on the second substrate 21; the orthographic projection of the second sub-black matrix part BM on the second substrate 21 covers the orthographic projection of the second sub-conductive part 222 on the second substrate 21. The first sub-conductive part 221 and the second sub-conductive part 222 cross to form a mesh structure, and the meshed first sub-conductive part 221 and the second sub-conductive part 222 are charged by providing a dynamic voltage through an external driving circuit, acting as a top gate signal, so as to realize the control of the top gate voltage of the transistor T on the array substrate 1 side.

[0097] In a possible implementation, for Fig.10 , Fig.11 The material of the conductive part 22 of the corresponding array substrate includes: transparent metal oxide or metal. The transparent metal oxide may be, for example, indium tin oxide.

[0098] In a possible implementation, the voltage applied to the conductive portion 22 of the substrate 2 may be different from the common voltage applied to the common electrode 16 in the array substrate 1. In another possible implementation, the voltage applied to the conductive portion 22 of the substrate 2 may be the same as the common voltage applied to the common electrode 16 in the array substrate 1.

[0099] In one possible implementation, combining Fig.10 As shown, the opposite substrate 2 may further include: a color resist layer located between the spacer PS and the black matrix BM, and the color resist layer may include: a red color resist R, a green color resist, and a blue color resist.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including a display panel provided by an embodiment of the present invention. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0101] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0102] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0103] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: include: A first substrate, a transistor located on one side of the first substrate, and a first electrode; wherein the transistor comprises: a first gate, a source and a drain located on a side of the first gate away from the first substrate; The first electrode is located on the side of the source away from the first substrate, and the first electrode's projection on the first substrate covers at least part of the source's projection on the first substrate and covers at least part of the drain's projection on the first substrate, and the first electrode is insulated from the first gate.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: a pixel electrode; the first electrode and the pixel electrode are made of the same layer and material, and the first electrode and the pixel electrode are integrally connected.

3. The array substrate according to claim 2, characterized in that: The array substrate comprises: a plurality of gate lines extending along a first direction; the first electrode comprises: a first electrode portion and a second electrode portion arranged along a second direction; the second direction is perpendicular to the first direction; The array substrate comprises: a passivation layer located between a layer where the pixel electrode is located and a layer where the drain electrode is located; the passivation layer has a first via hole exposing a portion of the drain electrode; The first electrode portion covers the first via hole and overlaps with the drain electrode; the second electrode portion overlaps with the orthographic projection of the gate line on the first substrate.

4. The array substrate according to claim 3, characterized in that: The array substrate further comprises: a first active pattern located on a side of the drain electrode facing the first substrate and in contact with the drain electrode; the first active pattern comprises a first active portion overlapping the drain electrode, and a second active portion extending from the first active portion; The first via hole exposes a portion of the drain electrode away from a surface of one side of the first substrate, a side surface of the drain electrode, a portion of the second active portion away from a surface of one side of the first substrate, and a portion of the side surface of the second active portion, and exposes a portion of the passivation layer adjacent to the second active portion.

5. The array substrate according to claim 3, characterized in that: The source includes: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion along a second direction; An orthographic projection of the second electrode portion on the first substrate covers the first source branch, the second source branch, and an area between the first source branch and the second source branch.

6. The array substrate according to claim 3, characterized in that: The maximum depth of the first via hole is less than the maximum thickness of the passivation layer.

7. The array substrate according to claim 1, wherein: The array substrate further includes: a pixel electrode; the first electrode and the pixel electrode are made of the same layer and the same material, and the first electrode and the pixel electrode are insulated from each other.

8. The array substrate according to claim 7, characterized in that: The array substrate comprises: a plurality of gate lines extending along a first direction; the first electrode comprises: a third electrode portion, a fourth electrode portion, and a fifth electrode portion extending along a third direction and connecting the third electrode portion and the fourth electrode portion; the third direction intersects both the first direction and the second direction; The third electrode portion and the pixel electrode are located on the same side of the gate line; the orthographic projection of the fourth electrode portion on the first substrate overlaps with the orthographic projection of the gate line on the first substrate.

9. The array substrate according to claim 8, characterized in that: The array substrate further comprises: a passivation layer located between the layer where the pixel electrode is located and the layer where the drain electrode is located, a switching electrode located at the layer where the drain electrode is located, a second active pattern located at a side of the switching electrode facing the first substrate and in contact with the switching electrode, a gate insulating layer located at a side of the second active pattern facing the first substrate, a common electrode layer located at a side of the gate insulating layer facing the first substrate, and a second via hole penetrating the passivation layer and the gate insulating layer; the second active pattern comprises a third active portion overlapping the switching electrode, and a fourth active portion extending from the third active portion; the common electrode layer comprises: a plurality of common electrode strips extending along the first direction; The second via hole exposes a portion of the transfer electrode facing away from a surface of one side of the first substrate, a side surface of the transfer electrode, a portion of the fourth active portion facing away from a surface of one side of the first substrate and a portion of the side surface of the fourth active portion, and a portion of the common electrode strip facing away from a surface of one side of the first substrate; the third electrode portion covers the second via hole and overlaps at least the transfer electrode and the common electrode strip.

10. The array substrate according to claim 8, characterized in that: The source includes: a source main portion, and a first source branch portion and a second source branch portion extending from the source main portion along a second direction; The orthographic projection of the fourth electrode portion on the first substrate covers the first source branch, the second source branch, and an area between the first source branch and the second source branch.

11. The array substrate according to claim 3 or 9, characterized in that: The passivation layer also has a first groove which is recessed from the surface away from the first substrate side toward the first substrate side; the first groove is an orthographic projection of the first substrate, covering at least part of the orthographic projection of the source electrode on the first substrate, and covering at least part of the orthographic projection of the drain electrode on the first substrate.

12. The array substrate according to claim 11, characterized in that: The second electrode portion is located in the first groove; or the fourth electrode portion is located in the first groove.

13. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 12, and also comprises an opposite substrate arranged opposite to the array substrate.

14. The display panel according to claim 13, wherein: The array substrate has a first groove; the opposing substrate includes: a second substrate, and a spacer located on the side of the second substrate facing the array substrate, the orthographic projection of the spacer on the first substrate overlaps with the orthographic projection of the first groove on the first substrate; the surface of the spacer facing the array substrate is covered with a conductive part; the conductive part is in contact with the first electrode.

15. The display panel according to claim 14, wherein: The conductive part is a whole layer of transparent planar electrode.

16. The display panel according to claim 14, wherein: The counter substrate further comprises: a black matrix layer located on the side of the spacer facing the second substrate; the black matrix layer comprises: a plurality of first sub-black matrix portions extending along the first direction, and a plurality of second sub-black matrix portions extending along the second direction; The conductive part includes: a plurality of first sub-conductive parts extending along the first direction, and a plurality of second sub-conductive parts extending along the second direction; the orthographic projection of the first sub-black matrix part on the second substrate covers the orthographic projection of the first sub-conductive part on the second substrate; the orthographic projection of the second sub-black matrix part on the second substrate covers the orthographic projection of the second sub-conductive part on the second substrate.

17. The display panel according to claim 16, wherein: The material of the conductive part includes: transparent metal oxide or metal.

18. The display panel according to claim 14, wherein: The array substrate further includes: a common electrode layer; the voltage loaded on the conductive part is different from the voltage loaded on the common electrode layer; or the voltage loaded on the conductive part is the same as the voltage loaded on the common electrode layer.

19. A display device, characterized in that: Comprising a display panel as described in any one of claims 13-18.

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