Wire harness layout optimization method based on 3D simulation

Abstract

The present invention discloses a wiring harness layout optimization method based on three-dimensional simulation. The present invention relates to the technical field of wiring harness layout optimization and solves the technical problem of unreasonable layout caused by not comprehensively considering the interference problem between wiring harness layouts due to multiple factors. The present invention constructs a model and defines wiring harness specification parameters through three-dimensional modeling software, and judges whether there is spatial interference in the preliminary planned route based on the model and the electrical schematic diagram. If interference exists, the interference area and cause are analyzed and obtained, the number of causes is judged, and a single or multiple types of cause signals are generated. For a single cause signal, information is obtained to generate optimization information. For multiple types of cause signals, it is judged whether there is cause interaction, and optimization information is generated if there is, and path analysis signals are generated if there is no cause interaction. The path analysis signals are analyzed to obtain all planned routes, calculate the planning priority value of each path, and generate optimization information based on the maximum planning priority value. The problem is properly solved through system analysis, reducing design changes and cost increases.

Description

Technical Field

[0001] The present invention relates to the technical field of wiring harness layout optimization, in particular to a wiring harness layout optimization method based on three-dimensional simulation. Background Art

[0002] With the widespread use of electronic devices and electrical systems in various products, the rationality of the wiring harness layout, as a key component connecting various electrical components, has become crucial. Traditional wiring harness layout design often relies on manual experience, and in complex physical spaces, it is difficult to fully consider multiple factors such as space utilization, electrical performance, and assembly process. With the trend of product miniaturization and integration, more wiring harnesses need to be arranged within limited physical space. Manual design can easily lead to interference between wiring harnesses and between wiring harnesses and other components, affecting product performance and reliability.

[0003] When using some existing wiring harness layout optimization methods, manual design can easily lead to interference between wiring harnesses and between wiring harnesses and other components, affecting product performance and reliability. Furthermore, as electrical systems become more complex and performance requirements become more stringent, manual design can make it difficult to accurately ensure that parameters such as resistance, capacitance, and inductance meet design standards. Furthermore, manually designed wiring harness layouts can cause numerous inconveniences during assembly, reducing efficiency and increasing costs. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the present invention provides a wiring harness layout optimization method based on three-dimensional simulation, which solves the problem of unreasonable layout caused by not comprehensively considering the interference between wiring harness layouts due to multiple factors.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: Based on a three-dimensional simulation wiring harness layout optimization method, the method specifically includes the following steps:

[0006] Determine the physical space and create a 3D model of the physical space using 3D modeling software, while defining the specifications of the wiring harness;

[0007] Obtaining a preliminary planned route based on the three-dimensional model and in combination with the electrical system schematic diagram of the physical space, determining whether there is spatial interference on the preliminary planned route, and generating a determination result, including a determination of whether there is interference or not;

[0008] Analyze the generated interference results, obtain the interference area and its interference causes, determine the number of interference causes, generate a single cause signal or multiple types of cause signals, analyze the generated single cause signal, obtain the corresponding single cause information, and generate corresponding optimization information based on the single cause information;

[0009] Analyze the generated multi-type cause signals, obtain the corresponding multi-type cause information, and determine whether there is cause interaction in the multi-type cause information. If so, generate the corresponding optimization information based on the multi-type cause information; otherwise, generate a path analysis signal;

[0010] Analyze the generated path analysis signal to obtain all planned routes, calculate the space utilization value based on the effective occupied space volume of the planned path, analyze the required number of resistors, capacitors, and inductors to calculate the parameter ratio, assign the operation convenience to obtain the assembly process value, and calculate the planning priority value of the planned path;

[0011] According to the interference situation of the planned paths, interference paths and non-interference paths are obtained, and the interference paths corresponding to the interference reasons less than the preset value are selected as the paths to be analyzed. At the same time, the maximum planning priority value among the paths to be analyzed and the non-interference paths is selected as the standard to generate optimization information.

[0012] As a further solution of the present invention, the specific method of generating the judgment result is:

[0013] Based on the obtained three-dimensional model, a preliminary planned route is obtained in combination with the electrical system schematic diagram of the physical space, and it is determined whether there is spatial interference in the preliminary planned route. The preliminary planned route and the physical space are obtained, and the models of the wiring harness and surrounding components in the preliminary planned route are checked. If there is interference between the wiring harness and other objects, an interference result is generated. Conversely, if there is no interference between the wiring harness and other objects, a non-interference result is generated.

[0014] As a further solution of the present invention, the specific method of analyzing the generated interference results and generating corresponding optimization information based on single cause information is as follows:

[0015] Obtain the corresponding interference areas and their corresponding interference causes in the preliminary planned path, determine the number of interference causes, generate a single cause signal or multiple types of cause signals, and analyze both;

[0016] Analyze the generated single cause signal to obtain corresponding single cause information, and generate corresponding optimization information based on the single cause information;

[0017] As a further solution of the present invention, the specific method of analyzing the generated multi-type cause signals is:

[0018] Obtain the corresponding multi-type cause information, and then determine whether there is any cause interaction in the multi-type cause information. If so, generate the corresponding optimization information based on the multi-type cause information. Otherwise, re-plan and analyze the preliminary planned path and generate a path analysis signal.

[0019] As a further solution of the present invention, the specific method of calculating the space utilization value based on the effective occupied space volume of the planned path is:

[0020] Get the volume Vz of the physical space, and get the effective occupied space volume Vi corresponding to the planned path i, and according to the formula Calculate the space utilization rate corresponding to the planned path i, and then quantify the space utilization rate to obtain the corresponding space utilization value.

[0021] As a further solution of the present invention, the specific method of analyzing and calculating the parameter ratio values of the satisfied quantities of resistors, capacitors, and inductors is as follows:

[0022] According to the formula Calculate the resistance R corresponding to the planned path i, where l is the length of the planned path and S is the cross-sectional area of the harness. is the resistivity;

[0023] According to the formula Calculate the capacitance C corresponding to the planned path i, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates;

[0024] According to the formula Calculate the inductance L corresponding to the planned path i, where Magnetic permeability, l is the length of the wire, D is the distance between the two wires, and r is the radius of the wire;

[0025] The obtained resistance, capacitance, and inductance are compared with the corresponding design standards respectively, and the number of parameters that meet the design standards is determined. At the same time, the corresponding parameter proportion values are calculated and recorded as electrical performance values.

[0026] As a further solution of the present invention, the specific method of calculating the planning priority value of the planned path is:

[0027] According to the formula The planning priority value Q corresponding to the planned path is calculated, where K is the space utilization value, H is the electrical performance value, and A is the assembly process value. 、 and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1;

[0028] Similarly, the planning priority value Q of all planned paths i is calculated and recorded as Qi.

[0029] As a further solution of the present invention, the specific method of selecting the maximum planning priority value in the path to be analyzed and the non-interference path as the standard to generate the optimization information is:

[0030] The interference path after classification is obtained and recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference path corresponding to the interference cause less than the preset value is screened and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two to generate optimization information.

[0031] The present invention provides a wiring harness layout optimization method based on three-dimensional simulation. Compared with the existing technology, it has the following advantages:

[0032] By leveraging specialized 3D modeling and analysis tools, this invention comprehensively and meticulously examines interference between the wiring harness and surrounding component models within the initially planned route. This improves the accuracy and efficiency of interference detection compared to traditional manual analysis. Where interference exists, systematic analysis of the interference area and causes allows for targeted and effective optimization measures. Whether interference is caused by a single or multiple factors, these issues can be addressed, minimizing design changes and cost increases associated with interference.

[0033] In-depth analysis of the planned path's electrical performance, calculating parameters like resistance, capacitance, and inductance using precise formulas and rigorously comparing them to design standards, can proactively identify potential electrical issues and ensure stable electrical system operation. This quantitative analysis, compared to traditional empirical judgment, can more accurately meet electrical performance requirements and improve product electrical reliability.

[0034] From the perspective of operational convenience, the assembly processability of the planned path is quantified based on the volume of the operating space, making the evaluation of the assembly process more scientific and objective. Designing the wiring harness layout in this way can improve assembly efficiency, reduce assembly difficulty, and minimize manual errors, thereby reducing production costs.

[0035] A mathematical model was established that comprehensively considers space utilization, electrical performance, and assembly process values. Multiple planned paths were sorted and screened by calculating planning priority values. This multi-factor approach optimizes the overall wiring harness layout, selecting the optimal path that strikes a balance between space utilization, electrical performance, and assembly process, ultimately improving overall product performance and quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a diagram of the steps of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] For example 1, please refer to Figure 1 , the present application provides a wiring harness layout optimization method based on three-dimensional simulation, the method specifically comprising the following steps:

[0039] Step S1: First, determine the scope of the physical space and create a three-dimensional model of the entire physical space. The model is created here through professional three-dimensional modeling software such as CATIA, UG, SolidWorks, etc., and the specification parameters of the wire harness are defined. The specification parameters here include the diameter, quantity, material of the wire, thickness and characteristics of the insulation layer, etc.

[0040] Step S2: Based on the constructed accurate 3D model, closely associate it with the electrical system schematic diagram in the physical space to obtain a preliminary planned route. During this process, it is necessary to rigorously judge whether there is any spatial interference in the preliminary planned route and generate a corresponding accurate judgment result. The judgment result is clearly divided into two categories: interference results and no interference results. The specific judgment method is as follows:

[0041] Comprehensively obtain information about the preliminary planned route and the physical space in which it is located, and use professional three-dimensional analysis tools to conduct meticulous inspections on the models of the wiring harness and surrounding components in the preliminary planned route. Taking the automobile wiring harness layout as an example, in the three-dimensional model of the automobile engine compartment, the preliminary planned wiring harness is connected from the battery to various electrical devices, such as the engine control unit, headlights, etc. When the planned route is checked for interference, if it is found that the wiring harness and a protruding component of the engine, such as the intake manifold, overlap in spatial position, it indicates that there is interference between the wiring harness and other objects. At this time, an interference result should be generated immediately. On the contrary, if after a full inspection, the wiring harness and all components in the engine compartment, including the engine body, radiator, various pipelines, etc., maintain a safe distance in spatial position and there is no overlapping part, then a non-interference result is generated, and the generated non-interference result is not processed.

[0042] Step S3: After the interference result is generated, a systematic and in-depth analysis is required. First, with the help of professional 3D model analysis software, the specific area where interference occurs in the preliminary planned path is accurately located. Taking the car engine compartment as an example, in this complex 3D space, if a section of the wiring harness connecting the battery to the engine control unit is found to be interfering, the spatial range where this section of the wiring harness is located is the interference area.

[0043] Next, a comprehensive investigation is conducted to determine the causes of interference in this interference area. These can be caused by a variety of factors, such as an unreasonable design of the wiring harness itself, which fails to effectively avoid surrounding components within a limited space; or because the actual installation position of some components in the engine compartment deviates from the original design, encroaching on the space originally planned for the wiring harness; or because the selected wiring harness is too thick, exceeding the capacity of the reserved space, etc. After identifying all the causes of interference, the number of causes is carefully counted. If only one cause causes interference, the system will generate a single cause signal;

[0044] If there are two or more different reasons for the interference, a multi-cause signal is generated. Afterwards, targeted analysis and optimized treatment measures are implemented for each of the two different types of signals.

[0045] When a single-cause signal is received, the signal is analyzed in depth to obtain accurate and detailed single-cause information. For example, in the wiring harness layout of the automobile engine compartment, the single-cause signal shows that the interference is caused by a certain section of the wiring harness running directly through the engine's intake manifold installation area.

[0046] Based on this single cause information, corresponding optimization information can be formulated, such as replanning the wiring harness path so that it is arranged along the wire trough or bracket at the edge of the engine compartment to avoid the intake manifold. If multiple cause signals are generated, further careful analysis is required to grasp comprehensive multiple cause information. Subsequently, it is determined whether there is cause interaction between these multiple cause information. The so-called cause interaction refers to the existence of intersection correlation between different interference causes.

[0047] For example, within a vehicle's engine compartment, analysis of multiple cause information reveals that, on the one hand, some wiring harnesses are concentrated in a confined space due to poor initial design. On the other hand, to meet the power requirements of newly added electronic equipment, thicker wiring harnesses were selected. These thicker wiring harnesses were concentrated in an area with poor initial design, resulting in significant space shortages and interference. This is an example of cause interaction. In this case, optimization information generated based on these multiple cause information may include rerouting the wiring harnesses to disperse the concentrated wiring harnesses, and re-evaluating the wiring harness specifications to select a more appropriate thickness to alleviate space pressure while still meeting electrical performance requirements. If the multiple cause information is determined to be non-interaction, for example, the interference may be caused by the addition of a large auxiliary cooling device in the engine compartment, which changes the original spatial layout, while another may be caused by the improperly designed location of several wiring harness anchor points, resulting in ineffective wiring harness retention during installation and increased risk of collision with surrounding components. However, these two causes are not directly related. At this point, it is necessary to comprehensively re-plan and analyze the entire preliminary planned path and generate a path analysis signal to provide a strong basis for the subsequent redesign of a more reasonable wiring harness layout solution that is more suitable for the current complex environment of the engine compartment.

[0048] Step S4: Analyze the generated path analysis signal, generate multiple groups of planned paths based on the physical space and in combination with the schematic diagram of the electrical system, and label them as i, where i=1, 2, ..., j, where j represents the number of planned routes. The generation method here divides the entire system into different functional areas according to the function and location of the electrical equipment. In each area, first preliminarily determine the basic path of the wiring harness from the power supply to each electrical device, and try to make the equipment connection lines in the same functional area relatively concentrated. Then, separately analyze the space utilization, electrical performance, and assembly processability corresponding to the planned route i;

[0049] The specific method of analyzing the space utilization of the planned path i is to obtain the spatial volume Vz of the physical space and the effective occupied space volume Vi corresponding to the planned path i. The effective occupied space volume is obtained through the specification parameters in the three-dimensional model and is calculated according to the formula Calculate the space utilization rate corresponding to the planned path i, and then quantify the space utilization rate to obtain the corresponding space utilization value. The quantization here specifically converts the obtained percentage into the corresponding numerical value. For example, if the calculated space utilization rate is 80%, the space utilization value after quantization is 0.8.

[0050] The specific method for analyzing the electrical performance of the planned path i is to calculate the resistance, capacitance and inductance corresponding to the planned path i respectively. The method for calculating the resistance is as follows: Calculate the resistance R corresponding to the planned path i, where l is the length of the planned path and S is the cross-sectional area of the harness. is the resistivity;

[0051] The way to calculate the capacitance is, according to the formula Calculate the capacitance C corresponding to the planned path i, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates;

[0052] The inductance is calculated according to the formula Calculate the inductance L corresponding to the planned path i, where Magnetic permeability, l is the length of the wire, D is the distance between the two wires, and r is the radius of the wire;

[0053] The obtained resistance, capacitance and inductance are compared with the corresponding design standards respectively, and the design standards here correspond to the resistance, capacitance and inductance, and the number of parameters that meet the design standards is determined, and the corresponding parameter proportion values are calculated at the same time, and the proportion values are recorded as electrical performance values, and the parameter proportion values here are specifically expressed as the proportion values of qualified parameters. For example, after comparison, if the resistance and capacitance are the same as the design standards, the parameter proportion obtained by further calculation is 2 / 3.

[0054] The specific method for analyzing the assembly processability of planned path i is to assign a value to the operational convenience of planned path i to obtain an assembly process value. The method for assigning the operational convenience is to obtain the corresponding operating space and perform a corresponding rating based on the volume of the operating space. The rating levels include narrow (operating space volume is less than 0.05 cubic meters), normal (operating space volume is between 0.05 cubic meters and 0.2 cubic meters), and wide (operating space volume is greater than 0.2 cubic meters), and the values are assigned to them as 1, 2, and 3, respectively.

[0055] Then substitute the obtained space utilization value, electrical performance value and assembly process value into the formula The planning priority value Q corresponding to the planned path is calculated, where K is the space utilization value of the planned path, H is the electrical performance value of the planned path, and A is the assembly process value of the planned path. 、 and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1, for example, the electrical performance weight is 0.4, the space utilization weight is 0.3, and the assembly process weight is 0.3. Similarly, the planning priority value Q of all planned paths i is calculated and recorded as Qi, and sorted from large to small according to the value; the specific planning priority value Q is between 0 and 1, and the closer the value is to 1, the more reasonable the planned path is.

[0056] Step S5: Obtain the sorted planned paths, perform interference analysis on the planned paths, classify them into interference paths and non-interference paths, and analyze the two paths comprehensively;

[0057] The interference path after classification is obtained and recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference paths corresponding to the interference cause less than the preset value are screened, and the specific value of the preset value is set by the operator. For the interference paths with interference causes greater than the preset value, they are directly eliminated and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two, and optimization information is generated.

[0058] Example 2: This example is implemented on the basis of Example 1, and differs from Example 1 in the following aspects:

[0059] In step S4, the space utilization rate of the planned path i can also be calculated by projecting the area. The specific calculation formula is: Specifically, the wiring harness and layout space are projected onto a plane. For example, in PCB routing, the wiring harness and the PCB routing area are typically projected onto the PCB plane. The area of the wiring harness on the projected surface can be determined by measuring or calculating the shape of the harness projection. The area of the layout space on the projected surface is the area available for routing on the PCB.

[0060] Example 3: This example is implemented on the basis of Example 1, and differs from Example 1 and Example 2 in the following aspects:

[0061] In step S4, the space utilization rate of the planned path i can also be calculated by the total volume method. The specific calculation formula is: Specifically, the total volume of a wiring harness refers to the sum of the volumes occupied by all wiring harnesses in three-dimensional space. This can be calculated by measuring or modeling the shape and size of the wiring harnesses. The total layout space volume refers to the volume of the three-dimensional space reserved for wiring harnesses, such as the space inside a cabinet for wiring or the space available for wiring harnesses in a car's engine compartment.

[0062] The fourth embodiment, as the fourth embodiment of the present invention, focuses on combining the implementation processes of the first embodiment, the second embodiment and the third embodiment.

[0063] Some of the data in the above formulas are calculated based on their numerical values and are not substituted into parameter units for calculation. At the same time, the contents not described in detail in this specification belong to the existing technology known to those skilled in the art.

[0064] The above embodiments are only used to illustrate the technical method of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A wiring harness layout optimization method based on three-dimensional simulation, characterized in that: The method specifically comprises the following steps: Determine the physical space and create a 3D model of the physical space using 3D modeling software, while defining the specifications of the wiring harness; Obtaining a preliminary planned route based on the three-dimensional model and in combination with the electrical system schematic diagram of the physical space, determining whether there is spatial interference on the preliminary planned route, and generating a determination result, including a determination of whether there is interference or not; Analyze the generated interference results, obtain the interference area and its interference causes, determine the number of interference causes, generate a single cause signal or multiple types of cause signals, analyze the generated single cause signal, obtain the corresponding single cause information, and generate corresponding optimization information based on the single cause information; Analyze the generated multi-type cause signals, obtain the corresponding multi-type cause information, and determine whether there is cause interaction in the multi-type cause information. If so, generate the corresponding optimization information based on the multi-type cause information; otherwise, generate a path analysis signal; Analyze the generated path analysis signal to obtain all planned routes, calculate the space utilization value based on the effective occupied space volume of the planned routes, analyze the number of resistors, capacitors, and inductors that meet the requirements, and calculate the parameter ratios, which are recorded as electrical performance values. Specifically, compare the obtained resistance, capacitance, and inductance with the corresponding design standards, determine the number of parameters that meet the design standards, and calculate the corresponding parameter ratios, which are recorded as electrical performance values. The operation convenience of the planned path is assigned to obtain the assembly process value, and the planning priority value of the planned route is calculated at the same time. Specifically, the obtained space utilization value, electrical performance value and assembly process value are comprehensively calculated; According to the interference situation of the planned route, the interference path and non-interference path are obtained, and the interference path corresponding to the interference reason less than the preset value is selected as the path to be analyzed. At the same time, the maximum planning priority value among the paths to be analyzed and the non-interference path is selected as the standard to generate optimization information.

2. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of generating the judgment result is: Based on the obtained three-dimensional model, a preliminary planned route is obtained in combination with the electrical system schematic diagram of the physical space, and it is determined whether there is spatial interference in the preliminary planned route. The preliminary planned route and the physical space are obtained, and the models of the wiring harness and surrounding components in the preliminary planned route are checked. If there is interference between the wiring harness and other objects, an interference result is generated. Conversely, if there is no interference between the wiring harness and other objects, a non-interference result is generated.

3. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of calculating the space utilization value based on the effective occupied space volume of the planned route is: Get the volume Vz of the physical space, and at the same time get the effective occupied space volume Vi corresponding to the planned route i, and according to the formula Calculate the space utilization rate corresponding to the planned route i, and then quantify the space utilization rate to obtain the corresponding space utilization value.

4. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of analyzing the generated path analysis signal is as follows: According to the formula Calculate the resistance R corresponding to the planned route i, where l is the length of the planned route, S is the cross-sectional area of the harness, is the resistivity; According to the formula Calculate the capacitance C corresponding to the planned route i, where is the dielectric constant, S x is the area facing the plates, and d is the distance between the plates; According to the formula Calculate the inductance L corresponding to the planned route i, where Magnetic permeability, l0 is the length of the wire, D is the distance between the two wires, and r is the radius of the wire.

5. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of calculating the planning priority value of the planned route is: According to the formula The planning priority value Q corresponding to the planned route is calculated, where K is the space utilization value, H is the electrical performance value, and A is the assembly process value. 、 and are the weight coefficients corresponding to the space utilization value, electrical performance value and assembly process value, respectively, and + + =1; Similarly, the planning priority value Q of all planned routes i is calculated and recorded as Qi.

6. The wiring harness layout optimization method based on three-dimensional simulation according to claim 1, characterized in that: The specific method of selecting the maximum planning priority value in the path to be analyzed and the non-interference path as the standard to generate the optimization information is: The interference path after classification is obtained and recorded as a, and a=1, 2, ..., n, where n represents the number of interference paths. Then, the interference cause corresponding to the interference path a is obtained, and the interference path corresponding to the interference cause less than the preset value is screened and recorded as the path to be analyzed. Then, the non-interference path is obtained and labeled as b, and b=1, 2, ..., m, where m represents the number of non-interference paths. At the same time, all the paths to be analyzed are obtained, and the path with the largest planning priority value is selected as the standard based on the two to generate optimization information.

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