Time sequence path optimization method and device, equipment and storage medium

Abstract

The invention discloses a time sequence path optimization method and device, equipment and a storage medium. The method comprises the following steps: obtaining an FPGA segmentation result, and carrying out time sequence modeling on the FPGA segmentation result to obtain a target time sequence logic; based on the resource limitation of each FPGA, performing multiple times of iterative optimization on each time sequence path link to obtain optimized time sequence logic output by each time of iterative optimization; and updating the FPGA segmentation result by utilizing the optimized sequential logic of each target path to obtain a segmentation update result, and determining an optimal FPGA segmentation result by utilizing the optimized sequential logic according to the change of a cutting connection line CutSize in the segmentation update result. According to the technical scheme provided by the embodiment of the invention, before actual system-level wiring and TDM ratio allocation are not carried out, optimization of the segmentation result is realized, the problem that a critical path in the FPGA segmentation result is too long is solved, and the operation dominant frequency of the DUT is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip logic design, and in particular to a timing path optimization method, device, equipment and storage medium. Background Art

[0002] The principle of FPGA prototype verification is to synthesize the chip RTL code into the FPGA to verify the chip's functions. The capacity of a single FPGA is often difficult to accommodate all the logic functions of the chip, so it is necessary to try to divide the large design into several small parts and configure them into multiple FPGAs to realize the logic functions of the entire design.

[0003] Currently, automatic segmentation can be achieved through segmentation engines. Existing segmentation engine algorithms mainly focus on the size of the cut connection (CutSize) between the segments or the optimization of the TDM ratio (timing drive ratio). Existing segmentation engines often ignore the identification of timing paths, resulting in a relatively scattered distribution of critical paths, too many segmentation channels passing through the critical paths, and greatly increasing the delay of the critical paths. Summary of the invention

[0004] The present invention provides a timing path optimization method, device, equipment and storage medium to solve the problem of too long critical path in FPGA segmentation results.

[0005] In a first aspect, the present invention provides a timing path optimization method, comprising:

[0006] Acquire FPGA segmentation results, and perform timing modeling on a target path in the FPGA segmentation results to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold;

[0007] Based on the resource limitation of each FPGA, each timing path link is iteratively optimized multiple times to obtain an optimized timing logic output by each iterative optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware functional modules through the target path;

[0008] The FPGA segmentation result is updated by using the optimized timing logic of each target path to obtain an updated segmentation result, and the optimal FPGA segmentation result is determined by using the optimized timing logic according to the change of the cut connection CutSize in the updated segmentation result.

[0009] In a second aspect, the present invention provides a timing path optimization device, comprising:

[0010] A timing modeling module, used to obtain an FPGA segmentation result, and perform timing modeling on a target path in the FPGA segmentation result to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold;

[0011] A timing path optimization module, which is used to perform multiple iterations of optimization on each timing path link based on the resource constraints of each FPGA, so as to obtain an optimized timing logic output by each iteration optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware function modules through the target path;

[0012] The optimal segmentation result determination module is used to update the FPGA segmentation result using the optimized timing logic of each target path to obtain a segmentation update result, and determine the optimal FPGA segmentation result using the optimized timing logic according to the change of the cut connection CutSize in the segmentation update result.

[0013] In a third aspect, the present invention provides an electronic device, the electronic device comprising:

[0014] at least one processor;

[0015] and a memory communicatively coupled to the at least one processor;

[0016] The memory stores a computer program that can be executed by at least one processor, and the computer program is executed by at least one processor so that the at least one processor can execute the timing path optimization method of the first aspect.

[0017] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer instructions, which are used to enable a processor to implement the timing path optimization method of the first aspect when executed.

[0018] The timing path optimization scheme provided by the present invention performs multiple iteration optimizations on the target path in the target timing logic of the segmentation result based on the resource limitation of the FPGA before actual system-level wiring and TDM ratio allocation are performed, and the FPGA segmentation result including the optimal timing path arrangement mode is determined according to the change of CutSize in the optimized segmentation result, thereby shortening the timing path as much as possible, optimizing the segmentation result, solving the problem of too long critical path in the FPGA segmentation result, and improving the operating main frequency of the DUT (Design Under Test).

[0019] It should be understood that the content described in this section is not intended to identify the key or important features of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a timing path optimization method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a flow chart of a timing path optimization method provided according to Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of iterative optimization provided according to Embodiment 2 of the present invention;

[0024] Figure 4 is another iterative optimization schematic diagram provided according to the second embodiment of the present invention;

[0025] Figure 5 is a structural diagram of a timing path optimization device provided according to Embodiment 3 of the present invention;

[0026] Figure 6 It is a structural schematic diagram of an electronic device provided according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In the description of the present invention, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are an "or" relationship. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] The main goal of the existing segmentation engine algorithm is to minimize CutSize to reduce the coupling between the segmented data blocks, thereby improving processing efficiency, and adjusting the time-division multiplexing ratio between different FPGAs to balance resource utilization and system performance. The timing information of the critical path of a multi-FPGA system usually needs to be generated after system-level routing and time-division multiplexing ratio allocation. Before this, if the timing information needs to be evaluated, the average TDM ratio can only be used for estimation, without considering the concept of timing path, resulting in an overly long timing path in the segmentation result, resulting in a critical path delay that is too high, which is far from the actual result.

[0030] Embodiment 1

[0031] Figure 1 A flowchart of a timing path optimization method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of optimizing the timing path in the FPGA segmentation result. The method can be executed by a timing path optimization device. The timing path optimization device can be implemented in the form of hardware and / or software. The timing path optimization device can be configured in an electronic device. The electronic device can be composed of two or more physical entities or one physical entity.

[0032] like Figure 1 As shown, a timing path optimization method provided in the first embodiment of the present invention specifically includes the following steps:

[0033] S101. Obtain FPGA segmentation results, and perform timing modeling on a target path in the FPGA segmentation results to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold.

[0034] In this embodiment, the FPGA segmentation result can be determined by using a conventional segmentation engine, and then the target path in the FPGA segmentation result can be subjected to timing modeling to obtain the target timing logic. The target timing logic can be understood as the timing connection relationship information between the hardware function modules of multiple FPGAs and the target path, and its expression can be a timing logic diagram. The target path includes at least a critical path, that is, the longest timing path.

[0035] S102. Based on the resource limitation of each FPGA, perform multiple iterative optimizations on each timing path link to obtain an optimized timing logic output by each iterative optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware functional modules through the target path.

[0036] In this embodiment, the target path can be iteratively optimized multiple times under the constraint of the resource limit of each FPGA in the target timing logic to shorten the target path, and the corresponding optimized timing logic can be obtained after each iterative optimization. In each iterative optimization process, the method of shortening the target path can be preset, such as shortening the target path by changing the position of the hardware function module of the FPGA, and the number of optimization iterations and the stop condition of the optimization iteration can also be preset, such as when the preset number of optimization iterations is reached or the length of the critical path obtained for multiple consecutive times does not change, the iterative optimization is stopped. Among them, when there are multiple timing path links, each timing path link can be iteratively optimized multiple times, and each target path can obtain the corresponding optimized timing logic after each iterative optimization. Each optimized timing logic may include the timing path link after iterative optimization and the remaining timing path link that has not been iteratively optimized.

[0037] S103, using the optimized timing logic of each target path to update the FPGA segmentation result to obtain a segmentation update result, and according to the change of the cut connection CutSize in the segmentation update result, using the optimized timing logic to determine the optimal FPGA segmentation result.

[0038] In this embodiment, every time an optimized timing logic is determined, the segmentation information contained in the optimized timing logic can be updated to the FPGA segmentation result, thereby obtaining a segmentation update result. The change in CutSize (cutting line) of each segmentation update result can be determined separately, and the optimal FPGA segmentation result can be determined using the optimized timing logic according to the value of the change. For example, the segmentation update result corresponding to the CutSize with the largest reduction is first determined, and the optimized timing logic corresponding to the segmentation update result is determined as the target optimized timing logic. When there are multiple timing path links, the target optimized timing logic corresponding to each timing path link can be obtained. By integrating these target optimized timing logics and updating them to the FPGA segmentation result, the optimal FPGA segmentation result can be obtained.

[0039] The technical solution of the embodiment of the present invention performs multiple iterative optimizations on the target path in the target timing logic of the segmentation result based on the resource limitation of the FPGA before the actual system-level wiring and TDM ratio allocation are performed, and the FPGA segmentation result including the optimal timing path arrangement mode is determined according to the change of CutSize in the optimized segmentation result, thereby shortening the timing path as much as possible, optimizing the segmentation result, solving the problem of too long critical path in the FPGA segmentation result, and improving the operating main frequency of the DUT (Design Under Test).

[0040] Optionally, the iterative optimization of each timing path link is performed multiple times based on the resource limitation of each FPGA to obtain the optimized timing logic output by each iterative optimization, including:

[0041] The resource limitation of each FPGA is determined as a constraint condition, and under the constraint of the constraint condition, the reduction of the cut connection CutSize and the shortening of the target path are taken as optimization goals. For each timing path link, the length of the target path is iteratively optimized multiple times by changing the position of the hardware functional module to obtain the optimized timing logic output by each iterative optimization.

[0042] Specifically, under the constraints of FPGA resource limitations, each timing path link can be optimized by reducing CutSize and shortening the target path, and the target path can be iteratively optimized by changing the position of the hardware function module. After each iterative optimization, the corresponding optimized timing logic can be obtained.

[0043] Optionally, determining the optimal FPGA segmentation result by using the optimized timing logic according to the change of the cut line CutSize in the segmentation update result includes:

[0044] For each timing path link in each of the optimized timing logics, determine a first number of cut lines CutSize of the current timing path link, and determine a second number of cut lines CutSize in the timing path link corresponding to the last iterative optimization, and store the timing path links corresponding to the first number whose value is smaller than the second number in an alternative list; if the alternative list is not empty, sort the timing path links in the alternative list according to the corresponding CutSize global reduction, wherein the CutSize global reduction is the total reduction of the cut lines CutSize in the segmentation update result; determine the timing path link corresponding to the CutSize global reduction that meets the first preset condition as the first optimal timing path link, and generate the first optimal FPGA segmentation result using the first optimal timing path link, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than the preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic.

[0045] Specifically, a corresponding alternative list can be created in advance for each sequential path link in the target timing logic. The timing path links in each optimized timing logic can be traversed, and for each timing path link, the difference in the number of CutSizes of the current timing path link and the CutSize in the timing path link corresponding to the previous iterative optimization can be determined. If the CutSize of the current timing path link is less than the CutSize of the previous time, the current timing path link is stored in the alternative list corresponding to the timing path link. If the alternative list is not empty, the timing path links in the alternative list can be sorted according to the size of the global reduction of CutSize, so as to determine the maximum global reduction of CutSize of the timing path link. Finally, the timing path link corresponding to the global reduction of CutSize that meets the first preset condition is used to generate the (first) optimal FPGA segmentation result, such as updating the timing path link to the FPGA segmentation result to obtain the optimal FPGA segmentation result. Among them, the preset number can be preset 2.

[0046] Embodiment 2

[0047] Figure 2 This is a flowchart of a timing path optimization method provided in the second embodiment of the present invention. The technical solution of the embodiment of the present invention is further optimized on the basis of the above-mentioned optional technical solutions, and a specific method for optimizing the timing path in the FPGA segmentation result is given.

[0048] Optionally, under the constraint of the restriction condition, with the reduction of the CutSize of the cutting line and the shortening of the target path as the optimization goals, for each timing path link, the length of the target path is optimized multiple times by changing the position of the hardware function module, including: under the constraint of the restriction condition, for each of the hardware function modules, with the shortening of the first target path and the reduction of the CutSize of the associated cutting line as the optimization goals, by changing the position of the first target hardware function module, the first target path is optimized multiple times to obtain the first optimized timing logic output by each iterative optimization, and the first target hardware function module is packaged to obtain the second target hardware function module; Under the constraints of the restriction conditions, for each of the hardware function modules, shortening the second target path and reducing the associated cutting connection CutSize are optimization goals, and the second target path is iteratively optimized multiple times by changing the position of the second target hardware function module to obtain the second optimized timing logic output by each iterative optimization; wherein the first target hardware function module is the hardware function module other than itself in the timing path link where the current hardware function module is located, the first target path is the target path included in the timing path link where the current hardware function module is located, and the second target path is the target path between the current hardware function module and the first target hardware function module. The advantage of such a setting is that by iteratively optimizing the target path multiple times using the above method, multiple ways to shorten the timing path can be quickly obtained.

[0049] Optionally, after storing the timing path link corresponding to the first quantity whose value is smaller than the second quantity into the candidate list, it also includes: if the candidate list is empty, determining the difference between the first quantity and the corresponding second quantity, and determining the timing path link that meets the third preset condition as the third optimal timing path link, and using the third optimal timing path link to generate the second optimal FPGA segmentation result; wherein the third preset condition includes that the difference is less than the first preset value, and the maximum delay of the critical path in the segmentation update result corresponding to the timing path link is less than the maximum delay of the critical path in the target timing logic. The advantage of this setting is that by screening the timing path links with a small global increase in CutSize but a shortened critical path, the optimal FPGA segmentation result containing the optimal timing path is obtained.

[0050] Optionally, after determining the difference between the first number and the corresponding second number, it also includes: if it is determined that there is no timing path link that meets the third preset condition, then the timing path link corresponding to the first number whose value is increased but the increase is less than the second preset value is stored in the candidate list; if the candidate list is not empty, the timing path links in the candidate list are sorted according to the corresponding CutSize global reduction; the timing path link corresponding to the CutSize global reduction that meets the first preset condition is determined as the fourth optimal timing path link, and the third optimal FPGA segmentation result is generated using the fourth optimal timing path link, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than the preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic. The advantage of such a setting is that when there is no timing path link that meets the preset condition, the optimal FPGA segmentation result containing the optimal timing path is obtained by relaxing the conditions for screening the timing path link.

[0051] As shown in ., a timing path optimization method provided by Embodiment 2 of the present invention specifically includes the following steps:

[0052] S201 , obtaining FPGA segmentation results, and performing timing modeling on the FPGA segmentation results to obtain target timing logic.

[0053] S202. Determine the resource limitation of each FPGA as a constraint condition, and under the constraint of the constraint condition, for each of the hardware function modules, take shortening the first target path and reducing the associated cutting connection CutSize as optimization goals, and perform multiple iterative optimizations on the first target path by changing the position of the first target hardware function module to obtain a first optimized timing logic output by each iterative optimization, and package the first target hardware function module to obtain a second target hardware function module.

[0054] The first target hardware function module is a hardware function module other than the current hardware function module itself in the timing path link where the current hardware function module is located, and the first target path is a target path included in the timing path link where the current hardware function module is located.

[0055] Specifically, the associated CutSize can be understood as the CutSize of the timing path link where the current hardware function module is located. After each iteration optimization of the first target path in each timing path link, a first optimized timing logic can be obtained accordingly.

[0056] For example, Figure 3is a schematic diagram of iterative optimization. Figure 4 Another iterative optimization diagram is shown below. Figure 3 and Figure 4 The rectangle in the figure is the FPGA, and ①, ②, ③, and ④ are all hardware function modules. If the current hardware function module is ①, the timing path link before iterative optimization is as follows: Figure 3 As shown on the left, after an iterative optimization, the position of a single target hardware functional module has changed, and the timing path link can be Figure 3 As shown on the right. If the current hardware function module is ①, the timing path link before iterative optimization is as follows Figure 4 As shown on the left, after multiple iterations of optimization, the positions of multiple first target hardware functional modules have changed, and the timing path links can be Figure 4 Shown on the right.

[0057] S203. Under the constraints of the restriction conditions, for each of the hardware functional modules, shortening the second target path and reducing the associated cutting connection CutSize are taken as optimization goals, and the second target path is iteratively optimized multiple times by changing the position of the second target hardware functional module to obtain the second optimized timing logic output by each iterative optimization to obtain the second optimized timing logic output by each iterative optimization.

[0058] The second target path is a target path between the current hardware function module and the first target hardware function module.

[0059] Specifically, for each timing path link, the first target hardware function module can be packaged as a whole, which is the second target hardware function module. Under the constraints of the restriction condition, the position of the second target hardware function module is moved to shorten the length of the target path between the second target hardware function module and the current hardware function module, and reduce the associated CutSize.

[0060] S204: Update the FPGA segmentation result using the optimized timing logic of each target path to obtain a segmentation update result.

[0061] S205. For each timing path link in each of the optimized timing logics, determine a first number of cut lines CutSize of the current timing path link, and determine a second number of cut lines CutSize in the corresponding timing path link after the last iterative optimization, and store the timing path links corresponding to the first number whose value is smaller than the second number into an alternative list.

[0062] Specifically, each timing path link corresponds to at least one candidate list. The timing path link with a smaller CutSize after iterative optimization can be stored in the candidate list corresponding to the link, so that each candidate list stores multiple optimization iteration results of the same timing path link.

[0063] S206 , determining whether the candidate list is empty, if so, executing step 209 , if not, executing step 207 .

[0064] Specifically, it is determined whether there is a non-empty candidate list, if so, step 207 is executed, if not, step 209 is executed.

[0065] S207 . Sort the timing path links in the candidate list according to the corresponding CutSize global reduction amount.

[0066] The global reduction of CutSize is the total reduction of the CutSize of the cut lines in the segmentation update result.

[0067] Exemplarily, the timing path links in the candidate list may be sorted in descending order according to the corresponding global reduction amounts of CutSize to obtain a sorting result.

[0068] S208 . Determine a timing path link corresponding to the global reduction amount of CutSize that meets a first preset condition as a first optimal timing path link, and generate a first optimal FPGA segmentation result using the first optimal timing path link.

[0069] Among them, the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than the preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target sequential logic.

[0070] Specifically, if there is a global reduction of CutSize that meets the first preset condition, the corresponding timing path link is determined as the first optimal timing path link.

[0071] Optionally, the using the first optimal timing path link to generate a first optimal FPGA segmentation result includes:

[0072] Determine a change in the timing drive ratio of the segmentation update result corresponding to the CutSize global reduction that meets the second preset condition, wherein the second preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reductions is greater than or equal to a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic; based on the change, determine a second optimal timing path link from the timing path links corresponding to the CutSize global reduction that meets the second preset condition, and generate a first optimal FPGA segmentation result using the first optimal timing path link and the second optimal timing path link.

[0073] Specifically, if there is a global reduction in CutSize that satisfies the second preset condition, the change in the timing drive ratio of the corresponding segmentation update result is determined. If the change indicates an increase in the timing drive ratio, the timing path link corresponding to the timing drive ratio of the minimum increase can be determined as the second optimal timing path link. If the change indicates a decrease in the timing drive ratio, the timing path link corresponding to the timing drive ratio of the maximum decrease can be determined as the second optimal timing path link. The (first) optimal FPGA segmentation result can be generated by updating the first optimal timing path link and the second optimal timing path link to the FPGA segmentation result.

[0074] S209, determine the difference between the first quantity and the corresponding second quantity, and judge whether there is a timing path link that meets the third preset condition, if so, execute step 210, if yes, execute step 211.

[0075] The third preset condition includes that the difference is smaller than the first preset value, and the maximum delay of the critical path in the segmentation update result corresponding to the timing path link is smaller than the maximum delay of the critical path in the target timing logic.

[0076] Exemplarily, the first preset value may be preset to 1% of the global reduction amount of CutSize corresponding to the FPGA segmentation result.

[0077] S210: Determine a timing path link that meets a third preset condition as a third optimal timing path link, and use the third optimal timing path link to generate a second optimal FPGA segmentation result.

[0078] Specifically, if there is no timing path link whose CutSize quantity decreases, that is, the candidate lists are all empty, then the timing path link that satisfies the increase in CutSize quantity less than the first preset value and the corresponding maximum delay of the critical path in the segmentation update result decreases can be determined as the third optimal timing path link. By updating the third optimal timing path link to the FPGA segmentation result, a (second) optimal FPGA segmentation result is generated.

[0079] S211. Store the timing path links corresponding to the first number whose value is increased compared to the second number but whose increase is less than the second preset value into the candidate list.

[0080] Specifically, if there is no timing path link that meets the third preset condition, the adjusted steps can be performed after the adjustment step S205, wherein the adjusted steps can be: for each timing path link in each of the optimized timing logics, the timing path link corresponding to the first quantity whose value is increased compared to the second quantity but the increase is less than the second preset value is stored in the corresponding alternative list.

[0081] S212: Determine whether the candidate list is empty, if so, end, if not, execute step 213.

[0082] Specifically, it can be determined again whether there is a non-empty candidate list, if not, then the process ends, if yes, then step 213 is executed. If there is no non-empty candidate list, then the timing path of the current FPGA segmentation result is already the optimal FPGA segmentation result.

[0083] S213. Sort the timing path links in the candidate list according to the corresponding CutSize global reduction; determine the timing path link corresponding to the CutSize global reduction that meets the first preset condition as the fourth optimal timing path link, and use the fourth optimal timing path link to generate a third optimal FPGA segmentation result.

[0084] Among them, the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than the preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target sequential logic.

[0085] Specifically, if there is a non-empty alternative list, the timing path links in the alternative list can be sorted according to the amount of global reduction in CutSize. The timing path link corresponding to the global reduction in CutSize that meets the first preset condition is determined as the fourth optimal timing path link. The change in the timing drive ratio of the segmentation update result corresponding to the global reduction in CutSize that meets the second preset condition is determined; based on the change, the fifth optimal timing path link is determined from the timing path links corresponding to the global reduction in CutSize that meets the second preset condition, and the fourth optimal timing path link and the fifth optimal timing path link are used to generate the third optimal FPGA segmentation result.

[0086] The timing path optimization method provided by the embodiment of the present invention performs multiple iterative optimizations on the target path by utilizing the above-mentioned method, and quickly obtains multiple methods of shortening the timing path. By screening the timing path links with a small global increase in CutSize but a shortened critical path, an optimal FPGA segmentation result including the optimal timing path is obtained. When there is no timing path link that meets the preset conditions, the FPGA segmentation result including the optimal timing path is obtained by relaxing the conditions for screening the timing path links.

[0087] Embodiment 3

[0088] Figure 5 This is a schematic diagram of the structure of a timing path optimization device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device includes: a time series modeling module 301, a time series path optimization module 302 and an optimal segmentation result determination module 303, wherein:

[0089] A timing modeling module, used to obtain an FPGA segmentation result, and perform timing modeling on a target path in the FPGA segmentation result to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold;

[0090] A timing path optimization module, which is used to perform multiple iterations of optimization on each timing path link based on the resource constraints of each FPGA, so as to obtain an optimized timing logic output by each iteration optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware function modules through the target path;

[0091] The optimal segmentation result determination module is used to update the FPGA segmentation result using the optimized timing logic of each target path to obtain a segmentation update result, and determine the optimal FPGA segmentation result using the optimized timing logic according to the change of the cut connection CutSize in the segmentation update result.

[0092] The timing path optimization device provided in the embodiment of the present invention performs multiple iterative optimizations on the target path in the target timing logic of the segmentation result based on the resource limitation of the FPGA before the actual system-level wiring and TDMratio allocation are performed, and the FPGA segmentation result including the optimal timing path arrangement mode is determined according to the change of CutSize in the optimized segmentation result, so that the timing path is shortened as much as possible, the segmentation result is optimized, the problem of too long critical path in the FPGA segmentation result is solved, and the operating main frequency of DUT (Design Under Test) is improved.

[0093] Optionally, the timing path optimization module is specifically used to determine the resource limitation of each FPGA as a constraint condition, and under the constraint of the constraint condition, take the reduction of the cut connection CutSize and the shortening of the target path as the optimization goal, and for each timing path link, perform multiple iterative optimizations on the length of the target path by changing the position of the hardware functional module to obtain the optimized timing logic output by each iterative optimization.

[0094] Furthermore, under the constraints of the constraints, the reduction of the CutSize of the cutting line and the shortening of the target path are taken as optimization goals, and for each timing path link, the length of the target path is optimized multiple times by changing the position of the hardware function module, including: under the constraints of the constraints, for each of the hardware function modules, the shortening of the first target path and the reduction of the CutSize of the associated cutting line are taken as optimization goals, and the first target path is optimized multiple times by changing the position of the first target hardware function module to obtain the first optimized timing logic output by each iterative optimization, and the first target hardware function module is packaged to obtain the second target hardware function module; under the constraints of the constraints , for each of the hardware function modules, taking shortening the second target path and reducing the associated cutting connection CutSize as the optimization goal, the second target path is iteratively optimized for multiple times by changing the position of the second target hardware function module to obtain the second optimized timing logic output by each iterative optimization to obtain the second optimized timing logic output by each iterative optimization; wherein, the first target hardware function module is the hardware function module other than itself in the timing path link where the current hardware function module is located, the first target path is the target path included in the timing path link where the current hardware function module is located, and the second target path is the target path between the current hardware function module and the first target hardware function module.

[0095] Optionally, the optimal segmentation result determination module includes:

[0096] A first screening unit is used to determine, for each timing path link in each of the optimized timing logics, a first number of cut lines CutSize of the current timing path link, and determine a second number of cut lines CutSize in the corresponding timing path link after the last iterative optimization, and store the timing path links corresponding to the first number whose value is smaller than the second number in the candidate list;

[0097] A first sorting unit, configured to sort the timing path links in the candidate list according to the corresponding global reduction of CutSize if the candidate list is not empty, wherein the global reduction of CutSize is the total reduction of CutSize of the cut links in the segmentation update result;

[0098] The first optimal segmentation result determination unit is used to determine the timing path link corresponding to the CutSize global reduction that meets the first preset condition as the first optimal timing path link, and use the first optimal timing path link to generate a first optimal FPGA segmentation result, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic.

[0099] Furthermore, the method of generating a first optimal FPGA segmentation result using the first optimal timing path link includes: determining a change in the timing drive ratio of the segmentation update result corresponding to the CutSize global reduction that satisfies a second preset condition, wherein the second preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reductions is greater than or equal to a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic; based on the change, determining a second optimal timing path link from the timing path links corresponding to the CutSize global reduction that satisfies the second preset condition, and generating the first optimal FPGA segmentation result using the first optimal timing path link and the second optimal timing path link.

[0100] Optionally, the optimal segmentation result determination module further includes:

[0101] A second optimal segmentation result determining unit is used for, after storing the timing path link corresponding to the first number whose value becomes smaller than the second number into the candidate list, if the candidate list is empty, determining the difference between the first number and the corresponding second number, and determining the timing path link that meets the third preset condition as the third optimal timing path link, and generating the second optimal FPGA segmentation result by using the third optimal timing path link;

[0102] The third preset condition includes that the difference is smaller than the first preset value, and the maximum delay of the critical path in the segmentation update result corresponding to the timing path link is smaller than the maximum delay of the critical path in the target timing logic.

[0103] Optionally, the optimal segmentation result determination module further includes:

[0104] A second screening unit is configured to store, in the candidate list, a timing path link corresponding to the first number whose value is increased compared to the second number but whose increase is less than the second preset value, if it is determined that there is no timing path link satisfying a third preset condition after determining the difference between the first number and the corresponding second number;

[0105] A second sorting unit, configured to sort the timing path links in the candidate list according to the corresponding CutSize global reduction amount if the candidate list is not empty;

[0106] The third optimal segmentation result determination unit is used to determine the timing path link corresponding to the CutSize global reduction that meets the first preset condition as a fourth optimal timing path link, and use the fourth optimal timing path link to generate a third optimal FPGA segmentation result, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic.

[0107] The timing path optimization device provided in the embodiment of the present invention can execute the timing path optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0108] Embodiment 4

[0109] Figure 6 A schematic diagram of the structure of an electronic device 40 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0110] like Figure 6As shown, the electronic device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 to the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0111] A number of components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0112] The processor 41 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 41 executes the various methods and processes described above, such as a timing path optimization method.

[0113] In some embodiments, the timing path optimization method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the timing path optimization method described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the timing path optimization method in any other appropriate manner (e.g., by means of firmware).

[0114] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0115] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0116] The computer device provided above can be used to execute the timing path optimization method provided by any of the above embodiments, and has corresponding functions and beneficial effects.

[0117] Embodiment 5

[0118] In the context of the present invention, a computer-readable storage medium may be a tangible medium, wherein the computer-executable instructions, when executed by a computer processor, are used to perform a timing path optimization method, the method comprising:

[0119] Acquire FPGA segmentation results, and perform timing modeling on a target path in the FPGA segmentation results to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold;

[0120] Based on the resource limitation of each FPGA, each timing path link is iteratively optimized multiple times to obtain an optimized timing logic output by each iterative optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware functional modules through the target path;

[0121] The FPGA segmentation result is updated by using the optimized timing logic of each target path to obtain an updated segmentation result, and the optimal FPGA segmentation result is determined by using the optimized timing logic according to the change of the cut connection CutSize in the updated segmentation result.

[0122] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by an instruction execution system, device or equipment or used with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0123] The computer device provided above can be used to execute the timing path optimization method provided by any of the above embodiments, and has corresponding functions and beneficial effects.

[0124] It is worth noting that in the embodiment of the above-mentioned timing path optimization device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0125] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A timing path optimization method, characterized in that: include: Acquire FPGA segmentation results, and perform timing modeling on a target path in the FPGA segmentation results to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold; Based on the resource limitation of each FPGA, each timing path link is iteratively optimized multiple times to obtain an optimized timing logic output by each iterative optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware functional modules through the target path; The FPGA segmentation result is updated by using the optimized timing logic of each target path to obtain an updated segmentation result, and the optimal FPGA segmentation result is determined by using the optimized timing logic according to the change of the cut connection CutSize in the updated segmentation result.

2. The method according to claim 1, characterized in that Based on the resource limitation of each FPGA, each timing path link is iteratively optimized multiple times to obtain the optimized timing logic output by each iterative optimization, including: The resource limitation of each FPGA is determined as a constraint condition, and under the constraint of the constraint condition, the reduction of the cut connection CutSize and the shortening of the target path are taken as optimization goals. For each timing path link, the length of the target path is iteratively optimized multiple times by changing the position of the hardware functional module to obtain the optimized timing logic output by each iterative optimization.

3. The method according to claim 2, characterized in that Under the constraints, the optimization goal is to reduce the CutSize of the cutting line and shorten the target path. For each timing path link, the length of the target path is optimized multiple times by changing the position of the hardware function module, including: Under the constraint of the restriction condition, for each of the hardware function modules, taking shortening the first target path and reducing the associated cutting connection CutSize as the optimization goal, by changing the position of the first target hardware function module, performing multiple iterative optimizations on the first target path to obtain the first optimized timing logic output by each iterative optimization, and packaging the first target hardware function module to obtain the second target hardware function module; Under the constraint of the restriction condition, for each of the hardware function modules, shortening the second target path and reducing the associated cutting connection CutSize are taken as optimization goals, and the second target path is iteratively optimized multiple times by changing the position of the second target hardware function module to obtain a second optimized sequential logic outputted by each iterative optimization; Among them, the first target hardware function module is a hardware function module other than itself in the timing path link where the current hardware function module is located, the first target path is a target path included in the timing path link where the current hardware function module is located, and the second target path is a target path between the current hardware function module and the first target hardware function module.

4. The method according to any one of claims 1 to 3, characterized in that The step of determining the optimal FPGA segmentation result by using the optimized timing logic according to the change of the cut line CutSize in the segmentation update result includes: For each timing path link in each of the optimized timing logics, determine a first number of cut lines CutSize of the current timing path link, and determine a second number of cut lines CutSize in the corresponding timing path link after the last iterative optimization, and store the timing path links corresponding to the first number whose value is smaller than the second number in the candidate list; If the candidate list is not empty, the timing path links in the candidate list are sorted according to the corresponding global reduction of CutSize, wherein the global reduction of CutSize is the total reduction of CutSize of the cut links in the segmentation update result; The timing path link corresponding to the CutSize global reduction that meets the first preset condition is determined as the first optimal timing path link, and the first optimal timing path link is used to generate a first optimal FPGA segmentation result, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic.

5. The method according to claim 4, characterized in that The step of generating a first optimal FPGA segmentation result by using the first optimal timing path link includes: Determine a change in the timing drive ratio of the segmentation update result corresponding to the CutSize global reduction that satisfies a second preset condition, wherein the second preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reductions is greater than or equal to a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target sequential logic; According to the change amount, a second optimal timing path link is determined from the timing path links corresponding to the global reduction amount of CutSize that meets the second preset condition, and a first optimal FPGA segmentation result is generated using the first optimal timing path link and the second optimal timing path link.

6. The method according to claim 4, characterized in that After storing the timing path links corresponding to the first number whose value is smaller than the second number into the candidate list, the method further includes: If the candidate list is empty, determining the difference between the first number and the corresponding second number, determining the timing path link that meets the third preset condition as the third optimal timing path link, and using the third optimal timing path link to generate a second optimal FPGA segmentation result; The third preset condition includes that the difference is smaller than the first preset value, and the maximum delay of the critical path in the segmentation update result corresponding to the timing path link is smaller than the maximum delay of the critical path in the target timing logic.

7. The method according to claim 6, characterized in that After determining the difference between the first quantity and the corresponding second quantity, the method further includes: If it is determined that there is no timing path link that meets the third preset condition, storing the timing path link corresponding to the first number whose value is increased compared to the second number but whose increase amount is less than the second preset value into the candidate list; If the candidate list is not empty, the timing path links in the candidate list are sorted according to the corresponding CutSize global reduction; The timing path link corresponding to the CutSize global reduction that meets the first preset condition is determined as the fourth optimal timing path link, and the third optimal FPGA segmentation result is generated using the fourth optimal timing path link, wherein the first preset condition includes that the maximum CutSize global reduction is a positive number, the number of the maximum CutSize global reduction is less than a preset number, and the maximum delay of the critical path in the segmentation update result corresponding to the maximum CutSize global reduction is less than the maximum delay of the critical path in the target timing logic.

8. A timing path optimization device, characterized in that: include: A timing modeling module, used to obtain an FPGA segmentation result, and perform timing modeling on a target path in the FPGA segmentation result to obtain a target timing logic, wherein the target timing logic includes a connection relationship between hardware function modules of different FPGAs and the target path, and the target path is a timing path whose length is greater than a preset threshold; A timing path optimization module, which is used to perform multiple iterations of optimization on each timing path link based on the resource constraints of each FPGA, so as to obtain an optimized timing logic output by each iteration optimization, wherein the optimized critical path in the optimized timing logic is shorter than the critical path in the target timing logic, and the timing path link is a link formed by connecting hardware function modules through the target path; The optimal segmentation result determination module is used to update the FPGA segmentation result using the optimized timing logic of each target path to obtain a segmentation update result, and determine the optimal FPGA segmentation result using the optimized timing logic according to the change of the cut connection CutSize in the segmentation update result.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the timing path optimization method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing path optimization method according to any one of claims 1 to 7 when executed.

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