A high-speed bus based on ring network and time trigger and a control method thereof

Abstract

The application belongs to the technical field of embedded computing system and device, and discloses a high-speed bus based on ring network and time trigger and a control method thereof. The high-speed bus comprises a control type ring bus and a plurality of information processing type ring buses. The physical link of the control type ring bus is connected to form a ring bus topology architecture through all computer nodes in an electronic system. The physical link of each information processing type ring bus is connected to form a ring bus topology architecture through at least two computer nodes according to system computing resource configuration. The control type ring bus and the information processing type ring bus each comprise a ring bus controller, a high-speed data sending unit and a high-speed data receiving unit in each computer node in the physical link. The high-speed bus has the advantages of flexible system expansion, low cost, high bus rate, simple bus protocol control logic and convenient debugging.

Description

Technical Field

[0001] The present invention belongs to the field of embedded computing systems and equipment, and relates to a high-speed bus design technology for a distributed embedded computing system in a supersonic unmanned aerial vehicle, and specifically to a high-speed bus based on a ring network and time triggering and a control method thereof. Background Art

[0002] The interfaces of information processing nodes in supersonic unmanned aerial vehicles (UAVs) require both high real-time control tasks and high computing power and communication bandwidth. With the rapid development of high-speed bus technology, 100G Ethernet-based RDMA technology has significantly shortened data transfer time between computing nodes, significantly reducing data transmission latency for distributed computing. However, current RDMA technology typically relies on switches for rapid distributed data transmission. These switches are typically large and costly, and disposable aircraft have high cost requirements. Therefore, traditional switch-based RDMA technology is not suitable for current mission applications.

[0003] The current avionics systems of supersonic unmanned aerial vehicles have the following problems:

[0004] (1) Serious waste of system computing resources. Currently, multi-core processors are widely used. However, in control nodes, only one or two cores of the multi-core processors are usually used. For example, in a guidance control system, there are five control nodes, including flight control, front and rear servos, inertial navigation, and satellite navigation. Each node usually uses a quad-core processor. In actual applications, nearly two-thirds of the processor computing power, that is, about 10 processor cores and nearly half of the FPGA computing resources, are wasted. These wasted computing resources cannot be used by other subsystems.

[0005] (2) The unbalanced distribution of computing power in the system leads to difficulties in the thermal design of nodes with concentrated computing power (for example, the computing power of guidance payload nodes is usually hundreds of times that of flight control nodes). In addition, under the condition of strong volume constraints, it is usually necessary to impose constraints on the computer working time of the nodes with concentrated computing power, strictly limit their heat generation, and also add additional energy storage devices, which increases the system volume to a certain extent and limits the flexibility of the aircraft's combat missions. In contrast, some nodes cannot be fully utilized due to their advantageous location and large space.

[0006] (3) Poor system scalability. The front-end data collection and back-end information processing of the load-type node are tightly coupled, which requires the entire node to be upgraded when the system is upgraded.

[0007] (4) The 1394 bus has flexible nodes for addition and removal, making it suitable for flight control buses. However, its single-node cost is high and it does not support the high bandwidth requirements of information processing tasks.

[0008] Therefore, it is necessary to design a high-speed bus that can realize high-speed connection of various computing resources, thereby achieving flexible deployment of computing power. Summary of the Invention

[0009] In order to solve the technical problems of serious waste of computing resources, unbalanced computing power distribution, poor scalability and other technical problems existing in the avionics systems of existing supersonic unmanned aerial vehicles, the present invention discloses a high-speed bus based on a ring network and time triggering, wherein the high-speed bus includes a control ring bus and multiple information processing ring buses.

[0010] Among them, the physical link of the control ring bus is connected through all computer nodes in the electronic system to form a ring bus topology architecture, and the physical link of each information processing ring bus is connected through at least two computer nodes according to the system computing resource configuration to form a ring bus topology architecture.

[0011] The control-type ring bus and the information processing-type ring bus both include a ring bus controller, a high-speed data sending unit, and a high-speed data receiving unit located in each of the computer nodes in their physical links. The signal output end of the ring bus controller is connected to the high-speed data sending unit, and the signal input end of the ring bus controller is connected to the high-speed data receiving unit. The ring bus controller receives or sends data according to the data forwarding logic and time slot information.

[0012] Furthermore, the computer nodes include control nodes and information processing nodes, and the control ring bus is set to one or two according to the time when each computer node starts working after the electronic system is powered on.

[0013] Furthermore, when all the computer nodes start working simultaneously after the electronic system is powered on, there is one control-type ring bus;

[0014] After the electronic system is powered on, the computer nodes in the first part start working at the same time, and the computer nodes in the second part start working after the computer nodes in the first part have been working for a period of time. There are two control ring buses, one of which connects all the computer nodes in the first part, and the other connects all the computer nodes in the second part.

[0015] Furthermore, the high-speed data receiving unit includes a high-speed serial SERDES receiver and a data receiving control logic module, the signal input end of the high-speed serial SERDES receiver is connected to the receiving port of the optoelectronic transceiver, and the signal output end of the high-speed serial SERDES receiver is connected to the signal input end of the ring bus controller;

[0016] The high-speed data transmission unit includes a high-speed serial SERDES transmitter and a data transmission control logic module, the signal output end of the high-speed serial SERDES transmitter is connected to the signal transmission port of the optoelectronic transceiver, and the signal input end of the high-speed serial SERDES transmitter is connected to the signal output end of the ring bus controller;

[0017] The ring bus controller includes a data forwarding control logic module and a time-triggered protocol control logic module. The data forwarding control logic module performs data forwarding logic configuration, and the time-triggered protocol control logic module performs data sending time slot and data receiving time slot configuration. According to the data forwarding logic, the bus data received by the high-speed data receiving unit is received and cached in the receiving data time slot, and the bus data is output in the sending data time slot.

[0018] Furthermore, the high-speed serial SERDES receiver and the high-speed serial SERDES transmitter each include any one of a GTX transceiver integrated in an FPGA, a GTH transceiver integrated in an FPGA, a SERDES serial-parallel interface driver, and a SERDES parallel-serial interface driver.

[0019] Furthermore, the high-speed data receiving unit includes a data buffer, and the data buffer is used to buffer the sent bus data.

[0020] Furthermore, the control-type ring bus and the information processing-type ring bus also include a logical cross switch located in each computer node in its physical link, the control end of the logical cross switch is connected to the ring bus controller, and the signal end is connected to the high-speed data sending unit and the high-speed data receiving unit. The ring bus controller controls the on-off of the software-configurable cross switch according to the data forwarding logic.

[0021] Furthermore, when there are mutually redundant information processing type ring buses in the high-speed bus, the high-speed bus also includes a redundancy controller located in the computer node, and the redundancy controller is connected to the ring bus controller of the mutually redundant information processing type ring bus.

[0022] An embodiment of the present invention further provides a control method for a high-speed bus based on a ring network and time triggering, wherein the control method controls the operation of the high-speed bus based on a ring network and time triggering described in the above embodiment, and the control method comprises the following steps:

[0023] When the electronic system is powered on, a communication link is established for each computer node in the control ring bus according to the control function of each computer node, and a communication link is established for each computer node in the information processing ring bus according to the information calculation function of each computer node, thereby completing the establishment of a logical loop;

[0024] A bus start period STOF is configured for the computer node belonging to the master control node in the electronic system, and the master control node outputs an STOF synchronization frame to the ring bus controllers of the remaining computer nodes in the electronic system according to the bus start period STOF;

[0025] Each of the control-type ring buses and each of the information processing-type ring buses receives or sends data based on the STOF synchronization frame, the ring bus control cycle and the time slot information.

[0026] Compared with the prior art, the beneficial effects achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: the high-speed bus of the present invention is suitable for low-latency, high-speed data communication of various control tasks and payload tasks of the distributed computing platform in supersonic unmanned aerial vehicles, and has the characteristics of flexible system expansion, low cost, high bus rate, simple bus protocol control logic, and convenient debugging. Specifically, the high-speed bus has the following advantages:

[0027] (1) The computing power of electronic systems can be flexibly arranged, and the system computing power distribution is more balanced, which reduces the difficulty of node thermal design.

[0028] (2) Fully utilize the various computing resources in the computing platform of the system. Through high-speed bus interconnection, high-determinism and low-latency data communication of various computing resources in the distributed computing platform is achieved, improving the utilization rate of system resources.

[0029] (3) A control ring bus and an information processing ring bus based on a time-triggered protocol are used to connect the devices in the system, ensuring the highly deterministic execution of strong real-time control tasks and information processing tasks in hypersonic aircraft.

[0030] (4) The physical link of the high-speed bus is a ring bus topology architecture. The topological relationship of the communication link can be defined by software and can meet the requirements of different application scenarios. At the same time, based on the physical link, the mapping of physical channel input channel, physical output channel and any ring bus controller can be realized through the software-configurable cross switch inside each node, and various logical rings can be constructed to meet the different application scenario requirements of control information processing and payload information processing for high reliability, strong real-time, high bandwidth, etc. For example, redundant loops can be constructed on any two ring physical links, thereby ensuring the reliability of data flow; for example, a logical ring with doubled bandwidth can be constructed on the basis of two physical links, thereby improving the communication bandwidth of information processing tasks; for example, adjacent nodes in the two rings can be constructed into several small rings according to the task deployment situation, thereby meeting the closed-loop communication requirements of different tasks.

[0031] (5) The present invention adopts a decentralized design concept. Compared with the conventional complex network switch design, it does not need to connect with peripheral devices in a point-to-point manner (that is, the switch node includes both physical ports for connecting to various peripheral devices and the design architecture of link switching functional circuits), which greatly reduces the system cost.

[0032] (6) The decoupling of front-end high-speed sensor data acquisition and control and back-end information processing is achieved, which is conducive to the agile upgrade of the system's core computing performance.

[0033] (7) The high-speed bus of the present invention is flexible to expand and easy to debug. The addition or removal of computer nodes in its physical link is relatively simple. It only needs to be connected to the corresponding physical link as required. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 A schematic diagram of a high-speed bus connection formed by all computer nodes in an electronic system disclosed in an embodiment of the present invention;

[0036] Figure 2 This is a system architecture diagram of a single ring bus node in a high-speed bus disclosed in an embodiment of the present invention;

[0037] Figure 3 A system architecture diagram of a high-speed bus comprising multiple ring bus nodes disclosed in an embodiment of the present invention;

[0038] Figure 4A schematic diagram of a redundant ring formed by two loops in a high-speed bus disclosed in an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of a high-speed bus disclosed in an embodiment of the present invention, wherein two loops constitute one ring;

[0040] Figure 6 This is a schematic diagram of two independent rings formed by two loops in the high-speed bus disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features of the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0043] The embodiment of the present invention discloses a high-speed bus based on a ring network and time triggering. The high-speed bus can be divided into a control ring bus and multiple information processing ring buses according to the service flow. Figure 1 As shown, the physical link of the control-type ring bus is connected through all computer nodes in the electronic system to form a ring bus topology architecture, and the physical link of each information processing-type ring bus is connected through at least two computer nodes to form a ring bus topology architecture based on the system computing resource configuration.

[0044] See also Figure 2 and Figure 3 As shown, the control ring bus and the information processing ring bus each include a ring bus controller, a high-speed data sending unit, and a high-speed data receiving unit located in each computer node in their physical links. The signal output end of the ring bus controller is connected to the high-speed data sending unit, and the signal input end of the ring bus controller is connected to the high-speed data receiving unit. The ring bus controller receives or sends data based on data forwarding logic and time slot information. Specifically, each ring bus (control ring bus and information processing ring bus) includes a ring bus controller, a high-speed data receiving unit, and a high-speed data sending unit.

[0045] Furthermore, the computer nodes include control nodes and information processing nodes, and the control ring bus is set to one or two according to the time when each computer node starts working after the electronic system is powered on.

[0046] Furthermore, when all the computer nodes start working simultaneously after the electronic system is powered on, there is one control-type ring bus;

[0047] After the electronic system is powered on, the computer nodes in the first part start working at the same time, and the computer nodes in the second part start working after the computer nodes in the first part have been working for a period of time. There are two control ring buses, one of which connects all the computer nodes in the first part, and the other connects all the computer nodes in the second part.

[0048] Specifically, when all devices (i.e., computer nodes) in an electronic system are powered on simultaneously, a single control ring bus is sufficient. However, when some devices in the electronic system are powered on only after the system has been operating for a period of time, two control ring buses are required: one connecting all computer nodes that must be powered on immediately after the system is powered on, and the other connecting all computer nodes that are powered on later.

[0049] Further, see Figure 2 and Figure 3 As shown, the high-speed data receiving unit includes a high-speed serial SERDES receiver and a data receiving control logic module. The signal input end of the high-speed serial SERDES receiver is connected to the receiving port of the optoelectronic transceiver, and the signal output end of the high-speed serial SERDES receiver is connected to the signal input end of the ring bus controller. By setting up an optoelectronic transceiver, the requirements of high transmission rate and long transmission distance can be met. If data is transmitted through the optoelectronic transceiver, an optical splitter and an optical path switch can also be connected to its input and output interfaces. The connection method is as follows: (1) The optical splitter splits the external input optical signal into two, one for the optoelectronic transceiver and the other for the optical path switch, thereby realizing signal forwarding.

[0050] (2) The optical path switch implements the two-choice switching control of the optical signal. The optical path switch is in the straight-through mode by default. When the node is powered on and working normally, the interface controller switches the output optical signal of the optical path switch to the optical signal output by the optoelectronic transceiver of the node.

[0051] The high-speed data transmission unit includes a high-speed serial SERDES transmitter and a data transmission control logic module. The signal output end of the high-speed serial SERDES transmitter is connected to the signal transmission port of the optoelectronic transceiver, and the signal input end of the high-speed serial SERDES transmitter is connected to the signal output end of the ring bus controller.

[0052] The ring bus controller includes a data forwarding control logic module and a time-triggered protocol control logic module. The data forwarding control logic module configures the data forwarding logic, while the time-triggered protocol control logic module configures the transmit and receive data time slots. Based on the data forwarding logic, the controller receives and buffers bus data received by the high-speed data receiving unit in the receive data time slot and outputs the bus data in the transmit data time slot. In specific implementations, each computer node receives data received by the high-speed data receiving unit in the receive data time slot according to the configured time slot information and automatically stores the data via the AXI bus. In the transmit data time slot, the node sends the data it needs to send to the ring bus via the high-speed data sending unit.

[0053] Furthermore, the high-speed serial SERDES receiver and the high-speed serial SERDES transmitter each include any one of a GTX transceiver integrated in an FPGA, a GTH transceiver integrated in an FPGA, a SERDES serial-parallel interface driver, and a SERDES parallel-serial interface driver.

[0054] Furthermore, the high-speed data receiving unit includes a data buffer, and the data buffer is used to buffer the sent bus data.

[0055] Further, see Figure 3 As shown, the control-type ring bus and the information processing-type ring bus also include a logical cross switch located in each of the computer nodes in their physical links. The control end of the logical cross switch is connected to the ring bus controller, and the signal end is connected to the high-speed data sending unit and the high-speed data receiving unit. The ring bus controller controls the on-off of the software-configurable cross switch according to the data forwarding logic.

[0056] Specifically, if a computer node is located on two or more control ring buses or information processing ring buses, at this time, at least one software-configurable logical cross-switch can be deployed in the computer node. The software-configurable logical cross-switch can realize the mapping between the ring bus controller and the physical link, thereby constructing various logical loops based on the physical link.

[0057] The mapping relationship between the ring bus controller and the physical link includes: (1) the external input data of any ring bus controller can be connected to the input data of any physical channel; (2) the bus output data of any ring bus controller can be connected to the output data and bus output switching signal of any physical channel; (3) the input data of any physical channel can be connected to the output data of any physical channel (when forwarding data).

[0058] Further, see Figure 4 As shown, when there are mutually redundant information processing type ring buses in the high-speed bus, the high-speed bus also includes a redundancy controller located in the computer node, and the redundancy controller is connected to the ring bus controller of the mutually redundant information processing type ring bus.

[0059] When designing the high-speed bus of the present invention, taking two hardware loops as an example, the number of computer nodes in the electronic system is ≥4. For all computer nodes in the electronic system, such as Figure 1 As shown, one of the computer nodes can be set as the master control node (usually a flight control node, such as control node 1), one computer node can be set as a backup master control node (such as control node n), and the remaining computer nodes can be set as slave computer nodes (information control nodes 1 to n and the remaining control nodes). The logical loops of the control ring bus and the information processing ring bus that can be constructed include but are not limited to the following:

[0060] (1), see Figure 4 As shown, two redundant rings (2 rings, each with 1 physical link for sending and receiving) are constructed to back up each other. In each computer node, two ring bus controllers are connected through a redundancy controller, so that the two related ring buses constructed are redundant with each other.

[0061] (2) See Figure 5 As shown, a loop containing two physical channels is constructed (one ring, two physical links for sending and receiving). It can be understood as follows: each node has a ring bus controller, and the two loops of the four nodes form a large loop.

[0062] (3) See Figure 6 As shown in the figure, two small loops are constructed, each of which can contain three adjacent computing nodes (several loops, with one physical link for each transmission and reception). This can be understood as: three adjacent nodes are connected to form a loop.

[0063] An embodiment of the present invention further provides a control method for a high-speed bus based on a ring network and time triggering, wherein the control method controls the operation of the high-speed bus based on a ring network and time triggering of the above embodiment, and the control method comprises the following steps:

[0064] Step 1: When the electronic system is powered on, a communication link is established with each computer node in each control-type ring bus according to the control function of each computer node, and a communication link is established with each computer node in each information processing-type ring bus according to the information computing function of each computer node, thereby completing the establishment of a logical loop;

[0065] Step 2: configuring a bus start period STOF for the computer node belonging to the master control node in the electronic system, and the master control node outputs an STOF synchronization frame to the ring bus controllers of the remaining computer nodes in the electronic system according to the bus start period STOF;

[0066] Step 3: Each of the control-type ring buses and each of the information processing-type ring buses receives or sends data based on the STOF synchronization frame, the ring bus control cycle, and the time slot information.

[0067] More specifically, the process of controlling the operation of the high-speed bus through the above control method is as follows:

[0068] (1) System power on;

[0069] (2) Establishing a connection between the control ring bus and the ring bus:

[0070] ——The adjacent computing nodes in the ring bus establish connections first;

[0071] ——All nodes establish connections for the entire loop based on the links established with adjacent nodes.

[0072] (3) Establish a connection between each information ring bus according to the system computing resource configuration:

[0073] ——The adjacent computer nodes in each ring bus establish connections first;

[0074] ——All computer nodes in each ring bus are connected to each other based on the links between adjacent nodes.

[0075] (4) Establish various logical links (i.e., communication links) according to the functional domains of the computer nodes. Each node, based on its own control function and information computing function, uses software-configurable logical crossbar switches to build various logical loops on the basis of physical links:

[0076] --The working cycle of the bus controller of the control bus of all nodes is consistent with the system control cycle;

[0077] ——The working cycle of the bus controller of the information processing ring bus of all nodes is based on the information processing functional domain (such as infrared, radar, etc.).

[0078] (5) The master node sets the STOF (Start of Frame) period: The STOF period can be set according to the system control period (for example, 5ms).

[0079] (6) The control ring bus where the master node is located periodically sends out STOF synchronization frames.

[0080] (7) The ring bus controllers on the control ring bus and information processing ring bus where all computing nodes are located are synchronized with the STOF synchronization frame, that is, the starting point of the bus cycle access is synchronized with the starting point of the STOF frame of the master node.

[0081] (8) Computer nodes in electronic systems, and the ring bus controllers on the control ring bus and information processing ring bus where they are located, receive data on the bus according to the STOF frame starting point, the ring bus control cycle, and the time slot information allocated to the node in the ring bus, and generate the bus output switching signal of the ring bus to control the data transmission of the corresponding physical channel. Specifically, it includes the following two processes:

[0082] --When the ring bus controller does not need to send data externally, the high-speed data receiving and forwarding unit of the physical channel splits the data output by the high-speed SDRDES receiver into two parts. One part sends the data to the external bus data input terminal of the ring bus controller according to the configuration of the software-configurable logical crossbar switch, and the other part forwards the data to the high-speed data sending unit of the corresponding physical channel according to the configuration of the software-configurable logical crossbar switch. The high-speed data sending unit forwards the data to the ring bus.

[0083] ——When the ring bus controller needs to send data outward, within the computing node's own time slot and when the bus data switching signal is valid, the bus output data is sent to the high-speed data sending unit of the corresponding physical channel according to the configuration of the software-configurable logical cross switch, and the high-speed data sending unit forwards the data to the ring bus.

[0084] The high-speed bus of the present invention is suitable for low-latency, high-speed data communications for various control and payload tasks in distributed computing platforms in supersonic unmanned aerial vehicles. It features flexible system expansion, low cost, high bus speed, simple bus protocol control logic, and convenient debugging. Specifically, the high-speed bus has the following advantages:

[0085] (1) The computing power of electronic systems can be flexibly arranged, and the system computing power distribution is more balanced, which reduces the difficulty of node thermal design.

[0086] (2) Fully utilize the various computing resources in the computing platform of the system. Through high-speed bus interconnection, high-determinism and low-latency data communication of various computing resources in the distributed computing platform is achieved, improving the utilization rate of system resources.

[0087] (3) A control ring bus and an information processing ring bus based on a time-triggered protocol are used to connect the devices in the system, ensuring the highly deterministic execution of strong real-time control tasks and information processing tasks in hypersonic aircraft.

[0088] (4) The physical link of the high-speed bus is a ring bus topology architecture. The topological relationship of the communication link can be defined by software and can meet the requirements of different application scenarios. At the same time, based on the physical link, the mapping of physical channel input channel, physical output channel and any ring bus controller can be realized through the software-configurable cross switch inside each node, and various logical rings can be constructed to meet the different application scenario requirements of control information processing and payload information processing for high reliability, strong real-time, high bandwidth, etc. For example, redundant loops can be constructed on any two ring physical links, thereby ensuring the reliability of data flow; for example, a logical ring with doubled bandwidth can be constructed on the basis of two physical links, thereby improving the communication bandwidth of information processing tasks; for example, adjacent nodes in the two rings can be constructed into several small rings according to the task deployment situation, thereby meeting the closed-loop communication requirements of different tasks.

[0089] (5) The present invention adopts a decentralized design concept. Compared with the conventional complex network switch design, it does not need to connect with peripheral devices in a point-to-point manner (that is, the switch node includes both physical ports for connecting to various peripheral devices and the design architecture of link switching functional circuits), which greatly reduces the system cost.

[0090] (6) The decoupling of front-end high-speed sensor data acquisition and control and back-end information processing is achieved, which is conducive to the agile upgrade of the system's core computing performance.

[0091] (7) The high-speed bus of the present invention is flexible to expand and easy to debug. The addition or removal of computer nodes in its physical link is relatively simple. It only needs to be connected to the corresponding physical link as required.

[0092] Obviously, those skilled in the art should understand that the various modules or steps of the above-mentioned embodiments of the present invention can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices. Alternatively, they can be implemented using program code executable by the computing device, so that they can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described can be performed in a different order than herein, or they can be made into separate integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. Thus, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0093] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A high-speed bus based on a ring network and time triggering, applied to supersonic unmanned aerial vehicles, characterized in that: The high-speed bus includes a control ring bus and multiple information processing ring buses. The physical link of the control ring bus is connected through all computer nodes in the electronic system to form a ring bus topology. The physical link of each information processing ring bus is connected through at least two computer nodes according to the system computing resource configuration to form a ring bus topology. The control-type ring bus and the information processing-type ring bus both include a ring bus controller, a high-speed data sending unit, and a high-speed data receiving unit located in each of the computer nodes in their physical links. The signal output end of the ring bus controller is connected to the high-speed data sending unit, and the signal input end of the ring bus controller is connected to the high-speed data receiving unit. The ring bus controller receives or sends data according to the data forwarding logic and time slot information.

2. The high-speed bus based on ring network and time triggering according to claim 1, characterized in that: The computer nodes include control nodes and information processing nodes. The control ring bus is set to one or two according to the time when each computer node starts working after the electronic system is powered on.

3. The high-speed bus based on ring network and time triggering according to claim 2, characterized in that: When all the computer nodes start working at the same time after the electronic system is powered on, there is one control ring bus; After the electronic system is powered on, the computer nodes in the first part start working at the same time, and the computer nodes in the second part start working after the computer nodes in the first part have been working for a period of time. There are two control ring buses, one of which connects all the computer nodes in the first part, and the other connects all the computer nodes in the second part.

4. The high-speed bus based on ring network and time triggering according to claim 1, characterized in that: The high-speed data receiving unit includes a high-speed serial SERDES receiver and a data receiving control logic module, the signal input end of the high-speed serial SERDES receiver is connected to the receiving port of the optoelectronic transceiver, and the signal output end of the high-speed serial SERDES receiver is connected to the signal input end of the ring bus controller; The high-speed data transmission unit includes a high-speed serial SERDES transmitter and a data transmission control logic module, the signal output end of the high-speed serial SERDES transmitter is connected to the signal transmission port of the optoelectronic transceiver, and the signal input end of the high-speed serial SERDES transmitter is connected to the signal output end of the ring bus controller; The ring bus controller includes a data forwarding control logic module and a time-triggered protocol control logic module. The data forwarding control logic module performs data forwarding logic configuration, and the time-triggered protocol control logic module performs data sending time slot and data receiving time slot configuration. According to the data forwarding logic, the bus data received by the high-speed data receiving unit is received and cached in the receiving data time slot, and the bus data is output in the sending data time slot.

5. The high-speed bus based on ring network and time triggering according to claim 4, characterized in that: The high-speed serial SERDES receiver and the high-speed serial SERDES transmitter each include any one of a GTX transceiver integrated in an FPGA, a GTH transceiver integrated in an FPGA, a SERDES serial-parallel interface driver, and a SERDES parallel-serial interface driver.

6. The high-speed bus based on ring network and time triggering according to claim 4, characterized in that: The high-speed data receiving unit includes a data buffer, and the data buffer is used to buffer the sent bus data.

7. The high-speed bus based on ring network and time triggering according to claim 1, characterized in that: The control-type ring bus and the information processing-type ring bus also include a logical cross switch located in each computer node in their physical links. The control end of the logical cross switch is connected to the ring bus controller, and the signal end is connected to the high-speed data sending unit and the high-speed data receiving unit. The ring bus controller controls the on-off of the logical cross switch according to the data forwarding logic.

8. The high-speed bus based on ring network and time triggering according to claim 1, characterized in that: When the high-speed bus includes the mutually redundant information processing type ring buses, the high-speed bus further includes a redundancy controller located in the computer node, and the redundancy controller is connected to the ring bus controller of the mutually redundant information processing type ring buses.

9. A control method for a high-speed bus based on a ring network and time triggering, characterized in that: The control method controls the operation of the high-speed bus based on the ring network and time triggering according to any one of claims 1 to 8, and the control method includes: When the electronic system is powered on, a communication link is established for each computer node in the control ring bus according to the control function of each computer node, and a communication link is established for each computer node in the information processing ring bus according to the information calculation function of each computer node, thereby completing the establishment of a logical loop; A bus start period STOF is configured for the computer node belonging to the master control node in the electronic system, and the master control node outputs an STOF synchronization frame to the ring bus controllers of the remaining computer nodes in the electronic system according to the bus start period STOF; Each of the control-type ring buses and each of the information processing-type ring buses receives or sends data based on the STOF synchronization frame, the ring bus control cycle and the time slot information.

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