Computing system, switch and data transmission method

Abstract

The embodiment of the invention provides a computing system, a switch and a data transmission method, and relates to the technical field of computing systems. The computing system comprises a first computing device, a second computing device, a first switch, a second switch and a plurality of first storage devices, wherein the first computing device is connected with the first switch, and the second computing device is connected with the second switch; each first storage device is connected with the first switch or the second switch, and at least one first storage device connected with the first switch is further connected with the second switch. In the embodiment of the invention, whether the first computing equipment or the second computing equipment accesses the data of the first storage equipment, the first computing equipment or the second computing equipment can directly access the first storage equipment through the switches connected with the first computing equipment or the second computing equipment without passing through other switches, so that the access time delay of accessing the first storage equipment is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of computing systems, and in particular, to a computing system, a switch, and a data transmission method. Background Art

[0002] With the development of artificial intelligence and big data, the volume of business has exploded. In order to process various businesses as quickly as possible, computing devices need to reduce the latency of accessing storage devices to increase data transmission speed. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a computing system, a switch, and a data transmission method for reducing the access delay of accessing a storage device.

[0004] In order to achieve the above purpose, the following technical solutions are provided:

[0005] In a first aspect, a computing system is provided. The computing system includes: a first computing device, a second computing device, a first switch, a second switch, and a plurality of first storage devices; the first computing device is connected to the first switch, and the second computing device is connected to the second switch; each first storage device is connected to the first switch or the second switch, and at least one first storage device connected to the first switch is also connected to the second switch.

[0006] In the above computing system, since at least one storage device is connected to the first switch and the second switch at the same time, when accessing data of the first storage device, both the first computing device and the second computing device can directly access the first storage device through the switches to which they are connected, without passing through other switches, thereby reducing the access delay to the first storage device.

[0007] In some optional implementations, the first switch and the second switch each include multiple memory exchange ports, each memory exchange port includes multiple docking ends; the first storage device includes a first type of connection end and a second type of connection end; wherein the first type of connection end corresponds one-to-one to and is connected to the docking end of the first switch, and the second type of connection end corresponds one-to-one to and is connected to the docking end of the second switch.

[0008] In the computing system provided by the present implementation, each memory exchange port of each first switch is connected to multiple first storage devices, so the number of channels provided by the first switch and the second switch to access a single first storage device is reduced, but the number of first storage devices accessible by the first switch and the second switch is increased, so that the total number of channels of the multiple first storage devices accessible by the first switch and the second switch remains unchanged, so the multiple first switches and the second switches can still provide high-bandwidth access channels to ensure high transmission efficiency between the first switch and the first storage device and between the second switch and the first storage device.

[0009] In some optional implementations, the first switch and the second switch both include multiple docking terminals; the first storage device includes a control chip and multiple memories; the memory expansion module includes a first type of connection terminal and a second type of connection terminal; wherein the first type of connection terminal corresponds to and is connected to the docking terminal of the first switch one-to-one, and the second type of connection terminal corresponds to and is connected to the docking terminal of the second switch one-to-one; the control chip also includes multiple memory connection terminals, and the multiple memory connection terminals correspond to and are connected to the multiple memories one-to-one. wherein more memories can be connected through the control chip to increase the memory capacity of the computing system.

[0010] In some optional implementations, the first switch and the second switch are not connected via a signal connection line.

[0011] In this implementation, the first switch and the second switch may not be connected by a signal connection line, so that the number of memory exchange ports in the first switch and the second switch that can be connected to the first storage device can be increased, and further, the number of first storage devices connected to the first switch and the second switch can be increased, thereby increasing the storage capacity of the computing system.

[0012] In some optional implementations, the method further includes: a third switch and a plurality of second storage devices; the third switch is connected to each second storage device; and the third switch is connected to the first switch or the second switch.

[0013] In this implementation, considering that the number of memory exchange ports in the first switch and the second switch and the number of docking ends in each memory exchange port are limited, the maximum number of first storage devices that can be connected to the first switch and the second switch is limited. To this end, the computing system is also provided with a third switch and a plurality of second storage devices, and the third switch is connected to each second storage device, thereby expanding the storage capacity of the computing system. At the same time, in order to ensure that the third switch can access the first storage device, the third switch can be connected to any one of the first switch and the second switch, or the third switch is connected to the first switch and the second switch at the same time, so that the third switch can access all the first storage devices and the second storage devices, and at least one of the first switch and the second switch can also access the second storage device.

[0014] In some optional implementations, at least part of the second storage device is connected to the first switch; and / or at least part of the second storage device is connected to the second switch.

[0015] In this implementation, at least part of the second storage devices are connected to the first switch or the second switch, and correspondingly, at least part of the first storage devices are connected to the third switch, that is, the number of second storage devices connected to the first switch or the second switch is equal to the number of first storage devices connected to the third switch, so that the first computing device or the second computing device can access part of the second storage devices through the corresponding switch without accessing across the second switch. Similarly, when the third switch is connected to the third computing device, the third computing device can access part of the first storage device through part of the third switch without accessing across other switches, thereby reducing access latency and improving the performance of the computing system.

[0016] In some optional implementations, a manager is further included, which is communicated with the first switch, the second switch and the third switch respectively; the manager is used to generate first routing information and second routing information according to the connection relationship between the first switch, the second switch and the third switch and the multiple first storage devices and the multiple second storage devices, and send the first routing information to the first switch and send the second routing information to the second switch; wherein the first routing information includes the shortest path for the first switch to access each first storage device and each second storage device; the second routing information includes the shortest path for the second switch to access each first storage device and the shortest path for the second switch to access each second storage device.

[0017] The first switch is used to store the first routing information, and the second switch is used to store the second routing information; the first switch is used to find the shortest path to access the storage device to be accessed according to the data request and the first routing information, and access the storage device to be accessed according to the shortest path; wherein the data request is used to indicate the storage device to be accessed; the storage device to be accessed is any one of the multiple first storage devices and the multiple second storage devices; or, the second switch is used to find the shortest path to access the storage device to be accessed according to the data request and the second routing information, and access the storage device to be accessed according to the shortest path.

[0018] In a second aspect, a switch is provided. The switch is the first switch or the second switch in the computing system provided in the first aspect, and the switch is configured to: receive a data request, the data request is used to indicate a storage device to be accessed, and the storage device to be accessed is any one of multiple first storage devices in the computing system; search for the shortest path to access the storage device to be accessed according to the data request; and access the storage device to be accessed according to the shortest path.

[0019] In a third aspect, a manager is provided, which is configured to: generate multiple routing information according to the connection relationship between the switch and multiple storage devices, where different routing information corresponds to the shortest path for different switches to access each storage device; and send the multiple routing information to the corresponding switches.

[0020] In a fourth aspect, a data transmission method is provided. The data transmission method is applied to a switch, which is the first switch or the second switch in the computing system provided in the first aspect. The data transmission method includes: receiving a data request, the data request is used to indicate a storage device to be accessed, and the storage device to be accessed is any one of the multiple first storage devices provided in the first aspect; searching for the shortest path to access the storage device to be accessed according to the data request; and accessing the storage device to be accessed according to the shortest path.

[0021] In some optional implementations, routing information is received from a manager, where the routing information includes the shortest path for each switch to access each storage device.

[0022] Among them, the technical effects brought about by any possible implementation method of the second aspect and the fourth aspect can refer to the technical effects brought about by different implementation methods of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0024] Figure 1 A schematic diagram of a computing system provided for some embodiments of the present application;

[0025] Figure 2 A schematic diagram of the architecture of a computing system provided for some embodiments of the present application;

[0026] Figure 3 A schematic diagram of the architecture of a computing system provided for some other embodiments of the present application;

[0027] Figure 4 A schematic diagram of the architecture of a computing system provided for some embodiments of the present application;

[0028] Figure 5 A schematic diagram of the architecture of a computing system provided for some other embodiments of the present application;

[0029] Figure 6 A schematic diagram of the architecture of a computing system provided for some embodiments of the present application;

[0030] Figure 7 A schematic diagram of the architecture of a computing system provided for some embodiments of the present application;

[0031] Figure 8 A schematic diagram of the architecture of a computing system provided for some embodiments of the present application;

[0032] Fig. 9 A flowchart of a data transmission method provided in some embodiments of the present application. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only embodiments of a part of the present application, rather than all embodiments. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0034] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] It should be understood that in the embodiments of the present application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three or more, and "at least one of the following (items)" or similar expressions refers to any combination of these items, including any combination of single or plural items (items). For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0036] Through the description of the following implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and conciseness of the description, only the division of the following functional modules is used as an example. In actual applications, the following functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described below.

[0037] Figure 1 A schematic diagram of the structure of a computing system provided in an embodiment of the present application.

[0038] like Figure 1 As shown, the computing system 100 may include a computing device 108 and an extended storage device. The computing device 108 is provided with a local storage device, and the computing system local storage device may include a main memory 104 and a solid state disk (SSD) 106.

[0039] The central processing unit (CPU) 101 can access data stored in registers 102, cache 103, and other data storage devices. For example, the central processing unit 101 can also access data in the main memory 104 and the solid-state drive 106.

[0040] For example, the main memory 104 may be a dynamic random access memory, a double data rate synchronous dynamic random access memory (DDR SDRAM) or other types of memory. The main memory 104 may be referred to as a main memory, i.e., a memory that exchanges information with the central processor 101 in the computing device.

[0041] In this embodiment, due to the limited package pins of the central processor 101 and the limitation of the mainboard layout of the computing device, it is difficult for the memory channel to continue to grow and cannot meet the storage capacity requirements of the computing device. To this end, the computing device can be connected to an external expansion storage device to expand the storage capacity of the computing device through the expansion storage device. For example, the expansion storage device can include a remote memory (far memory) 105.

[0042] Compared with local storage devices, extended storage devices have large storage capacity, slow access speed, and large access delay. For example, the access delay of register 102 is about 0.2 nanoseconds (ns), the access delay of cache 103 is about 40ns, the access delay of main memory 104 ranges from about 80ns to 140ns, the access delay of remote memory 105 ranges from about 2μs to 4 microseconds (μs), and the access delay of solid-state drive 106 ranges from about 50μs to 100μs. It can be seen that the memory capacity of the extended storage device increases, but the access speed also decreases step by step, and the access delay increases step by step. The increase in delay will lead to a decrease in the performance of the computing system, so how to reduce the delay of the processor accessing the extended memory becomes a problem to be solved.

[0043] In some optional embodiments, the registers 102 and cache 103 of other central processors 101 can also be used as extended memory, and the access delay of the registers 102 and cache 103 of other CPUs ranges from about 170ns to 250ns, because addressing and other operations are required when accessing the remote memory 105, and the main technology used by the solid-state drive 106 is NAND flash memory. When performing a write operation, an erase operation needs to be performed first, which will increase the access delay, so compared with the remote memory 105 and the solid-state drive 106, the access delay of the registers 102 and cache 103 of other CPUs is lower, but the memory capacity of the registers 102 and cache 103 of other CPUs is limited and cannot meet the storage requirements of the computing device.

[0044] To this end, the extended storage device in the embodiment of the present application may also include a storage device 107, the storage device 107 supports the computer express link (CXL) protocol, and the computing device is connected to the storage device 107 to use the storage device 107 as an extended storage device of the computing device. Of course, in other embodiments, the extended storage device may also include only the storage device 107, without including the remote memory 105. Alternatively, in other embodiments, the storage device and the storage device may support protocols other than the CXL protocol, as long as the latency of the computing device accessing the storage device is small.

[0045] It should be noted that the CXL protocol is an open interconnection protocol that enables high-speed and efficient interconnection between CPUs and graphics processors (GPUs), field-programmable gate arrays (FPGAs) or other accelerators, thereby meeting the requirements of high-performance heterogeneous computing. The CXL protocol supports the CPU of a computing device to access a CXL storage device without occupying the memory slot of the computing device.

[0046] That is, a storage device (hereinafter referred to as "storage device") 107 supporting the CXL protocol can be connected to a computing device as an extended memory, and the computing device can access the memory of the storage device through the CXL protocol just as it accesses local memory through a memory channel within the computing device. Typically, a computing device is connected to a CXL storage device via a CXL link. Specifically, the CXL protocol supports dynamic random access memory (DRAM), high bandwidth memory (HBM), persistent memory (PMEM), and storage-class memory (SCM) as extended memory.

[0047] Figure 2 It is a schematic diagram of the architecture of a computing system 100 provided in an embodiment of the present application.

[0048] like Figure 2 As shown, the computing system 100 may include a computing device 108 and a storage device 107. The computing device 108 may be a server, a host, or other device with storage space (such as memory) expansion requirements. Figure 2 The particular form of computing device 108 shown is not intended to be limiting.

[0049] The computing device 108 may be multiple, for example Figure 2There are two computing devices shown, namely, a first computing device 110 and a second computing device 112. The computing device 108 may include a CPU, a GPU or other devices with processing capabilities, so that the storage device 107 can be read and written through the CXL protocol according to application requirements.

[0050] The storage device 107 includes a control chip 1071 and multiple memories 1072. The control chip includes multiple connection terminals. Exemplarily, the connection terminal of the control chip 1071 may be a CXL bus interface, wherein the connection terminal of the control chip 1071 may be connected to the computing device 108, so that the computing device 108 may access the memory 1072 through the control chip 1071.

[0051] It is understandable that the control chip 1071 may also be referred to as a memory expansion (CXL memory expander) chip, a CXL memory controller (CXL memory expander controller) or a CXL memory pooling (CXL memory expander pooling) chip.

[0052] The memory 1072 may be a non-volatile memory (NVM) or a volatile memory. For example, the memory 1072 may be a dual inline memory module (DIMM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a solid state drive (SSD), or a persistent memory (PMEM). The memory 1072 is an actual physical carrier that provides storage space for the computing device.

[0053] The memory 1072 may be one or more. When there is one memory 1072, the memory 1072 may be a dual inline memory DIMM or a solid state drive SSD. When there are multiple memories 1072, the multiple memories 1072 may all be dual inline memory DIMMs, or the multiple memories may all be solid state drives SSDs, or some of the multiple memories 1072 may be dual inline memory DIMMs and some may be solid state drives SSDs.

[0054] Of course, in other embodiments, when the memory 1072 is one, the memory 1072 may also be other types of memory such as SDRAM or PMEM. When the number of memories 1072 is multiple, the multiple memories 1072 may all be other types of memory such as SDRAM or PMEM, or the multiple memories may include at least two of SDRAM, PMEM, DIMM or SSD. The above-mentioned flexible implementation and deployment methods can make the computing device compatible with memories 1072 of more media types. The embodiments of the present application do not limit the media type, quantity and deployment method of the memory 1072. It is understandable that with the development of technology, the memory 1072 may also be other storage types of memory or hard disk.

[0055] The control chip 1071 can connect multiple memories 1072 to the computing device 108, and provide an access channel that supports the CXL protocol, so that the computing device 108 can access the memory 1072 through the CXL protocol. In other words, the storage device 107 can be connected to the computing device 108 as an extended memory through the CXL bus interface, thereby increasing the storage capacity of the computing device 108 by an order of magnitude and greatly expanding the storage capacity. Specifically, the CXL protocol allows the computing device 108 to increase its storage capacity to tens of terabytes (TB) through the storage device.

[0056] It is understood that in a specific implementation, the computing system 100 may be any Figure 2 The present application embodiment does not limit the specific composition structure of the computing system 100. In addition, Figure 2 The components shown in the figure do not constitute a limitation on the computing system 100. Figure 2 In addition to the components shown, computing system 100 may include more or fewer components than shown, or combine certain components, or arrange the components differently. Figure 2 The positional relationship between the storage device 107 and the computing device is only an example, and the storage device may also be disposed within the computing device.

[0057] In this embodiment, the computing device 108 in the computing system 100 can access the memory 1072 through the control chip 1071 in the storage device 107. The latency range of accessing the memory 1072 is about 170ns-250ns. Compared with the remote memory 105 and the solid-state drive 106, the latency of accessing the storage device 107 is lower. Therefore, the computing device 108 can use the storage device 107 as its own extended storage space through the CXL protocol to expand the capacity of the computing device. However, the number of ports of the control chip 1071 in the storage device 107 is limited, generally not more than 8 ports. Therefore, the number of computing devices 108 that can be interconnected through the control chip 1071 is limited, and only a small number of computing devices or clusters can be connected.

[0058] In order to solve the above problems, an embodiment of the present application further provides a computing system 100. Figure 3 The schematic diagram of the architecture of a computing system 100 provided in an embodiment of the present application is shown. The computing system may include a computing device 108, a switch 120, a storage device 107 and a manager 140. The computing device 108 is connected to the storage device 107 via the corresponding switch 120.

[0059] The number of computing devices 108 may be multiple, for example Figure 3 The first computing device 110, the second computing device 112, the third computing device 113, and the fourth computing device 114 are shown. Each computing device 108 is used to read and write the storage device 107 through the CXL protocol and the corresponding switch 120 according to application requirements. It can be understood that each computing device 108 can be connected to a switch 120, and multiple computing devices 108 can be connected to the same switch 120 or to different switches 120, which is not limited in the embodiment of the present application.

[0060] The switch 120 is a compute express link switch (CXL switch) supporting the CXL protocol, and is used to connect multiple storage devices and provide high-performance, low-latency data transmission. In this embodiment, the switch 120 can be one or more. When the switch 120 is one, multiple computing devices 108 are connected to the switch 120, and the switch 120 is also connected to one or more storage devices 107. The computing device 108 can be connected to the storage device 107 through the switch 120.

[0061] When there are multiple switches 120, multiple computing devices 108 can be connected to corresponding switches 120 respectively, and multiple switches 120 are interconnected. For example, Figure 3The first switch 121, the second switch 122, the third switch 123, the fourth switch 124, the fifth switch 125 and the sixth switch 126 are shown. The first switch 121 is connected to the first computing device 110 and the third computing device 113, the second switch 122 is connected to the second computing device 112 and the fourth computing device 114, and the first switch 121 is connected to the third switch 123 and the fourth switch 124 respectively, the second switch 122 is connected to the third switch 123 and the fourth switch 124 respectively, the third switch 123 is connected to the fifth switch 125 and the sixth switch 126 respectively, and the fourth switch 124 is connected to the fifth switch 125 and the sixth switch 126 respectively.

[0062] It is understandable that the above-mentioned topological connection structure between the switches 120 is merely exemplary, as long as each computing device 108 can access each storage device 107 through the topological structure between the switches 120 .

[0063] Each switch 120 is connected to at least one storage device 107, and the connection mode may be through a wired or optical fiber cable. Exemplarily, the first switch 121 and the second switch 122 are each connected to one storage device 107, and the third switch 123, the fourth switch 124, the fifth switch 125, and the sixth switch 126 are each connected to multiple storage devices 107. The first switch 121 and the second switch 122 provide a high-bandwidth and low-latency data transmission channel for the computing device 108 connected thereto, so that the computing device 108 and the storage device 107 can communicate and exchange data quickly and efficiently.

[0064] The fabric manager (FM) 140 is connected to each switch 120 in communication, for example, the fabric manager 140 is connected to the first switch 121, the second switch 122, the third switch 123, the fourth switch 124, the fifth switch 125 and the sixth switch 126 in communication. The fabric manager 140 is a process for managing the storage space of the storage device. The fabric manager 140 may run in the CPU or baseboard management controller (BMC) of any computing device 108, or in the processor of the switch 120, or the fabric manager FM may run in the CPU, BMC or controller of an independent device. The embodiment of the present application does not limit the specific running location of the fabric manager FM.

[0065] It should be noted that different computing devices have different names for BMC, for example, some computing devices 108 are called BMC, some computing devices 108 are called iLO (Integrated lights-out), and some computing devices 108 are called Integrated Dell Remote Access Controller (iDRAC). Whether it is called BMC, iLO or iDRAC, it can be understood as the BMC in the embodiments of the present application.

[0066] The manager 140 is connected in communication with each computing device 108 and the switch 120 to obtain information about the storage devices 107 connected to the multiple switches 120 and manage the space of these storage devices 107. When the computing device 108 applies for storage space from the manager FM, the manager FM can allocate storage space of corresponding capacity to the computing device 108, so that the computing device 108 can use the allocated storage space.

[0067] The computing system is further described below by taking an example in which the computing system includes two computing devices, two switches, and each switch includes 16 memory exchange ports.

[0068] In a specific example, Figure 4 The schematic diagram of the architecture of a computing system 100 provided by an embodiment of the present application is shown. The computing system 100 may include a first computing device 110, a second computing device 112, a first switch 121, a second switch 122, a plurality of storage devices 107 and a manager 140.

[0069] The storage device 107 includes a plurality of first storage devices 131 and a plurality of second storage devices 132. The first switch 121 includes 16 memory exchange ports, and each memory exchange port includes 16 docking terminals. One of the 16 memory exchange ports of the first switch 121 is connected to the first computing device 110, and another memory exchange port of the first switch 121 is connected to the second switch 122. Therefore, the remaining 14 memory exchange ports of the first switch 121 can be connected to one first storage device 131 respectively.

[0070] In order to ensure that the communication between the first switch 121 and the first storage device 131 has sufficient bandwidth, see Figure 4, each memory exchange port of the first switch 121 needs to be connected to a first storage device 131 through a connection line X16, even if the 16 docking ends of each memory exchange port of the first switch 121 are connected to a first storage device 131, in other words, the first switch 121 can only connect to 14 first storage devices 131. Similarly, the second switch 122 can only connect to 14 second storage devices 132, so a total of 28 storage devices can be connected through the first switch 121 and the second switch 122.

[0071] The first switch 121 can directly access the first storage device 131, and can also access the second storage device 132 through the second switch 122. However, since the first switch 121 needs to access the second switch 122 first when accessing the second storage device 132, the latency is relatively high. Similarly, the second switch 122 can directly access the second storage device 132, and can also access the first storage device 131 through the first switch 121. However, since the second switch 122 needs to access the first switch 121 first when accessing the first storage device 131, the access latency is relatively high.

[0072] It is understandable that when the computing system 100 includes multiple computing devices 108 and multiple switches 120, based on the complex topology between the computing devices 108, the switches 120 and the storage devices 107, when the computing device 108 wants to access a storage device, it may need to access multiple switches 120, for example. Figure 3 When the first computing device 110 connected to the first switch 121 wants to access the storage device connected to the fifth switch 125, it needs to access the first switch 121, the third switch 123, and the fifth switch 125 in sequence before accessing the storage device connected to the fifth switch 125. For each additional level of switch 120 that needs to be accessed, the latency of the computing device accessing the storage device may increase by 100ns-150ns, thereby further affecting the performance of the computing system. At the same time, due to the interconnection structure between the switches 120, the memory exchange port of the switch 120 will also be occupied, reducing the number of connections of the storage devices of the computing system, thereby reducing the storage capacity of the computing system.

[0073] To this end, the present application embodiment also provides a computing system 100, see Figure 5 , Figure 5The schematic diagram of the architecture of a computing system 100 provided by an embodiment of the present application is shown. The computing system 100 includes a first computing device 110, a second computing device 112, a first switch 121, a second switch 122, and a plurality of first storage devices 131. The first computing device 110 is connected to the first switch 121, and the second computing device 112 is connected to the second switch 122; each first storage device 131 is connected to the first switch 121 or the second switch 122, and at least one first storage device 131 connected to the first switch 121 is also connected to the second switch 122. In other words, at least one first storage device 131 is connected to the first switch 121 and the second switch 122 at the same time. Exemplarily, the connection mode may be through a wired or optical fiber cable.

[0074] At least one first storage device 131 is connected to the first switch 121 and the second switch 122 at the same time, including multiple situations: one is that only one first storage device 131 among the multiple first storage devices 131 is connected to the first switch 121 and the second switch 122 at the same time, and the other first storage devices 131 among the multiple first storage devices 131 are either connected to the first switch 121 or the second switch 122. In this way, the first computing device 110 can directly access the first storage device 131 through the first switch, and the second computing device 112 can directly access the first storage device 131 through the second switch 122, without the need for cross-switch access, thereby reducing the access delay between the computing device and a storage device.

[0075] For example, if the first computing device 110 wants to access the first storage device 131-m1, the first computing device 110 only needs to send a data request to the first switch 121 connected to the first computing device 110, and the data request is used to indicate the first storage device 131-m1 to be accessed. The first switch 121 responds to the data request, obtains the address of the first storage device 131-m1 to be accessed, and accesses the first storage device 131-m1 according to the address of the first storage device 131-m1 without passing through the second switch, thereby reducing the access delay between the computing device and the storage device.

[0076] One is that some of the first storage devices 131 among the multiple first storage devices 131 are connected to the first switch 121 and the second switch 122 at the same time, and another part of the first storage devices 131 among the multiple first storage devices 131 are connected to either the first switch 121 or the second switch 122. In this way, the first computing device 110 can directly access the part of the first storage devices 131 through the first switch, and the second computing device 112 can directly access the part of the first storage devices 131 through the second switch 122, without the need to access across switches, thereby reducing the access latency between the computing device and the part of the storage devices.

[0077] For example, there are 26 first storage devices 131 connected to the first switch 121 and the second switch 122 at the same time, 2 first storage devices 131 are connected to the first switch 121, and 2 first storage devices 131 are connected to the second switch device. In this way, the first computing device 110 can directly access the 28 first storage devices 131 through the first switch 121, and the second computing device 112 can directly access the 28 first storage devices 131 through the second switch 122, without the need for cross-switch access, thereby reducing the access latency between the computing device and the storage device.

[0078] One is, Figure 5 Each of the multiple first storage devices 131 shown is connected to both the first switch 121 and the second switch 122. In this way, the first computing device 110 can directly access each first storage device 131 through the first switch, and the second computing device 112 can directly access each first storage device 131 through the second switch 122 without cross-switch access, thereby reducing the access latency between the computing device and each storage device.

[0079] In other embodiments, only some of the first storage devices 131 in the computing system 100 may be connected to the first switch 121 and the second switch 122 at the same time.

[0080] In other embodiments, more than two computing devices and a greater number of switches may be provided in the computing system, and each switch may be connected to multiple storage devices. When the number of computing devices is greater than the number of switches, multiple computing devices may be connected to the same switch, and when the number of computing devices is less than the number of switches, the computing devices may be connected to multiple switches, or the computing devices may correspond to and be connected to some switches one by one, and the switches not connected to the computing devices may be connected to the switches connected to the computing devices, so that the computing devices may access all storage devices through one or more switches.

[0081] Figure 5In the example shown, since the first switch 121 is connected to all the first storage devices 131 and the second switch 122 is also connected to all the first storage devices 131, the first switch 121 and the second switch 122 do not need to access the first storage devices 131 through other switches. Therefore, in an optional embodiment, the first switch 121 and the second switch 122 are not connected through a signal connection line.

[0082] exist Figure 4 In the computing system shown, a signal connection line is required between the first switch 121 and the second switch 122 for connection, so that the first switch 121 can access the second storage device through the second switch 122, and the second switch 122 can access the first storage device through the first switch 121. The signal connection line can be a transmission carrier such as a wire or an optical fiber cable. In this embodiment, no signal connection line is set between the first switch 121 and the second switch 122 for connection, so that the number of memory exchange ports that can be connected to the first storage device 131 in the first switch 121 and the second switch 122 can be increased, and then the number of first storage devices 131 connected to the first switch 121 and the second switch 122 can be increased, so that the storage capacity of the computing system can be increased. At this time, one connection end of the memory exchange port of the first switch 121 is connected to the first computing device 110, and each of the remaining connection ends can be connected to a first storage device 131 respectively. Similarly, one connection end of the memory exchange port of the second switch 122 is connected to the second computing device 112, and each of the remaining connection ends can be connected to a first storage device 131 respectively.

[0083] For example, the first switch 121 includes 16 memory exchange ports, wherein one memory exchange port in each first switch 121 is connected to the first computing device 110, and the remaining 15 memory exchange ports are respectively connected to the corresponding first storage device 131. Figure 4 The computing system shown is connected to the storage device via 14 memory exchange ports. The computing system provided by this embodiment has a higher storage device density and a larger storage capacity.

[0084] The following is an illustrative description of each part of the computing system in the above embodiment.

[0085] See also Figure 6 , Figure 6The schematic diagram of the architecture of a computing system 100 provided by an embodiment of the present application is shown. The computing system 100 may include a first computing device 110, a second computing device 112, a first switch 121, a second switch 122, a plurality of first storage devices 131 and a manager 140. The first computing device 110 is connected to the first switch 121, and the second computing device 112 is connected to the second switch 122; the first switch 121 is connected to each first storage device 131, and the second switch 122 is connected to each first storage device 131; illustratively, the connection mode may be connected by wire or optical fiber cable. The plurality of first storage devices 131 are respectively a first storage device 131-1, a first storage device 131-2, a first storage device 131-3, a first storage device 131-4, a first storage device 131-5, ... a first storage device 131-30. No signal connection line is set between the first switch 121 and the second switch 122 for connection.

[0086] The first switch 121 includes a plurality of memory exchange ports, each memory exchange port includes a plurality of docking terminals, and accordingly, the first storage device 131 includes a plurality of connection terminals, a portion of which are first-type connection terminals, and another portion are second-type connection terminals. The first-type connection terminals of the first storage device 131 correspond one-to-one to and are connected to the docking terminals of the first switch 121, and the second-type connection terminals of the first storage device 131 correspond one-to-one to and are connected to the docking terminals of the second switch 122. For example, the first storage device 131 includes 16 connection terminals, 8 of which are first-type connection terminals and 8 are second-type connection terminals, then the 8 first-type connection terminals of the first storage device 131 correspond one-to-one to and are connected to the docking terminals of the first switch 121, and the 8 second-type connection terminals of the first storage device 131 correspond one-to-one to and are connected to the docking terminals of the second switch 122. Therefore, the first storage device 131 is connected to the first switch 121 and the second switch 122 respectively, and the first switch 121 and the second switch 122 both provide a high-bandwidth data transmission channel for accessing the first storage device 131, which can ensure high transmission efficiency between the first switch 121 and the second switch 122 and the first storage device 131.

[0087] In other examples, the connection ends of the first storage device 131 may all be first connection ends, so that the first storage device 131 is only connected to the first switch 121, or the connection ends of the first storage device 131 may all be second connection ends, so that the first storage device 131 is only connected to the second switch 122.

[0088] Specifically, the first storage device 131 includes a control chip 1071 and multiple memories 1072; the control chip 1071 includes a first type connection terminal and a second type connection terminal; wherein the first type connection terminal of the control chip 1071 can be used as the first type connection terminal of the first storage device 131 to correspond to and connect with the docking terminal of the first switch 121, and the second type connection terminal of the control chip 1071 can be used as the second type connection terminal of the first storage device 131 to correspond to and connect with the docking terminal of the second switch 122; the control chip 1071 also includes multiple memory connection terminals, and the multiple memory connection terminals are used to connect with multiple memories 1072. The control chip 1071 connects the first switch 121 with the multiple memories 1072 through the first type connection terminal, and connects the second switch 122 with the multiple memories 1072 through the second type connection terminal.

[0089] Exemplarily, the first switch 121 includes 16 memory exchange ports, each memory exchange port includes 16 docking ends, that is, the number of docking ends of each first switch is 256. Accordingly, the number of connection ends of each first storage device is 16, wherein one memory exchange port of the first switch 121 is connected to the first computing device 110, and the remaining 15 memory exchange ports are respectively connected to one first storage device 131, so that the first switch can connect more first storage devices 131.

[0090] A part of the docking ends of each memory exchange port of the first switch 121 is connected to a first storage device 131, and another part of the docking ends of each memory exchange port is connected to another first storage device 131. Of course, each memory exchange port of the first switch 121 can also be connected to more than two first storage devices 131. In other words, the memory exchange ports of the first switch 121 are connected to at least two first storage devices 131 through the connection ends to ensure that each first switch 121 is connected to all the first storage devices 131, so that the first switch can be connected to more first storage devices. The second switch 122 is connected to the first storage device 131 in the same way.

[0091] For example, Figure 6 The connection mode of the first switch 121 and the second switch 122 and the plurality of first storage devices 131 is shown, wherein Figure 6The first switch 121 shown in the figure is connected to the plurality of first storage devices 131 through the connection lines ×8, which means that each of the 15 memory exchange ports of the first switch 121 has 8 docking ends connected to the 8 first-type connection ends of one first storage device 131, and the remaining 8 docking ends are connected to the 8 first-type connection ends of another first storage device 131. The second switch 122 is connected to the first storage device 131 through the connection lines ×8, which means that each of the memory exchange ports of the second switch 122 has 8 docking ends connected to the 8 second-type connection ends of the first storage device 131, and the remaining 8 docking ends are connected to the 8 second-type connection ends of another first storage device 131, so that the number m1 of the first storage devices 131 connected to the first switch 121 and the second switch 122 is 30. Figure 4 In the computing system shown, the number of storage devices 107 commonly connected to the first switch 121 and the second switch 122 is only 28, which shows that the computing system of this embodiment has a higher density of storage devices connected and has a larger storage capacity.

[0092] It should be noted that the number of docking ends connected to a single first storage device 131 in the first switch 121 and the second switch 122 can be adjusted so that the first switch 121 and the second switch 122 can connect to more first storage devices. For example, each memory exchange port of the first switch 121 includes 16 docking ends, so that every 4 docking ends in each memory exchange port of the first switch 121 are connected to the same first storage device 131, that is, each memory exchange port of the first switch 121 is connected to a total of 4 different first storage devices 131, so that the first switch 121 can connect to 60 first storage devices 131. It can be understood that the above examples are only examples listed for better understanding of the technical solutions of the embodiments of the present application. In some examples, 10 docking ends of the first memory exchange port of the first switch 121 are respectively connected to 10 first-type connection ends of the first storage device 131, and the remaining 6 connection ends are connected to 6 first-type connection ends of another first storage device 131. Correspondingly, 6 docking ends of the first memory exchange port of the second switch 122 are connected to 6 second-type connection ends of the first storage device 131, and the remaining 10 docking ends are connected to 10 second-type connection ends of the first storage device 131. Those skilled in the art can set the number of first-type connection ends of each first storage device 131 connected to the first switch 121 and the number of second connection ends connected to the second switch 122 according to actual needs, so that the first switch 121 and the second switch 122 can provide a high-bandwidth data transmission channel for accessing the first storage device 131.

[0093] The manager 140 is respectively connected to the first switch 121 and the second switch 122 for communication. The manager 140 generates first routing information and second routing information according to the connection relationship between the first switch 121, the second switch 122 and the plurality of first storage devices 131.

[0094] The first switch 121 stores first routing information, and the second switch 122 is used to store second routing information; wherein the first routing information includes the access address of the first switch 121 to access each first storage device 131; the second routing information includes the access address of each second switch 122 to access each first storage device 131.

[0095] When the first computing device 110 receives a service request to access the first storage device 131, the first computing device 110 selects whether to execute the service request to access the first storage device 131 itself or assign it to the second computing device 112 according to its own working conditions and the working conditions of the second computing device 112. When the first computing device 110 is processing a service, it is in a "working state", otherwise it is in an "idle state".

[0096] For example, when the first computing device 110 is in a "working state", a service request for accessing the first storage device 131-1 is received. In order to speed up the processing of the service, the service request can be forwarded to the second computing device 112, so that the second computing device 112 in an "idle state" processes the service request for accessing the first storage device 131-1. In response to the service request, the second computing device 112 generates a data request and sends it to the second switch 122. The data request is used to indicate the first storage device 131-1 to be accessed; the second switch 122 searches for the address of the first storage node 131-1 from the routing information stored in itself according to the data request; and accesses the first storage device 131-1 according to the address of the first storage node 131-1.

[0097] Since each memory exchange port of each first switch 121 in the computing system provided by this embodiment is connected to multiple first storage devices 131, compared with Figure 4In the computing system shown, each memory exchange port of each first switch is connected to only one storage device. In this embodiment, the number of channels provided by the first switch 121 and the second switch 122 for accessing a single first storage device 131 is reduced, but the number of first storage devices accessible by the first switch 121 and the second switch 122 is increased, so that the total number of channels provided by the first switch 121 and the second switch 122 for accessing multiple first storage devices 131 remains unchanged. Therefore, multiple first switches 121 and the second switch 122 can still provide high-bandwidth access channels to ensure high transmission efficiency between the first switch 121 and the first storage device 131 and between the second switch 122 and the first storage device 131.

[0098] At the same time, the first switch 121 and the second switch 122 are both connected to all the first storage devices 131, so that the first switch 121 and the second switch 122 can directly access all the first storage devices 131 without cross-switch access, thereby reducing access latency and improving storage device density and having a larger storage capacity.

[0099] It can be understood that the above examples are only provided to better illustrate the computing system provided by the present embodiment. The number of first storage devices connected to the first switch and the second switch is related to the number of memory exchange ports of the first switch and the second switch and the number of docking ends of each memory exchange port. When the number of memory exchange ports of the first switch and the second switch and the number of docking ends of each memory exchange port are different, the number of connected first storage devices also changes accordingly, and this application does not make specific limitations.

[0100] In an optional embodiment, in order to further increase the storage capacity of the computing system, the number of storage devices in the computing system may be further increased. Figure 7 , Figure 7 FIG. 1 is a schematic diagram showing an architecture of a computing system 100 provided in an embodiment of the present application. Figure 6 Based on the computing system shown, the computing system 100 may further include a third switch 123 and a plurality of second storage devices 132. The third switch 123 is connected to each second storage device 132; the third switch 123 is connected to the first switch 121 and / or the second switch 122, and the connection may be through a wired or optical fiber cable.

[0101] Considering the limited number of memory exchange ports in the first switch 121 and the second switch 122 and the limited number of docking ports in each memory exchange port, the maximum number of first storage devices 131 that can be connected to the first switch 121 and the second switch 122 will be limited. To this end, in the embodiment of the present application, the computing system 100 is further provided with a third switch 123 and a plurality of second storage devices 132, and the third switch 123 is connected to each second storage device 132, thereby expanding the storage capacity of the computing system, and at the same time, in order to ensure that the third switch 123 can access the first storage device 131. The third switch 123 can be connected to any one of the first switch 121 and the second switch 122, or the third switch 123 is connected to the first switch 121 and the second switch 122 at the same time, so that the third switch can access all the first storage devices 131 and the second storage devices 132, and at least one of the first switch 121 and the second switch 122 can also access the second storage device 132.

[0102] In a specific example, see Figure 7 , Figure 7 The schematic diagram of the architecture of a computing system 100 provided by an embodiment of the present application is shown. The computing system 100 may include a first computing device 110, a second computing device 112, a first switch 121, a second switch 122, a third switch 123, a plurality of first storage devices 131 and a plurality of second storage devices 132.

[0103] The first computing device 110 is connected to the first switch 121, and the second computing device 112 is connected to the second switch 122; the first switch 121 is connected to each first storage device 131, the second switch 122 is connected to each first storage device 131, and the third switch 123 is connected to each second storage device 132; illustratively, the connection mode may be connected by wire or optical fiber cable. The plurality of first storage devices 131 are respectively the first storage device 131-1, the first storage device 131-2, the first storage device 131-3, the first storage device 131-4, the first storage device 131-5, ... the first storage device 131-30. No signal line connection is set between the first switch 121 and the second switch 122. The plurality of second storage devices 132 are respectively the second storage device 132-1, the second storage device 132-2, the second storage device 132-3, ... the first storage device 132-14. The third switch 123 is connected to the second computing device 112-1.

[0104] The first switch 121 includes a plurality of memory exchange ports, each of which includes a plurality of docking terminals. Accordingly, the first storage device 131 includes a plurality of connection terminals, a portion of which are first-type connection terminals, and another portion of which are second-type connection terminals; wherein the first-type connection terminals of each first storage device 131 correspond to and are connected to the docking terminals of the first switch 121 one by one, and the second-type connection terminals of each first storage device 131 correspond to and are connected to the docking terminals of the second switch 122 one by one. Thus, the first switch 121 and the second switch 122 both provide a high-bandwidth data transmission channel for accessing the first storage device 131, which can ensure a high transmission efficiency between the first switch 121 and the second switch 122 and the first storage device 131.

[0105] Exemplarily, the first switch 121 includes 16 memory exchange ports, each memory exchange port includes 16 docking ends, that is, the number of docking ends of each first switch is 256. Correspondingly, the number of connection ends of each first storage device is 16, wherein one memory exchange port of the first switch 121 is connected to the first computing device 110, and each of the remaining 15 memory exchange ports is connected to a first storage device 131. A part of the docking ends of each memory exchange port of the first switch 121 is connected to a first storage device 131, and another part of the docking ends of each memory exchange port is connected to another first storage device 131, that is, the memory exchange ports of the first switch 121 can be connected to two first storage devices 131 through the connection ends, so as to ensure that each first switch 121 is connected to all the first storage devices 131, so that the first switch can connect more first storage devices. Of course, the memory exchange ports of the first switch 121 can be connected to more than two first storage devices 131 through the connection ends.

[0106] One memory exchange port of the second switch 122 is connected to the second computing device 112, another memory exchange port is connected to one memory exchange port of the third switch 123, and the remaining 14 memory exchange ports are all connected to the first storage device. One memory exchange port of the third switch 123 is connected to one memory exchange port of the second switch 122, and the remaining 15 memory exchange ports are all connected to the second storage device 132.

[0107] For example, Figure 7As shown, 14 memory exchange ports in the first switch 121 are connected to a plurality of first storage devices through a connection line X8, that is, 8 docking ends of each memory exchange port in the 14 memory exchange ports of the first switch 121 are respectively connected to 8 first-type connection ends of a first storage device, and the remaining 8 docking ends are respectively connected to 8 first-type connection ends of another first storage device, so that the first switch 121 is connected to 28 first storage devices through the 14 memory exchange ports. The remaining one memory exchange port in the first switch 121 is connected to the 28th first storage device through the connection line X5, and is connected to the 29th first storage device through the connection line X11, that is, 5 docking ends of the remaining one memory exchange port of the first switch 121 are respectively connected to 5 first-type connection ends of the 28th first storage device, and the remaining 11 docking ends are respectively connected to 11 first-type connection ends of the 29th first storage device, so that the first switch 121 is connected to a total of 29 first storage devices through the 15 memory exchange ports.

[0108] There are 13 memory exchange ports in the second switch 122 connected to multiple first storage devices 131 through the connection line X8, that is, 8 docking ends of each of the 13 memory exchange ports in the first switch 121-2 are respectively connected to 8 second-type connection ends of a first storage device 131, and the remaining 8 docking ends are respectively connected to 8 second-type connection ends of another first storage device 131, so that the second switch 122 is connected to 26 first storage devices through the 13 memory exchange ports. The remaining memory exchange port in the second switch 122 is connected to the 27th first storage device 131-27 through the connection line X8, connected to the 28th first storage device 131-28 through the connection line ×3, and connected to the 29th first storage device 131-29 through the connection line ×5, that is, 8 docking ends of the remaining memory exchange port of the second switch 122 are connected to the 8 second-type connection ends of the 27th first storage device 131-27, 3 docking ends are connected to the 28th first storage device 131-28, and the remaining 5 docking ends are connected to the 5 connection ends of the 29th first storage device 131-29, so that the second switch 122 is connected to a total of 29 first storage devices 131 through the 14 memory exchange ports, so that the first switch 121 and the second switch 122 are connected to each first storage device.

[0109] Similarly, each memory exchange port of the third switch 123 is connected to multiple second storage devices 132 via a connecting line X16, that is, the 16 docking ends in each memory exchange port of the third switch 123 are connected to the same second storage device 132, for example, the 16 docking ends in the first memory exchange port of the third switch 123 are connected to the first second storage device 132-1, the 16 docking ends in the second memory exchange port of the third switch 123 are connected to the second second storage device 132-2, and so on, so that the third switch 123 is connected to a total of 14 second storage devices 132.

[0110] It is understandable that, in other embodiments, the computing system may further include a third computing device, which is connected to the third switch 123. The third computing device may access the second storage device 132 through the third switch 123, or access the first storage device through the third switch 123 and the second switch 122 in sequence.

[0111] In an optional implementation, when the computing system includes multiple first switches 121, multiple second switches 122, and multiple third switches 123, the connection structure between the multiple first switches 121, multiple second switches 122, and multiple third switches is relatively complex, and there may be multiple paths when accessing the same first storage device 131 or second storage device 132. Figure 7 The computing system shown also includes a manager 140. The manager 140 is respectively connected to the first switch 121, the second switch 122, and the third switch 123. The manager 140 does not occupy the memory switch ports of the first switch 121, the second switch 122, and the third switch 123, and thus does not affect the number of first storage devices 131 connected to the first switch 121 and the second switch 122, and does not affect the number of second storage devices 132 connected to the third switch 123.

[0112] The manager 140 is used to obtain the connection relationship between multiple first switches 121, multiple second switches 122, multiple third switches 123, multiple first storage devices 131, and multiple second storage devices 132, and generate first routing information sent to the first switch 121, second routing information sent to the second switch 122, and third routing information sent to the third switch 123 according to the connection relationship between the multiple first switches 121, multiple second switches 122, multiple third switches 123, multiple first storage devices 131, and multiple second storage devices 132.

[0113] The first routing information is stored in the first switch 121, the second routing information is stored in the second switch 122, and the third routing information is stored in the third switch 123. The first routing information includes the shortest path for each first switch 121 to access each first storage device 131 and each second storage device 132; the second routing information includes the shortest path for each second switch 122 to access each first storage device 131 and each second storage device 132; and the third routing information includes the shortest path for each third switch 123 to access each first storage device 131 and each second storage device 132.

[0114] When the first computing device 110 or the second computing device 112 receives a service request, the first computing device 110 or the second computing device 112 selects whether to execute the service request by itself or assign it to other computing devices according to its own working conditions and the working conditions of other computing devices. For example, when the first computing device 110 is in a "working state", a service request to access the second storage device 132-1 is received. In order to speed up the processing of the service, the second computing device 112 in an "idle state" can be made to process the service request to access the second storage device 132-1. In response to the service request, the second computing device 112 generates a data request and sends it to the second switch 122. The data request is used to indicate the second storage device 132-1 to be accessed.

[0115] It is understood that in other examples, the computing system Figure 7 On the basis of, when multiple first switches, multiple second switches and third switches are included, there may be multiple paths when accessing the same storage device to be accessed. For example, when the second switch 122 accesses the second storage device 132-1, there may be multiple paths such as the second switch 122-third switch 123-second storage device 132-1, the second switch 122-third switch 123-third switch 123-second storage device 132-1, the second switch 122-third switch 123-fourth switch 124-second storage device 132-1, etc. Therefore, the second switch 122 needs to find the shortest path to access the second storage device 132-1 from the second routing information stored in itself according to the data request, which is the second switch 122-third switch 123-second storage device 132-1; and access the second storage device 132-1 according to the shortest path, thereby avoiding accessing too many first switches or second switches and reducing the latency of accessing the storage device. Compared with Figure 4In the computing system shown, each memory exchange port of each switch 120 is connected to only one storage device 107. In this embodiment, the number of channels provided by the first switch 121 and the second switch 122 for accessing a single first storage device 131 is reduced, but the total number of channels provided by the first switch 121 and the second switch 122 for accessing multiple first storage devices 131 remains unchanged, so the first switch 121 and the second switch 122 can still provide high-bandwidth access channels. At the same time, each first switch 121 is connected to all first storage devices 131, so that each first switch 121 can directly access all first storage devices 131 without cross-switch access, thereby reducing access latency, and improving storage device density, with a larger storage capacity.

[0116] It is understandable that when there are multiple third switches 123, the connection method between the multiple third switches 123 and the multiple second storage devices 132 can refer to the connection method between the first switch 121 and the second switch 122 and the multiple first storage devices 131, and the embodiment of the present application will not be repeated.

[0117] It should be noted that when the number of third switches 123 is equal to the total number of first switches 121 and second switches, each third switch 123 can be connected to one first switch 121 or one second switch 122 respectively, and the first switches 121 or second switches 122 connected to different third switches 123 are not repeated, so that each first switch 121, second switch 122 and third switch 123 can access all first storage devices 131 and second storage devices 132.

[0118] In an optional embodiment, if Figure 8 In the schematic diagram of the architecture of the computing system 100 shown, at least part of the second storage device 132 is connected to the first switch 121 or the second switch 122 .

[0119] In this embodiment, at least part of the second storage devices 132 are connected to the first switch 121 or the second switch 122, and correspondingly, at least part of the first storage devices 131 are connected to the third switch 123, that is, the number of second storage devices 132 connected to the first switch 121 or the second switch 122 is equal to the number of first storage devices 131 connected to the third switch 123, so that the first computing device 110 or the second computing device 112 can access part of the second storage devices 132 through the corresponding switch without accessing across the second switch 122. Similarly, when the third switch is connected to the third computing device, the third computing device can access part of the first storage device 131 through part of the third switch 123 without accessing across other switches, thereby reducing the access latency and improving the performance of the computing system.

[0120] Corresponding to the computing system provided in the above embodiment, the embodiment of the present application also provides a data transmission method, see Fig. 9 , Fig. 9 A flow chart of a data transmission method provided by an embodiment of the present application is shown. The method can be applied to a switch 120, which can be the first switch 121, the second switch 122 or the third switch 123 in the computing system provided by the above embodiment, and the method includes: S10: receiving a data request, the data request is used to indicate the storage device to be accessed; S20: searching for the shortest path to access the storage device to be accessed according to the data request; S30: accessing the storage device to be accessed according to the shortest path. Exemplarily, the storage device 107 to be accessed can be any one of the multiple first storage devices 131 and the multiple second storage devices 132 in the computing system provided by the above embodiment.

[0121] In this embodiment, the switch 120 finds the shortest path to access the storage device 107 to be accessed in response to the data request, and accesses the storage device 107 to be accessed according to the address of the storage device 107 to be accessed, thereby reducing the access delay between the switch 120 and the storage device 107.

[0122] In an optional embodiment, the method further includes receiving routing information from a manager, where the routing information includes the shortest path for each switch to access each storage device.

[0123] In this embodiment, the switch 120 receives and stores routing information from the manager 140 to facilitate subsequent access to the corresponding storage device 107 via the shortest path, thereby reducing the number of times passing through other switches 120 during the access process, thereby reducing the access delay between the switch 120 and the storage device 107.

[0124] Since the data transmission method provided in the embodiment of the present application corresponds to the computing system provided in the above-mentioned embodiments, the previous embodiments are also applicable to the data transmission method provided in the present embodiment and will not be described in detail in the present embodiment.

[0125] The embodiment of the present application also provides a switch 120, which can be the first switch 121 or the second switch 122 in the computing system provided in the above embodiment, and the switch 120 is configured to: receive a data request, the data request is used to indicate the storage device to be accessed; find the shortest path to access the storage device to be accessed according to the data request; access the storage device to be accessed according to the shortest path. Exemplarily, the storage device 107 to be accessed can be any one of the multiple first storage devices 131 and the multiple second storage devices 132 in the computing system provided in the above embodiment.

[0126] In an optional embodiment, the switch 120 is configured to receive routing information from the manager 140 , where the routing information includes the shortest path for each switch to access each storage device.

[0127] In this embodiment, the switch 120 responds to the data request, searches for the shortest path to access the storage device 107 to be accessed from the routing information stored in itself, and accesses the storage device 107 to be accessed according to the address of the storage device 107, thereby reducing the access delay between the switch 120 and the storage device 107.

[0128] The embodiment of the present application also provides a manager 140, which is configured to: generate multiple routing information according to the connection relationship between the switch and multiple storage devices, and different routing information corresponds to the shortest path for different switches to access each storage device; send the multiple routing information to the corresponding switch. Exemplarily, the switch can be any one of the first switch 121 and the second switch 122 in the computing system provided in the above embodiment, and the storage device 107 to be accessed can be any one of the multiple first storage devices 131 and the multiple second storage devices 132 in the computing system provided in the above embodiment.

[0129] In this embodiment, the manager 140 can generate multiple routing information based on the connection relationship between the switch 120 and multiple storage devices 107, and send the routing information to the corresponding switch 120. For example, the manager 140 can generate first routing information based on the connection relationship between the first switch 121 and the first storage device 131 and the second storage device 132, and send the first routing information to the first switch 121, so that the switch 120 can access the corresponding storage device 107 through the shortest path according to the data request, thereby reducing the number of times passing through other switches during the access process and reducing the access delay between the switch and the storage device.

[0130] The embodiment of the present application also provides a computer-readable storage medium. All or part of the data access methods in the above method embodiments can be completed by a computer program to instruct the relevant hardware, and the program can be stored in the above computer-readable storage medium. When the program is executed, it can include the process of each method embodiment as described above. The computer-readable storage medium can be an internal storage device of the communication device (including the data sending end and / or the data receiving end) of any of the above embodiments, such as a hard disk or memory of the communication device. The above computer-readable storage medium can also be an external storage device of the above communication device, such as a plug-in hard disk equipped on the above communication device, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both the internal storage device of the above communication device and an external storage device. The above computer-readable storage medium is used to store the above computer program and other programs and data required by the above communication device. The above computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0131] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A computing system, characterized in that: include: A first computing device, a second computing device, a first switch, a second switch, and a plurality of first storage devices; The first computing device is connected to the first switch, and the second computing device is connected to the second switch; Each of the first storage devices is connected to the first switch or the second switch, and at least one of the first storage devices connected to the first switch is also connected to the second switch.

2. The computing system according to claim 1, characterized in that The first switch and the second switch each include a plurality of memory exchange ports, each of the memory exchange ports includes a plurality of docking ends; The first storage device includes a first type connection end and a second type connection end; wherein the first type connection end corresponds to and is connected to the docking end of the first switch in a one-to-one manner, and the second type connection end corresponds to and is connected to the docking end of the second switch in a one-to-one manner.

3. The computing system according to claim 2, characterized in that The first switch and the second switch each include a plurality of docking terminals; The first storage device includes a control chip and a plurality of memories; the control chip includes the first type of connection end and the second type of connection end; wherein the first type of connection end corresponds to and is connected to the docking end of the first switch in a one-to-one manner, and the second type of connection end corresponds to and is connected to the docking end of the second switch in a one-to-one manner; The control chip also includes a plurality of memory connection terminals, and the plurality of memory connection terminals correspond to and are connected to the plurality of memories one by one.

4. The computing system according to claim 1, characterized in that: The first switch and the second switch are not connected via a signal connection line.

5. The computing system according to any one of claims 1 to 4, characterized in that: Also includes: a third switch and a plurality of second storage devices; The third switch is connected to each second storage device; the third switch is connected to the first switch or the second switch.

6. The computing system according to claim 5, characterized in that: At least part of the second storage device is connected to the first switch; and / or, At least part of the second storage device is connected to the second switch.

7. The computing system according to claim 5 or 6, characterized in that: Also included is a manager, the manager is communicatively connected to the first switch, the second switch and the third switch respectively; The manager is used to generate first routing information and second routing information according to the connection relationship between the first switch, the second switch and the third switch and the plurality of first storage devices and the plurality of second storage devices, and send the first routing information to the first switch, and send the second routing information to the second switch; wherein the first routing information includes the shortest path for the first switch to access each of the first storage devices and each of the second storage devices; the second routing information includes the shortest path for the second switch to access each of the first storage devices and the shortest path for the second switch to access each of the second storage devices; The first switch is used to store the first routing information, and the second switch is used to store the second routing information; The first switch is used to find the shortest path to access the storage device to be accessed according to the data request and the first routing information, and access the storage device to be accessed according to the shortest path; wherein the data request is used to indicate the storage device to be accessed; the storage device to be accessed is any one of the multiple first storage devices and the multiple second storage devices; Alternatively, the second switch is used to find the shortest path to access the storage device to be accessed according to the data request and the second routing information, and access the storage device to be accessed according to the shortest path.

8. A switch, the switch being the first switch or the second switch in the computing system according to any one of claims 1 to 7, characterized in that: The switch is configured as: receiving a data request, wherein the data request is used to indicate a storage device to be accessed, wherein the storage device to be accessed is any one of a plurality of first storage devices in the computing system; Finding the shortest path to access the storage device to be accessed according to the data request; The storage device to be accessed is accessed according to the shortest path.

9. A data transmission method, applied to a switch, wherein the switch is the first switch or the second switch in the computing system according to any one of claims 1 to 7, characterized in that: include: receiving a data request, wherein the data request is used to indicate a storage device to be accessed, wherein the storage device to be accessed is any one of a plurality of first storage devices in the computing system; Finding the shortest path to access the storage device to be accessed according to the data request; The storage device to be accessed is accessed according to the shortest path.

10. The data transmission method according to claim 9, characterized in that: Receive routing information from the manager, where the routing information includes the shortest path for each switch to access each storage device.

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