Image windowing control circuit, control method thereof and image sensor

Abstract

The invention provides an image windowing control circuit, a control method thereof and an image sensor, the circuit comprises a row decoding module and a column decoding module, a plurality of first address decoding units in the row decoding module are cascaded, and a plurality of second address decoding units in the column decoding module are cascaded. And inputting the initial row address and the initial column address into a corresponding first address decoding unit and a corresponding second address decoding unit, thereby determining an initial address of the to-be-windowed window according to the synchronizing signal, generating a corresponding row gating signal and a corresponding column gating signal through the first clock signal and the second clock signal, determining the window size of the to-be-windowed window, and starting the to-be-windowed window according to the initial address of the to-be-windowed window. Pixel sequential control and read-out processing control are carried out on the windowing position of the active pixel array, so that a windowing control function is realized; during windowing control, only the row and the column corresponding to the windowing position are subjected to time sequence and read signal processing, and the non-windowing row and column circuit is in a non-working state, so that the current consumption is reduced, and the power consumption of the image sensor is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to an image windowing control circuit and a control method thereof, and an image sensor. Background Art

[0002] The main function of an image sensor is to capture images. It can convert optical images into electrical signals to create static or dynamic images. This conversion process makes image sensors essential in cameras, camcorders, mobile phone cameras, and other image acquisition devices. The windowing function of an image sensor can capture and output specific areas of an image, reduce the amount of data processing by the image sensor, and thus reduce system costs. In related technologies, the windowing function is implemented by a traditional CMOS (Complementary Metal Oxide Semiconductor) image sensor, which inputs different row address input signals and column address input signals at different times. N rows or N columns need to change addresses 2N times, which is a large number of changes and complex to control, especially when multiple windows are used for windowing.

[0003] Therefore, how to provide an image windowing technical solution that is simple and easy to operate is a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a technical solution for image windowing control to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0006] According to a first aspect of an embodiment of the present application, there is provided an image windowing control circuit, comprising:

[0007] A row decoding module, comprising N first address decoding units, the N first address decoding units are cascaded in sequence and output N row selection signals to the outside, the first address decoding units receive the row address, the synchronization signal, and the first clock signal, and the i-th first address decoding unit determines the row start signal in the row selection signal according to the start row address of the window to be opened;

[0008] A column decoding module, comprising M second address decoding units, the M second address decoding units are cascaded in sequence and output M column selection signals to the outside, the second address decoding unit receives the column address, the synchronization signal, and the second clock signal, and the jth second address decoding unit determines the column start signal in the column selection signal according to the start column address of the window to be opened;

[0009] The row decoding module and the column decoding module are controlled to perform synchronous windowing according to the synchronization signal, the row decoding module performs row windowing according to the row start signal and the first clock signal, and the column decoding module performs column windowing according to the column start signal and the second clock signal, so as to perform image windowing control;

[0010] Wherein, i and j are integers, 1≤i≤N, 1≤j≤M, N is the number of the first address decoding units, and M is the number of the second address decoding units.

[0011] In one embodiment of the present application, the first address decoding unit includes an address memory, an AND gate address decoder, an AND gate, a first D flip-flop, a second D flip-flop and an OR gate, wherein a first input terminal of the AND gate address decoder is connected to an output terminal of the address memory, an output terminal of the AND gate address decoder is connected to a first input terminal of the AND gate, an output terminal of the AND gate is connected to a first input terminal of the first D flip-flop, an output terminal of the first D flip-flop is connected to a first input terminal of the OR gate, and an output terminal of the second D flip-flop is connected to a second input terminal of the OR gate, wherein a second input terminal of the AND gate address decoder is connected to the row address, a second input terminal of the AND gate is connected to the synchronization signal, a second input terminal of the first D flip-flop and a first input terminal of the second D flip-flop are connected to the first clock signal, an output terminal of the OR gate outputs the row selection signal, a second input terminal of the second D flip-flop in the first address decoding unit of the next stage is connected to an output terminal of the OR gate in the first address decoding unit of the previous stage, and a second input terminal of the second D flip-flop in the first first address decoding unit is connected to a low level.

[0012] In one embodiment of the present application, the structure of the second address decoding unit is the same as that of the first address decoding unit. In the second address decoding unit, the second input terminal of the AND gate address decoder is connected to the column address, the second input terminal of the AND gate is connected to the synchronization signal, the second input terminal of the first D flip-flop and the first input terminal of the second D flip-flop are connected to the second clock signal, the output terminal of the OR gate outputs the column selection signal, the second input terminal of the second D flip-flop in the next stage of the second address decoding unit is connected to the output terminal of the OR gate in the first stage of the first address decoding unit, and the second input terminal of the second D flip-flop in the first second address decoding unit is connected to a low level.

[0013] According to a second aspect of an embodiment of the present application, a control method applied to the image windowing control circuit as described above is also provided, comprising:

[0014] Acquire the window opening information of the window to be opened, wherein the window opening information includes a start address, the synchronization signal, and a clock signal;

[0015] Determine the starting signal of the window to be opened according to the starting address, the synchronization signal and the clock signal;

[0016] Windowing is performed according to the start signal and the clock signal to complete image windowing control.

[0017] In one embodiment of the present application, the starting address includes the row starting address and the column starting address, the clock signal includes the first clock signal and the second clock signal, and the starting signal of the window to be opened is determined according to the starting address, the synchronization signal, and the clock signal, including: determining the row starting signal based on the row starting address, the synchronization signal, and the first clock signal; determining the column starting signal based on the column starting address, the synchronization signal, and the second clock signal; wherein the starting signal includes the row starting signal and the column starting signal.

[0018] In one embodiment of the present application, a row start signal is determined based on the row start address, the synchronization signal, and the first clock signal, including: matching the row start address with a preset row storage address, and if the row start address matches the preset row storage address, address decoding the row start address based on the synchronization signal to obtain a row start decoding signal; triggering the row start decoding signal according to the rising edge of the first clock signal to obtain the row start signal.

[0019] In one embodiment of the present application, when the window to be windowed is single, windowing is performed according to the start signal and the clock signal, including: shift-triggering the row start signal based on the first clock signal to obtain a plurality of row selection signals; shift-triggering the column start signal based on the second clock signal to obtain a plurality of column selection signals; and performing row windowing and column windowing on the window to be windowed according to the row selection signal and the column selection signal.

[0020] In one embodiment of the present application, when there are multiple windows to be windowed, windowing is performed according to the start signal and the clock signal, including: if the start addresses of the multiple windows to be windowed are the same, related address windowing is performed based on the start signal of the same start address and the clock signal corresponding to the window to be windowed; if the start addresses of the multiple windows to be windowed are different, image windowing control is performed based on a single image windowing operation.

[0021] According to a third aspect of the embodiments of the present application, an image sensor is further provided, wherein the image sensor includes the image windowing control circuit as described above, including:

[0022] A row driving module, connected to the row decoding module, generating a pixel control signal according to the row selection signal;

[0023] An active pixel array, connected to the row driving module, generating a row control signal according to the pixel control signal;

[0024] An image processing module, connected to the active pixel array and the column decoding module, determines the window to be opened according to the row control signal and the column selection signal and performs image processing on the image of the window to be opened to obtain an image processing signal;

[0025] The output module is connected to the image processing module, and sorts and outputs the image processing signal to obtain a target image.

[0026] The present application provides an image windowing control circuit and a control method thereof, and an image sensor. The circuit includes a row decoding module and a column decoding module. A plurality of first address decoding units in the row decoding module are cascaded, and a plurality of second address decoding units in the column decoding module are cascaded. The starting row address and the starting column address are input into the corresponding first address decoding unit and the second address decoding unit, so as to determine the starting address of the window to be windowed according to the synchronization signal, and generate the corresponding row selection signal and column selection signal through the first clock signal and the second clock signal, and determine the window size of the window to be windowed, so as to perform pixel timing control and readout processing control on the windowing position of the active pixel array, so as to realize the windowing control function; during the windowing control, only the rows and columns corresponding to the windowing position are processed with timing and readout signals, and the circuits of the rows and columns not windowed are not in a working state, so as to reduce the current consumption and the power consumption of the image sensor. The circuit windowing of the present application is simple and convenient to realize, the control is reliable, and the low power consumption can be realized, and it can be applied to CMOS image sensor chips of different array sizes.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0029] Figure 1 This is a block diagram of a conventional CMOS image sensor that can implement the windowing function;

[0030] Figure 2 is a schematic diagram of a column decoder or a row decoder in a conventional CMOS image sensor;

[0031] Figure 3 This is a schematic diagram of the timing of opening a single window in a traditional CMOS image sensor;

[0032] Figure 4 is a schematic diagram of a row decoding module or a column decoding module in an image windowing control circuit shown in an exemplary embodiment of the present invention;

[0033] Figure 5 It is a schematic diagram of the timing of single window opening by an image window opening control circuit shown in an exemplary embodiment of the present invention;

[0034] Figure 6 It is a timing diagram of windows in different rows or different columns of a same row when a multi-window window opening is performed by an image window opening control circuit according to an exemplary embodiment of the present invention;

[0035] Figure 7 is a flow chart of a control method of an image windowing control circuit shown in an exemplary embodiment of the present invention;

[0036] Figure 8 is a block diagram of an image sensor according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0038] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0040] The main function of an image sensor is to capture an image. It can convert an optical image into an electrical signal to create a static or dynamic image. This conversion process makes image sensors essential in cameras, camcorders, mobile phone cameras, and other image acquisition devices. The windowing function of an image sensor can capture and output specific areas of an image, reducing the amount of data processing required by the image sensor, thereby reducing system costs.

[0041] In related technologies, such as Figure 1 As shown, a conventional CMOS (Complementary Metal Oxide Semiconductor) image sensor can realize a windowing function. The conventional CMOS (Complementary Metal Oxide Semiconductor, CMOS) image sensor includes a row decoder 110, a row driver 120, an active pixel array 130, a correlated double sampling (CDS, correlated double sampling) array (CDS+ADC array) 140, a column decoder 150 and a signal output module 160.

[0042] The row decoder 110 generates a driver row strobe signal RS for the row driver 120. <1> , RS <2> ,…,RS <t-1>and RS <t>.like Figure 2 As shown, the row decoder 110 includes a plurality of row decoder units (111, 112 to 11T), each of which receives a row address input signal RS_addr_in. <b:1>, and output the row selection signal RS <t>The row decoder unit 11t includes two parts: RS address and AND gate address decoding circuit. The difference between each row decoder unit 11t is that the RS address is different. For example, when N is 256, the row address 1 = 000000002 (000000002 represents the binary code 00000000, 1 10 represents decimal 1, the following description is consistent), row address 2 = 000000012 (2 10 ), ..., row address 255 = 1111, 11102 (255 10 ), row address 256 = 111111112 (256 10 ), where t is an integer, 1≤t≤T, and T is the number of row decoder units.

[0043] The row driver 120 is used to generate control signals RS, TX and SEL to control T rows of the active pixel array 130. The active pixel array 130 outputs an active pixel signal OUT corresponding to each column. <1> ,OUT <2> ,…,OUT <t-1>、OUT <t>.

[0044] The column decoder 150 generates a column select signal CS for the correlated double sampling array 140. <1> , CS <2> ,…,CS <r-1>and CS <r>.like Figure 2 As shown, the structure of column decoder 150 is the same as that of decoder 110, except that the row address input signal RS_addr_in <b:1>Becomes the column address input signal CS_addr_in <b:1>, output row selection signal RS <t>Becomes the column select signal CS <r>, where r is an integer, 1≤r≤R, and R is the number of column decoder units.

[0045] Column strobe signal CS <1> , CS <2> ,…,CS <r-1>and CS <r>Connect to the corresponding column circuit of the correlated double sampling array 140, and select the active pixel signal OUT <1> ,OUT <2> ,…,OUT <t-1>、OUT <t>Double sampling processing is performed, and the processed image signal is sent to the signal output module for output.

[0046] like Figure 3 As shown, the conventional CMOS image sensor inputs different row address input signals RS_addr_o at different times. <b:1>and column address input signal CS_addr_o <b:1>, N rows or N columns need to change the address 2N times, N rows or N columns need to change the address 2N times, the number of changes is large, and the control is very complicated. When opening windows, the window opening efficiency is low, and it is very easy to make window opening errors. In some important observation scenarios, it will directly affect the observation results. For example, when using star sensors, if the image window opening error occurs, star observation cannot be performed directly.

[0047] In order to solve the above problems, the present application provides an image windowing control circuit, comprising:

[0048] A row decoding module, comprising N first address decoding units, the N first address decoding units are cascaded in sequence and output N row selection signals to the outside, the first address decoding unit receives the row address, the synchronization signal, and the first clock signal, and the i-th first address decoding unit determines the row start signal in the row selection signal according to the start row address of the window to be opened;

[0049] A column decoding module, comprising M second address decoding units, the M second address decoding units are cascaded in sequence and output M column selection signals to the outside, the second address decoding unit receives the column address, the synchronization signal, and the second clock signal, and the jth second address decoding unit determines the column start signal in the column selection signal according to the start column address of the window to be opened;

[0050] Control the row decoding module and the column decoding module to perform synchronous windowing according to the synchronization signal, the row decoding module performs row windowing according to the row start signal and the first clock signal, and the column decoding module performs column windowing according to the column start signal and the second clock signal, so as to perform image windowing control;

[0051] Wherein, i, j are integers, 1≤i≤N, 1≤j≤M, N is the number of first address decoding units, and M is the number of second address decoding units.

[0052] In detail, Figure 4 As shown, the first address decoding unit includes an address memory, an AND gate address decoder, an AND gate, a first D flip-flop, a second D flip-flop and an OR gate, wherein the first input terminal of the AND gate address decoder is connected to the output terminal of the address memory, and receives the preset row storage address RS_addr_o stored in the address memory. <b:1>The output terminal of the AND gate address decoder is connected to the first input terminal of the AND gate, the output terminal of the AND gate is connected to the first input terminal of the first D flip-flop, the output terminal of the first D flip-flop is connected to the first input terminal of the OR gate, and the output terminal of the second D flip-flop is connected to the second input terminal of the OR gate, wherein the second input terminal of the AND gate address decoder is connected to the row address RS_addr_in <b:1>The second input terminal of the AND gate is connected to the synchronization signal SYNC_RS, the second input terminal of the first D flip-flop and the first input terminal of the second D flip-flop are connected to the first clock signal CLK_RS, and the output terminal of the OR gate outputs the row selection signal RS , the second input end of the second D flip-flop in the first address decoding unit of the next level is connected to the output end of the OR gate in the first address decoding unit of the previous level, and the second input end of the second D flip-flop in the first first address decoding unit is low level.

[0053] In more detail, Figure 4 As shown, the structure of the second address decoding unit is the same as that of the first address decoding unit. In the second address decoding unit, the first input terminal of the AND gate address decoder is connected to the output terminal of the address memory, and receives the column storage address CS_addr_o stored in the address memory. <b:1>The second input of the AND gate address decoder is connected to the column address CS_addr_in <b:1>The second input terminal of the AND gate is connected to the synchronization signal SYNC_CS, the second input terminal of the first D flip-flop and the first input terminal of the second D flip-flop are connected to the second clock signal CLK_CS, and the output terminal of the OR gate outputs the column selection signal CS <j>The second input end of the second D flip-flop in the second address decoding unit of the next level is connected to the output end of the OR gate in the first address decoding unit of the previous level, and the second input end of the second D flip-flop in the first second address decoder unit inputs a low level.

[0054] It should be noted that if Figures 1 to 5 As shown, the * in the drawings represents an alternative symbol, that is, * can be RS (row) or CS (column).

[0055] like Figures 1 to 6 As shown, the working principle of the image window control circuit provided by this application is as follows:

[0056] If the image windowing circuit can generate a strobe signal for a 1280 (H) × 1024 (V) active pixel array, where H represents the horizontal direction (column) and V represents the vertical direction (row). Figure 1 As shown, the row decoding module is the row decoder 110, the column decoding module is the column decoder 150, the row decoding module includes a 1024-level first address decoding unit, the column decoding module includes a 1280-level second address decoding unit, the 1024-level first address decoding unit is connected to the 1024-level row driver to generate a plurality of control signals (RS, TX, SEL) for controlling the 1024-row active pixel array, the 1280-level second address decoding unit is used to generate a column selection signal CS<1:1280> of the correlated double sampling array, wherein the number of address decoding units in the row decoding module and the column decoding module in the image windowing control circuit can be determined according to actual conditions and is not limited thereto.

[0057] The first address decoding unit and the second address decoding unit realize the row or column address decoding function through the storage address in the address memory and the AND gate address decoder, and the first D flip-flop and the second D flip-flop realize the row or column shift selection function.

[0058] The single window opening sequence is as follows Figure 5 As shown, when the window opening conditions of a single window are: the window opening window size is 256 (H) × 512 (V), the starting row address RS_addr_o<10:1> starts from the 512th row, and the starting column address CS_addr_o<11:1> starts from the 128th column (randomly selected starting address), the starting row address and the starting column address can change according to actual conditions.

[0059] 1. Single window opening includes row window opening steps and column window opening steps

[0060] ①Single window opening line window opening steps:

[0061] The starting row address RS_addr_in<10:1>001,1111,11112 (512) is input to the second input terminal of the AND gate address decoder in the first address decoding unit of the 512th level. 10 ), the first address decoding unit of the 512th level starts address decoding; when the 10-bit starting row address RS_addr_in<10:1> in the first address decoding unit of the 512th level is the same as the preset row storage address RS_addr_o<10:1> in the address memory, the AND gate address decoder outputs a high level; the AND gate address decoder output and the synchronization signal SYNC_RS are both high levels, so that the output end of the AND gate outputs a high level, that is, the first input end of the first D flip-flop is high level; in the first cycle of the first clock signal CLK_RS, the high level of the input is triggered and output by the first clock signal CLK_RS, and a high level pulse signal with the first rising edge of the first clock signal CLK_RS as the starting time and the width of the CLK_RS cycle of the first clock signal is obtained. Since the first address decoding unit of the 512th level is the row starting address input unit, the second input end of the second D flip-flop is low level, and the output of the second D flip-flop is low level, therefore, the OR gate outputs the row selection signal RS <512> .

[0062] In the second cycle of CLK_RS of the first clock signal, the second input terminal of the second D flip-flop in the first address decoding unit of the 513th stage is connected to the output terminal of the OR gate in the first address decoding unit of the 512th stage. Therefore, the first half cycle RS of the second cycle of CLK_RS of the first clock signal <512> The first clock signal CLK_RS is at a high level, and the high level of the input is triggered and outputted, and a high level pulse signal with the second rising edge of the first clock signal CLK_RS as the starting time and the CLK_RS cycle width of the first clock signal is obtained. Since the first address decoding unit of the 513th level is not the starting row of the window opening window, it is not necessary to input the starting row address. Therefore, the first input end of the OR gate in the first address decoding unit of the 513th level is low level, and the second input end of the OR gate is a high level pulse signal, and the output end of the OR gate outputs the row selection signal RS to the outside. <513> ; From the third cycle to the 512th cycle of the first clock signal CLK_RS, the RS is generated in time-sharing manner in accordance with the above steps. <514> ,…,RS <1023> The row selection signal is used to perform the window row timing control function.

[0063] ②Single window opening steps:

[0064] The starting row address CS_addr_in<11:1>00,0111,11112 (128 10 ), the 128th-level second address decoding unit starts address decoding; when the 11-bit starting column address CS_addr_in<11:1> in the 128th-level second address decoding unit is the same as the column storage address CS_addr_o<11:1> in the address memory, the AND gate address decoder outputs a high level; the AND gate address decoder output and the synchronization signal SYNC_CS are both high levels, so that the output end of the AND gate outputs a high level, that is, the first input end of the first D flip-flop is high level; in the first cycle of the second clock signal CLK_CS, the input high level is triggered and output by the second clock signal CLK_CS, and a high level pulse signal with the first rising edge of the second clock signal CLK_CS as the starting time and the width of the second clock signal CLK_CS cycle is obtained. Since the 128th-level second address decoding unit is a column starting address input unit, the second input end of the second D flip-flop is low level, and the second D flip-flop output is low level, therefore, the OR gate outputs a row selection signal RS to the outside. <512> .

[0065] In the second cycle of the second clock signal CLK_CS, the second input terminal of the second D flip-flop in the second address decoding unit of the 129th stage is connected to the output terminal of the OR gate in the second address decoding unit of the 128th stage. Therefore, the first half cycle CS of the second cycle of the second clock signal CLK_CS <128> The high level of the input is triggered and outputted through the CLK_CS of the second clock signal, and a high level pulse signal with the second rising edge of the CLK_CS of the second clock signal as the starting time and the CLK_RS cycle width of the second clock signal is obtained. Since the second address decoding unit of the 129th level is not the starting row of the window window, it is not necessary to input the starting column address. Therefore, the first input end of the OR gate in the second address decoding unit of the 129th level is low level, the second input end of the OR gate is a high level pulse signal, and the output end of the OR gate outputs the column selection signal CS to the outside. <129> ; From the third cycle to the 256th cycle of the second clock signal CLK_CS, the principle is consistent with the above steps, and CS is generated in time-sharing <130> ,…,CS <383> The column selection signal performs the window column timing control function.

[0066] like Figure 6 As shown, multiple windows are opened through the image window control circuit. The window opening conditions when multiple windows are opened are as follows: 4 windows are opened, the window size is 60 (H) × 50 (V) rows, and the starting row address RS_addr_o<10:1> of the first window and the second window is from 100 10 Start, the first window starting column address CS_addr_o<11:1> from 100 10 The second window starts with the column address CS_addr_o<11:1> from 200 10 The third and fourth window start row addresses RS_addr_o<10:1> start from 300 10 Start, the third window starting column address CS_addr_o<11:1> from 300 10 Start, the fourth window starting column address CS_addr_o<11:1> from 500 10 start.

[0067] 2. 4-window windowing includes row windowing steps and column windowing steps:

[0068] ① The row window opening steps of the 4 windows to be opened include:

[0069] Analyzing the starting addresses of the four windows, we can see that the window opening rows of the first window and the second window overlap by 50 rows. When performing the single window row window opening operation steps, enter the window opening window starting row address 00,0110,00112 (100 10 ), the number of clock cycles of the first clock signal CLK_RS is 51 10 , the row selection control of the first window opening window and the second window opening window is completed through the timing control of the above single window row window opening operation steps.

[0070] Analyzing the starting addresses of the four windows, we know that the windowing rows of the third and fourth windows overlap by 50 rows, but they are different from the rows of the first and second windows. A new row windowing step is required. Enter the starting row address of the windowing window as 01,0010,10112 (300 10 ), the number of clock cycles of the first clock signal CLK_RS is 51 10 , the row selection control of the 3rd window opening window and the 4th window opening window is completed through the above timing control.

[0071] ② The steps of opening the four windows to be opened include:

[0072] Because the first window opening window and the second window opening window have the same window opening row but different window columns, two single window column window opening operations connected end to end are performed; when the first single window column window opening operation is performed, the starting column address of the window opening window needs to be entered as 000,0110,00112 (100 10 ), the number of clock cycles of the second clock signal CLK_CS is 61 10 , when opening the second single window column window, you need to enter the starting column address of the window 000,1100,01112 (200 10 ), the number of clock cycles of the second clock signal CLK_CS is 61 10 , through the above two single window column opening operations, the column selection control of the first window and the second window opening column is completed.

[0073] The third and fourth window opening windows are in different rows from the first and second window opening windows, but have the same window opening row and different window columns. Two end-to-end single window column window opening operations are performed. When the third single window column window opening operation is performed, the starting column address of the window opening window needs to be entered as 001,0010,10112 (300 10 ), the number of clock cycles of the second clock signal CLK_CS is 61 10 , when opening the fourth single window column window, you need to enter the starting column address of the window 001,1111,00112 (500 10 ), the number of clock cycles of the second clock signal CLK_CS is 61 10 , through the above two single window column windowing operations, the column selection control of the third window and the fourth window windowing columns is completed.

[0074] like Figure 7 As shown, the present application also provides a control method of an image windowing control circuit, which is applied to the image windowing control circuit as described above, comprising:

[0075] Obtain the window opening information of the window to be opened, the window opening information includes the starting address, synchronization signal, and clock signal;

[0076] Determine the starting signal of the window to be opened according to the starting address, the synchronization signal and the clock signal;

[0077] Windowing is performed according to the start signal and the clock signal to complete image windowing control.

[0078] Specifically, Figure 4 As shown, the image windowing control circuit includes a row decoding module and a column decoding module. The row decoding module includes a plurality of first address decoding units, and the column decoding module includes a plurality of second address decoding units. The starting address of the window to be opened is obtained. <b:1>, synchronization signal SYNC_* and clock signal CLK_*, the starting address *_addr_in <b:1>, the synchronization signal SYNC_* and the clock signal CLK_* are input into the first address decoding unit and the second address decoding unit corresponding to the starting address of the window to be windowed, a starting signal of the window to be windowed is generated, and the window is opened according to the starting signal and the clock signal to realize the image windowing processing.

[0079] In more detail, the start address includes a row start address and a column start address, the clock signal includes a first clock signal and a second clock signal, and the start signal of the window to be opened is determined according to the start address, the synchronization signal, and the clock signal, including: determining the row start signal based on the row start address, the synchronization signal, and the first clock signal; determining the column start signal based on the column start address, the synchronization signal, and the second clock signal; wherein the start signal includes a row start signal and a column start signal. Specifically, in combination Figure 4 As shown, enter the row start address into RS_addr_in <b:1>The first input end of the AND gate address decoder in the corresponding first address decoding unit, the synchronization signal SYNC_RS is input to the second input end of the AND gate, the first clock signal CLK_RS is input to the second input end of the first D flip-flop and the first input end of the second D flip-flop, and the second input end of the second D flip-flop is input to a low level, so that the corresponding first address decoding unit outputs a row start signal to the outside. Similarly, the column start address CS_addr_in <b:1>, the synchronization signal SYNC_CS, and the second clock signal CLK_CS are input into the corresponding second address decoding unit, so that the corresponding second address decoding unit outputs a column start signal.

[0080] In more detail, determining the row start signal based on the row start address, the synchronization signal, and the first clock signal includes: matching the row start address with a preset row storage address, and if the row start address matches the preset row storage address, address decoding the row start address based on the synchronization signal to obtain a row start decoding signal; and strobing and triggering the row start decoding signal according to the rising edge of the first clock signal to obtain a row start signal. Specifically, Figure 4 As shown, the AND gate address decoder matches the input row start address with the preset row storage address in the RS address memory. If the row start address RS_addr_in <b:1>and the preset row storage address RS_addr_o <b:1>If the first address decoding unit of the corresponding level is not the first address decoding unit corresponding to the starting row, the starting address needs to be input into the correct first address decoding unit; if the row starting address RS_addr_in <b:1>and the preset row storage address RS_addr_o <b:1>If the AND gate address decoder outputs a high level, the AND gate address decoder performs address decoding on the level signal output by the AND gate address decoder according to the high level synchronization signal SYNC_RS to obtain a high level row start decoding signal, and then the high level row start decoding signal is triggered by the rising edge of the first clock signal, the first D flip-flop outputs a high level, and the OR gate outputs a row start signal RS. Similarly, the principle of generating the column start signal is the same as that of the row start signal, which will not be described in detail here.

[0081] In more detail, when the window to be windowed is single, windowing is performed according to the start signal and the clock signal, including: shift-triggering the row start signal based on the first clock signal to obtain multiple row selection signals; shift-triggering the column start signal based on the second clock signal to obtain multiple column selection signals; and performing row windowing and column windowing on the window to be windowed according to the row selection signal and the column selection signal. Specifically, after determining the start signal of the window to be opened, since the second input terminal of the second D flip-flop in the first address decoding unit (second address decoding unit) of the next level is connected to the output terminal of the OR gate in the first address decoding unit (second address decoding unit) of the previous level, in the first half cycle of the next cycle of the first clock signal, the second input terminal of the second D flip-flop in the first address decoding unit of the next level is connected to a high level, and the row start signal is shift-triggered by the next rising edge of the first clock signal to obtain multiple row selection signals, and the column start signal is shift-triggered by the next rising edge of the second clock signal to obtain multiple column selection signals, thereby realizing row windowing and column windowing of the window to be opened according to multiple row selection signals and multiple column selection signals.

[0082] In more detail, when there are multiple windows to be opened, windowing is performed according to the start signal and the clock signal, including: if the start addresses of multiple windows to be opened are the same, relevant address windowing is performed based on the start signal of the same start address and the clock signal corresponding to the window to be opened; if the start addresses of multiple windows to be opened are different, image windowing control is performed based on a single image windowing operation.

[0083] Specifically, when there are multiple windows to be opened, the starting addresses of the multiple windows to be opened are analyzed. If the starting addresses of two or more windows to be opened have the same row starting address or column starting address, for example, the row starting address of the first window to be opened is 100 rows, the column starting address is 100 rows, the size of the first window to be opened is 60 (H) × 50 (V), the row starting address of the second window to be opened is 100 rows, the column starting address is 300 rows, the size of the second window to be opened is 60 (H) × 60 (V), and the window opening step of the first window to be opened is the same as that of the single window to be opened. Since the row starting address of the second window to be opened is the same as that of the first window to be opened, it is not necessary to determine the row starting address. Then, according to the row starting signal of the second window to be opened and the number of clock cycles of the corresponding first clock signal CLK_RS, 61 10 Perform row address windowing; and perform separate windowing on the column address of the second window, thereby obtaining the second window to be windowed. If the size of the second window to be windowed is the same as that of the first window to be windowed, then row windowing is not required. If the starting addresses of multiple windows to be windowed are different, for example: the row starting address of the third window to be windowed is 100 rows, the column starting address is 100 rows, the size of the first window to be windowed is 60 (H) × 50 (V), the row starting address of the second window to be windowed is 300 rows, the column starting address is 500 rows, and the size of the second window to be windowed is 60 (H) × 50 (V), then it is necessary to perform two windowing processes through the windowing step of a single window to be windowed, thereby realizing the windowing control of the two windowing windows.

[0084] like Figure 8 As shown, the present application also provides an image sensor, characterized in that the image windowing control circuit as described above is arranged in the image sensor, and the image sensor comprises:

[0085] The row driver module 820 is connected to the row decoder module 810 and receives the row selection signal RS Generate pixel control signals (RST, TX, SEL);

[0086] The active pixel array 830 is connected to the row driving module 820 and generates a row control signal OUT according to the pixel control signal (RST, TX, SEL). ;

[0087] The image processing module 840 is connected to the active pixel array 830 and the column decoding module 850, and receives the row control signal OUT and column select signal CS <j>Determine the window to be opened and perform image processing on the image of the window to be opened to obtain an image processing signal;

[0088] The output module 860 is connected to the image processing module 840 to sort and output the image processing signal to obtain a target image.

[0089] In more detail, the image processing module includes a correlated double sampling unit, which samples the windowed image multiple times according to the row control signal and the column selection signal to obtain an image processing signal; the image processing module can also include an analog-to-digital conversion unit, which is connected to the correlated double sampling unit to perform analog-to-digital conversion on the image processing signal to obtain a digital signal image processing signal.

[0090] The present application provides an image windowing control circuit and a control method thereof, and an image sensor. The circuit includes a row decoding module and a column decoding module. A plurality of first address decoding units in the row decoding module are cascaded, and a plurality of second address decoding units in the column decoding module are cascaded. The starting row address and the starting column address are input into the corresponding first address decoding unit and the second address decoding unit, so as to determine the starting address of the window to be windowed according to a synchronization signal, and generate corresponding row selection signals and column selection signals through first clock signals and second clock signals to determine the window size of the window to be windowed, so as to perform pixel timing control and readout processing control on the windowing position of the active pixel array, so as to realize the windowing control function; at the same time, during the windowing control, only the rows and columns corresponding to the windowing position are subjected to timing and readout signal processing, and the circuits of the rows and columns not windowed are not in a working state, so as to reduce current consumption and reduce the power consumption of the image sensor. The image windowing circuit provided in the present application can realize not only the windowing of a single image but also the rapid windowing of multiple windows to be opened by changing a single address and a clock cycle. The circuit has low power consumption and can be applied to CMOS image sensor chips of different array sizes, with a wide range of applications. When performing star observation, it is easy to realize multi-window windowing for star identification observation, which is convenient for star identification observation.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.< / j> < / j> < / t> < / r> < / r> < / t> < / r> < / t> < / t> < / t>

Claims

1. An image windowing control circuit, characterized in that: include: A row decoding module, comprising N first address decoding units, the N first address decoding units are cascaded in sequence and output N row selection signals to the outside, the first address decoding units receive the row address, the synchronization signal, and the first clock signal, and the i-th first address decoding unit determines the row start signal in the row selection signal according to the start row address of the window to be opened; A column decoding module, comprising M second address decoding units, the M second address decoding units are cascaded in sequence and output M column selection signals to the outside, the second address decoding unit receives the column address, the synchronization signal, and the second clock signal, and the jth second address decoding unit determines the column start signal in the column selection signal according to the start column address of the window to be opened; Controlling the row decoding module and the column decoding module to perform synchronous windowing according to the synchronization signal, the row decoding module performs row windowing according to the row start signal and the first clock signal, and the column decoding module performs column windowing according to the column start signal and the second clock signal, so as to perform image windowing control; Wherein, i and j are integers, 1≤i≤N, 1≤j≤M, N is the number of the first address decoding units, and M is the number of the second address decoding units.

2. The image windowing control circuit according to claim 1, characterized in that: The first address decoding unit includes an address memory, an AND gate address decoder, an AND gate, a first D flip-flop, a second D flip-flop and an OR gate, wherein a first input terminal of the AND gate address decoder is connected to an output terminal of the address memory, an output terminal of the AND gate address decoder is connected to a first input terminal of the AND gate, an output terminal of the AND gate is connected to a first input terminal of the first D flip-flop, an output terminal of the first D flip-flop is connected to a first input terminal of the OR gate, and an output terminal of the second D flip-flop is connected to a second input terminal of the OR gate, wherein a second input terminal of the AND gate address decoder is connected to the row address, a second input terminal of the AND gate is connected to the synchronization signal, a second input terminal of the first D flip-flop and a first input terminal of the second D flip-flop are connected to the first clock signal, an output terminal of the OR gate outputs the row selection signal, a second input terminal of the second D flip-flop in the first address decoding unit of the next stage is connected to an output terminal of the OR gate in the first address decoding unit of the previous stage, and a second input terminal of the second D flip-flop in the first first address decoding unit is connected to a low level.

3. The image windowing control circuit according to claim 2, characterized in that: The structure of the second address decoding unit is the same as that of the first address decoding unit. In the second address decoding unit, the second input terminal of the AND gate address decoder is connected to the column address, the second input terminal of the AND gate is connected to the synchronization signal, the second input terminal of the first D flip-flop and the first input terminal of the second D flip-flop are connected to the second clock signal, the output terminal of the OR gate outputs the column selection signal, the second input terminal of the second D flip-flop in the next level of the second address decoding unit is connected to the output terminal of the OR gate in the first level of the first address decoding unit, and the second input terminal of the second D flip-flop in the first second address decoding unit is connected to a low level.

4. A control method applied to the image windowing control circuit according to any one of claims 1 to 3, characterized in that: include: Acquire the window opening information of the window to be opened, wherein the window opening information includes a start address, the synchronization signal, and a clock signal; Determine the starting signal of the window to be opened according to the starting address, the synchronization signal and the clock signal; Windowing is performed according to the start signal and the clock signal to complete image windowing control.

5. The control method of the image windowing control circuit according to claim 4, characterized in that: The starting address includes the row starting address and the column starting address, the clock signal includes the first clock signal and the second clock signal, and determining the starting signal of the window to be opened according to the starting address, the synchronization signal, and the clock signal includes: Determine a row start signal based on the row start address, the synchronization signal, and the first clock signal; Determine a column start signal based on the column start address, the synchronization signal, and the second clock signal; The start signal includes the row start signal and the column start signal.

6. The control method of the image windowing control circuit according to claim 5, characterized in that: Determining a row start signal based on the row start address, the synchronization signal, and the first clock signal includes: Matching the row start address with a preset row storage address, and if the row start address matches the preset row storage address, performing address decoding on the row start address based on the synchronization signal to obtain a row start decoding signal; The row start decoding signal is triggered according to the rising edge of the first clock signal to obtain the row start signal.

7. The control method of the image windowing control circuit according to claim 6, characterized in that: When the window to be windowed is single, windowing is performed according to the start signal and the clock signal, including: Shift-triggering the row start signal based on the first clock signal to obtain a plurality of row selection signals; Shift-triggering the column start signal based on the second clock signal to obtain a plurality of column selection signals; Row windowing and column windowing are performed on the window to be windowed according to the row selection signal and the column selection signal.

8. The control method of the image windowing control circuit according to claim 7, characterized in that: When there are multiple windows to be windowed, windowing is performed according to the start signal and the clock signal, including: If the starting addresses of the plurality of windows to be windowed are the same, relevant address windowing is performed based on the starting signal of the same starting address and the clock signal corresponding to the window to be windowed; If the starting addresses of the plurality of windows to be opened are all different, the image window opening control is performed based on a single image window opening operation.

9. An image sensor, characterized in that: It is provided with an image windowing control circuit as described in any one of claims 1 to 3, and the image sensor comprises: A row driving module, connected to the row decoding module, generating a pixel control signal according to the row selection signal; An active pixel array, connected to the row driving module, generating a row control signal according to the pixel control signal; An image processing module, connected to the active pixel array and the column decoding module, determines the window to be opened according to the row control signal and the column selection signal and performs image processing on the image of the window to be opened to obtain an image processing signal; The output module is connected to the image processing module, and sorts and outputs the image processing signal to obtain a target image.

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