Memory, preparation method thereof and electronic equipment

Abstract

The invention relates to a memory, a preparation method thereof and electronic equipment. The memory includes: a substrate; a plurality of first word lines extending along a first direction perpendicular to the substrate; the storage units comprise first gate insulation layers surrounding the outer side walls of the first word lines; the bit lines extend in the third direction parallel to the substrate and are distributed at intervals in the second direction; the second direction and the third direction intersect and are perpendicular to the first direction; a plurality of reference signal lines extending along the first direction; the memory unit further comprises a second gate insulating layer covering the outer side wall of the reference signal line; the first gate insulating layer and the second gate insulating layer both comprise ferroelectric materials; the second word lines are located on the side, away from the reference signal line, of the second gate insulation layer, and the second word lines extend in the first direction. By adopting the memory, the storage density can be increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory device and a method for preparing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. However, the storage density of memories in related technologies is still low. Summary of the invention

[0004] Based on this, it is necessary to provide a memory and a preparation method thereof, and an electronic device to address the problem of low storage density of memories in related technologies.

[0005] In order to achieve the above objectives, in a first aspect, the present application provides a memory, including:

[0006] substrate;

[0007] A plurality of first word lines extending along a first direction perpendicular to the substrate;

[0008] a plurality of memory cells, each memory cell comprising a first gate insulating layer surrounding an outer sidewall of the first word line;

[0009] A plurality of bit lines extending along a third direction parallel to the substrate and spaced apart along the second direction; the second direction intersects the third direction and is perpendicular to the first direction;

[0010] A plurality of reference signal lines extending along the first direction; the storage unit further comprises a second gate insulating layer covering the outer sidewalls of the reference signal lines; the first gate insulating layer and the second gate insulating layer both comprise ferroelectric material;

[0011] A plurality of second word lines are located on a side of the second gate insulating layer away from the reference signal line, and the second word lines extend along the first direction.

[0012] The above-mentioned memory includes a substrate, a plurality of first word lines, a plurality of storage cells, a plurality of bit lines, a plurality of reference signal lines and a plurality of second word lines. Among them, the plurality of first word lines extend along a first direction perpendicular to the substrate; the storage cell includes a first gate insulating layer surrounding the outer side wall of the first word line; a plurality of bit lines extend along a third direction parallel to the substrate and are spaced and distributed along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a plurality of reference signal lines extend along the first direction; the storage cell also includes a second gate insulating layer covering the outer side wall of the reference signal line; the first gate insulating layer and the second gate insulating layer both include ferroelectric material; a plurality of second word lines are located on the side of the second gate insulating layer away from the reference signal line, and the second word lines extend along the first direction. Since the material of the gate insulating layer is a ferroelectric material, there is no need to form an additional capacitor, so the storage density of the memory can be effectively improved to achieve high-density storage. In addition, the storage cells are all double-gate ferroelectric field effect transistors, which can store at least 1.5 bits of data, which can further improve the storage density compared to the situation in the related art where a storage cell can only store 1 bit of data. In addition, the memory in this embodiment can be stacked into multiple layers along the third direction perpendicular to the substrate, and the storage array of each layer can also include multiple storage units arranged in an array, thereby realizing a 3D stacked memory, which can further improve the storage density.

[0013] In some embodiments, the side wall portion of the first gate insulation layer in contact with the bit line serves as the bit line contact region of each of the memory cells, and the side wall portion in contact with the reference signal line serves as the reference signal line contact region of each of the memory cells; the bit line contact regions of the plurality of memory cells sharing the same first word line are arranged at intervals along the first direction.

[0014] In some embodiments, the second word lines, the reference signal lines, and the bit lines of the memory cells are arranged at intervals along the second direction.

[0015] In some embodiments, the memory also includes a semiconductor layer, which is connected to the bit line and is located between the reference signal line and a second gate insulation layer covering the outer side wall of the reference signal line, and between the bit line and the second gate insulation layer covering the outer side wall of the bit line.

[0016] In some embodiments, the reference signal line is grounded, and the reference signal line is connected to the semiconductor layer.

[0017] In some embodiments, the semiconductor layer at least partially surrounds the first word line, and the first gate insulation layer is provided between the first word line and the semiconductor layer; the second word line is located on a side of the semiconductor layer away from the first word line, and the second gate insulation layer is provided between the second word line and the semiconductor layer.

[0018] In some embodiments, the first gate insulating layer and the second gate insulating layer include different materials.

[0019] In some embodiments, in two storage cells belonging to the same row between two adjacent bit lines, the two reference signal lines and two first word lines corresponding to the two storage cells are located between the two bit lines, the two storage cells share the same second word line, and the shared second word line is located between the two reference signal lines.

[0020] In some embodiments, a plurality of the storage units are stacked in multiple layers along the first direction, and the memory further comprises:

[0021] A plurality of first isolation walls sequentially penetrate the spacing regions between the storage units in each layer along the first direction; wherein the plurality of storage units spaced apart and distributed along the first direction contact the same first isolation wall.

[0022] In some embodiments, a side of the reference signal line away from the first word line is further provided with a plurality of extension portions, and the extension portions on the same reference signal line are spaced apart along the first direction; the second gate insulating layer surrounds the outer side walls of the extension portions.

[0023] In some embodiments, the memory further includes a plurality of conductive layers, each of the conductive layers being located between each of the second word lines and the second gate insulating layer.

[0024] In some embodiments, the ferroelectric material includes ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0025] In some embodiments, the memory further includes a plurality of second isolation walls, which sequentially penetrate each layer of the memory cells along the first direction and extend along the second direction, and are located between two adjacent bit lines.

[0026] In some embodiments, the memory further includes a dielectric layer, the bit line is located between two adjacent dielectric layers, and the semiconductor layer and the second gate insulating layer are sequentially disposed between the bit line and the dielectric layer.

[0027] In a second aspect, the present application also provides an electronic device, which includes the memory as described in any of the previous embodiments.

[0028] In the above embodiments, the electronic device includes the memory as described above, which can realize high-density and large-capacity data storage.

[0029] In a third aspect, the present application further provides a method for preparing a memory, the method for preparing the memory comprising:

[0030] providing a substrate;

[0031] forming a stacked structure on the substrate, wherein the stacked structure includes conductive layers and dielectric layers stacked alternately;

[0032] forming a plurality of first trenches in the stacked structure, wherein the sidewalls of the first trenches expose the end surfaces of the alternately stacked conductive layers and dielectric layers;

[0033] Transversely etching each layer of the conductive layer exposed in the first groove to form a plurality of second grooves, wherein the second grooves extend along a second direction parallel to the substrate;

[0034] forming a plurality of third grooves in the stacked structure;

[0035] forming a second gate insulating layer, a semiconductor layer and a bit line in the second trench, wherein the second gate insulating layer covers an outer sidewall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line;

[0036] forming a first gate insulating layer, a first word line and a reference signal line in each of the third trenches;

[0037] A plurality of second word lines are formed in the stacked structure. Each of the second word lines extends along the first direction and is located on a side of the second gate insulating layer away from the reference signal line.

[0038] The preparation method of the above-mentioned memory is formed on the substrate, wherein the stacked structure includes an alternately stacked conductive layer and a dielectric layer; a plurality of first grooves are formed in the stacked structure, and the sidewalls of the first grooves expose the end faces of the alternately stacked conductive layer and the dielectric layer; each layer of the conductive layer exposed in the first groove is laterally etched to form a plurality of second grooves, and the second grooves extend along a second direction parallel to the substrate; a plurality of third grooves are formed in the stacked structure; a second gate insulating layer, a semiconductor layer and a bit line are correspondingly formed in the second grooves, the second gate insulating layer covers the outer sidewall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line; a first gate insulating layer, a first word line and a reference signal line are formed in each of the third grooves; a plurality of second word lines are formed in the stacked structure, and each second word line extends along the first direction and is located on the side of the second gate insulating layer away from the reference signal line. Since the material of the gate insulating layer is a ferroelectric material, no additional capacitor needs to be formed, so the storage density of the memory can be effectively improved to achieve high-density storage. In addition, the memory cells are all dual-gate ferroelectric field effect transistors, which can store at least 1.5 bits of data, which can further improve the storage density compared to the situation in the related art where a memory cell can only store 1 bit of data. In addition, the memory in this embodiment can be stacked into multiple layers along the third direction Z perpendicular to the substrate, and each layer of the memory array can also include multiple memory cells arranged in an array, thereby realizing a 3D stacked memory, which can further improve the storage density.

[0039] In some embodiments, the side wall portion of the first gate insulation layer in contact with the bit line serves as the bit line contact region of each of the memory cells, and the side wall portion in contact with the reference signal line serves as the reference signal line contact region of each of the memory cells; the bit line contact regions of the plurality of memory cells sharing the same first word line are arranged at intervals along the first direction.

[0040] In some embodiments, each of the reference signal lines is respectively connected to a reference signal line contact region of the memory cell; the second gate insulation layer also covers an outer side wall of the reference signal line, and a portion of the second gate insulation layer away from the outer side wall of the reference signal line in contact with the conductive layer serves as a second word line contact region of each of the memory cells.

[0041] In some embodiments, forming a second gate insulating layer, a semiconductor layer and a bit line in the second trench includes:

[0042] forming a continuously distributed second gate insulating layer on an inner wall of the first trench, an inner wall of the second trench, and an inner wall of the third trench;

[0043] forming the semiconductor layer on the second gate insulating layer;

[0044] forming a conductive material layer in the first trench and in the second trench;

[0045] The conductive material layer in the first trench is removed, and the conductive material layer in the remaining second trench is used as the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of polarization of a ferroelectric dielectric under the action of an electric field provided in an embodiment;

[0048] Figure 2 is a schematic structural diagram of a ferroelectric field effect transistor provided in an embodiment;

[0049] Figure 3 A diagram showing the correspondence between the polarization directions of two layers of ferroelectric dielectrics and stored data in a ferroelectric field effect transistor provided in an embodiment;

[0050] Figure 4 is a curve diagram of gate voltage and drain current of a ferroelectric field effect transistor provided in an embodiment;

[0051] Figure 5 A circuit diagram of a basic storage unit of a memory provided in an embodiment;

[0052] Figure 6 is a top view of a memory provided in one embodiment;

[0053] Figure 7 In one embodiment, Figure 6 Cross-sectional view along the A-A' direction;

[0054] Figure 8 In one embodiment, Figure 7 Top view cross section along the C-C' direction;

[0055] Fig. 9 In one embodiment, Figure 6 Cross-sectional view along the B-B' direction;

[0056] Fig.10 is a flow chart of a method for preparing a memory provided in an embodiment;

[0057] Fig.11 A top view of a structure obtained in step S102 in a method for preparing a memory provided in an embodiment;

[0058] Fig.12 In one embodiment, Fig.11 Cross-sectional view along the A-A' direction;

[0059] Fig.13 A top view of a structure obtained in step S104 in a method for preparing a memory provided in an embodiment;

[0060] Fig.14 In one embodiment, Fig.13 Cross-sectional view along the A-A' direction;

[0061] Fig.15 A top view of a structure obtained in step S105 in a method for preparing a memory provided in an embodiment;

[0062] Fig.16 In one embodiment, Fig.15 Cross-sectional view along the A-A' direction;

[0063] Fig.17 In another embodiment, Fig.15 Cross-sectional view along the A-A' direction;

[0064] Fig.18 is a flow chart of step S106 in a method for preparing a memory provided in an embodiment;

[0065] Fig.19 A top view of a structure obtained in step S1062 in a method for preparing a memory provided in an embodiment;

[0066] Fig. 20 In one embodiment, Fig.19 Cross-sectional view along the A-A' direction;

[0067] Fig.21 is a flow chart of step S1063 in a method for preparing a memory provided in an embodiment;

[0068] Fig. 22 is a top view of a structure obtained in step S1063a of a method for preparing a memory provided in an embodiment;

[0069] Fig.23 In one embodiment, Fig. 22 Cross-sectional view along the A-A' direction;

[0070] Fig.24is a top view of a structure obtained in step S1063c in a method for preparing a memory provided in an embodiment;

[0071] Fig.25 In one embodiment, Fig.24 Cross-sectional view along the A-A' direction;

[0072] Fig.26 is a top view of a structure obtained in step S1063e in a method for preparing a memory provided in an embodiment;

[0073] Fig. 27 In one embodiment, Fig.26 Cross-sectional view along the A-A' direction;

[0074] Fig.28 A top view of a structure obtained in step S1064 in a method for preparing a memory provided in an embodiment;

[0075] Fig.29 In one embodiment, Fig.28 Cross-sectional view along the A-A' direction;

[0076] Fig.30 is a flowchart of step S107 in a method for preparing a memory provided in an embodiment;

[0077] Fig.31 A top view of a structure obtained in step S1071 in a method for preparing a memory provided in an embodiment;

[0078] Fig.32 In one embodiment, Fig.30 Cross-sectional view along the A-A' direction;

[0079] Fig.33 A top view of a structure obtained in step S1072 in a method for preparing a memory provided in an embodiment;

[0080] Fig.34 In one embodiment, Fig.33 Cross-sectional view along the A-A' direction;

[0081] Fig.35 A top view of a structure obtained in step S1073 in a method for preparing a memory provided in an embodiment;

[0082] Fig.36 In one embodiment, Fig.33 Cross-sectional view along the A-A' direction.

[0083] Explanation of the accompanying drawings: 100-channel layer, 110-first ferroelectric layer, 120-first gate structure, 130-second ferroelectric layer, 140-second gate structure, 150-first doped region, 160-second doped region, 200-ferroelectric field effect transistor, 310-dielectric layer, 320-conductive layer, 330-second isolation wall, 400-substrate, 610-first trench, 620-second trench, 630-third trench, 10-second gate insulating layer, 20-semiconductor layer, 30-first sacrificial layer, 40-second sacrificial layer, 50-conductive layer, 510-bit line, 60-third sacrificial layer, 70-first gate insulating layer, 710-first isolation wall, 80-first word line, 90-reference signal line, 11-second word line. DETAILED DESCRIPTION

[0084] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0086] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as the second element, component, region, layer or part.

[0087] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0088] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0089] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0090] Ferroelectric memory is a non-volatile memory that uses the ferroelectric effect of ferroelectric dielectrics to achieve data storage and non-volatility. The ferroelectric effect means that when a certain electric field is applied to the ferroelectric dielectric, the central atoms of the ferroelectric dielectric move under the action of the electric field and reach a stable state; when the electric field is removed from the ferroelectric dielectric, the central atoms will remain in their original position.

[0091] Figure 1 is a schematic diagram of the polarization of ferroelectric dielectrics under the action of an electric field, as shown in Figure 1As shown in the figure, ferroelectric dielectrics exhibit polarization hysteresis characteristics and have two different polarization directions, which can correspond to the storage of one bit of data. Specifically, when an electric field is applied to the ferroelectric dielectric, the central atoms of the ferroelectric dielectric move in the crystal along the direction of the electric field and stop at a low-energy state position; when the electric field is reversed and applied to the ferroelectric dielectric, the central atoms of the ferroelectric dielectric move in the crystal along the direction of the reversed electric field and stop at another low-energy state position. The movement of a large number of central atoms in the crystal will form ferroelectric domains, and the ferroelectric domains will form polarized charges under the action of the electric field.

[0092] A basic storage unit in a conventional memory is usually composed of a capacitor and a field effect transistor, and a layer of crystalline ferroelectric dielectric is deposited between two electrode plates of the capacitor. However, the storage density of the conventional memory is low.

[0093] like Figure 2 As shown, when designing a most basic memory cell included in the memory, the present application forms two gate insulating layers composed of ferroelectric dielectrics on the upper and lower surfaces of a channel layer to form a ferroelectric field effect transistor with a double gate. The transistor simultaneously realizes the functions of selecting the memory cell and the storage capacitor, thereby constituting a most basic memory cell of the memory provided by the present application.

[0094] In order to facilitate the understanding of the function of simultaneously enabling the storage unit and the storage capacitor, Figure 2 The double-gate ferroelectric field effect transistor formed on the upper and lower surfaces of the channel layer shown in FIG. Figure 2 As shown, a first ferroelectric layer 110 and a first gate structure 120 are sequentially formed on the upper surface of the channel layer 100. A second ferroelectric layer 130 and a second gate structure 140 are sequentially formed on the lower surface of the channel layer 100, and the channel layer 100 serves as a semiconductor layer of the transistor. Subsequently, a first doped region 150 and a second doped region 160 are respectively formed on the exposed surface of the channel layer 100 to serve as a source region and a drain region of the ferroelectric field effect transistor, so as to form a complete dual-gate ferroelectric field effect transistor.

[0095] Figure 3 This is the correspondence between the polarization direction of the two layers of ferroelectric dielectric in the double-gate ferroelectric field effect transistor and the data it represents, such as Figure 3As shown, assuming that the upper ferroelectric dielectric and the lower dielectric have no electric field reversal, the data "00" can be represented; assuming that the upper ferroelectric dielectric and the lower dielectric have electric field reversal, the data "11" can be represented; assuming that the upper ferroelectric dielectric has no electric field reversal and the lower dielectric has electric field reversal, the data "01" can be represented. (Similarly, assuming that the upper ferroelectric dielectric has electric field reversal and the lower dielectric has not electric field reversal, the data "10" can be represented). In addition, since the naming of the upper and lower dielectrics can be flexibly interchanged in actual application scenarios, the situation where one layer of ferroelectric dielectric has electric field reversal and the other layer of ferroelectric dielectric has not electric field reversal can be represented as data "01 / 10". When the electric field is removed, the central atoms of the two layers of ferroelectric dielectrics are in a low energy state, and the position of the central atoms remains unchanged, so that the stored data will not be lost even in the case of power failure, so the non-volatility of the stored data can be achieved.

[0096] By using this ferroelectric dielectric as the gate insulating layer, a gate of a dual-gate ferroelectric field-effect transistor will exhibit two gates with varying threshold voltages (V th ) of the channel current (I D )-gate voltage (V GS ) curve, that is, a gate has two states, which are used to represent the data of "1" and "0". These two states can be obtained by applying a sufficiently large positive voltage or negative voltage to one gate of the double-gate ferroelectric field effect transistor. Therefore, Figure 4 As shown in the figure, the data information stored in the dual-gate ferroelectric field effect transistor can be r (the voltage corresponding to the dotted line in the figure) is used to read data. Through a dual-gate transistor, at least three states can be realized (i.e., at least 1.5 bits of data can be stored). That is to say, for a basic storage unit of the memory designed in this application, it can store at least 1.5 bits of data.

[0097] Figure 5 A circuit diagram corresponding to a basic storage unit in the memory provided by this application, such as Figure 5 As shown, the first gate structure of the ferroelectric field effect transistor 200 is connected to the first word line WL1, the second gate structure of the ferroelectric field effect transistor 200 is connected to the second word line WL2, the drain of the ferroelectric field effect transistor 200 is connected to the bit line BL, and the source of the ferroelectric field effect transistor 200 is grounded. Alternatively, the first gate structure of the ferroelectric field effect transistor 200 is connected to the first word line WL1, the second gate structure of the ferroelectric field effect transistor 200 is connected to the second word line WL2, the source of the ferroelectric field effect transistor 200 is connected to the bit line BL, and the drain of the ferroelectric field effect transistor 200 is grounded.

[0098] By applying appropriate voltages to the first word line WL1, the second word line WL2 and the bit line BL corresponding to the memory cell, the first ferroelectric layer and the second ferroelectric layer have the same or different polarization directions, thereby completing the data writing process. When reading the data stored in the memory cell, it is only necessary to apply an appropriate intermediate voltage V to the word line WL1 and / or WL2 corresponding to the memory cell. R , and according to whether the source and drain of the ferroelectric field effect transistor 200 are turned on, the threshold voltage of the ferroelectric field effect transistor 200 can be determined, and the data stored in the storage unit can be determined according to the size of the threshold voltage to realize data reading.

[0099] In order to realize a memory composed of multiple storage units in physical structure, the present application provides a memory. Figure 6 is a top view of the memory in this application, Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the A-A' direction, Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure along the C-C' direction, Fig. 9 for Figure 6 Schematic diagram of the cross-sectional structure along the B-B' direction. Figure 6-Figure 9 The memory includes a substrate 400, a plurality of first word lines 80, a plurality of memory cells, a plurality of bit lines 510, a plurality of reference signal lines 90, and a plurality of second word lines 11. The plurality of first word lines 80 extend along a first direction perpendicular to the substrate 400. The memory cell includes a first gate insulating layer 70 surrounding the outer sidewalls of the first word lines 80. The plurality of bit lines 510 extend along a third direction parallel to the substrate 400 and are spaced apart along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction. The plurality of reference signal lines 90 extend along the first direction, and the memory cell also includes a second gate insulating layer 10 covering the outer sidewalls of the reference signal lines 90 and the outer sidewalls of the bit lines 510, and the first gate insulating layer 70 and the second gate insulating layer 10 both include ferroelectric materials. The plurality of second word lines 11 are located on a side of the second gate insulating layer 10 away from the reference signal lines 90, and the second word lines 11 extend along the first direction.

[0100] like Figure 6-Figure 9 As shown, the first direction may be the X direction, the second direction may be the Y direction, and the third direction may be the Z direction. In addition, in order to facilitate understanding of this solution, Figure 6 The dotted box in the figure can be regarded as a storage unit. For the memory provided in the present application, the semiconductor layer 20 included in a storage unit can be as follows: Figure 2 The channel layer shown in FIG. 1 , the first gate insulating layer 70 may be used as Figure 2 The first ferroelectric layer shown, the second gate insulating layer 10 can be used as Figure 2The second ferroelectric layer shown. Optionally, the first direction and the second direction intersect, and are preferably perpendicular to each other.

[0101] In one implementation, combining Figure 6-Figure 9 , multiple memory cells are also spaced apart along a second direction Y parallel to the substrate 400. At this time, multiple memory cells are spaced apart along the second direction Y and the third direction Z, respectively, to form a memory array in the same layer. The second direction Y is the row direction, and the third direction Z is the column direction. Accordingly, multiple first word lines 80 are spaced apart along the second direction Y, multiple memory cells in the same column share the same bit line 510, and multiple memory cells in the same row are connected to different first word lines 80. Multiple second word lines 11 extend along the first direction X and are spaced apart along the second direction Y. Among multiple memory cells in the same row, two adjacent memory cells share the same second word line 11. The multiple bit lines 510 and the multiple reference signal lines 90 are also spaced apart along the second direction Y. At this time, the multiple bit lines 510 are spaced apart along the second direction Y, multiple storage cells in the same column are connected to the same bit line 510, and multiple storage cells in the same row are connected to different bit lines 510; the multiple reference signal lines 90 are spaced apart along the second direction Y and the third direction Z, multiple storage cells in the same column are connected to different reference signal lines 90, and multiple storage cells in the same row are connected to different reference signal lines 90.

[0102] In another implementation, combining Figure 6-Figure 9 , the plurality of memory cells are also spaced apart along the first direction X. At this time, the plurality of memory cells are stacked into multiple layers of memory cells along the first direction X, and each layer of memory cells includes multiple memory cells spaced apart along the third direction Z. The second direction Y is the row direction, and the third direction Z is the column direction. Accordingly, the plurality of first word lines 80 are spaced apart along the third direction Z, and the plurality of memory cells in the same layer and the same column share the same bit line 510. The plurality of second word lines 11 extend along the first direction X and are spaced apart along the third direction Z. Among the plurality of memory cells in the same row, two adjacent memory cells share the same second word line 11. The multiple bit lines 510 and the multiple reference signal lines 90 are also spaced apart along the second direction Y. At this time, the multiple bit lines 510 are spaced apart along the first direction X and the second direction Y, respectively. Multiple storage cells in the same column are connected to the same bit line 510, and multiple storage cells in the same row are connected to different bit lines 510. The multiple reference signal lines 90 are spaced apart along the second direction Y and the third direction Z, respectively. Multiple storage cells in the same column are connected to different reference signal lines 90, and multiple storage cells in the same row are connected to different reference signal lines 90.

[0103] In another implementation, combining Figure 6-Figure 9, the plurality of memory cells are also spaced apart along the first direction X and the second direction Y, respectively. At this time, the plurality of memory cells are stacked into multiple layers of memory cells along the first direction X, and each layer of memory cells includes multiple memory cells spaced apart along the third direction Z. The plurality of first word lines 80, the plurality of second word lines 11, the plurality of bit lines 510, and the plurality of reference signal lines 90 are arranged in a manner similar to the above two implementations.

[0104] Exemplarily, the first word line 80 , the second word line 11 and the reference signal line 90 are disposed on the same surface perpendicular to the substrate 400 , the first direction X and the second direction Y are parallel to the surface, and the third direction Z is perpendicular to the surface.

[0105] Optionally, a ground layer may be provided in the substrate 400 , and each reference signal line 90 is connected to the ground layer, and the potentials of the reference signal lines 90 may be kept consistent.

[0106] The above-mentioned memory includes a substrate 400, a plurality of first word lines 80, a plurality of memory cells, a plurality of bit lines 510, a plurality of reference signal lines 90, and a plurality of second word lines 11. Among them, the plurality of first word lines 80 extend along a first direction perpendicular to the substrate 400. The memory cell includes a first gate insulating layer 70 surrounding the outer sidewalls of the first word lines 80. The plurality of bit lines 510 extend along a third direction parallel to the substrate 400 and are spaced apart along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction. The plurality of reference signal lines 90 extend along the first direction, and the memory cell also includes a second gate insulating layer 10 covering the outer sidewalls of the reference signal lines 90 and the outer sidewalls of the bit lines 510, and the first gate insulating layer 70 and the second gate insulating layer 10 both include ferroelectric materials. The plurality of second word lines 11 are located on a side of the second gate insulating layer 10 away from the reference signal lines 90, and the second word lines 11 extend along the first direction. Since the material of the gate insulating layer is a ferroelectric material, no additional capacitor needs to be formed, so the storage density of the memory can be effectively improved to achieve high-density storage. In addition, the memory cells are all dual-gate ferroelectric field effect transistors, which can store at least 1.5 bits of data, which can further improve the storage density compared to the situation in the related art where a memory cell can only store 1 bit of data. In addition, the memory in this embodiment can be stacked into multiple layers along the first direction X perpendicular to the substrate 400, and each layer of the memory array can also include multiple memory cells arranged in an array, so as to realize a 3D stacked memory, thereby further improving the storage density.

[0107] In some embodiments, the side wall portion of the first gate insulation layer 70 in contact with the bit line 510 serves as the bit line contact region of each memory cell, and the side wall portion in contact with the reference signal line 90 serves as the reference signal line contact region of each memory cell, and the bit line contact regions of multiple memory cells sharing the same first word line 80 are arranged at intervals along the first direction.

[0108] In some embodiments, Figure 6-Figure 9 As shown, a plurality of extensions are provided on one side of the reference signal line 90 away from the first word line 80 , and the extensions on the same reference signal line 90 are spaced apart along the first direction; the second gate insulating layer 10 surrounds the outer sidewalls of the extensions.

[0109] In some embodiments, the second word lines 11 , the reference signal lines 90 , and the bit lines 510 of the memory cells are arranged at intervals along the second direction.

[0110] In some embodiments, the memory also includes a semiconductor layer 20, which is connected to the bit line 510 and is located between the reference signal line 90 and the second gate insulation layer 10 covering the outer side wall of the reference signal line 90, and is located between the bit line 510 and the second gate insulation layer 10 covering the outer side wall of the bit line 510.

[0111] Since the semiconductor layer 20 is located between the reference signal line 90 and the second gate insulating layer 10 covering the outer wall of the reference signal line 90, and is located between the bit line 510 and the second gate insulating layer 10 covering the outer wall of the bit line 510, the contact area between the semiconductor layer 20 and the second gate insulating layer 10 can be increased. This allows for greater adhesion between them, a compact structure, and is also beneficial for improving the storage density of the memory and realizing a high-density memory structure.

[0112] In some embodiments, the reference signal line 90 is grounded and connected to the semiconductor layer 20 .

[0113] In some embodiments, the semiconductor layer 20 at least partially surrounds the first word line 80, and a first gate insulating layer 70 is provided between the first word line 80 and the semiconductor layer 20. The second word line 11 is located on a side of the semiconductor layer 20 away from the first word line 80, and a second gate insulating layer 10 is provided between the second word line 11 and the semiconductor layer 20.

[0114] In some embodiments, Figure 6-Figure 9 As shown, multiple storage units are stacked into multiple layers along a first direction, and the memory also includes multiple first isolation walls 710, which sequentially penetrate the spacing areas between each layer of storage units along the first direction, wherein multiple storage units spaced apart and distributed along the first direction contact the same first isolation wall 710.

[0115] In the above embodiment, by providing the first isolation wall 710, insulation can be formed between many adjacent memory cells at the same time, thereby reducing the number of process steps and lowering the implementation cost.

[0116] In some embodiments, Figure 6-Figure 9As shown, the memory further includes a plurality of conductive layers 320 , each conductive layer 320 being located between each second word line 11 and a second word line contact region.

[0117] Among them, the material of the conductive layer 320 may include polycrystalline silicon, single crystal silicon or metal material. Furthermore, the metal material may include metals such as copper, gold, titanium, silver, aluminum, etc., or may include multilayer metals composed of the metals of the above materials, or may include metal alloys, etc., which are not limited in this embodiment.

[0118] In some embodiments, the ferroelectric material includes ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0119] In some embodiments, Figure 6-Figure 9 As shown, the memory further includes a plurality of second isolation walls 330 , each of which sequentially penetrates each layer of memory cells along the first direction and extends along the second direction, and is located between two adjacent bit lines 510 .

[0120] In some embodiments, Figure 6-Figure 9 As shown, the memory further includes a dielectric layer 310 , each bit line 510 is located between two adjacent dielectric layers 310 , and a semiconductor layer 20 and a second gate insulating layer 10 are sequentially disposed between the bit line 510 and the dielectric layer 310 .

[0121] The material of the dielectric layer 310 may be one or a combination of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO 2 ).

[0122] Based on the same inventive concept, the present application also provides an electronic device, which may be a television, a mobile phone, a computer, a tablet, etc. The electronic device includes the memory as described above.

[0123] In the above embodiments, the electronic device includes the aforementioned memory, which can realize high-density and large-capacity data storage.

[0124] Based on the same inventive concept, the present application also provides a method for preparing a memory, such as Fig.10 As shown, the preparation method comprises the following steps:

[0125] S101: providing a substrate.

[0126] Among them, the material of the substrate can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0127] S102: forming a stacked structure on a substrate, wherein the stacked structure includes conductive layers and dielectric layers stacked alternately.

[0128] The material of the dielectric layer 310 may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). The material of the conductive layer 320 may include polysilicon, single crystal silicon, or a metal material. Further, the metal material may include metals such as copper, gold, titanium, silver, and aluminum, or may include a multilayer metal composed of the metals of the above materials, or may include a metal alloy, etc. This embodiment is not limited here.

[0129] like Fig.11 and Fig.12 As shown, a deposition process may be used to alternately deposit conductive layers 320 and dielectric layers 310 on the substrate 400 to ultimately form a stacked structure.

[0130] The deposition process may include but is not limited to one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer 310 (SOD). The specific deposition process to be used may be determined comprehensively based on the process cost requirements and the specific materials of the conductive layer 320 and the dielectric layer 310, and this embodiment does not limit this.

[0131] In addition, to facilitate understanding of this solution, Fig.12The example shows that the conductive layer 320 and the dielectric layer 310 are both deposited with three layers. However, it can be understood that in other suitable application scenarios, the number of layers of the conductive layer 320 and the dielectric layer 310 can also be other suitable numbers of layers, which is not limited in this embodiment.

[0132] S103: forming a plurality of first trenches in the stacked structure, wherein sidewalls of the first trenches expose end surfaces of alternately stacked conductive layers and dielectric layers.

[0133] Optionally, a plurality of first trenches 610 may be formed in the stacked structure by using a photolithography and etching process. Furthermore, a hard mask layer may be first formed on the stacked structure, and then a photoresist layer may be formed on the hard mask layer, and then a portion of the hard mask layer may be removed by photolithography and etching processes to form a patterned hard mask layer, and finally the stacked structure may be etched based on the patterned hard mask layer to form a plurality of first trenches 610 in the stacked structure.

[0134] S104: performing transverse etching on each conductive layer exposed in the first trench to form a plurality of second trenches, wherein the second trenches extend along a second direction parallel to the substrate.

[0135] like Fig.13 as well as Fig.14 As shown, the first direction may be an X direction, the second direction may be a Y direction, and the third direction may be a Z direction.

[0136] Optionally, the second trench 620 can be formed by etching each conductive layer 320 through the first trench 610. By utilizing the different etching selectivities between the conductive layer 320 and the dielectric layer 310, the conductive layer 320 is selectively etched in the conductive layer 320 and the dielectric layer 310 exposed in the first trench 610, thereby forming the second trench 620.

[0137] Exemplarily, the removal process of removing the conductive layer 320 to form the second trench 620 may include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high concentration plasma etching (HDP).

[0138] Optional, such as Fig.14 As shown, during the process of forming the second trench 620 , over-etching may be performed to remove a portion of the substrate 400 .

[0139] S105: forming a plurality of third trenches in the stacked structure.

[0140] like Figure 15-16As shown, a plurality of third trenches 630 may be formed in the stacked structure by using a photolithography and etching process. Furthermore, a hard mask layer may be formed on the stacked structure first, and then a photoresist layer may be formed on the hard mask layer, and then a portion of the hard mask layer may be removed by photolithography and etching processes to form a patterned hard mask layer, and finally the stacked structure may be etched based on the patterned hard mask layer to form a plurality of third trenches 630 in the stacked structure.

[0141] Furthermore, in a method for preparing a memory provided in another embodiment of the present application, as Fig.17 As shown, the position of each third trench 630 corresponds to the position of each second trench 620 one by one, and the orthographic projection of each second trench 620 on the substrate 400 completely covers the orthographic projection of each third trench 630 on the substrate 400 .

[0142] S106: forming a second gate insulating layer, a semiconductor layer and a bit line in the second trench, wherein the second gate insulating layer covers an outer side wall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line.

[0143] The material of the semiconductor layer 20 includes polycrystalline silicon, amorphous silicon, oxide materials (for example, indium gallium zinc oxide (IGZO), indium oxide-zinc oxide (IZO), indium tin oxide (ITO), zinc oxide and two-dimensional materials (for example, graphene, molybdenum disulfide, etc.). The material of the second gate insulating layer 10 can be a ferroelectric material, and the ferroelectric material can include ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0144] The constituent material of the bit line 510 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2 ); Metal silicides include tungsten silicon (WSi).

[0145] In some embodiments, Fig.18 As shown, the above step S106 includes:

[0146] S1061 : forming a continuously distributed second gate insulating layer 10 on the inner wall of the first trench 610 , the inner wall of the second trench 620 , and the inner wall of the third trench 630 .

[0147] Optionally, an atomic layer deposition method may be used to form a continuously distributed second gate insulating layer 10 on the inner wall of each trench.

[0148] S1062 : forming a semiconductor layer 20 on the second gate insulating layer 10 .

[0149] Optionally, the semiconductor layer 20 may be formed on the second gate insulating layer 10 by atomic layer deposition.

[0150] like Fig.19 and Fig. 20 As shown, the second gate insulating layer 10 is continuously distributed on the inner wall of each trench, and the semiconductor layer 20 is also continuously distributed on the second gate insulating layer 10 .

[0151] Optionally, in the process of forming the third trench 630, in order to ensure the integrity of the first trench 610 and the second trench 620, some trench filling material may be filled first. After the third trench 630 is formed, before forming the second gate insulating layer 10, the semiconductor layer 20 and the bit line 510, the excess trench filling material is removed uniformly to form a Fig.16 The structure shown. Fig.19 As shown, a second gate insulating layer 10 is continuously formed on the inner wall of each trench.

[0152] S1063 : forming a conductive material layer 50 in the first trench 610 and the second trench 620 .

[0153] In some embodiments, Fig.21 As shown, the above step S1063 may include the following steps:

[0154] S1063 a : filling the first sacrificial layer 30 in the first trench 610 , the second trench 620 , and the third trench 630 .

[0155] like Fig. 22 and Fig.23 As shown, the first sacrificial layer 30 completely fills the interior of each trench.

[0156] S1063 b : removing the first sacrificial layer 30 filled in the first trench 610 and the third trench 630 , and removing the semiconductor layer 20 on the inner wall of the first trench 610 and the inner wall of the third trench 630 .

[0157] S1063 c : filling the first trench 610 and the third trench 630 with the second sacrificial layer 40 .

[0158] Optionally, the second sacrificial layer 40 and the first sacrificial layer 30 may be made of different materials.

[0159] like Fig.24 and Fig.25As shown, the first sacrificial layer 30 completely fills the inside of the first trench 610 and the inside of the third trench 630 .

[0160] S1063d: removing the second sacrificial layer 40 located in the first trench 610 , and removing the first sacrificial layer 30 filled in the second trench 620 close to the first trench 610 .

[0161] Optionally, the second sacrificial layer 40 located in the first trench 610 can be removed first, and then the first sacrificial layer 30 filled in the second trench 620 near the first trench 610 can be removed by using a method similar to the formation of each second trench 620, taking advantage of the difference in etching selectivity between the first sacrificial layer 30 filled in the second trench 620 and the semiconductor layer 20 on the sidewall of the second trench 620 and the second sacrificial layer 40 filled in the third trench 630.

[0162] Exemplarily, the process of removing the first sacrificial layer 30 filled in the second trench 620 near the first trench 610 may include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP).

[0163] S1063e: Fill the conductive material layer 50 in the first trench 610 and in the second trench 620 close to the first trench 610 .

[0164] Fig.26 This is a top view of the structure obtained in step S1063e in the method for preparing a memory provided in an embodiment of the present application. Fig. 27 for Fig.26 Schematic diagram of the cross-sectional structure along the A-A' direction.

[0165] S1064 : removing the conductive material layer 50 and the semiconductor layer 20 in the first trench 610 , and retaining the conductive material layer 50 in the second trench 620 as the bit line 510 .

[0166] like Fig.28 and Fig.29 As shown, the second gate insulating layer 10 covers the outer wall of the bit line 510 , the semiconductor layer 20 is located between the second gate insulating layer 10 and the bit line 510 , and the second gate insulating layer 10 , the semiconductor layer 20 and the bit line 510 are arranged in sequence in a direction away from the inner wall of the second trench 620 .

[0167] Optional, such as Fig.29 As shown, after removing the conductive material layer 50 and the semiconductor layer 20 in the first trench 610, a third sacrificial layer 60 can be formed to fill the first trench 610 to facilitate subsequent processes. The third sacrificial layer 60 can serve as a first isolation wall 710 after the memory is manufactured.

[0168] S107 : forming a first gate insulating layer 70 , a first word line 80 and a reference signal line 90 in each third trench 630 .

[0169] In some embodiments, Fig.30 As shown, the above step S107 includes:

[0170] S1071 : Fill the third trench 630 with a conductive material to form a reference signal line 90 .

[0171] like Fig.31 and Fig.32 As shown, the constituent materials of the reference signal line 90 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2 ); Metal silicides include tungsten silicon (WSi).

[0172] S1072 : removing the second sacrificial layer 40 located in the third trench 630 .

[0173] like Fig.33 and Fig.34 As shown, Fig.33 This is a top view of the structure obtained in step S1072 in the method for preparing a memory provided in one embodiment of the present application. Fig.34 for Fig.33 Schematic diagram of the cross-sectional structure along the A-A' direction.

[0174] S1073 : depositing a first gate insulating layer 70 and a first word line 80 in sequence in the third trench 630 .

[0175] like Fig.35 and Fig.36 As shown, Fig.35 This is a top view of the structure obtained in step S1073 in the method for preparing a memory provided in one embodiment of the present application. Fig.36 for Fig.35 Schematic diagram of the cross-sectional structure along the A-A' direction.

[0176] The material of the first gate insulating layer 70 may be a ferroelectric material, and the ferroelectric material may include ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0177] Optionally, the material of the first gate insulating layer 70 may be the same as that of the second gate insulating layer 10 , and the deposition process used for the first gate insulating layer 70 may be the same as that used for the second gate insulating layer 10 .

[0178] Optionally, the first gate insulating layer 70 may be formed on the inner wall of each third trench 630 by atomic layer deposition.

[0179] The constituent material of the first word line 80 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO 2 ); Metal silicides include tungsten silicon (WSi).

[0180] S108: forming a plurality of second word lines in the stacked structure, each second word line extending along the first direction and located on a side of the second gate insulating layer away from the reference signal line, such as Figure 6-Figure 9 shown.

[0181] In some embodiments, the side wall portion of the first gate insulation layer 70 in contact with the bit line 510 serves as the bit line contact region of each memory cell, and the side wall portion in contact with the reference signal line 90 serves as the reference signal line contact region of each memory cell, and the bit line contact regions of multiple memory cells sharing the same first word line 80 are arranged at intervals along the first direction.

[0182] In some embodiments, each reference signal line 90 is respectively connected to the reference signal line contact area of ​​the storage cell; the second gate insulation layer 10 also covers the outer wall of the reference signal line 90, and the part of the second gate insulation layer 10 away from the outer wall of the reference signal line 90 in contact with the conductive layer 320 serves as the second word line contact area of ​​each storage cell.

[0183] Optional, such as Fig.30 As shown, after forming a plurality of bit lines 510 and a plurality of reference signal lines 90, a second isolation wall 330 may be formed between each row of memory cells.

[0184] Figure 6 A top view of the structure obtained in step S108 in the method for preparing a ferroelectric memory provided in one embodiment of the present application, Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the A-A' direction. Figure 6 and Figure 7As shown, each second word line 11 extends along the first direction and is respectively connected to the second gate insulating layer 10 of the memory cell through the conductive layer 320 .

[0185] The preparation method of the above-mentioned memory is formed on a substrate by forming a stacked structure, the stacked structure includes alternately stacked conductive layers and dielectric layers; forming a plurality of first grooves in the stacked structure, the sidewalls of the first grooves expose the end faces of the alternately stacked conductive layers and dielectric layers; transversely etching each layer of the conductive layer exposed in the first groove to form a plurality of second grooves, the second grooves extending along a second direction parallel to the substrate; forming a plurality of third grooves in the stacked structure; correspondingly forming a second gate insulating layer, a semiconductor layer and a bit line in the second grooves, the second gate insulating layer covering the outer side wall of the bit line, the semiconductor layer being located between the second gate insulating layer and the bit line; forming a first gate insulating layer, a first word line and a reference signal line in each third groove; forming a plurality of second word lines in the stacked structure, each second word line extending along the first direction and being located on the side of the second gate insulating layer away from the reference signal line. Since the material of the gate insulating layer is a ferroelectric material, no additional capacitor needs to be formed, so the storage density of the memory can be effectively improved to achieve high-density storage. In addition, the memory cells are all dual-gate ferroelectric field effect transistors, which can store at least 1.5 bits of data, which can further improve the storage density compared to the situation in the related art where a memory cell can only store 1 bit of data. In addition, the memory in this embodiment can be stacked into multiple layers along the third direction Z perpendicular to the substrate 400, and each layer of the memory array can also include multiple memory cells arranged in an array, so as to realize a 3D stacked memory, thereby further improving the storage density.

[0186] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A memory, characterized in that: include: substrate; A plurality of first word lines extending along a first direction perpendicular to the substrate; a plurality of memory cells, each memory cell comprising a first gate insulating layer surrounding an outer sidewall of the first word line; A plurality of bit lines extending along a third direction parallel to the substrate and spaced apart along the second direction; the second direction intersects the third direction and is perpendicular to the first direction; A plurality of reference signal lines extending along the first direction; the storage unit further comprises a second gate insulating layer covering the outer sidewalls of the reference signal lines; the first gate insulating layer and the second gate insulating layer both comprise ferroelectric material; A plurality of second word lines are located on a side of the second gate insulating layer away from the reference signal line, and the second word lines extend along the first direction.

2. The memory according to claim 1, characterized in that: The side wall portion of the first gate insulating layer in contact with the bit line serves as a bit line contact region of each of the memory cells, and the side wall portion in contact with the reference signal line serves as a reference signal line contact region of each of the memory cells; The bit line contact regions of the plurality of memory cells sharing the same first word line are arranged at intervals along the first direction.

3. The memory according to claim 1, characterized in that: The second word lines, the reference signal lines, and the bit lines of the memory cells are arranged at intervals along the second direction.

4. The memory according to claim 1, characterized in that: The memory further includes a semiconductor layer connected to the bit line and located between the reference signal line and a second gate insulating layer covering an outer sidewall of the reference signal line, and between the bit line and the second gate insulating layer covering an outer sidewall of the bit line.

5. The memory according to claim 4, characterized in that: The reference signal line is grounded and connected to the semiconductor layer.

6. The memory according to claim 4, characterized in that: The semiconductor layer at least partially surrounds the first word line, and the first gate insulating layer is provided between the first word line and the semiconductor layer; the second word line is located on a side of the semiconductor layer away from the first word line, and the second gate insulating layer is provided between the second word line and the semiconductor layer.

7. The memory according to claim 1, characterized in that: The first gate insulating layer and the second gate insulating layer include different materials.

8. The memory according to claim 1, characterized in that: In two storage cells belonging to the same row between two adjacent bit lines, the two reference signal lines and the two first word lines corresponding to the two storage cells are located between the two bit lines, the two storage cells share the same second word line, and the shared second word line is located between the two reference signal lines.

9. The memory according to claim 1, characterized in that: A plurality of the storage units are stacked in multiple layers along the first direction, and the memory further comprises: A plurality of first isolation walls sequentially penetrate the spacing regions between the storage units in each layer along the first direction; wherein the plurality of storage units spaced apart and distributed along the first direction contact the same first isolation wall.

10. The memory according to claim 1, characterized in that: A plurality of extensions are further provided on a side of the reference signal line away from the first word line, and the extensions on the same reference signal line are spaced apart and distributed along the first direction; the second gate insulating layer surrounds the outer sidewalls of the extensions.

11. The memory according to claim 1, characterized in that: The memory further includes a plurality of conductive layers, each of which is located between each of the second word lines and the second gate insulating layer.

12. The memory according to claim 1, characterized in that: The ferroelectric material includes ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

13. The memory according to claim 1, characterized in that: The memory further includes a plurality of second isolation walls, which sequentially penetrate each layer of the memory cells along the first direction and extend along the second direction, and are located between two adjacent bit lines.

14. The memory according to claim 1, characterized in that: The memory further includes a dielectric layer, the bit line is located between two adjacent dielectric layers, and the semiconductor layer and the second gate insulating layer are sequentially arranged between the bit line and the dielectric layer.

15. An electronic device, characterized in that: The electronic device comprises the memory according to any one of claims 1-14.

16. A method for preparing a memory, characterized in that: The preparation method of the memory comprises: providing a substrate; forming a stacked structure on the substrate, wherein the stacked structure includes conductive layers and dielectric layers stacked alternately; forming a plurality of first trenches in the stacked structure, wherein the sidewalls of the first trenches expose the end surfaces of the alternately stacked conductive layers and dielectric layers; Transversely etching each layer of the conductive layer exposed in the first groove to form a plurality of second grooves, wherein the second grooves extend along a second direction parallel to the substrate; forming a plurality of third grooves in the stacked structure; forming a second gate insulating layer, a semiconductor layer and a bit line in the second trench, wherein the second gate insulating layer covers an outer sidewall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line; forming a first gate insulating layer, a first word line and a reference signal line in each of the third trenches; A plurality of second word lines are formed in the stacked structure. Each of the second word lines extends along the first direction and is located on a side of the second gate insulating layer away from the reference signal line.

17. The method for preparing a memory according to claim 16, characterized in that: The side wall portion of the first gate insulating layer in contact with the bit line serves as a bit line contact region of each of the memory cells, and the side wall portion in contact with the reference signal line serves as a reference signal line contact region of each of the memory cells; The bit line contact regions of the plurality of memory cells sharing the same first word line are arranged at intervals along the first direction.

18. The method for preparing a memory according to claim 16, characterized in that: Each of the reference signal lines is respectively connected to the reference signal line contact area of ​​the storage unit; the second gate insulation layer also covers the outer wall of the reference signal line, and the part of the second gate insulation layer away from the outer wall of the reference signal line in contact with the conductive layer serves as the second word line contact area of ​​each of the storage units.

19. The method for preparing a memory according to claim 16, characterized in that: The forming of a second gate insulating layer, a semiconductor layer and a bit line in the second trench comprises: forming a continuously distributed second gate insulating layer on an inner wall of the first trench, an inner wall of the second trench, and an inner wall of the third trench; forming the semiconductor layer on the second gate insulating layer; forming a conductive material layer in the first trench and in the second trench; The conductive material layer in the first trench is removed, and the conductive material layer in the remaining second trench is used as the bit line.

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