Three-dimensional structure SiC super junction diode and preparation method thereof

Abstract

The invention provides a three-dimensional structure SiC super junction diode and a preparation method thereof, a p + type SiC epitaxial layer of the diode is provided with a plurality of hemispheres arranged at intervals, an n + type SiC epitaxial layer is deposited on the p + type SiC epitaxial layer, and an n + type electron transport layer is arranged between the two hemispheres at the left side part and located in the n + type SiC epitaxial layer; the field oxygen passivation layer is deposited on the right side part of the n + type SiC epitaxial layer, and a groove is formed in the position, directly facing the center of each hemisphere, of the anode PAD. According to the invention, the three-dimensional structure etching mask is realized by using the annealing reflux process technology of the alkaline earth doped silicon oxide mask, so that the problem of realizing the three-dimensional structure super junction structure is solved, the p + type SiC epitaxial layer is of a three-dimensional super junction structure with a plurality of hemispheres, and the super junction diode prepared based on the structure has more excellent voltage resistance balance capability; and lower resistance can be realized under the condition of the same voltage class.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a three-dimensional SiC super junction diode and a preparation method thereof. Background Art

[0002] Silicon carbide super junction (SJ) device is a new type of power semiconductor device that combines the excellent properties of silicon carbide materials and the advantages of super junction structure. It has good application prospects in electric vehicles, renewable energy, industrial power supplies and consumer electronics. The research and development of silicon carbide super junction devices is advancing rapidly and is expected to bring significant technological innovation in the field of high-efficiency power electronics.

[0003] The prior art often uses a two-dimensional silicon carbide superjunction structure to prepare a super device. The electric field expansion speed of the two-dimensional silicon carbide superjunction structure is relatively fast, which is not conducive to balancing the blocking voltage and on-resistance of the device. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a three-dimensional SiC super junction diode and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, the present invention provides a three-dimensional structure SiC super junction diode comprising: an n+ type SiC substrate, a p+ type SiC epitaxial layer, an n+ type SiC epitaxial layer, an n+ type electron transport layer, a field oxygen passivation layer, an ohmic contact, an anode PAD, a passivation protection layer and a cathode PAD;

[0006] Among them, the p+ type SiC epitaxial layer is in the form of multiple hemispheres, which are arranged at intervals on the n+ type SiC substrate; the n+ type SiC epitaxial layer is deposited on the p+ type SiC epitaxial layer, and the n+ type electron transport layer is arranged between the two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer; the field oxygen passivation layer is deposited on the right side of the n+ type SiC epitaxial layer, the anode PAD is deposited on the left side of the n+ type SiC epitaxial layer, and there is a groove facing the center of each hemisphere; the passivation protection layer is deposited on the field oxygen passivation layer, the ohmic contact is arranged on the back side of the n+ type SiC substrate, and the cathode PAD is deposited on the ohmic contact.

[0007] In a second aspect, the present invention provides a method for preparing a three-dimensional SiC super junction diode, comprising:

[0008] S100, selecting an n+ type SiC substrate and growing a p+ type SiC epitaxial layer thereon;

[0009] S200, etching the p+ type SiC epitaxial layer using a hemispherical mask to make it present a multi-hemispherical structure;

[0010] S300, epitaxially growing an n+ type SiC epitaxial layer on the plurality of hemispherical structures, and forming an n+ type electron transport layer in the spacing region of the hemispherical structures on the left side of the n+ type SiC epitaxial layer by ion implantation and activation after implantation;

[0011] S400, opening a window to form a groove by dry etching from top to bottom at a position directly opposite to the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer, and then performing sacrificial oxidation;

[0012] S500, growing a field oxygen passivation layer on the right side of the n+ type SiC epitaxial layer using a PECVD process;

[0013] S600, depositing Ni metal on the back side of the n+ type SiC substrate to form an ohmic contact;

[0014] S700, depositing a Schottky metal on the left side of the p+ type SiC epitaxial layer to form an anode PAD;

[0015] S800 , forming a passivation protection layer on the field oxide passivation layer using a photolithography process and depositing Ti / Ni / Ag metal on the back side of the ohmic contact to form a cathode PAD.

[0016] Beneficial effects:

[0017] The present invention provides a three-dimensional structure SiC super junction diode and a preparation method thereof, wherein the p+ type SiC epitaxial layer of the prepared diode is in the form of multiple hemispheres, which are arranged at intervals on the n+ type SiC substrate; the n+ type SiC epitaxial layer is deposited on the p+ type SiC epitaxial layer, the n+ type electron transport layer is arranged between the two hemispheres on the left side, and is located inside the n+ type SiC epitaxial layer; the field oxygen passivation layer is deposited on the right side of the n+ type SiC epitaxial layer, the anode PAD is deposited on the left side of the n+ type SiC epitaxial layer, and there is a groove facing the center of each hemisphere; the passivation protection layer is deposited on the field oxygen passivation layer. The present invention uses the annealing reflow process technology of the alkaline earth doped silicon oxide mask to realize the three-dimensional structure etching mask, solves the problem of realizing the three-dimensional structure super junction structure, and makes the p+ type SiC epitaxial layer present a three-dimensional super junction structure with multiple hemispheres. The super junction diode prepared based on this structure has a better voltage resistance balance capability, and can achieve lower resistance under the same voltage level conditions.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic structural diagram of a three-dimensional SiC super junction diode provided by the present invention;

[0020] Figure 2-Figure 14 It is a schematic diagram of the process of a method for preparing a three-dimensional SiC super junction diode provided by the present invention. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0022] like Figure 1 As shown, the present invention provides a three-dimensional structure SiC super junction diode including: n+ type SiC substrate 1, p+ type SiC epitaxial layer 2, n+ type SiC epitaxial layer 3, n+ type electron transport layer 4, field oxygen passivation layer 5, ohmic contact 6, anode PAD7, passivation protection layer 8 and cathode PAD9;

[0023] Among them, the p+ type SiC epitaxial layer 2 is in the form of multiple hemispheres, which are arranged at intervals on the n+ type SiC substrate 1; the n+ type SiC epitaxial layer 3 is deposited on the p+ type SiC epitaxial layer 2, and the n+ type electron transport layer 4 is arranged between the two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer 3; the field oxygen passivation layer 5 is deposited on the right side of the n+ type SiC epitaxial layer 3, the anode PAD7 is deposited on the left side of the n+ type SiC epitaxial layer 3, and there is a groove facing the center of each hemisphere; the passivation protection layer 8 is deposited on the field oxygen passivation layer 5, the ohmic contact 6 is arranged on the back side of the n+ type SiC substrate 1, and the cathode PAD9 is deposited on the ohmic contact 6.

[0024] like Figure 1 As shown, the number of hemispheres of the present invention is 5, among which the hemisphere with the largest diameter is arranged at the center, and two hemispheres are arranged on the left and right sides respectively; the two hemispheres on the same side have the same diameter, and the diameters of the two hemispheres on the right are larger than the diameters of the two hemispheres on the left.

[0025] In a second aspect, the present invention provides a method for preparing a three-dimensional SiC super junction diode, comprising:

[0026] S100, selecting an n+ type SiC substrate 1, and growing a p+ type SiC epitaxial layer 2 thereon;

[0027] In this step, a p+ type SiC epitaxial layer 2 is grown on an n+ type SiC substrate 1. Wherein: the substrate thickness is 350 μm, the carrier concentration is 5e18, and 5e18 is converted to 5×10 18 cm -3, the rest of the concentrations can be converted; the thickness of the p+ epitaxial layer is 6 to 20 μm, and the carrier concentration is 2e16 to 6e16, such as Figure 2 shown.

[0028] S200, etching the p+ type SiC epitaxial layer 2 using a hemispherical mask to make it present a multi-hemispherical structure;

[0029] In a specific implementation of the present invention, S200 includes:

[0030] S210, growing an alkaline earth doped silicon oxide layer on the p+ type SiC epitaxial layer 2; wherein the thickness of the grown alkaline earth doped silicon oxide layer is 6 to 20 μm, such as Figure 3 shown.

[0031] S220, using photolithography and etching processes to open square windows in the alkaline earth-doped silicon oxide layer to form an etching mask, wherein there is a certain interval between adjacent windows of the etching mask;

[0032] In this step, photolithography and etching processes are used to open square windows in the alkaline earth doped silicon oxide layer, and the side length of the window is 6 to 20 μm. Figure 4 shown.

[0033] S230, using a rapid thermal annealing process, reflowing the etching mask to form a hemispherical mask;

[0034] This step uses a rapid thermal annealing process to reflow the alkaline earth doped silicon oxide etching mask to form a hemispherical mask. The annealing temperature is 900 to 1000 degrees and the time is 120 to 180 seconds. Figure 5 shown.

[0035] S240, placing a hemispherical mask on the p+ type SiC epitaxial layer 2, and etching it using a dry etching process to make it present a multi-hemispherical structure;

[0036] Using a dry etching process, the p+ type SiC epitaxial layer 2 is etched to form a hemispherical structure. The etching selectivity is maintained at 1, such as Figure 6 shown.

[0037] The present invention uses an annealing reflow process technology of an alkaline earth doped silicon oxide mask to realize a three-dimensional structure etching mask, thereby realizing a three-dimensional super junction structure.

[0038] S300, epitaxially growing an n+ type SiC epitaxial layer 3 on the multiple hemispherical structures, such as Figure 7 As shown, in the spacing region of the hemispherical structure in the left part of the n+ type SiC epitaxial layer 3, ion implantation is used and activated after implantation to form an n+ type electron transport layer 4, as shown in FIG. Figure 8 shown.

[0039] The thickness of the n+ type SiC epitaxial layer 3 is 4 to 28 μm, and the carrier concentration is 2e16 to 6e16, at which the n+ type SiC epitaxial layer 3 and the p+ type SiC epitaxial layer 2 reach charge balance. The implanted ions used to form the n+ type electron transport layer 4 are nitrogen, and the total concentration is 1e18-5e18.

[0040] S400, opening a window to form a groove at a position directly opposite to the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer 3 by dry etching from top to bottom, and then performing sacrificial oxidation;

[0041] S500 , growing a field oxygen passivation layer 5 on the right side of the n+ type SiC epitaxial layer 3 using a PECVD process;

[0042] The present invention uses a dry etching process to first open a window in the source electrode region. Then, sacrificial oxidation is performed and a front field oxygen passivation layer 5 is grown using a PECVD process. Fig.10 shown.

[0043] S600, depositing Ti or Ni metal on the back side of the n+ type SiC substrate 1 to form an ohmic contact 6;

[0044] In this step, Ti or Ni metal is deposited on the back of the n+ type SiC substrate 1 by electron beam evaporation process, and then an ohmic contact 6 is formed by rapid thermal annealing process; wherein the thickness of Ti or Ni metal is 75-100nm; the annealing temperature is 950-1050°C, and the annealing time is 120s-300s. Fig.11 shown.

[0045] S700, depositing a Schottky metal on the left side of the p+ type SiC epitaxial layer 2 to form an anode PAD7;

[0046] In a specific implementation of the present invention, S700 includes:

[0047] S710, depositing Schottky metal Ti or Ni on the left side of the p+ type SiC epitaxial layer 2 by electron beam evaporation or magnetron sputtering process;

[0048] S720, using photolithography and wet etching processes to open windows to form Schottky contact patterns, and then using a rapid thermal annealing process to form the Schottky contact patterns, wherein the annealing temperature is 400 to 600° C. and the annealing time is 5 min to 10 min;

[0049] S730, using electron beam evaporation or magnetron sputtering process to deposit Al metal on the left side of the p+ type SiC epitaxial layer 2, and then using photolithography and wet etching process to open a window to form a PAD pattern, forming an anode PAD7, such as Fig.12 shown.

[0050] S800 , forming a passivation protection layer 8 on the field oxide passivation layer 5 using a photolithography process and depositing Ti / Ni / Ag metal on the back side of the ohmic contact 6 to form a cathode PAD9 .

[0051] In a specific implementation of the present invention, S800 includes:

[0052] S810, forming a passivation protection layer 8 on the field oxide passivation layer 5 by using a photolithography process, such as Fig.13 As shown; the thickness of the passivation protection layer 8 is 6um;

[0053] S820, using electron beam evaporation process to form Ti / Ni / Ag on the back of the p+ type SiC epitaxial layer 2 to form a cathode PAD9, such as Fig.14 As shown; wherein, the cathode PAD9 thickness is 200nm, 200nm or 1000nm.

[0054] It is worth noting that the overall resistance of the super junction device is related to the carrier concentration in the drift region. Based on the charge balance theory, the super junction device can use a drift region with a high carrier concentration to prepare the device. Therefore, the resistance of the diode of the present application is lower than that of the traditional structure. The avalanche breakdown of the device is due to the internal peak electric field reaching the critical breakdown field strength. The electric field vector of the traditional two-dimensional silicon carbide super junction structure to prepare the super device can be decomposed into: the superposition of electric field vectors in the horizontal and vertical directions. If the electric field in any direction extends too fast, it will cause avalanche breakdown of the device. The three-dimensional structure of the SiC super junction diode of the present application has a slower electric field extension capability than the two-dimensional structure. Therefore, better super junction device performance can be obtained.

[0055] The present invention provides a three-dimensional structure SiC super junction diode and a preparation method thereof, wherein the p+ type SiC epitaxial layer of the prepared diode is in a plurality of hemispherical shapes, which are arranged at intervals on an n+ type SiC substrate; the n+ type SiC epitaxial layer is deposited on the p+ type SiC epitaxial layer, the n+ type electron transport layer is arranged between the two hemispherical shapes on the left side, and is located inside the n+ type SiC epitaxial layer; the field oxygen passivation layer is deposited on the right side of the n+ type SiC epitaxial layer, the anode PAD is deposited on the left side of the n+ type SiC epitaxial layer, and there is a groove facing the center of each hemisphere; the passivation protection layer is deposited on the field oxygen passivation layer. The present invention uses the annealing reflow process technology of the alkaline earth doped silicon oxide mask to realize the three-dimensional structure etching mask, which solves the problem of realizing the three-dimensional structure super junction structure, so that the p+ type SiC epitaxial layer is in a three-dimensional super junction structure with multiple hemispherical shapes, and the super junction diode prepared based on the structure has a better voltage resistance balance capability, and can achieve lower resistance under the same voltage level conditions.

[0056] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0057] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A three-dimensional SiC super junction diode, characterized in that: include: n+ type SiC substrate (1), p+ type SiC epitaxial layer (2), n+ type SiC epitaxial layer (3), n+ type electron transport layer (4), field oxide passivation layer (5), ohmic contact (6), anode PAD (7), passivation protection layer (8) and cathode PAD (9); The p+ type SiC epitaxial layer (2) is in the form of a plurality of hemispheres, which are arranged at intervals on the n+ type SiC substrate (1); the n+ type SiC epitaxial layer (3) is deposited on the p+ type SiC epitaxial layer (2); the n+ type electron transport layer (4) is arranged between the two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer (3); the field oxygen passivation layer (5) is deposited on the right side of the n+ type SiC epitaxial layer (3); the anode PAD (7) is deposited on the left side of the n+ type SiC epitaxial layer (3), and a groove is provided at the center of each hemisphere; the passivation protection layer (8) is deposited on the field oxygen passivation layer (5); the ohmic contact (6) is arranged on the back side of the n+ type SiC substrate (1); and the cathode PAD (9) is deposited on the ohmic contact (6).

2. The three-dimensional SiC super junction diode according to claim 1, characterized in that: The number of hemispheres is 5, among which the hemisphere with the largest diameter is arranged at the center, and two hemispheres are arranged on the left and right sides respectively; the two hemispheres on the same side have the same diameter, and the diameters of the two hemispheres on the right are larger than those of the two hemispheres on the left.

3. A method for preparing a three-dimensional SiC super junction diode, characterized in that: include: S100, selecting an n+ type SiC substrate (1), and growing a p+ type SiC epitaxial layer (2) thereon; S200, etching the p+ type SiC epitaxial layer (2) using a hemispherical mask so that the p+ type SiC epitaxial layer (2) presents a multi-hemispherical structure; S300, epitaxially growing an n+ type SiC epitaxial layer (3) on the plurality of hemispherical structures, and forming an n+ type electron transport layer (4) by ion implantation and activation after implantation in the spacing region of the hemispherical structures on the left side of the n+ type SiC epitaxial layer (3); S400, opening a window from top to bottom by dry etching at a position directly opposite to the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer (3) to form a groove, and then performing sacrificial oxidation; S500, growing a field oxygen passivation layer (5) on the right side of the n+ type SiC epitaxial layer (3) using a PECVD process; S600, depositing Ni metal on the back side of the n+ type SiC substrate (1) to form an ohmic contact (6); S700, depositing a Schottky metal on the left side of the p+ type SiC epitaxial layer (2) to form an anode PAD (7); S800, forming a passivation protection layer (8) on the field oxide passivation layer (5) using a photolithography process and depositing Ti / Ni / Ag metal on the back side of the ohmic contact (6) to form a cathode PAD (9).

4. The method for preparing a three-dimensional SiC super junction diode according to claim 3, characterized in that: S200 includes: S210, growing an alkaline earth doped silicon oxide layer on the p+ type SiC epitaxial layer (2); S220, using photolithography and etching processes to open square windows in the alkaline earth-doped silicon oxide layer to form an etching mask, wherein there is a certain interval between adjacent windows of the etching mask; S230, using a rapid thermal annealing process, reflowing the etching mask to form a hemispherical mask; S240, placing the hemispherical mask on the p+ type SiC epitaxial layer (2), and etching it using a dry etching process to make it present a multi-hemispherical structure.

5. The method for preparing a three-dimensional SiC super junction diode according to claim 4, characterized in that: The thickness of the n+ type SiC substrate (1) is 350 μm, and the carrier concentration is 5e18; the thickness of the p+ type SiC epitaxial layer (2) is 6-20 μm, and the carrier concentration is 2e16-6e16.

6. The method for preparing a three-dimensional SiC super junction diode according to claim 3, characterized in that: The thickness of the n+ type SiC epitaxial layer (3) is 4 to 28 μm, and the carrier concentration is 2e16 to 6e16; at this concentration, the n+ type SiC epitaxial layer (3) and the p+ type SiC epitaxial layer (2) achieve charge balance.

7. The method for preparing a three-dimensional SiC super junction diode according to claim 4, characterized in that: In S300, the implanted ions used to form the n+ type electron transport layer (4) are nitrogen, and the total concentration is 1e18-5e18.

8. The method for preparing a three-dimensional SiC super junction diode according to claim 4, characterized in that: S600 includes: Ti or Ni metal is deposited on the back side of the n+ type SiC substrate (1) using an electron beam evaporation process, and then an ohmic contact (6) is formed using a rapid thermal annealing process; wherein the thickness of the Ti or Ni metal is 75 to 100 nm; the annealing temperature is 950 to 1050° C., and the annealing time is 120 s to 300 s, as shown in FIG11 .

9. The method for preparing a three-dimensional SiC super junction diode according to claim 3, characterized in that: S700 includes: S710, depositing Schottky metal Ti or Ni on the left side of the p+ type SiC epitaxial layer (2) using electron beam evaporation or magnetron sputtering technology; S720, forming a Schottky contact pattern by using a photolithography and wet etching process, and then forming the Schottky contact pattern by using a rapid thermal annealing process; wherein the annealing temperature is 400 to 600° C., and the annealing time is 5 minutes to 10 minutes; S730, using electron beam evaporation or magnetron sputtering process to deposit Al metal on the left side of the p+ type SiC epitaxial layer (2), and then using photolithography and wet etching process to open a window to form a PAD pattern, forming an anode PAD (7).

10. The method for preparing a three-dimensional SiC super junction diode according to claim 3, characterized in that: S800 includes: S810, forming a passivation protection layer (8) on the field oxide passivation layer (5) using a photolithography process; the passivation protection layer (8) has a thickness of 6 um; S820, using an electron beam evaporation process to form Ti / Ni / Ag on the back side of the p+ type SiC epitaxial layer (2) to form a cathode PAD (9); wherein the thickness of the cathode PAD (9) is 200nm, 200nm or 1000nm.

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