Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate; a plurality of pixel units and a plurality of grid line groups. At least one pixel unit comprises a plurality of sub-pixels, and at least one sub-pixel comprises a sensing transistor and a driving transistor. Each grid line group comprises a first grid line and a second grid line which are positioned on the two sides of the pixel unit; for the first grid line and the second grid line corresponding to the sub-pixels in the same row, the sensing transistor is located on the side, closer to the second grid line, of the sub-pixels, and the driving transistor is located on the side, closer to the first grid line, of the sub-pixels. For two sub-pixels which are close to each other in the same row and are not located in the same pixel unit, at least one signal line in an area defined by the first connecting holes and the second connecting holes of the two sub-pixels is provided with a double-layer wiring structure, and the double-layer wiring structures of the same signal line are electrically connected with each other.

Description

[0001] This application is a divisional application. The application number of the original application is 201980002714.7, the original application date is November 29, 2019, and the name of the original application is "Display Panel and Display Device". The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Electroluminescent diodes such as organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) have the advantages of self-luminescence and low energy consumption. They are one of the hot topics in the current research field of electroluminescent display panels and have received widespread attention. Summary of the invention

[0004] The display panel provided by the embodiment of the present disclosure includes:

[0005] substrate substrate;

[0006] A plurality of pixel units are arrayed on the substrate, and at least one of the pixel units includes: a plurality of sub-pixels, and at least one of the sub-pixels includes: a sensing transistor and a driving transistor;

[0007] A plurality of gate line groups, each of the gate line groups comprising a first gate line and a second gate line located at two sides of the pixel unit;

[0008] For the first gate line and the second gate line corresponding to the sub-pixels in the same row, the sensing transistor is located at a side of the sub-pixel closer to the second gate line, and the driving transistor is located at a side of the sub-pixel closer to the first gate line;

[0009] In the same sub-pixel, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through the first connection hole, and the first electrode of the driving transistor is electrically connected to the power line through the second connection hole;

[0010] For two sub-pixels in the same row that are close to each other and not located in the same pixel unit, at least one signal line in the area surrounded by the first connection holes and the second connection holes of the two sub-pixels has a double-layer routing structure, and the double-layer routing structures of the same signal line are electrically connected to each other.

[0011] Optionally, in the embodiment of the present disclosure, the sub-pixel further comprises: an anode, a light-emitting functional layer and a cathode layer which are stacked; wherein, in the same sub-pixel, the second electrode of the driving transistor is electrically connected to the anode;

[0012] The display panel further includes:

[0013] A plurality of auxiliary wirings; wherein the auxiliary wirings are located in a gap between two adjacent sub-pixel columns, and the cathode layer is electrically connected to the auxiliary wirings through a first via hole;

[0014] A plurality of detection lines; wherein the detection line is located in a gap between two adjacent sub-pixel columns, the detection line is insulated from the auxiliary wiring, and the detection line is electrically connected to the second electrode of the sensing transistor;

[0015] The signal line includes: at least one of the auxiliary line, the detection line and the power line.

[0016] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0017] A pixel defining layer, located between the layer where the anode is located and the light-emitting functional layer;

[0018] A planarization layer, located on a side of the pixel defining layer facing the base substrate;

[0019] A first conductive layer; located on a side of the planarization layer facing the substrate;

[0020] A first insulating layer, located on a side of the first conductive layer facing the base substrate;

[0021] A second conductive layer is located on a side of the first insulating layer facing the base substrate;

[0022] The auxiliary routing includes:

[0023] A first auxiliary wiring, located in the first conductive layer and extending along the column direction of the sub-pixels;

[0024] A second auxiliary wiring, located in the second conductive layer;

[0025] The first auxiliary wiring is electrically connected to the second auxiliary wiring through a second via hole penetrating the first insulating layer.

[0026] Optionally, in an embodiment of the present disclosure, the second auxiliary routing includes a plurality of first auxiliary portions arranged at intervals; wherein, in the same auxiliary routing, the first auxiliary routing is electrically connected to the corresponding first auxiliary portions through the second vias, respectively.

[0027] Optionally, in the embodiment of the present disclosure, in the same auxiliary routing line, the orthographic projection of the first auxiliary routing line on the base substrate and the orthographic projection of the corresponding first auxiliary part on the base substrate have an overlapping area.

[0028] Optionally, in the embodiment of the present disclosure, the orthographic projection of the first auxiliary portion on the base substrate covers the orthographic projection of the corresponding second via hole on the base substrate.

[0029] Optionally, in the embodiment of the present disclosure, for a plurality of first auxiliary portions electrically connected to the same first auxiliary wiring, one sub-pixel row corresponds to one first auxiliary portion.

[0030] Optionally, in the embodiment of the present disclosure, for a plurality of first auxiliary portions electrically connected to the same first auxiliary wiring, a sub-pixel row separated by at least one sub-pixel row corresponds to one first auxiliary portion.

[0031] Optionally, in the embodiment of the present disclosure, each of the first auxiliary parts is electrically connected to the corresponding first auxiliary trace through at least four second vias.

[0032] Optionally, in the embodiment of the present disclosure, for the first auxiliary portion, the first gate line and the second gate line corresponding to the same row of sub-pixels, the first auxiliary portion is closer to the second gate line.

[0033] Optionally, in the embodiment of the present disclosure, the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the anode on the base substrate.

[0034] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0035] A plurality of first connecting parts, which are in the same layer as the anode and insulated;

[0036] The first via hole comprises: a first sub-via hole penetrating the pixel defining layer and a second sub-via hole penetrating the planarization layer;

[0037] The cathode layer is electrically connected to the first connection portion through the first sub-via, and the first connection portion is electrically connected to the auxiliary trace through the second sub-via.

[0038] Optionally, in the embodiment of the present disclosure, an orthographic projection of the first sub-via on the base substrate and an orthographic projection of the second sub-via on the base substrate at least partially do not overlap.

[0039] Optionally, in an embodiment of the present disclosure, one auxiliary wiring corresponds to a plurality of first via holes, and one first via hole corresponds to one sub-pixel row;

[0040] For the first via holes and the first gate lines and the second gate lines corresponding to the same row of sub-pixels, the orthographic projection of the first sub-via hole on the base substrate and the orthographic projection of the second gate line on the base substrate have an overlapping area; and the orthographic projection of the second sub-via hole on the base substrate is located between the orthographic projections of the first gate line and the second gate line on the base substrate.

[0041] Optionally, in an embodiment of the present disclosure, for the second sub-vias, the second vias and the second gate lines corresponding to the same row of sub-pixels, the orthographic projection of the second sub-vias on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projections of all the second vias on the base substrate.

[0042] Optionally, in the embodiment of the present disclosure, the width of a portion of the first auxiliary wiring that overlaps with the orthographic projection of the first auxiliary portion along the sub-pixel row direction is a first width, and the width of a portion of the first auxiliary wiring that overlaps with the orthographic projection of the first gate line along the sub-pixel row direction is a second width;

[0043] The first width is greater than the second width.

[0044] Optionally, in the embodiment of the present disclosure, a portion of the first auxiliary trace having the second width is close to the second connection hole.

[0045] Optionally, in an embodiment of the present disclosure, the first auxiliary wiring is located in a gap between two adjacent pixel unit columns.

[0046] Optionally, in the embodiment of the present disclosure, at least two adjacent pixel unit columns are formed into a first column group, one of the first column groups corresponds to a first auxiliary wiring, and the first auxiliary wiring is located in a gap between two adjacent pixel unit columns in the corresponding first column group.

[0047] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0048] A second insulating layer, located on a side of the second conductive layer facing the base substrate;

[0049] An active semiconductor layer, located on a side of the second insulating layer facing the substrate;

[0050] A third insulating layer is located on a side of the active semiconductor layer facing the substrate;

[0051] A light-shielding metal layer, located on a side of the third insulating layer facing the base substrate;

[0052] The light-shielding metal layer includes: at least one light-shielding electrode; wherein one of the light-shielding electrodes is located in one of the sub-pixels;

[0053] In the same sub-pixel, the orthographic projection of the light-shielding electrode on the base substrate at least covers the orthographic projection of the channel region of the driving transistor on the base substrate.

[0054] Optionally, in the embodiment of the present disclosure, at least one of the sub-pixels further comprises: a storage capacitor; wherein a first electrode of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the storage capacitor is electrically connected to the second electrode of the driving transistor;

[0055] The second electrode of the storage capacitor is also electrically connected to the light shielding electrode through a third connection hole.

[0056] Optionally, in an embodiment of the present disclosure, the detection line includes:

[0057] A first detection wiring is located in the first conductive layer and extends along the column direction of the sub-pixels;

[0058] A second detection wiring, located on the second conductive layer;

[0059] The first detection wiring is electrically connected to the second detection wiring through a third via hole penetrating the first insulating layer.

[0060] Optionally, in an embodiment of the present disclosure, the second detection line includes a plurality of second auxiliary parts arranged at intervals; wherein, in the same detection line, the first detection line is electrically connected to the corresponding second auxiliary parts through the third vias respectively.

[0061] Optionally, in an embodiment of the present disclosure, in the same detection line, an orthographic projection of the first detection line on the base substrate and an orthographic projection of the corresponding second auxiliary portion on the base substrate have an overlapping area.

[0062] Optionally, in the embodiment of the present disclosure, the orthographic projection of the second auxiliary portion on the base substrate covers the orthographic projection of the corresponding third via hole on the base substrate.

[0063] Optionally, in an embodiment of the present disclosure, for a plurality of second auxiliary portions electrically connected to the same first detection wiring, one sub-pixel row corresponds to one second auxiliary portion.

[0064] Optionally, in an embodiment of the present disclosure, for a plurality of second auxiliary portions electrically connected to the same first detection wiring, a sub-pixel row separated by at least one sub-pixel row corresponds to one second auxiliary portion.

[0065] Optionally, in the embodiment of the present disclosure, one of the second auxiliary parts and one of the first auxiliary parts correspond to the same sub-pixel row.

[0066] Optionally, in the embodiment of the present disclosure, for the first auxiliary part and the second auxiliary part corresponding to the sub-pixels in the same row, the second via hole of the first auxiliary part and the third via hole of the second auxiliary part are arranged in a staggered manner.

[0067] Optionally, in the embodiment of the present disclosure, each of the second auxiliary parts is electrically connected to the corresponding first detection trace through at least three third vias.

[0068] Optionally, in the embodiment of the present disclosure, for the second auxiliary portion and the first gate line and the second gate line corresponding to the same row of sub-pixels, the second auxiliary portion is closer to the second gate line.

[0069] Optionally, in the embodiment of the present disclosure, the width of a portion of the first detection line that overlaps with the orthographic projection of the second auxiliary portion along the sub-pixel row direction is a third width, and the width of a portion of the first detection line that overlaps with the orthographic projection of the first gate line along the sub-pixel row direction is a fourth width;

[0070] The third width is greater than the fourth width.

[0071] Optionally, in an embodiment of the present disclosure, a portion of the first detection trace having the fourth width is close to the second connection hole.

[0072] Optionally, in an embodiment of the present disclosure, for the first detection routing and the first auxiliary routing arranged in the gap between the same pixel unit column, the orthographic projection of the first sub-via corresponding to the first auxiliary routing on the base substrate also has an overlapping area with the orthographic projection of the first detection routing on the base substrate.

[0073] Optionally, in an embodiment of the present disclosure, one of the first detection lines and one of the first auxiliary lines are both arranged in a gap between the same pixel unit column.

[0074] Optionally, in an embodiment of the present disclosure, the power cord includes:

[0075] A first power supply line is located in the first conductive layer and extends along the column direction of the sub-pixels;

[0076] A second power supply line is located on the second conductive layer;

[0077] The first power line is electrically connected to the second power line through a fourth via hole penetrating the first insulating layer.

[0078] Optionally, in an embodiment of the present disclosure, at least one column of pixel units is spaced between the first power line and the first auxiliary line.

[0079] Optionally, in an embodiment of the present disclosure, the second power supply line includes a plurality of third auxiliary parts arranged at intervals; wherein, in the same power supply line, the first power supply line is electrically connected to the corresponding third auxiliary parts through the fourth vias respectively.

[0080] Optionally, in the embodiment of the present disclosure, in the same power line, the orthographic projection of the first power line on the base substrate and the orthographic projection of the corresponding third auxiliary portion on the base substrate have an overlapping area.

[0081] Optionally, in the embodiment of the present disclosure, the orthographic projection of the third auxiliary portion on the base substrate covers the orthographic projection of the corresponding fourth via hole on the base substrate.

[0082] Optionally, in the embodiment of the present disclosure, each of the third auxiliary parts is electrically connected to the corresponding first power line through at least four fourth vias.

[0083] Optionally, in the embodiment of the present disclosure, for a plurality of third auxiliary portions electrically connected to the same first power line, one sub-pixel row corresponds to one third auxiliary portion.

[0084] Optionally, in an embodiment of the present disclosure, for a plurality of third auxiliary portions electrically connected to the same first power line, a sub-pixel row separated by at least one sub-pixel row corresponds to one third auxiliary portion.

[0085] Optionally, in the embodiment of the present disclosure, one of the third auxiliary parts and one of the first auxiliary parts correspond to the same sub-pixel row.

[0086] Optionally, in the embodiment of the present disclosure, for the third auxiliary portion and the first gate line and the second gate line corresponding to the same row of sub-pixels, the third auxiliary portion is closer to the second gate line.

[0087] Optionally, in the embodiment of the present disclosure, the width of the portion of the first power line that overlaps with the orthographic projection of the third auxiliary portion along the sub-pixel row direction is a fifth width, and the width of the portion of the first power line that overlaps with the orthographic projection of the first gate line along the sub-pixel row direction is a sixth width;

[0088] The fifth width is greater than the sixth width.

[0089] Optionally, in the embodiment of the present disclosure, a portion of the first power trace having the sixth width is close to the second connection hole.

[0090] Optionally, in an embodiment of the present disclosure, for the first connection holes and the third auxiliary parts corresponding to the same row of sub-pixels, a fourth via hole corresponding to the third auxiliary part and the first connection hole are arranged in a straight line along the sub-pixel row direction.

[0091] The embodiment of the present disclosure also provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] Figure 1 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0093] Figure 2a A schematic diagram of a top view of a display panel provided in an embodiment of the present disclosure;

[0094] Figure 2b A schematic diagram of a top view structure of some display panels provided in an embodiment of the present disclosure;

[0095] Figure 3 Schematic diagrams of layout structures of some further display panels provided in the embodiments of the present disclosure;

[0096] Figure 4a for Figure 3 The cross-sectional structure diagram of the display panel shown along the AA' direction;

[0097] Figure 4b for Figure 3 The cross-sectional structure diagram of the display panel shown along the BB' direction;

[0098] Figure 4c for Figure 3 The cross-sectional structure diagram of the display panel shown along the CC' direction;

[0099] Figure 5a for Figure 3 A schematic diagram of the structure of a light-shielding metal layer in a display panel shown;

[0100] Figure 5b for Figure 3 A schematic diagram of the structure of an active semiconductor layer in a display panel shown;

[0101] Figure 5c for Figure 3 A schematic structural diagram of a second conductive layer in a display panel shown;

[0102] Figure 5d for Figure 3 A schematic structural diagram of a first conductive layer in a display panel shown;

[0103] Figure 6 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0104] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0105] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0106] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0107] Electroluminescent diodes are generally current-driven and require a stable current to drive them to emit light. In addition, a pixel driving circuit is used in the display panel to drive the electroluminescent diode to emit light. Among them, the electroluminescent diode includes an anode, a light-emitting functional layer, and a cathode layer stacked in sequence on a substrate. The pixel driving circuit is electrically connected to the anode to load a signal to the anode. In addition, a low voltage signal VSS is loaded to the cathode layer to make the electroluminescent diode emit light. However, in actual applications, the light-emitting surface of the top-emitting electroluminescent diode is on the cathode layer side. In order to increase the transmittance of the cathode, the cathode is generally made of transparent conductive material or made very thin, which results in a relatively large square resistance of the cathode. In this way, when the display panel is working, the current flowing through the cathode will be larger, and the voltage drop (IR-Drop) on the cathode will be larger, resulting in uneven brightness of the light at different positions of the display panel.

[0108] The display panel provided by the embodiment of the present disclosure may include: a substrate; a plurality of pixel units arranged in an array on the substrate, and a plurality of gate line groups. Among them, at least one pixel unit includes: a plurality of sub-pixels, and at least one sub-pixel includes: a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line located on both sides of the pixel unit; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the sensing transistor is located on the side of the sub-pixel closer to the second gate line, and the driving transistor is located on the side of the sub-pixel closer to the first gate line; in the same sub-pixel, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through the first connection hole, and the first electrode of the driving transistor is electrically connected to the power line through the second connection hole; for two sub-pixels in the same row that are close to each other and not located in the same pixel unit, at least one signal line in the area surrounded by the first connection hole and the second connection hole of the two sub-pixels has a double-layer routing structure, and the double-layer routing structures of the same signal line are electrically connected to each other. In this way, by setting a double-layer routing structure that is electrically connected to each other, the resistance of the signal line provided with the double-layer routing structure can be reduced, thereby reducing the influence of IR Drop on the luminous uniformity of the display panel and improving the display effect of the display panel.

[0109] In a specific implementation, in the embodiment of the present disclosure, at least one sub-pixel may include a pixel driving circuit and an electroluminescent diode L. The display panel provided by the embodiment of the present disclosure is described below in conjunction with the structure of the pixel driving circuit.

[0110] like Figure 1 As shown, the pixel driving circuit generally includes: a driving transistor T1, a switching transistor T2, a sensing transistor T3 and a storage capacitor Cst. Among them, the gate of the switching transistor T2 is electrically connected to the first gate line G1, the first electrode (such as the source electrode) of the switching transistor T2 is electrically connected to the data line DA, and the second electrode (such as the drain electrode) of the switching transistor T2 is electrically connected to the gate of the driving transistor T1. The first electrode (such as the source electrode) of the driving transistor T1 is electrically connected to the power line VDD, the second electrode (such as the drain electrode) of the driving transistor T1 is electrically connected to the anode of the electroluminescent diode L, and the cathode of the electroluminescent diode L is electrically connected to the low voltage signal line VSS. The gate of the sensing transistor T3 is electrically connected to the second gate line G2, the first electrode (such as the source electrode) of the sensing transistor T3 is electrically connected to the second electrode (such as the drain electrode) of the driving transistor T1, and the second electrode (such as the drain electrode) of the sensing transistor T3 is electrically connected to the detection line SL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the second electrode of the storage capacitor Cst is electrically connected to the second electrode (such as the drain electrode) of the driving transistor T1.

[0111] The signal transmitted on the first gate line G1 controls the switch transistor T2 to turn on, so as to write the data voltage transmitted on the data line DA into the gate of the driving transistor T1, and controls the driving transistor T1 to generate a working current to drive the electroluminescent diode L to emit light. And the signal transmitted on the second gate line G2 controls the sensing transistor T3 to turn on, so as to output the working current generated by the driving transistor T1 to the detection line SL, and charge the detection line SL. After that, the voltage on each detection line SL is detected, and compensation calculation is performed according to the detected voltage to obtain the data voltage for display corresponding to each sub-pixel in the row.

[0112] For example, the power line VDD can transmit a constant first voltage, which is a positive voltage, and the low voltage signal line VSS can transmit a constant second voltage, which is a negative voltage. Alternatively, in some examples, the low voltage signal line VSS can also be grounded.

[0113] It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit can Figure 1 In addition to the structure shown, the structure may also include other numbers of transistors and capacitors, which is not limited in the embodiments of the present disclosure.

[0114] like Figure 2a and Figure 2b As shown, the display panel may include a plurality of pixel units PX, such as a plurality of pixel units PX, located in the display area AA. At least one pixel unit PX may include a plurality of sub-pixels. For example, each pixel unit may include a plurality of sub-pixels. Generally, in the display field, a pixel unit usually includes a plurality of sub-pixels that can display a single color (such as red, green or blue), and an electroluminescent diode and a pixel driving circuit are provided in each sub-pixel to display different colors by controlling the light emission ratio of sub-pixels of different colors, so the above-mentioned sub-pixels may be monochrome sub-pixels.

[0115] For example, Figure 2a and Figure 2b As shown, the pixel unit PX may include: a first color sub-pixel 010, a second color sub-pixel 020, and a third color sub-pixel 030. Among them, the first color sub-pixel is configured to emit light of a first color, the second color sub-pixel is configured to emit light of a second color, and the third color sub-pixel is configured to emit light of a third color. In some examples, the first color, the second color, and the third color can be selected from red, green, and blue. For example, the first color is red, the second color is green, and the third color is blue. Thus, the pixel unit PX is an arrangement structure of red, green, and blue sub-pixels. Of course, the embodiments of the present disclosure include but are not limited to this, and the above-mentioned first color, second color, and third color may also be other colors.

[0116] Exemplarily, the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are arranged in sequence along the row direction F2, and the sub-pixels in the same column have the same color. Of course, the embodiments of the present disclosure include but are not limited to this.

[0117] In the specific implementation, in the embodiment of the present disclosure, if Figure 2a and Figure 2b As shown, the display panel also includes: a plurality of auxiliary wirings 210, a plurality of detection lines SL, a plurality of data lines DA (DA-010, DA-020, DA-030) and a power line VDD. The detection line is insulated from the auxiliary wiring, and the auxiliary wiring 210 is located in the gap between two adjacent sub-pixel columns. The detection line SL is located in the gap between two adjacent sub-pixel columns, and the detection line is electrically connected to the second electrode of the sensing transistor. The first electrode of the driving transistor is electrically connected to the power line VDD.

[0118] The following takes the first color sub-pixel 010, the second color sub-pixel 020 and the third color sub-pixel 030 in the same pixel unit as an example to illustrate the various layers of the pixel driving circuit provided in some embodiments of the present disclosure. Figures 3 to 5d As shown, Figure 5a to Figure 5d Schematic diagram of each layer of the pixel driving circuit provided in some embodiments of the present disclosure. Figure 5a to Figure 5d Describe the positional relationship of the pixel driving circuit on the substrate.

[0119] Among them, Figures 3 to 5d As shown, the display panel may include: a pixel defining layer 330 located between the layer 500 where the anode is located and the light-emitting functional layer 600, a planarization layer 320 located on the side of the pixel defining layer 330 facing the substrate 100, a first conductive layer 200 located on the side of the planarization layer facing the substrate, and a first insulating layer 711 located on the side of the first conductive layer 200 facing the substrate 100; a second conductive layer 800 located on the side of the first insulating layer 711 facing the substrate 100, a second insulating layer 712 located on the side of the second conductive layer 800 facing the substrate 100, an active semiconductor layer 0320 located on the side of the second insulating layer 712 facing the substrate 100, a third insulating layer 713 located on the side of the active semiconductor layer 0320 facing the substrate 100, and a light-shielding metal layer 0310 located on the side of the third insulating layer 713 facing the substrate 100.

[0120] in, Figures 3 to 5dAlso shown are the first gate line G1, the second gate line G2, the detection line SL, the data lines DA-010, DA-020 and DA-030, the power line VDD, and the auxiliary wiring 210 connected to the pixel driving circuit. Among them, the data line DA-010 is electrically connected to the switch transistor T2 of the pixel driving circuit in the first color sub-pixel 010, the data line DA-020 is electrically connected to the switch transistor T2 of the pixel driving circuit in the second color sub-pixel 020, and the data line DA-030 is electrically connected to the switch transistor T2 of the pixel driving circuit in the third color sub-pixel 030.

[0121] For example, in combination Figure 3 and Figure 5a , shows a light shielding metal layer 0310 of the pixel driving circuit, which is located on the base substrate 100. The light shielding metal layer 0310 includes: a first connecting wire 0311, a second connecting wire 0312, and light shielding electrodes 0313-010, 0313-020, and 0313-030. Among them, the first connecting wire 0311 and the second connecting wire 0312 extend along the row direction F2. The first color sub-pixel 010 includes the light shielding electrode 0313-010, the second color sub-pixel 020 includes the light shielding electrode 0313-020, and the third color sub-pixel 030 includes the light shielding electrode 0313-030. Among them, the orthographic projections of the light shielding electrodes 0313-010, 0313-020, and 0313-030 on the base substrate 100 at least cover the orthographic projections of the channel region of the driving transistor on the base substrate 100.

[0122] For example, in combination Figure 3 and Figure 5b , shows the active semiconductor layer 0320 of the pixel driving circuit, and a third insulating layer 713 is provided between the active semiconductor layer 0320 and the light shielding metal layer 0310. The active semiconductor layer 0320 can be formed by patterning a semiconductor material. The active semiconductor layer 0320 can be used to make the active layers of the driving transistor T1, the switching transistor T2, and the sensing transistor T3 in the first color sub-pixel 010, the second color sub-pixel 020, and the third color sub-pixel 030, and each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. Furthermore, the active semiconductor layer 0320 further includes conductive regions 0323-010, 0323-020, and 0323-030, wherein the conductive region 0323-010 forms the first electrode of the storage capacitor Cst in the first color sub-pixel 010, the conductive region 0323-020 forms the first electrode of the storage capacitor Cst in the second color sub-pixel 020, and the conductive region 0323-030 forms the first electrode of the storage capacitor Cst in the third color sub-pixel 030. Of course, the embodiments of the present disclosure include but are not limited to this.

[0123] Further, the active layers of each transistor are arranged at intervals. Exemplarily, the active semiconductor layer 0320 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities. The above-mentioned conductive region can be a region with conductive properties formed after ion doping of the active semiconductor layer 0320. Of course, the embodiments of the present disclosure include but are not limited to this.

[0124] Exemplarily, the pixel driving circuit further includes a second conductive layer 800 located on the side of the active semiconductor layer 0320 away from the substrate 100. A second insulating layer 720 is formed between the active semiconductor layer 0320 and the second conductive layer 800 to protect the active semiconductor layer 0320. Figure 3 and Figure 5c As shown, a second conductive layer 800 is shown. The second conductive layer 800 is disposed on the second insulating layer 712, thereby being insulated from the active semiconductor layer 0320. The second conductive layer 800 may include a plurality of first gate lines G1, a plurality of second gate lines G2, and a plurality of gate portions (e.g., gate portions G-010, G-020, and G-030). Figure 3 and Figure 5c As shown, the gate of the switch transistor T2 may be the portion where the first gate line G1 overlaps with the active semiconductor layer 0320, and the gate of the sensing transistor T3 may be the portion where the second gate line G2 overlaps with the active semiconductor layer 0320. The gate portion G-010 is the gate of the driving transistor T1 in the first color sub-pixel 010, the gate portion G-020 is the gate of the driving transistor T1 in the second color sub-pixel 020, and the gate portion G-030 is the gate of the driving transistor T1 in the third color sub-pixel 030.

[0125] Furthermore, in a specific implementation, in the embodiment of the present disclosure, each gate line group includes a first gate line G1 and a second gate line G2; wherein a row of sub-pixels corresponds to a gate line group, and the first gate line G1 and the second gate line G2 in the same gate line group are located on both sides of the row of pixel units. Figure 2b and Figure 3 As shown, a row of sub-pixels is electrically connected to a first gate line G1 and a second gate line G2. In addition, the first gate line G1 and the second gate line G2 are arranged along the column direction F1 and extend along the row direction F2. For example, in the column direction F1, the first electrode of the storage capacitor Cst is located between the first gate line G1 and the second gate line G2.

[0126] It should be noted that Figure 5c The dashed rectangular boxes (not labeled) in illustrative figures show the portions where the second conductive layer 800 overlaps with the active semiconductor layer 0320 .

[0127] In a specific implementation, a first insulating layer 711 is provided on the side of the second conductive layer 800 facing away from the substrate 100 to protect the second conductive layer 800. Figure 3 and Figure 5d As shown, the first conductive layer 200 of the pixel driving circuit is shown, and the first conductive layer 200 is located on the side of the first insulating layer 711 away from the base substrate 100. The first conductive layer 200 includes: a plurality of data lines (for example: data lines DA-010, DA-020 and DA-030), and capacitor electrode parts Cst-010, Cst-020, Cst-030. The capacitor electrode part Cst-010 serves as the second pole of the storage capacitor Cst in the first color sub-pixel 010, the capacitor electrode part Cst-020 serves as the second pole of the storage capacitor Cst in the second color sub-pixel 020, and the capacitor electrode part Cst-030 serves as the second pole of the storage capacitor Cst in the third color sub-pixel 030.

[0128] For example, in a specific implementation, in the implementation of the present disclosure, the data lines DA-010, DA-020 and DA-030 can be extended along the column direction F1 and arranged along the row direction F2. Furthermore, the data lines DA-010, DA-020 and DA-030 are electrically connected to the source of the switch transistor through the protruding portions in the row direction F2.

[0129] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4a As shown, the pixel defining layer 330 may include a plurality of light-emitting opening areas KB. In addition, the display panel may further include: an anode layer 500 located between the planarization layer 320 and the pixel defining layer 330, and a light-emitting functional layer 600 located between the anode layer 500 and the cathode layer 400. And the anode layer 500 includes a plurality of mutually independent anodes 510; wherein, one anode 510 corresponds to one light-emitting opening area KB, and the orthographic projection of the anode 510 on the substrate substrate 100 and the orthographic projection of the corresponding light-emitting opening area KB on the substrate substrate 100 have an overlapping area. Exemplarily, the orthographic projection of the first via hole 310 on the substrate substrate 100 does not overlap with the orthographic projection of the anode 510 on the substrate substrate 100. In this way, the influence of the first via hole 310 on the flatness of the anode 510 can be avoided.

[0130] Among them, a flattening layer 320 is provided on the side of the first conductive layer 200 facing away from the base substrate 100, which is used to protect the first conductive layer 200 and achieve a flattening effect. A pixel defining layer 330 is provided on the side of the anode layer 500 facing away from the base substrate 100, and the pixel defining layer 330 has a plurality of light-emitting opening areas KB, and one anode 510 corresponds to one light-emitting opening area KB, so that the corresponding anode 510 is exposed through the light-emitting opening area KB. In other words, the first conductive layer 200 is located on the side of the anode layer 500 facing the base substrate 100. In this way, the first conductive layer 200 will not affect the luminous transmittance, so that the first conductive layer 200 will not be limited by the influence of width and thickness. Even if the cathode layer 400 is made of transparent conductive material or is prepared with an extremely thin thickness, the resistance of the cathode layer 400 can be reduced by setting the first conductive layer 200, thereby reducing the influence of IRDrop on the luminous uniformity of the display panel and improving the display effect of the display panel.

[0131] Exemplarily, in a specific implementation, in a top-emitting electroluminescent diode, the anode 510 may be a reflective anode to reflect light. In addition, the light-emitting functional layer 600 is in direct contact with the anode 510 through the light-emitting opening area KB, and the light-emitting functional layer 600 is in direct contact with the cathode layer 400, so as to drive the light-emitting functional layer 600 to emit light through the signal loaded on the anode 510 and the signal loaded on the cathode layer 400. Of course, the present disclosure includes but is not limited to this. For example, a hole transport layer and a hole injection layer may be provided between the light-emitting functional layer 600 and the anode 510, and an electron transport layer, an electron injection layer and other film layers may be provided between the light-emitting functional layer 600 and the cathode layer 400.

[0132] Exemplarily, in a specific implementation, the cathode layer 400 is generally a whole layer structure, covering the base substrate 100. That is to say, the anode 510, the light-emitting functional layer 600 and the cathode layer 400 are stacked to form an electroluminescent diode. Further, the orthographic projection of the anode 510 on the base substrate 100 can cover the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100. Moreover, the area of ​​the orthographic projection of the anode 510 on the base substrate 100 is larger than the area of ​​the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100. In other words, the edge of the orthographic projection of the anode 510 on the base substrate 100 can be made to have a certain distance from the edge of the orthographic projection of the corresponding light-emitting opening area KB on the base substrate 100, and the distance can be designed and determined according to the actual application environment, and is not limited here.

[0133] Figure 3 FIG. 2 is a schematic diagram showing the stacking position relationship of the light shielding metal layer 0310, the active semiconductor layer 0320, the second conductive layer 800 and the first conductive layer 200. Figures 3 to 5dAs shown, the portion of the data line DA-010 protruding along the row direction F2 is electrically connected to the source region of the switch transistor T2 of the first color sub-pixel 010 in the active semiconductor layer 0320 through at least one via hole (e.g., via hole 341-010) penetrating the first insulating layer 711 and the second insulating layer 712. The portion of the data line DA-020 protruding along the row direction F2 is electrically connected to the source region of the switch transistor T2 of the second color sub-pixel 020 in the active semiconductor layer 0320 through at least one via hole (e.g., via hole 341-020) penetrating the first insulating layer 711 and the second insulating layer 712. The portion of the data line DA-030 protruding along the row direction F2 is electrically connected to the source region of the switch transistor T2 of the third color sub-pixel 030 in the active semiconductor layer 0320 through at least one via hole (e.g., via hole 341-030) penetrating the first insulating layer 711 and the second insulating layer 712. Of course, the present disclosure includes but is not limited to this.

[0134] Combination Figures 3 to 5d In the partial figure, in each sub-pixel, the first electrode of the sensing transistor T3 is electrically connected to the second electrode of the driving transistor T1 through the first connection hole 0110. Specifically, for example Figure 3 and Figure 4b As shown, the source region of the sensing transistor T3 in the active semiconductor layer 0320 is electrically connected to the first electrode of the storage capacitor Cst through the first connection hole 0110 that penetrates the first insulating layer 711 and the second insulating layer 712. The drain region of the driving transistor T1 in the active semiconductor layer 0320 is electrically connected to the first electrode of the storage capacitor Cst through the fourth connection hole 0140 that penetrates the first insulating layer 711 and the second insulating layer 712. In this way, the first electrode of the sensing transistor T3 can be electrically connected to the second electrode of the driving transistor T1.

[0135] And, combined with Figures 3 to 5d In the partial figure, in each sub-pixel, the first electrode of the driving transistor T1 is electrically connected to the power line VDD through the second connection hole 0120. Specifically, for example Figure 3 and Figure 4b As shown, the first conductive layer 200 may also include: a plurality of fourth connection parts, and some sub-pixels each have a fourth connection part. For example, the second color sub-pixel 020 has a fourth connection part T1-020, and the third color sub-pixel 030 has a fourth connection part T1-030. One end of the fourth connection part T1-030 is electrically connected to the corresponding second connection wiring 0312 through a via 917 that penetrates the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713, and the other end is electrically connected to the source region of the active layer of the driving transistor through a second connection hole 0120 that penetrates the first insulating layer 711 and the second insulating layer 712. The fourth connection part T1-020 is similarly configured and will not be described in detail here.

[0136] Furthermore, the second electrode of the storage capacitor is also electrically connected to the light shielding electrode through the third connection hole. Figures 3 to 5d In the partial figure, the capacitor electrode portion Cst-030 is electrically connected to the light-shielding electrode 0313-030 through the third connection hole 0130 that penetrates the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713 to expand the capacitance value of the storage capacitor. The capacitor electrode portions Cst-010 and Cst-020 are similar and will not be described here. Furthermore, in the same sub-pixel, the positive projection of the light-shielding electrode on the base substrate 100 can cover the area surrounded by the first connection via and the second connection via.

[0137] In specific implementation, Figure 3 and Figure 4a As shown, the cathode layer 400 is electrically connected to the auxiliary wiring 210 through the first via hole 310. Exemplarily, the signal line having a double-layer wiring structure may include the auxiliary wiring 210. In this way, by providing the auxiliary wiring 210 and electrically connecting the cathode layer 400 to the auxiliary wiring 210, the resistance of the cathode layer is reduced. Thus, the influence of IR Drop on the light uniformity of the display panel can be reduced, and the display effect of the display panel can be improved.

[0138] In the specific implementation, in the embodiment of the present disclosure, if Figure 2a , Figure 3 , Figure 4a and Figure 5d As shown, the auxiliary wiring 210 may include: a first auxiliary wiring 211 located in the first conductive layer 200, and a second auxiliary wiring 212 located in the second conductive layer 800. The first auxiliary wiring 211 extends along the column direction F1 of the sub-pixel, and the first auxiliary wiring 211 is arranged along the row direction F2 of the sub-pixel. Of course, the embodiments of the present disclosure include but are not limited to this.

[0139] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 and Figure 5d As shown, the first auxiliary wiring 211 can be located in the gap between two adjacent sub-pixel columns, and the cathode layer 400 is electrically connected to the first auxiliary wiring 211 through the first via 310. Exemplarily, an auxiliary wiring 210 is located in the gap between the third color sub-pixel column and the first color sub-pixel column. Further, the first auxiliary wiring 211 can be located in the gap between two adjacent pixel unit columns. Of course, the embodiments of the present disclosure include but are not limited to this.

[0140] Optionally, in a specific implementation, in the implementation of the present disclosure, if Figures 2a to 3As shown, at least two adjacent pixel unit columns are formed into a first column group, and one first column group corresponds to a first auxiliary wiring 211, and the first auxiliary wiring 211 is located in the gap between two adjacent pixel unit columns in the corresponding first column group. Exemplarily, two adjacent pixel unit columns are formed into a first column group. For example, in the direction indicated by the F2 arrow (i.e., in the direction from left to right), the first pixel unit column and the second pixel unit column can be formed into the first first column group, and the third pixel unit column and the fourth pixel unit column can be formed into the second first column group. The first auxiliary wiring 211 corresponding to the first first column group is located in the gap between the first pixel unit column and the second pixel unit column, and the first auxiliary wiring 211 corresponding to the second first column group is located in the gap between the third pixel unit column and the fourth pixel unit column. The rest of the settings are similar and will not be described in detail here.

[0141] Optionally, in a specific implementation, in the implementation of the present disclosure, an auxiliary wiring 210 may be provided in the gap between every two adjacent pixel unit columns. For example, in the direction indicated by the arrow F2 (i.e., in the direction from left to right), an auxiliary wiring 210 is provided in the gap between the first pixel unit column and the second pixel unit column, an auxiliary wiring 210 is provided in the gap between the second pixel unit column and the third pixel unit column, and an auxiliary wiring 210 is provided in the gap between the third pixel unit column and the fourth pixel unit column. The rest of the settings are similar and will not be described in detail here.

[0142] In the specific implementation, in the implementation of this disclosure, if Figure 2a , Figure 3 and Figure 5d As shown, a detection line SL and an auxiliary wiring 210 are correspondingly arranged in the same gap between the same pixel unit column. For example, in the direction indicated by the F2 arrow (i.e., from left to right), the first pixel unit column and the second pixel unit column can be made into the first first column group, and the third pixel unit column and the fourth pixel unit column can be made into the second first column group. The auxiliary wiring 210 and the detection line SL corresponding to the first first column group are located in the gap between the first pixel unit column and the second pixel unit column, and the auxiliary wiring 210 and the detection line SL corresponding to the second first column group are located in the gap between the third pixel unit column and the fourth pixel unit column. The rest of the settings are similar and will not be described in detail here.

[0143] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 and Figure 4aAs shown, the display panel may further include: a plurality of first connection portions 520 which are insulated from the anode 510 and are in the same layer. Furthermore, the first via hole 310 may include: a first sub-via hole 311 penetrating the pixel defining layer 330 and a second sub-via hole 312 penetrating the planarization layer 320; wherein the cathode layer 400 is electrically connected to the first connection portion 520 through the first sub-via hole 311, and the first connection portion 520 is electrically connected to the auxiliary wiring 210 through the second sub-via hole 312, for example, the first connection portion 520 is electrically connected to the first auxiliary wiring 211 through the second sub-via hole 312. Since the planarization layer 320 is thicker than the other insulating layers in order to achieve a better planarization effect, the film layer between the cathode layer 400 and the auxiliary wiring 210 is thicker. If only one via hole is provided, the cathode layer 400 and the auxiliary wiring 210 may not be truly electrically connected and may be disconnected due to the depth of the via hole. Therefore, the embodiment of the present disclosure can preferentially electrically connect the auxiliary wiring 210 with the first connecting portion 520 through the second sub-via 312 by setting the first sub-via 311 and the second sub-via 312, and then electrically connect the first connecting portion 520 with the cathode layer 400 through the first sub-via 311, thereby avoiding the situation where only one via is set, resulting in a circuit breaker due to failure of real electrical connection.

[0144] In the specific implementation, in the implementation of this disclosure, if Figure 3 and Figure 4a As shown, the orthographic projection of the first sub-via 311 on the base substrate 100 and the orthographic projection of the second sub-via 312 on the base substrate 100 may be at least partially non-overlapping. Figure 3 and Figure 4a As shown, the orthographic projection of the first sub-via 311 on the base substrate 100 does not overlap with the orthographic projection of the second sub-via 312 on the base substrate 100. This can further avoid the problem that the cathode layer 400 and the auxiliary trace 210 cannot be electrically connected due to the via being too deep.

[0145] Furthermore, in order to further reduce the resistance of the cathode layer 400, in the specific implementation, in the implementation of the present disclosure, as Figure 3 and Figure 4a As shown, the first insulating layer 711 may have a second via hole 720, and the first auxiliary trace 211 is electrically connected to the second auxiliary trace 212 through the second via hole 720 that penetrates the first insulating layer 711. In this way, by providing the first auxiliary trace 211 and the second auxiliary trace 212 that are electrically connected to each other, and electrically connecting the cathode layer 400, the first auxiliary trace 211 and the second auxiliary trace 212, the resistance of the cathode layer 400 can be further reduced. Thereby, the influence of IR Drop on the light uniformity of the display panel can be further reduced, and the display effect of the display panel can be further improved.

[0146] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4a as well as Figure 5c As shown, the second auxiliary wiring 212 includes a plurality of first auxiliary parts 810 arranged at intervals; in the same auxiliary wiring 210, the first auxiliary wiring 211 is electrically connected to the corresponding first auxiliary part 810 through the second via 720. Further, in the same auxiliary wiring 210, the orthographic projection of the first auxiliary wiring 211 on the base substrate 100 and the orthographic projection of the corresponding first auxiliary part 810 on the base substrate 100 have an overlapping area. Exemplarily, in the same auxiliary wiring 210, the orthographic projection of the first auxiliary wiring 211 on the base substrate 100 covers the orthographic projection of the corresponding first auxiliary part 810 on the base substrate 100. In this way, the first auxiliary part 810 can also be arranged between the sub-pixel columns, so as to avoid the first auxiliary part 810 affecting the light-emitting display.

[0147] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4a as well as Figure 5c As shown, the orthographic projection of the first auxiliary portion 810 on the base substrate 100 covers the orthographic projection of the corresponding second via hole 720 on the base substrate 100. In this way, the second via hole 720 can also be arranged between the sub-pixel columns, thereby avoiding affecting the light-emitting display.

[0148] In the specific implementation, in the implementation of this disclosure, if Figure 3 , Figure 4a as well as Figure 5c As shown, one first auxiliary wiring 211 may correspond to multiple first auxiliary parts 810. Moreover, the orthographic projection of one first auxiliary part 810 on the base substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 electrically connected to the same row of sub-pixels on the base substrate 100.

[0149] For example, Figure 2b As shown, for a plurality of first auxiliary parts 810 electrically connected to the same first auxiliary wiring 211, one sub-pixel row may correspond to one first auxiliary part 810. That is, each row of sub-pixels may correspond to one first auxiliary part 810. For example, in the direction of the arrow F1, one first auxiliary part 810 may be provided between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.

[0150] For example, Figure 3As shown, for the multiple first auxiliary parts 810 electrically connected to the same first auxiliary wiring 211, the sub-pixel rows separated by at least one sub-pixel row may correspond to a first auxiliary part 810. For example, in the direction of the arrow along F1, the sub-pixel rows separated by one sub-pixel row may correspond to a first auxiliary part 810, that is, the odd sub-pixel rows may correspond to a first auxiliary part 810, or the even sub-pixel rows may correspond to a first auxiliary part 810. Alternatively, in the direction of the arrow along F1, the sub-pixel rows separated by eleven sub-pixel rows may correspond to a first auxiliary part 810, that is, the first sub-pixel row may correspond to a first auxiliary part 810, the thirteenth sub-pixel row may correspond to a first auxiliary part 810, the twenty-fifth sub-pixel row may correspond to a first auxiliary part 810, and the rest may be deduced by analogy, and are not limited here. Of course, the present disclosure includes but is not limited to this.

[0151] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4a as well as Figure 5c As shown, the first auxiliary portion 810 extends along the column direction F1. Further, for the first auxiliary portion 810 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the first auxiliary portion 810 is closer to the second gate line G2.

[0152] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 as well as Figure 5d As shown, the width of the portion of the first auxiliary wiring 211 that overlaps with the orthographic projection of the first auxiliary portion 810 along the sub-pixel row direction is the first width W1, and the width of the portion of the first auxiliary wiring 211 that overlaps with the orthographic projection of the first gate line G1 along the sub-pixel row direction is the second width W2. The first width W1 is greater than the second width W2. In this way, the area of ​​the sub-pixel closest to the first auxiliary wiring 211 can be increased by making the first auxiliary wiring 211 avoid.

[0153] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 as well as Figure 5d As shown, the portion of the first auxiliary wiring 211 having the second width W2 can be made close to the second connection hole 0120. In this way, the portion of the first auxiliary wiring 211 close to the second connection hole 0120 can be avoided.

[0154] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4a as well as Figure 5cAs shown, each first auxiliary portion 810 can be electrically connected to the corresponding first auxiliary trace 211 through at least four second vias 720. Specifically, each first auxiliary portion 810 can be electrically connected to the corresponding first auxiliary trace 211 through four, five, six or more second vias 720. In this way, there can be multiple electrical connection contact points between each first auxiliary portion 810 and the first auxiliary trace 211. Even if a rupture or break occurs at any contact point, the electrical connection between the first auxiliary portion 810 and the first auxiliary trace 211 can still be achieved through other contact points, thereby further reducing the risk of disconnection between the first auxiliary portion 810 and the first auxiliary trace 211. Of course, the present disclosure includes but is not limited to this.

[0155] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4a As shown, an auxiliary routing line 210 may correspond to a plurality of first vias 310, and a first via 310 corresponds to a sub-pixel row; wherein, for the first vias 310 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the orthographic projection of the first sub-via 311 on the substrate substrate 100 and the orthographic projection of the second gate line G2 on the substrate substrate 100 have an overlapping area; and the orthographic projection of the second sub-via 312 on the substrate substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 on the substrate substrate 100.

[0156] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , and 3 and Figure 4a As shown, for the second sub-vias 312 , second vias 720 and second gate lines G2 corresponding to the same row of sub-pixels, the orthographic projection of the second sub-vias 312 on the base substrate 100 is located between the orthographic projection of the second gate line G2 on the base substrate 100 and the orthographic projections of all second vias 720 on the base substrate 100 .

[0157] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4a As shown, the plurality of second vias 720 corresponding to the same first auxiliary trace 211 may be arranged on the same straight line along the column direction F1 .

[0158] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the signal line with a double-layer wiring structure may include: a detection line SL. By setting the detection line SL as a double-layer wiring structure electrically connected to each other, the resistance of the detection line SL can be reduced, thereby reducing the influence of IR Drop on the light uniformity of the display panel and improving the display effect of the display panel.

[0159] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the detection line SL may include: a first detection line 221 located in the first conductive layer 200, and a second detection line 222 located in the second conductive layer 800. The first insulating layer 711 has a third via hole 730, and the first detection line 221 is electrically connected to the second detection line 222 through the third via hole 730 penetrating the first insulating layer 711.

[0160] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the first detection wiring 221 extends along the column direction F1 of the sub-pixels, and the first detection wiring 221 is arranged along the row direction F2 of the sub-pixels. Of course, the embodiments of the present disclosure include but are not limited to this.

[0161] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the first conductive layer 200 may further include: a plurality of second connection parts (i.e., capacitor electrode parts Cst-010, Cst-020, Cst-030), and the planarization layer 320 further includes a fifth connection hole 0150, and the fifth connection hole 0150 exposes a portion of the second connection part (i.e., capacitor electrode parts Cst-010, Cst-020, Cst-030); the anode 510 is electrically connected to the second connection part (i.e., capacitor electrode parts Cst-010, Cst-020, Cst-030) through the fifth connection hole 0150. Specifically, the planarization layer 320 has a fifth connection hole 0150, and each sub-pixel corresponds to a fifth connection hole 0150. Among them, the anode 510 in the first color sub-pixel 010 is electrically connected to the capacitor electrode part Cst-010 through the fifth connection hole 0150, the anode 510 in the second color sub-pixel 020 is electrically connected to the capacitor electrode part Cst-020 through the fifth connection hole 0150, and the anode 510 in the third color sub-pixel 030 is electrically connected to the capacitor electrode part Cst-030 through the fifth connection hole 0150.

[0162] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 , Figure 4b as well as Figure 5cAs shown, the second detection line 222 may further include: a plurality of second auxiliary parts 820 arranged at intervals; wherein, in the same detection line SL, the first detection line 221 is electrically connected to the corresponding second auxiliary part 820 through the third via 730. Moreover, one first detection line 221 corresponds to at least one second auxiliary part 820, and the first detection line 221 is electrically connected to the corresponding second auxiliary part 820 through the third via 730.

[0163] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, in the same detection line SL, the orthographic projection of the first detection line 221 on the base substrate 100 and the orthographic projection of the corresponding second auxiliary part 820 on the base substrate 100 have an overlapping area. Further, in the same detection line SL, the orthographic projection of the first detection line 221 on the base substrate 100 covers the orthographic projection of the corresponding second auxiliary part 820 on the base substrate 100. In this way, the second auxiliary part 820 can be prevented from affecting the display.

[0164] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the orthographic projection of the first connection portion 520 on the base substrate 100 does not overlap with the orthographic projection of the third via hole 730 on the base substrate 100 .

[0165] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4b as well as Figure 5c As shown, a first detection line 221 may correspond to a plurality of second auxiliary parts 820 , and an orthographic projection of a second auxiliary part 820 on the base substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 electrically connected to the same row of sub-pixels on the base substrate 100 .

[0166] For example, Figure 2b As shown, for multiple second auxiliary parts 820 electrically connected to the same first detection line 221, one sub-pixel row can correspond to one second auxiliary part 820. That is, each row of sub-pixels can correspond to one second auxiliary part 820. For example, in the direction of the arrow F1, a second auxiliary part 820 can be set between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.

[0167] For example, Figure 3As shown, for multiple second auxiliary parts 820 electrically connected to the same first detection wiring 221, the sub-pixel rows separated by at least one sub-pixel row can correspond to a second auxiliary part 820. For example, in the direction of the arrow along F1, the sub-pixel rows separated by one sub-pixel row can correspond to a second auxiliary part 820, that is, the odd sub-pixel rows can correspond to a second auxiliary part 820, or the even sub-pixel rows can correspond to a second auxiliary part 820. Alternatively, in the direction of the arrow along F1, the sub-pixel rows separated by eleven sub-pixel rows can correspond to a second auxiliary part 820, that is, the first sub-pixel row can correspond to a second auxiliary part 820, the thirteenth sub-pixel row can correspond to a second auxiliary part 820, the twenty-fifth sub-pixel row can correspond to a second auxiliary part 820, and the rest can be deduced by analogy, which is not limited here. Of course, the present disclosure includes but is not limited to this.

[0168] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4b as well as Figure 5c As shown, the second auxiliary portion 820 extends along the column direction F1. Further, for the second auxiliary portion 820 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the second auxiliary portion 820 is closer to the second gate line G2.

[0169] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4b as well as Figure 5c As shown, each second auxiliary portion 820 can be electrically connected to the corresponding first detection line 221 through at least three third vias 730. Specifically, each second auxiliary portion 820 can be electrically connected to the corresponding first detection line 221 through three, four, five or more third vias 730. In this way, there are multiple electrical connection contact points between each second auxiliary portion 820 and the first detection line 221. Even if a rupture or break occurs at any contact point, the connection between the second auxiliary portion 820 and the first detection line 221 can still be achieved through other contact points, thereby further reducing the risk of disconnection between the second auxiliary portion 820 and the first detection line 221. Of course, the present disclosure includes but is not limited to this.

[0170] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4b as well as Figure 5c As shown, the orthographic projection of the second auxiliary portion 820 on the base substrate 100 covers the orthographic projection of the corresponding third via hole 730 on the base substrate 100. In this way, the third via hole 730 can also be arranged between the sub-pixel columns, thereby avoiding affecting the light-emitting display.

[0171] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the third connection holes 0130 in a row of sub-pixels are arranged in a straight line along the row direction F2, and the fourth connection holes 0140 in a row of sub-pixels are also arranged in a straight line along the row direction F2. For the fourth via holes 720, the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the orthographic projection of the third via holes 730 on the base substrate 100 is located between the straight line where the third connection holes 0130 are located along the row direction F1 and the straight line where the fourth connection holes 0140 are located along the row direction F1.

[0172] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, the plurality of third vias 730 corresponding to the same first detection trace 221 may be arranged on the same straight line along the column direction F1 .

[0173] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4b As shown, two adjacent pixel unit columns are formed into a second column group, and each sub-pixel in the second column group is electrically connected to a first detection line 221. For example, in the direction indicated by the F2 arrow (i.e., from left to right), the first pixel unit column and the second pixel unit column are the first second column group, and the third pixel unit column and the fourth pixel unit column are the second second column group. The first detection line 221 corresponding to the first second column group is located in the gap between the first pixel unit column and the second pixel unit column, and the sensing transistor in each sub-pixel in the first second column group is electrically connected to the corresponding first detection line 221. The first detection line 221 corresponding to the second second column group is located in the gap between the third pixel unit column and the fourth pixel unit column, and the sensing transistor in each sub-pixel in the second second column group is electrically connected to the corresponding first detection line 221. The rest of the settings are similar and will not be described in detail here.

[0174] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4bAs shown, each first detection line 221 corresponds to a plurality of first connection lines 0311 electrically connected, and for the first connection line 0311 electrically connected to the same first detection line 221, each row of sub-pixels in the second column group corresponds to a first connection line 0311. Moreover, each row of sub-pixels in the second column group is electrically connected to the first detection line 221 through the corresponding first connection line 0311. Exemplarily, the first detection line 221 is electrically connected to the corresponding first connection line 0311 through a via 911 that penetrates the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713. Moreover, the first conductive layer 200 may further include: a plurality of third connection parts, each sub-pixel having a third connection part. For example, the first color sub-pixel 010 has a third connection part T3-010, the second color sub-pixel 020 has a third connection part T3-020, and the third color sub-pixel 030 has a third connection part T3-030. Furthermore, one end of the third connection portion T3-030 is electrically connected to the drain region of the active semiconductor layer 0320 serving as a sensing transistor through a via 912 penetrating the first insulating layer 711 and the second insulating layer 712, and the other end is electrically connected to the corresponding first connection wiring 0311 through a via 913 penetrating the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713. One end of the third connection portion T3-010 is electrically connected to the drain region of the active semiconductor layer serving as a sensing transistor through a via penetrating the first insulating layer and the second insulating layer, and the other end is electrically connected to the corresponding first connection wiring through vias penetrating the first insulating layer, the second insulating layer, and the third insulating layer. One end of the third connection portion T3-020 is electrically connected to the drain region of the active semiconductor layer serving as a sensing transistor through a via penetrating the first insulating layer and the second insulating layer, and the other end is electrically connected to the corresponding first connection wiring through vias penetrating the first insulating layer, the second insulating layer, and the third insulating layer. It should be noted that, Figure 4b The third connection part T3-030 is only taken as an example for explanation. The implementation methods of the third connection part T3-010 and the third connection part T3-020 can be inferred accordingly and will not be elaborated here.

[0175] In the specific implementation, in the embodiment of the present disclosure, if Figures 2a to 3 As shown, a first detection line 221 and a first auxiliary line 211 can be arranged in the gap between the same pixel unit column. In this way, by arranging the first detection line 221 transmitting the detection signal and the first auxiliary line 211 transmitting the fixed voltage in the same gap, the influence of the signal on the detection signal transmitted by the first detection line 221 can be reduced, and the accuracy of the signal transmitted by the first detection line 221 can be improved.

[0176] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4a As shown, for the first detection line 221 and the first auxiliary line 211 arranged in the gap between the same pixel unit column, the orthographic projection of the first sub-via 311 corresponding to the first auxiliary line 211 on the base substrate 100 also has an overlapping area with the orthographic projection of the first detection line 221 on the base substrate 100.

[0177] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4a As shown, for the first detection wiring 221 and the first auxiliary wiring 211 arranged in the gap between the same pixel unit column, the orthographic projection of the first connection portion 520 on the base substrate 100 also has an overlapping area with the orthographic projection of the first detection wiring 221 on the base substrate 100, and the orthographic projection of the first connection portion 520 on the base substrate 100 also has an overlapping area with the orthographic projection of the first auxiliary wiring 211 on the base substrate 100.

[0178] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b and Figure 3 As shown, a second auxiliary portion 820 and a first auxiliary portion 810 can correspond to the same sub-pixel row, which can simplify the design of the second auxiliary portion 820 and the first auxiliary portion 810 and reduce the design difficulty.

[0179] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b and Figure 3 As shown, for the first auxiliary part 810 and the second auxiliary part 820 corresponding to the same row of sub-pixels, the second via hole 720 of the first auxiliary part 810 and the third via hole 730 of the second auxiliary part 820 can be arranged in a staggered manner. For example, the geometric center of the second via hole 720 corresponds to the gap between the two third via holes 730.

[0180] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 as well as Figure 5d As shown, the width of the portion of the first detection line 221 that overlaps with the orthographic projection of the second auxiliary portion 820 along the sub-pixel row direction F2 is the third width W3, and the width of the portion of the first detection line 221 that overlaps with the orthographic projection of the first gate line G1 along the sub-pixel row direction F2 is the fourth width W4. The third width W3 is greater than the fourth width W4. In this way, the area of ​​the sub-pixel closest to the first detection line 221 can be increased by making the first detection line 221 avoid.

[0181] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 as well as Figure 5dAs shown, the portion of the first detection trace 221 having the fourth width W4 can be made close to the second connection hole 0120. In this way, the portion of the first detection trace 221 close to the second connection hole 0120 can be avoided.

[0182] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, the signal line with a double-layer wiring structure may include: a power line VDD. By setting the power line VDD as a double-layer wiring structure electrically connected to each other, the resistance of the power line VDD can be reduced, thereby reducing the influence of IR Drop on the light uniformity of the display panel and improving the display effect of the display panel.

[0183] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, the power line includes: a first power line 231 located in the first conductive layer 200, and a second power line 232 located in the second conductive layer 800. The first insulating layer 711 has a fourth via 740, and the first power line 231 is electrically connected to the second power line 232 through the fourth via 740 penetrating the first insulating layer 711.

[0184] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, the first power supply wiring 231 extends along the column direction F1 of the sub-pixels, and the first power supply wiring 231 is arranged along the row direction F2 of the sub-pixels. Of course, the embodiments of the present disclosure include but are not limited to this.

[0185] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4cAs shown, each first power supply line 231 is electrically connected to a plurality of second connection lines 0312. In the direction indicated by the arrow F2 (i.e., from left to right), the first pixel unit column is electrically connected to a first power supply line 231, and the last pixel unit column is electrically connected to a first power supply line 231. For the pixel unit columns other than the first pixel unit column and the last pixel unit column, two adjacent pixel unit columns are formed into a third column group, and each sub-pixel in the third column group is electrically connected to a first power supply line 231. For example, in the direction indicated by the arrow F2 (i.e., from left to right), the second pixel unit column and the third pixel unit column are the first third column group, and the fourth pixel unit column and the fifth pixel unit column are the second third column group. The first power supply line 231 corresponding to the first third column group is located in the gap between the second pixel unit column and the third pixel unit column, and the driving transistor in each sub-pixel in the first third column group is electrically connected to the corresponding first power supply line 231. The first power supply line 231 corresponding to the second third column group is located in the gap between the fourth pixel unit column and the fifth pixel unit column, and the driving transistor in each sub-pixel in the second third column group is electrically connected to the corresponding first power supply line 231. The rest of the settings are similar and will not be described in detail here.

[0186] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 , Figure 4a , Figure 4c as well as Figure 5d As shown, at least one column of pixel units is spaced between the first power line 231 and the first auxiliary line 211. Exemplarily, one column of pixel units may be spaced between the first power line 231 and the first auxiliary line 211. Alternatively, two, three, four or more columns of pixel units may be spaced between the first power line 231 and the first auxiliary line 211, which is not limited here.

[0187] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 as well as Figure 4c As shown, each first power supply line 231 is electrically connected to a plurality of second connection lines 0312, and, for the second connection lines 0312 electrically connected to the same first power supply line 231, each row of sub-pixels in the third column group corresponds to a second connection line 0312. Moreover, each row of sub-pixels in the third column group is electrically connected to the first power supply line 231 through the corresponding second connection line 0312. Exemplarily, the first power supply line 231 is electrically connected to the corresponding second connection line 0312 through a via 916 that penetrates the first insulating layer 711, the second insulating layer 712, and the third insulating layer 713.

[0188] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 , Figure 4c as well as Figure 5c As shown, the second power supply line 232 may include: a plurality of third auxiliary parts 830 arranged at intervals; wherein, in the same power supply line VDD, the first power supply line 231 is electrically connected to the corresponding third auxiliary part 830 through the fourth via 740. Moreover, one first power supply line 231 corresponds to at least one third auxiliary part 830, and the first power supply line 231 is electrically connected to the corresponding third auxiliary part 830 through the fourth via 740.

[0189] In the specific implementation, in the embodiment of the present disclosure, if Figure 3 and Figure 4c As shown, the orthographic projection of the first power supply line 231 on the base substrate 100 and the orthographic projection of the corresponding third auxiliary part 830 on the base substrate 100 have an overlapping area. Further, the orthographic projection of the first power supply line 231 on the base substrate 100 covers the orthographic projection of the corresponding third auxiliary part 830 on the base substrate 100. In this way, the third auxiliary part 830 can be prevented from affecting the display.

[0190] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4c as well as Figure 5c As shown, a first power supply line 231 may correspond to a plurality of third auxiliary parts 830 , and an orthographic projection of a third auxiliary part 830 on the base substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 electrically connected to the same row of sub-pixels on the base substrate 100 .

[0191] For example, Figure 2b As shown, for a plurality of third auxiliary parts 830 electrically connected to the same first power supply line 231, one sub-pixel row can correspond to one third auxiliary part 830. That is, each row of sub-pixels can correspond to one third auxiliary part 830. For example, in the direction of the arrow F1, one third auxiliary part 830 can be arranged between the first gate line G1 and the second gate line G2 electrically connected to each row of sub-pixels.

[0192] For example, Figure 3As shown, for a plurality of third auxiliary parts 830 electrically connected to the same first power supply line 231, a sub-pixel row separated by at least one sub-pixel row can correspond to a third auxiliary part 830. For example, in the direction of the arrow along F1, a sub-pixel row separated by one sub-pixel row can correspond to a third auxiliary part 830, that is, an odd sub-pixel row can correspond to a third auxiliary part 830, or an even sub-pixel row can correspond to a third auxiliary part 830. Alternatively, in the direction of the arrow along F1, a sub-pixel row separated by eleven sub-pixel rows can correspond to a third auxiliary part 830, that is, the first sub-pixel row can correspond to a third auxiliary part 830, the thirteenth sub-pixel row can correspond to a third auxiliary part 830, the twenty-fifth sub-pixel row can correspond to a third auxiliary part 830, and the rest can be deduced by analogy, which is not limited here. Of course, the present disclosure includes but is not limited to this.

[0193] In the specific implementation, in the implementation of this disclosure, if Figure 3 , Figure 4c as well as Figure 5c As shown, the third auxiliary portion 830 extends along the column direction F1. Further, for the third auxiliary portion 830 and the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the third auxiliary portion 830 is closer to the second gate line G2.

[0194] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4c as well as Figure 5c As shown, each third auxiliary portion 830 can be electrically connected to the corresponding first power trace 231 through at least four fourth vias 740. Specifically, each third auxiliary portion 830 can be electrically connected to the corresponding first power trace 231 through three, four, five or more fourth vias 740. In this way, there are multiple electrical connection contact points between each third auxiliary portion 830 and the first power trace 231. Even if a rupture or break occurs at any contact point, the connection between the third auxiliary portion 830 and the first power trace 231 can still be achieved through other contact points, thereby further reducing the risk of disconnection between the third auxiliary portion 830 and the first power trace 231. Of course, the present disclosure includes but is not limited to this.

[0195] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 , Figure 4c as well as Figure 5c As shown, the orthographic projection of the third auxiliary portion 830 on the base substrate 100 covers the orthographic projection of the corresponding fourth via hole 740 on the base substrate 100. In this way, the fourth via hole 740 can also be arranged between the sub-pixel columns, thereby avoiding affecting the light-emitting display.

[0196] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, for the fourth via hole 740 , the first gate line G1 and the second gate line G2 corresponding to the same row of sub-pixels, the orthographic projection of the fourth via hole 740 on the base substrate 100 is located between the orthographic projections of the first gate line G1 and the second gate line G2 on the base substrate 100 .

[0197] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, the plurality of fourth vias 740 corresponding to the same first power trace 231 can be arranged on the same straight line along the column direction F1.

[0198] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 and Figure 4c As shown, for the first connection holes 0110 and the third auxiliary parts 830 corresponding to the same row of sub-pixels, a fourth via hole 740 corresponding to the third auxiliary part 830 and the first connection hole 0110 can be arranged in a straight line along the sub-pixel row direction.

[0199] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b and Figure 3 As shown, a third auxiliary portion 830 and a first auxiliary portion 810 can correspond to the same sub-pixel row, which can simplify the design of the third auxiliary portion 830 and the first auxiliary portion 810 and reduce the design difficulty.

[0200] Further, in the embodiments of the present disclosure, if Figure 2b and Figure 3 As shown, a third auxiliary portion 830, a second auxiliary portion 820 and a first auxiliary portion 810 can correspond to the same sub-pixel row, which can further simplify the design of the third auxiliary portion 830, the second auxiliary portion 820 and the first auxiliary portion 810 and reduce the design difficulty.

[0201] In the specific implementation, in the embodiment of the present disclosure, if Figure 2b , Figure 3 as well as Figure 5d As shown, the width of the portion of the first power line 231 that overlaps with the orthographic projection of the third auxiliary portion 830 along the sub-pixel row direction F2 is the fifth width W5, and the width of the portion of the first power line 231 that overlaps with the orthographic projection of the first gate line G1 along the sub-pixel row direction F2 is the sixth width W6. The fifth width W5 is greater than the sixth width W6. In this way, the area of ​​the sub-pixel closest to the first power line 231 can be increased by making the first power line 231 avoid.

[0202] In the specific implementation, in the implementation of this disclosure, if Figure 2b , Figure 3 as well as Figure 5d As shown, the portion of the first power trace 231 having the sixth width W6 can be made close to the second connection hole 0120. In this way, the portion of the first power trace 231 close to the second connection hole 0120 can be avoided.

[0203] It should be noted that the first width, the second width, the third width, the fourth width, the fifth width and the sixth width can be designed and determined according to the actual application environment and are not limited here.

[0204] It should be noted that in actual processes, due to limitations of process conditions or other factors, the similarities among the above-mentioned features may not be completely the same, and there may be some deviations. Therefore, as long as the similarity relationship between the above-mentioned features roughly meets the above-mentioned conditions, they all belong to the protection scope of the present disclosure. For example, the above-mentioned similarities may be the same as allowed within the allowable error range.

[0205] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0206] In specific implementation, in the embodiment of the present disclosure, the display device may be as follows: Figure 6 The full-screen mobile phone shown.

[0207] Of course, in a specific implementation, the display device may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations of the present disclosure.

[0208] The display panel and display device provided by the embodiments of the present disclosure can reduce the resistance of the signal line provided with the double-layer wiring structure by setting a double-layer wiring structure that is electrically connected to each other, thereby reducing the influence of IR Drop on the luminous uniformity of the display panel and improving the display effect of the display panel.

[0209] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, comprising: substrate substrate; A plurality of pixel units are arrayed on the substrate, and at least one of the pixel units includes: a plurality of sub-pixels, and at least one of the sub-pixels includes: a sensing transistor and a driving transistor; A plurality of gate line groups, each of the gate line groups comprising a first gate line and a second gate line; For the first gate line and the second gate line corresponding to the pixel units in the same row, the sensing transistor is located on a side closer to the second gate line, and the driving transistor is located on a side closer to the first gate line; In the same sub-pixel, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through the first connection hole, and the first electrode of the driving transistor is electrically connected to the power line through the second connection hole; For two sub-pixels in the same row that are close to each other and not located in the same pixel unit, at least one signal line in an area surrounded by the first connection holes and the second connection holes of the two sub-pixels has a double-layer wiring structure, and the double-layer wiring structures of the same signal line are electrically connected to each other; The sub-pixel further comprises: an anode, a light-emitting functional layer and a cathode layer which are stacked; wherein, in the same sub-pixel, the second electrode of the driving transistor is electrically connected to the anode; The display panel further includes: A plurality of auxiliary wirings; wherein the auxiliary wirings are located in a gap between two adjacent sub-pixel columns, and the cathode layer is electrically connected to the auxiliary wirings through a first via hole; A plurality of detection lines; wherein the detection line is located in a gap between two adjacent sub-pixel columns, the detection line is insulated from the auxiliary wiring, and the detection line is electrically connected to the second electrode of the sensing transistor; The signal line includes: at least one of the auxiliary line, the detection line and the power line.

2. The display panel according to claim 1, wherein: The display panel further includes: A pixel defining layer, located between the layer where the anode is located and the light-emitting functional layer; A planarization layer, located on a side of the pixel defining layer facing the base substrate; A first conductive layer; located on a side of the planarization layer facing the substrate; A first insulating layer, located on a side of the first conductive layer facing the base substrate; A second conductive layer is located on a side of the first insulating layer facing the base substrate; The auxiliary routing includes: A first auxiliary wiring, located in the first conductive layer and extending along the column direction of the sub-pixels; A second auxiliary wiring, located in the second conductive layer; The first auxiliary wiring is electrically connected to the second auxiliary wiring through a second via hole penetrating the first insulating layer.

3. The display panel according to claim 2, wherein: The second auxiliary routing includes a plurality of first auxiliary portions arranged at intervals; wherein, in the same auxiliary routing, the first auxiliary routing is electrically connected to the corresponding first auxiliary portions through the second vias respectively.

4. The display panel according to claim 3, wherein: In the same auxiliary routing, the orthographic projection of the first auxiliary routing on the base substrate and the orthographic projection of the corresponding first auxiliary portion on the base substrate have an overlapping area.

5. The display panel according to claim 3, wherein: The orthographic projection of the first auxiliary portion on the base substrate covers the orthographic projection of the corresponding second via hole on the base substrate.

6. The display panel according to any one of claims 3 to 5, wherein: For a plurality of first auxiliary portions electrically connected to the same first auxiliary wiring, one sub-pixel row corresponds to one first auxiliary portion.

7. The display panel according to any one of claims 3 to 5, wherein: Each of the first auxiliary parts is electrically connected to the corresponding first auxiliary trace through at least four second vias.

8. The display panel according to any one of claims 3 to 5, wherein: The orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the anode on the base substrate.

9. The display panel according to any one of claims 3 to 5, wherein: The display panel further includes: A plurality of first connecting parts, which are in the same layer as the anode and insulated; The first via hole comprises: a first sub-via hole penetrating the pixel defining layer and a second sub-via hole penetrating the planarization layer; The cathode layer is electrically connected to the first connection portion through the first sub-via, and the first connection portion is electrically connected to the auxiliary trace through the second sub-via.

10. The display panel according to claim 9, wherein: An orthographic projection of the first sub-via on the base substrate and an orthographic projection of the second sub-via on the base substrate at least partially do not overlap.

11. The display panel according to any one of claims 2 to 5, wherein: The first auxiliary wiring is located in a gap between two adjacent sub-pixel columns.

12. The display panel according to any one of claims 2 to 5, wherein: The display panel further includes: A second insulating layer, located on a side of the second conductive layer facing the base substrate; An active semiconductor layer, located on a side of the second insulating layer facing the substrate; A third insulating layer is located on a side of the active semiconductor layer facing the substrate; A light-shielding metal layer, located on a side of the third insulating layer facing the base substrate; The light-shielding metal layer includes: at least one light-shielding electrode; wherein one of the light-shielding electrodes is located in one of the sub-pixels; In the same sub-pixel, the orthographic projection of the light-shielding electrode on the base substrate at least covers a portion of the orthographic projection of the channel region of the driving transistor on the base substrate.

13. The display panel according to claim 12, wherein: At least one of the sub-pixels further comprises: a storage capacitor; wherein a first electrode of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the storage capacitor is electrically connected to the second electrode of the driving transistor; The second electrode of the storage capacitor is also electrically connected to the light shielding electrode through a third connection hole.

14. The display panel according to any one of claims 2 to 5, wherein: The power cord comprises: A first power supply line is located in the first conductive layer and extends along the column direction of the sub-pixels; A second power supply line is located on the second conductive layer; The first power line is electrically connected to the second power line through a fourth via hole penetrating the first insulating layer.

15. The display panel according to claim 14, wherein: The second power supply line includes a plurality of third auxiliary parts arranged at intervals; wherein, in the same power supply line, the first power supply line is electrically connected to the corresponding third auxiliary parts through the fourth vias respectively.

16. The display panel according to claim 15, wherein: In the same power line, the orthographic projection of the first power line on the base substrate and the orthographic projection of the corresponding third auxiliary portion on the base substrate have an overlapping area.

17. The display panel according to claim 16, wherein: The orthographic projection of the third auxiliary portion on the base substrate covers the orthographic projection of the corresponding fourth via hole on the base substrate.

18. The display panel according to claim 17, wherein: Each of the third auxiliary parts is electrically connected to the corresponding first power line through at least four fourth vias.

19. The display panel according to claim 15, wherein: For a plurality of third auxiliary portions electrically connected to the same first power line, one sub-pixel row corresponds to one third auxiliary portion.

20. The display panel according to claim 15, wherein: For a plurality of third auxiliary portions electrically connected to the same first power line, a sub-pixel row separated by at least one sub-pixel row corresponds to one third auxiliary portion.

21. The display panel according to claim 19 or 20, wherein: One of the third auxiliary parts and one of the first auxiliary parts correspond to the same sub-pixel row.

22. The display panel according to claim 21, wherein: For the third auxiliary portion and the first gate line and the second gate line corresponding to the sub-pixels in the same row, the third auxiliary portion is closer to the second gate line.

23. The display panel according to any one of claims 15 to 20, wherein: The width of a portion of the first power line that overlaps with the orthographic projection of the third auxiliary portion along the sub-pixel row direction is a fifth width, and the width of a portion of the first power line that overlaps with the orthographic projection of the first gate line along the sub-pixel row direction is a sixth width; The fifth width is greater than the sixth width.

24. The display panel according to claim 23, wherein: The portion of the first power trace having the sixth width is close to the second connection hole.

25. The display panel according to any one of claims 15 to 20, wherein: For the first connection holes and the third auxiliary parts corresponding to the same row of sub-pixels, a fourth via hole corresponding to the third auxiliary part and the first connection hole are arranged in a straight line along the sub-pixel row direction.

26. A display device, wherein: Comprising a display panel as described in any one of claims 1-25.

Images