Display device and method for manufacturing display device

Abstract

The invention provides a display device and a method for manufacturing the display device. The display device includes a display panel and an input sensor. The input sensor may include a first detection electrode that may include a first detection pattern and a bridge pattern electrically connected to the first detection pattern. The bridge pattern may include a 1-1 conductive layer and a 1-2 conductive layer, and the first detection pattern may include a 2-1 conductive layer and a 2-2 conductive layer. A first opening portion exposing one surface of the 1-1 conductive layer may be defined in the 1-2 conductive layer, and a second opening portion exposing one surface of the 2-1 conductive layer may be defined in the 2-2 conductive layer. The one surface of the 1-1 conductive layer and the one surface of the 2-1 conductive layer may be in contact with each other.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure herein relate to a display device and a method for manufacturing a display device, for example, to a display device including an input sensor. Background Art

[0002] Multimedia devices such as televisions, mobile phones, tablet computers, navigation units, and game consoles include display devices that provide images to users through display screens. The display devices may provide a touch-based input scheme that enables users to intuitively and conveniently input information or commands.

[0003] The display device may include a display panel generating an image and an input sensor detecting a user's touch input. The input sensor may include a conductor detecting an external input.

[0004] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure include a display device in which a contact resistance between conductive layers of an input sensor is relatively reduced to relatively improve performance of the input sensor.

[0006] Aspects of some embodiments of the present disclosure also include a method for manufacturing a display device having relatively improved performance.

[0007] According to some embodiments of the present disclosure, a display device includes: a display panel including an emission area and a non-emission area adjacent to the emission area; and an input sensor including a detection area and a non-detection area adjacent to the detection area, and on the display panel. According to some embodiments, the input sensor may include a first detection electrode overlapping the detection area, and the first detection electrode may include: a first detection pattern; and a bridge pattern, which is in a different layer from the first detection pattern and is electrically connected to the first detection pattern through a contact hole passing through a sensor insulating layer. According to some embodiments, the bridge pattern may include a 1-1 conductive layer and a 1-2 conductive layer directly on one surface of the 1-1 conductive layer, and the first detection pattern may include a 2-1 conductive layer and a 2-2 conductive layer directly on one surface of the 2-1 conductive layer. According to some embodiments, a first opening portion exposing one surface of the 1-1 conductive layer may be defined in the 1-2 conductive layer, and a second opening portion exposing one surface of the 2-1 conductive layer may be defined in the 2-2 conductive layer. According to some embodiments, a surface of the 1-1 conductive layer overlapping with the first opening portion and a surface of the 2-1 conductive layer overlapping with the second opening portion may contact each other.

[0008] According to some embodiments, each of the first opening portion and the second opening portion may overlap the contact hole in a plan view.

[0009] According to some embodiments, a shape of the first opening portion in a plan view may correspond to a shape of the second opening portion in a plan view.

[0010] According to some embodiments, the first sensing pattern may include a mesh pattern in which a mesh opening portion overlapping the emission region is defined.

[0011] According to some embodiments, the mesh pattern may include a first line portion extending in a first direction and a second line portion extending in a second direction crossing the first direction, and the contact hole may be located at a point where the first line portion and the second line portion cross each other.

[0012] According to some embodiments, a resistance value of the 1-1 conductive layer may be smaller than a resistance value of the 1-2 conductive layer, and a resistance value of the 2-1 conductive layer may be smaller than a resistance value of the 2-2 conductive layer.

[0013] According to some embodiments, each of the 1-1 conductive layer and the 2-1 conductive layer may include aluminum, and each of the 1-2 conductive layer and the 2-2 conductive layer may include titanium.

[0014] According to some embodiments, the input sensor may further include a second detection electrode insulated from the first detection electrode and crossing the first detection electrode, and the second detection electrode may be provided in an integrated form and on the same layer.

[0015] According to some embodiments, the input sensor may further include a signal line in the non-detection area, and each of one end of the first detection electrode and one end of the second detection electrode may be electrically connected to the signal line corresponding thereto.

[0016] According to some embodiments, the bridge pattern may overlap with the second detection electrode and be at a different layer from the second detection electrode.

[0017] According to some embodiments, the second sensing electrodes may be on the same layer as the first sensing patterns.

[0018] According to some embodiments, in a plan view, a shape of each of the first opening portion and the second opening portion may correspond to a shape of a contact hole.

[0019] According to some embodiments, the display panel may include: a base layer including a display area and a non-display area; a transistor on the base layer and overlapping the display area; a light-emitting element overlapping the display area and electrically connected to the transistor; and an encapsulation layer on the light-emitting element, and the adhesive layer may not be between the encapsulation layer and the input sensor.

[0020] According to some embodiments, the bridge pattern may further include a 1-3 conductive layer directly on the other surface of the 1-1 conductive layer, and the first sensing pattern may further include a 2-3 conductive layer directly on the other surface of the 2-1 conductive layer.

[0021] According to some embodiments of the present disclosure, a display device includes: a display panel; and an input sensor directly on the display panel. According to some embodiments, the input sensor may include: a sensor base layer; a first sensor conductive layer on the sensor base layer; a sensor insulating layer on the sensor base layer, covering the first sensor conductive layer; and a second sensor conductive layer on the sensor insulating layer and electrically connected to the first sensor conductive layer through a contact hole passing through the sensor insulating layer. According to some embodiments, the first sensor conductive layer may include a 1-1 conductive layer, a 1-2 conductive layer directly on one surface of the 1-1 conductive layer, and a 1-3 conductive layer directly on another surface of the 1-1 conductive layer, and the second sensor conductive layer may include a 2-1 conductive layer, a 2-2 conductive layer directly on one surface of the 2-1 conductive layer, and a 2-3 conductive layer directly on another surface of the 2-1 conductive layer. According to some embodiments, a first opening portion exposing one surface of the 1-1 conductive layer may be defined in the 1-2 conductive layer, and a second opening portion exposing one surface of the 2-1 conductive layer may be defined in the 2-2 conductive layer. According to some embodiments, one surface of the 1-1 conductive layer overlapping the first opening portion and one surface of the 2-1 conductive layer overlapping the second opening portion may contact each other.

[0022] According to some embodiments, each of the first opening portion and the second opening portion may overlap the contact hole in a plan view.

[0023] According to some embodiments, a resistance value of the 1-1 conductive layer may be smaller than a resistance value of the 1-2 conductive layer, and a resistance value of the 2-1 conductive layer may be smaller than a resistance value of the 2-2 conductive layer.

[0024] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first sensor conductive layer, the first sensor conductive layer being on a sensor base layer and including a 1-1 conductive layer and a 1-2 conductive layer directly on one surface of the 1-1 conductive layer; forming a sensor insulating layer covering the first sensor conductive layer; forming a contact hole in the sensor insulating layer by using a mask; forming a 2-2 conductive layer on the sensor insulating layer; forming a first opening portion overlapping the contact hole in the 1-2 conductive layer, and forming a second opening portion overlapping the contact hole in the 2-2 conductive layer; and forming a 2-1 conductive layer on the 2-2 conductive layer to form a second sensor conductive layer including the 2-1 conductive layer and the 2-2 conductive layer. According to some embodiments, one surface of the 1-1 conductive layer overlapping the first opening portion and the second opening portion and one surface of the 2-1 conductive layer overlapping the first opening portion and the second opening portion may contact each other.

[0025] According to some embodiments, in the step of forming the first opening portion and the second opening portion, the 1-2 conductive layer and the 2-2 conductive layer may be etched using the same mask as that used in the step of forming the contact hole.

[0026] According to some embodiments, in a plan view, a shape of each of the first opening portion and the second opening portion may correspond to a shape of a contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of aspects of some embodiments of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and, together with the specification, are used to explain aspects of some embodiments of the present disclosure. In the accompanying drawings: Figure 1 is an assembled perspective view of an electronic device according to some embodiments of the present disclosure; Figure 2 is an exploded perspective view of an electronic device according to some embodiments of the present disclosure; Figure 3A and Figure 3B Each is along Figure 2 A cross-sectional view of the electronic device taken along line II' in FIG. FIG. 4A to FIG. 4C Each is a cross-sectional view of a display device according to some embodiments of the present disclosure; Figure 5 is a plan view of a display panel according to some embodiments of the present disclosure; Figure 6 is a cross-sectional view of a display panel and an input sensor according to some embodiments of the present disclosure; Figure 7is a plan view of an input sensor according to some embodiments of the present disclosure; Figure 8 is an enlarged plan view of a first detection electrode and a second detection electrode according to some embodiments of the present disclosure; Fig. 9 According to some embodiments of the present disclosure Figure 8 The plan view of the area AA' in ; Fig.10 According to some embodiments of the present disclosure Figure 8 The cross-sectional view corresponding to the line II-II' in; Fig.11 According to some embodiments of the present disclosure Fig.10 A cross-sectional view of the area BB' in FIG. Fig.12 is an enlarged plan view of a first detection electrode and a second detection electrode according to some embodiments of the present disclosure; and FIG. 13A to FIG. 13J Each is a cross-sectional view illustrating a portion of a method for manufacturing a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] It will be understood that in this specification, when an element (or region, layer, portion, etc.) is referred to as being “on”, “connected to” or “coupled to” another element, the element (or region, layer, portion, etc.) can be directly positioned on, directly connected to or directly coupled to the other element, or a third element can be positioned between the element (or region, layer, portion, etc.) and the other element.

[0029] The same reference numerals or symbols always refer to the same elements. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the elements are exaggerated. The term "and / or" includes one or more combinations that can be defined by the relevant elements.

[0030] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, unless the context clearly indicates otherwise, singular forms are also intended to include plural forms.

[0031] In addition, terms such as "below", "under", "on", and "over" are used to explain the relationship of elements shown in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings.

[0032] It will also be understood that when terms such as “including” or “having” are used herein to indicate the presence of stated features, quantities, steps, operations, elements, parts, or combinations thereof, it does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, parts, or combinations thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0034] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0035] Figure 1 is an assembled perspective view of an electronic device ELD according to some embodiments of the present disclosure. Figure 2 is an exploded perspective view of an electronic device ELD according to some embodiments of the present disclosure.

[0036] Reference Figure 1 , the electronic device ELD may be a device that is activated in response to an electrical signal and displays an image. For example, the electronic device ELD may be a large-sized device such as a television or an outdoor billboard, and may also be a small or medium-sized device such as a monitor, a mobile phone, a tablet computer, a navigation device, a game console. However, unless departing from the inventive concept of the present disclosure, the embodiments of the electronic device ELD are examples and are not limited to any one.

[0037] The electronic device ELD may be rigid or flexible. The term "flexible" means a property of being able to bend. For example, the flexible electronic device ELD may include a bendable device, a rollable device, or a foldable device.

[0038] In the following disclosure, the third direction DR3 may be defined as a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The front surface (or top surface) and the rear surface (or bottom surface) of each of the components constituting the electronic device ELD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The spacing distance between the front surface and the rear surface defined in the third direction DR3 may correspond to the thickness of the component.

[0039] The phrase "on a plane" used herein may be defined as being in a state when viewed in the third direction DR3 or in a plan view. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions.

[0040] The electronic device ELD may display an image IM in or toward the third direction DR3 through a display surface IS, and the display surface IS is parallel to a plane defined by the first direction DR1 and the second direction DR2. However, the embodiments of the present disclosure are not limited thereto, and the display surface IS may also include a curved surface bent from at least one side of the plane. The display surface IS on which the image IM is displayed may correspond to the front surface of the electronic device ELD. The image IM may include not only a dynamic image (e.g., a video image or a moving image), but also a still image or a static image. Figure 1 An icon image and a clock are shown as examples of the image IM.

[0041] The electronic device ELD may have a rectangular shape having a short side extending in a first direction DR1 on a plane (or in a plan view) and having a long side extending in a second direction DR2 intersecting the first direction DR1. However, the embodiments of the present disclosure are not limited thereto, and the electronic device ELD may have various shapes on a plane (or in a plan view) such as a circular shape, an elliptical shape, other polygonal shapes, etc.

[0042] The electronic device ELD can detect an external input TC applied from the outside. The external input TC may include various types of inputs such as touch, force, pressure, temperature, and light. In the present disclosure, a touch input applied to the front surface of the electronic device ELD by the hand of the user US is shown as an example of the external input TC. However, this is an example, and the external input TC may include all various types of inputs that may cause a change in the capacitance of the input sensor or otherwise provide an input signal to the electronic device ELD. The area of ​​the electronic device ELD that detects the external input TC is not limited to the front surface of the electronic device ELD, and the electronic device ELD may detect the external input TC of the user US applied to its side surface or rear surface according to the structure of the electronic device ELD.

[0043] The display surface IS of the electronic device ELD may include an image area IA and a frame area BZA. The image area IA may be an area on which an image IM is displayed. A user may see the image IM through the image area IA. According to some embodiments, the image area IA has a rectangular shape with a circular vertex. However, this is shown as an example, and the image area IA may have various shapes.

[0044] The border area BZA may be an area having a color (e.g., a set color or a predetermined color) and shielding from light. The border area BZA may be adjacent to the image area IA. For example, the border area BZA may be positioned outside the image area IA to surround the image area IA. Therefore, the shape of the image area IA may be substantially defined by the border area BZA. However, this is shown as an example. The border area BZA may be adjacent to only one side of the image area IA, the border area BZA may be positioned on the side surface of the electronic device ELD, or may be omitted.

[0045] Reference Figure 1 and Figure 2 , the electronic device ELD may include a window WM, a display device DD, an optical member AF, an electronic module EM, a power supply module PSM and a casing EDC.

[0046] The window WM may be positioned on the display device DD and the optical member AF. The window WM may protect the display device DD from scratches or external impacts applied to the display device DD. The front surface of the window WM may correspond to the display surface IS of the electronic device ELD described above.

[0047] The optical member AF may be positioned on the display device DD. The optical member AF may include various embodiments that relatively reduce the reflectivity of external light. For example, the optical member AF may include a polarizing film including a retarder and / or a polarizer, a plurality of reflective layers that cause reflected light to destructively interfere with each other, or a color filter arranged to correspond to the arrangement and emission color of pixels in the display panel DP.

[0048] The display device DD may generate an image IM output to the outside of the electronic device ELD and detect an external input TC. The display device DD may include a display panel DP and an input sensor ISP.

[0049] The display panel DP may display an image IM in response to the electrical signal. The display panel DP according to some embodiments may be a light-emitting display panel, but is not particularly limited thereto according to embodiments of the present disclosure. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0050] The input sensor ISP may be positioned on the display panel DP. The input sensor ISP may detect an external input TC to provide an input signal including information of the external input TC so that the display panel DP generates an image IM corresponding to the external input TC. The input sensor ISP may be driven by various methods such as a capacitive method, a resistive method, an infrared method, a sonic wave method, or a pressure method, and is not limited to any one. Although the input sensor ISP is described as being driven by a capacitive method, embodiments according to the present disclosure are not limited thereto.

[0051] The display device DD may include an active area AA and a peripheral area NAA adjacent to the active area AA (e.g., in the periphery of the active area AA or outside the coverage area of ​​the active area AA). The active area AA may be an area on which light emitting elements of the display panel DP or detection electrodes of the input sensor ISP are disposed, and may be activated in response to an electrical signal to display an image IM or detect an external input TC. The peripheral area NAA may be an area on which driving circuits, signal lines, pads (or "pads" or "solder pads"), etc. for driving elements positioned on the active area AA are disposed.

[0052] The active area AA may overlap the image area IA of the electronic device ELD, and the peripheral area NAA may overlap the bezel area BZA of the electronic device ELD. The bezel area BZA may prevent components positioned on the peripheral area NAA from being visible from the outside.

[0053] The electronic device ELD may further include a main circuit board MCB, a flexible circuit film FCB, a data driver DIC, a sensor control circuit T-IC, and a main controller 100 .

[0054] The main circuit board MCB may include a driving element. The main circuit board MCB may be electrically connected to each of the display panel DP and the input sensor ISP through a flexible circuit film FCB. The main circuit board MCB may be electrically connected to the electronic module EM through a connector.

[0055] The flexible circuit film FCB may be connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The input sensor ISP may be electrically connected to the display panel DP so that the input sensor ISP is electrically connected to the main circuit board MCB through the flexible circuit film FCB. However, the embodiments according to the present disclosure are not limited thereto. For example, the input sensor ISP may be electrically connected to the main circuit board MCB through an additional flexible circuit film, or the flexible circuit film FCB may be optionally omitted and the main circuit board MCB may be directly connected to the display panel DP.

[0056] Each of the data driver DIC, the sensor control circuit T-IC, and the main controller 100 may be provided in the form of an integrated chip. The data driver DIC may be mounted on the display panel DP, and the sensor control circuit T-IC and the main controller 100 may be mounted on the main circuit board MCB. However, the embodiments according to the present disclosure are not limited thereto. For example, the data driver DIC may be mounted on a flexible circuit film FCB.

[0057] The main controller 100 may control the overall operation of the electronic device ELD. For example, the main controller 100 may control the operation of each of the display panel DP and the input sensor ISP. In addition, the main controller 100 may control the operation of the electronic module EM. The main controller 100 may include at least one microprocessor.

[0058] The data driver DIC may include a driving circuit for driving pixels of the display panel DP. The data driver DIC may receive image data and control signals from the main controller 100. For example, the control signals may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, a data enable signal, and the like.

[0059] The sensor control circuit T-IC may provide an electrical signal for driving the input sensor ISP to the input sensor ISP. The sensor control circuit T-IC may receive a control signal such as a clock signal from the main controller 100.

[0060] The electronic module EM may include various functional modules required to drive the display device DD. For example, the electronic module EM may include a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. The modules of the electronic module EM may be mounted on the main circuit board MCB and electrically connected to the main circuit board MCB through a separate flexible circuit board.

[0061] The power module PSM may be electrically connected to the electronic module EM. The power module PSM may supply power required for the overall operation of the electronic device ELD. For example, the power module PSM may include a typical battery device.

[0062] The window WM and the housing EDC may be combined with each other to provide an appearance of the electronic device ELD. The window WM and the housing EDC may be combined with each other to define an internal space in which components of the electronic device ELD are accommodated. The display device DD, the flexible circuit film FCB, the main circuit board MCB, the electronic module EM, the power supply module PSM, etc. may be accommodated in the internal space. The display panel DP may be accommodated in the housing EDC by bending so that each of the flexible circuit film FCB and the main circuit board MCB faces the rear surface of the display device DD.

[0063] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates made of a combination thereof. The housing EDC may absorb an impact applied from the outside or prevent the introduction of foreign matter / moisture, etc. from the outside, thereby protecting the display device DD housed in the housing EDC.

[0064] Figure 3A and Figure 3B Each is along Figure 2 A cross-sectional view of the electronic device ELD taken along line II' in FIG. Figure 3A and Figure 3B Various embodiments according to stacked shapes of components included in the electronic device ELD are illustrated, and the foregoing description may be applied to the window WM, the display panel DP, and the input sensor ISP.

[0065] Reference Figure 3A and Figure 3B , the window WM may include a base film WBB and a frame pattern WBM. The base film WBB may include an optically transparent insulating material. The base film WBB may include at least one of a glass film and a synthetic resin film. The base film WBB may have a single-layer structure, or a multi-layer structure in which a plurality of films are combined with each other. The window WM may also include a functional layer such as an anti-fingerprint layer, a phase control layer, or a hard coating layer positioned on the base film WBB.

[0066] The frame pattern WBM may be a color layer disposed on one surface of the base film WBB. The frame pattern WBM may include a material having a color. For example, the frame pattern WBM may include a colored organic film. The frame pattern WBM may have a single-layer structure or a multi-layer structure. The frame pattern WBM having a multi-layer structure may include a color layer having a color and a light shielding layer having a non-color (specifically, black). The frame pattern WBM may be formed by deposition, printing, and coating.

[0067] The bezel pattern WBM may be arranged to coincide with the bezel area BZA (see Figure 1 A partial area of ​​the window WM in which the frame pattern WBM is disposed may have a light transmittance lower than a light transmittance of an area in which the frame pattern WBM is not disposed.

[0068] The first adhesive layer AL1 may be positioned between the window WM and the optical member AF. The window WM and the optical member AF may be bonded to each other through the first adhesive layer AL1. However, the embodiments according to the present disclosure are not limited thereto. For example, the first adhesive layer AL1 may be omitted, or the window WM may be positioned directly on the optical member AF.

[0069] Reference Figure 3A, the input sensor ISP may be directly positioned on the display panel DP. In the process of manufacturing the display device DD, the input sensor ISP may be formed on a substrate surface provided by the display panel DP through a continuous process. The input sensor ISP and the display panel DP may be combined into one without a separate adhesive layer.

[0070] Reference Figure 3A , the optical member AF may be positioned directly on the display device DD. For example, the optical member AF may be formed on the top surface of the input sensor ISP by a continuous process. The optical member AF may include a color filter, and the optical member AF may be provided by applying and patterning or printing the components of the color filter onto the substrate surface provided by the input sensor ISP.

[0071] However, the embodiments of the present disclosure are not limited thereto. Figure 3B , the optical member AF may be bonded to the display device DD through the second adhesive layer AL2. For example, the optical member AF may be provided in the form of a film such as a polarizing film, and may be bonded to the display device DD through the second adhesive layer AL2 positioned on the top surface of the input sensor ISP.

[0072] Reference Figure 3B , the display device DD may further include a third adhesive layer AL3 positioned between the input sensor ISP and the display panel DP. The input sensor ISP may be bonded to the display panel DP through the third adhesive layer AL3. For example, the input sensor ISP may be provided as a touch panel manufactured by a separate process from the process of manufacturing the display panel DP, and the input sensor ISP may be bonded to the display panel DP through the third adhesive layer AL3 positioned on the top surface of the display panel DP.

[0073] Each of the first adhesive layer AL1 , the second adhesive layer AL2 , and the third adhesive layer AL3 described above may include a transparent adhesive such as an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure sensitive adhesive (PSA). However, embodiments according to the present disclosure are not limited thereto.

[0074] Figure 3A and Figure 3B The stacking components and stacking order in the electronic device ELD shown in the figure are examples and are not limited thereto. For example, the electronic device ELD may further include a protective layer positioned below the display panel DP, or the optical component AF may be omitted. In addition, the stacking order of the optical component AF and the input sensor ISP may be changed, and the optical component AF may be positioned between the display panel DP and the input sensor ISP.

[0075] FIG. 4A to FIG. 4CEach is a cross-sectional view of a display device DD according to some embodiments of the present disclosure. The foregoing description can be applied to FIG. 4A to FIG. 4C The display panel DP and the input sensor ISP are shown in FIG.

[0076] Reference Figure 4A , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFL.

[0077] The base layer BL may provide a base surface on which the circuit element layer DP-CL is disposed. The base layer BL may be a rigid base, or a flexible base that can be bent, folded, or curled, etc. The base layer BL may include a plastic base, a glass base, a metal base, or an organic / inorganic composite material base, etc. The base layer BL may have a multilayer structure. For example, the base layer BL may include an inorganic layer, a synthetic resin layer, or a composite material layer.

[0078] The circuit element layer DP-CL may be positioned on the base layer BL. The circuit element layer DP-CL may include at least one insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer, the semiconductor pattern, and the conductive pattern of the circuit element layer DP-CL may be formed by coating, deposition, etc., and then patterning the insulating layer, the semiconductor layer, and the conductive layer by performing a photolithography process multiple times. The insulating layer, the semiconductor pattern, and the conductive pattern included in the circuit element layer DP-CL may provide driving elements such as transistors, signal lines, and pads in the circuit element layer DP-CL.

[0079] The display element layer DP-OLED may be positioned on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element. The light emitting element of the display element layer DP-OLED may be electrically connected to a driving element of the circuit element layer DP-CL. Therefore, the light emitting element may generate light to display an image in response to a signal provided by the driving element.

[0080] The encapsulation layer TFL may be positioned on the display element layer DP-OLED to seal the light emitting element. The encapsulation layer TFL may include at least one thin film for relatively improving the optical efficiency of the display element layer DP-OLED or protecting the display element layer DP-OLED.

[0081] Reference Figure 4B , the display panel DP according to some embodiments may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, an encapsulation substrate ES, and a sealant SM.

[0082] The circuit element layer DP-CL may be positioned on the base layer BL, and the display element layer DP-OLED may be positioned on the circuit element layer DP-CL.

[0083] The sealant SM may be positioned between the base layer BL and the encapsulation substrate ES. The sealant SM may bond the base layer BL and the encapsulation substrate ES to each other. The sealant SM may include an organic adhesive layer or glass frit, or the like.

[0084] The encapsulation substrate ES may be positioned on the display element layer DP-OLED. Each of the base layer BL and the encapsulation substrate ES may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc. The encapsulation substrate ES may be spaced apart from the display element layer DP-OLED by a gap (e.g., a set gap or a predetermined gap) in the third direction DR3. According to some embodiments, the display panel DP may further include a filling layer filled in the gap. The filling layer may include a hygroscopic agent or a resin material.

[0085] Reference Figure 4C , the input sensor ISP may include a sensor base layer ISL1, a first sensor conductive layer MTL1, a first sensor insulating layer ISL2, a second sensor conductive layer MTL2, and a second sensor insulating layer ISL3. The sensor base layer ISL1 may be directly positioned on the display panel DP. However, according to the embodiment of the present disclosure, it is not limited thereto, and the sensor base layer ISL1 may be omitted. In this case, the first sensor conductive layer MTL1 may be directly positioned on the display panel DP.

[0086] Each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may have a single-layer structure or a multi-layer structure. The conductive layer having a multi-layer structure may have a structure in which a transparent conductive layer and / or a metal layer are stacked in two or more layers. For example, the conductive layer having a multi-layer structure may have a structure in which a transparent conductive layer and a metal layer are stacked, or a structure in which metal layers including different metals are stacked.

[0087] The transparent conductive layer included in each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (IZTO), PEDOT, metal nanowires, or graphene, etc. The metal layer included in each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. A detailed structure of each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 will be described below.

[0088] In the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 each having a multi-layer structure, a metal having relatively high durability and low reflectivity may be applied to the outer side of the sensor conductive layer, and a metal having high conductivity may be applied to the inner layer of the sensor conductive layer. For example, each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may have a three-layer structure including titanium / aluminum / titanium or a three-layer structure including titanium / copper / titanium. In the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2, the structure including titanium / copper / titanium may have a low resistance characteristic compared to the structure including titanium / aluminum / titanium.

[0089] Each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include a detection electrode TE (see Figure 7 ), and can also include trace TL (see Figure 7 ).

[0090] The first sensor insulating layer ISL2 may be positioned on the first sensor conductive layer MTL1. The second sensor insulating layer ISL3 may be positioned on the second sensor conductive layer MTL2. Each of the first sensor insulating layer ISL2 and the second sensor insulating layer ISL3 may include an inorganic film or an organic film.

[0091] For example, the inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic film may include at least one of acrylic resin, methyl methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, perylene resin, and polyimide resin.

[0092] Figure 5 is a plan view of a display panel DP according to some embodiments of the present disclosure.

[0093] Reference Figure 5 , the display panel DP may include a base layer BL, pixels PX, signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL electrically connected to the pixels PX, a scan driver SDV, a data driver DIC, an emission driver EDV, and a pad PD1.

[0094] The base layer BL may provide a base surface on which elements and lines of the display panel DP are positioned. The base layer BL may include a display area DA and a non-display area NDA. The display area DA may be an area on which pixels PX are displayed and an image is displayed. The non-display area NDA may be an area adjacent to the display area DA (e.g., in the periphery of the display area DA or outside the footprint of the display area DA), on which lines and elements for driving the pixels PX are positioned and on which no image is displayed. The display area DA may be adjacent to the active area AA of the display device DD (see Figure 2 ), the non-display area NDA may correspond to the peripheral area NAA of the display device DD (see Figure 2 )correspond.

[0095] Each of the pixels PX may include a pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit, the pixel driving circuit including a transistor (eg, a switching transistor, a driving transistor, etc.) and a capacitor. Each of the pixels PX may emit light in response to an electrical signal applied to the pixel PX.

[0096] Each of the scan driver SDV, the data driver DIC, and the emission driver EDV may be positioned in the non-display area NDA. However, the embodiments according to the present disclosure are not limited thereto. For example, at least one of the scan driver SDV, the data driver DIC, and the emission driver EDV may be positioned in the display area DA, and thus the surface area of ​​the non-display area NDA may be relatively reduced.

[0097] The signal lines SL1 to SLm, EL1 to ELm, DL1 to DLn, CSL1, CSL2, and PL may include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, first lines CSL1 and second lines CSL2, and a power line PL. Here, m and n are each a natural number of 1 or more. Each of the pixels PX may be electrically connected to a scan line, a data line, and an emission line corresponding to the pixel among the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm, respectively. More types of signal lines may be provided in the display panel DP according to the configuration of the pixel driving circuit of the pixel PX.

[0098] The scan lines SL1 to SLm may extend in the first direction DR1 to be electrically connected to the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 to be electrically connected to the data driver DIC. The emission lines EL1 to ELm may extend in the first direction DR1 to be electrically connected to the emission driver EDV.

[0099] The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be positioned at different layers and connected to each other through a contact hole. However, the embodiments according to the present disclosure are not limited thereto. For example, in the power line PL, the portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be provided in the same layer in an integrated form.

[0100] A portion of the power line PL extending in the first direction DR1 may extend to the display area DA to be electrically connected to the pixel PX, and a portion of the power line PL extending in the second direction DR2 may be positioned in the non-display area NDA to extend toward the pad PD1. The power line PL may receive a power voltage to supply the power voltage to the pixel PX.

[0101] The first line CSL1 may be electrically connected to the scan driver SDV. The second line CSL2 may be electrically connected to the emission driver EDV.

[0102] The pad PD1 may be arranged adjacent to the lower end of the non-display area NDA. The pad PD1 may be arranged closer to the lower end of the display panel DP than the data driver DIC. The pads PD1 may be arranged to be spaced apart from each other in the first direction DR1. Each of the pads PD1 may be a portion to which a circuit board is electrically connected, and the circuit board provides a signal for controlling the operation of each of the scan driver SDV, the data driver DIC, and the emission driver EDV of the display panel DP.

[0103] Each of the pads PD1 may be connected to a corresponding signal line of the signal lines SL1 to SLm, EL1 to ELm, DL1 to DLn, CSL1, CSL2, and PL. For example, the power line PL, the first and second lines CSL1 and CSL2, and the data lines DL1 to DLn may be connected to the corresponding pads PD1, respectively. Each of the data lines DL1 to DLn may be connected to the corresponding pad PD1 through the data driver DIC.

[0104] The scan driver SDV may generate a scan signal in response to a scan control signal. The scan signal may be applied to the pixel PX through the scan lines SL1 to SLm. The data driver DIC may generate a data voltage corresponding to the image signal in response to the data control signal. The data voltage may be applied to the pixel PX through the data lines DL1 to DLn. The emission driver EDV may generate an emission signal in response to an emission control signal. The emission signal may be applied to the pixel PX through the emission lines EL1 to ELm.

[0105] The pixel PX may be provided with a data voltage in response to a scan signal. The pixel PX may display an image by emitting light having a brightness corresponding to the data voltage in response to an emission signal. The emission time of the pixel PX may be controlled by the emission signal. Therefore, the display panel DP may generate an image in the display area DA through the pixel PX.

[0106] Figure 6 is a cross-sectional view of a display panel DP and an input sensor ISP according to some embodiments of the present disclosure. Figure 6 A partial cross section of the display panel DP is shown.

[0107] Reference Figure 6 , the circuit element layer DP-CL, the display element layer DP-OLED, the encapsulation layer TFL and the input sensor ISP may be sequentially arranged on the base layer BL.

[0108] The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The circuit element may include a signal line, a driving circuit of a pixel, etc. The circuit element layer DP-CL may be formed by a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating or deposition, etc., and by a process of patterning the insulating layer, the semiconductor layer, and the conductive layer by photolithography.

[0109] The buffer layer BFL may include a plurality of stacked inorganic layers. The semiconductor pattern may be positioned on the buffer layer BFL. The buffer layer BFL relatively improves the bonding force between the base layer BL and the semiconductor pattern.

[0110] The transistor TR may be positioned on the base layer BL and connected to the display area DA (see Figure 5 ) are stacked. The transistor TR may include a first region A1, second regions S1 and D1, and a gate G1, and the first region A1 and the second regions S1 and D1 are semiconductor patterns. The semiconductor pattern may include polycrystalline silicon. However, the embodiments of the present disclosure are not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 6 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may be further positioned in another region of the pixel PX on a plane (or in a plan view). The semiconductor pattern may be arranged over the pixel PX according to a specific rule.

[0111] The semiconductor pattern may have different electrical characteristics depending on whether the semiconductor pattern is doped. The semiconductor pattern may include a first region A1 having a low doping concentration and conductivity and second regions S1 and D1 each having a relatively high doping concentration and conductivity. One second region S1 may be positioned on one side of the first region A1, and another second region D1 may be positioned on the other side of the first region A1. The second regions S1 and D1 may be doped with an n-type dopant or a p-type dopant. The p-type transistor includes a doped region doped with a p-type dopant. The first region A1 may be a non-doped region, or may be doped to have a lower concentration than each of the second regions S1 and D1.

[0112] Each of the second regions S1 and D1 may be substantially used as an electrode or a signal line. One second region S1 may correspond to a source of a transistor, and the other second region D1 may be a drain of the transistor. Figure 6 A portion of a connection signal line SCL provided from the semiconductor pattern is shown. Although not additionally shown, the connection signal line SCL may be connected to the drain of the transistor TR on a plane (or in a plan view).

[0113] The first insulating layer 10 is positioned on the buffer layer BFL. The first insulating layer 10 is commonly disposed on the plurality of pixels PX (see Figure 5 ) and covers the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In addition to the first insulating layer 10, the insulating layer of the circuit element layer DP-CL to be described below may be an inorganic layer and / or an organic layer and have a single-layer structure or a multi-layer structure.

[0114] The gate G1 is positioned on the first insulating layer 10. The gate G1 may include a metal layer having a multi-layer structure. The gate G1 overlaps the first area A1. The gate G1 may be used as a mask in a process of doping a semiconductor pattern.

[0115] The second insulating layer 20 covering the gate G1 is positioned on the first insulating layer 10. The second insulating layer 20 is commonly located in the pixel PX (see Figure 5 ). The upper electrode UE may be positioned on the second insulating layer 20. The upper electrode UE may overlap with the gate G1. The upper electrode UE may include a metal layer having a multi-layer structure. According to some embodiments of the present disclosure, the upper electrode UE may be omitted.

[0116] The third insulating layer 30 covering the upper electrode UE is positioned on the second insulating layer 20. The first connection electrode CNE1 may be positioned on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30.

[0117] The fourth insulating layer 40 is positioned on the third insulating layer 30. The fifth insulating layer 50 is positioned on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be positioned on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0118] The sixth insulating layer 60 covering the second connection electrode CNE2 is positioned on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. A light emitting element OLED as a display element is positioned on the sixth insulating layer 60. The light emitting element OLED may be aligned with the display area DA (see Figure 5 ) are stacked and electrically connected to the transistor TR.

[0119] The first electrode AE ​​(or anode) is positioned on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 passing through the sixth insulating layer 60. An opening portion OP is defined in the pixel defining film PDL. The opening portion OP of the pixel defining film PDL exposes at least a portion of the first electrode AE. The pixel defining film PDL may be an organic layer.

[0120] like Figure 6 As shown in , the display area DA may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. The non-emission area NPXA may surround the emission area PXA. According to some embodiments, the emission area PXA is defined to correspond to a partial area of ​​the first electrode AE ​​exposed by the opening portion OP.

[0121] The hole control layer HCL may be commonly positioned in the emission region PXA and the non-emission region NPXA. The hole control layer HCL may include a hole transport layer and further include a hole injection layer. The emission layer EML is positioned on the hole control layer HCL. The emission layer EML may be positioned in a region corresponding to the opening portion OP. That is, the emission layer EML may be divided and disposed in the pixel PX (see Figure 5 ) in each of them.

[0122] The electron control layer ECL is positioned on the emission layer EML. The electron control layer ECL may include an electron transport layer and further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly disposed in a plurality of pixels by using an open mask. The second electrode CE (or cathode) is positioned on the electron control layer ECL. The second electrode CE is disposed in an integral form and is commonly disposed in a plurality of pixels PX (see Figure 5 ). Figure 6 As shown in FIG. 4 , the encapsulation layer TFL is positioned on the second electrode CE.

[0123] The cover layer CPL may be positioned on the second electrode CE and in contact with the second electrode CE. The encapsulation layer TFL may be positioned on the cover layer CPL and include a plurality of thin films.

[0124] The encapsulation layer TFL may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2. The first and second inorganic layers IOL1 and IOL2 may protect the display element layer DP-OLED from moisture / oxygen, and the organic layer OL may protect the display element layer DP-OLED from foreign matter such as dust particles.

[0125] The input sensor ISP can be located on the display panel DP (see Figure 5 ). The input sensor ISP may be directly positioned on the display panel DP. The input sensor ISP may be directly positioned on the encapsulation layer TFL. The adhesive layer may not be positioned between the input sensor ISP and the encapsulation layer TFL. The input sensor ISP may be directly formed on the top surface of the encapsulation layer TFL through a continuous process.

[0126] The input sensor ISP may include a sensor base layer ISL1, a first sensor insulating layer ISL2, a second sensor insulating layer ISL3, a first sensor conductive layer MTL1, and a second sensor conductive layer MTL2. The sensor base layer ISL1 may be directly positioned on the packaging layer TFL. If necessary, the sensor base layer ISL1 may be omitted.

[0127] The first sensor conductive layer MTL1 may be positioned on the sensor base layer ISL1 and overlap the non-emission area NPXA. The first sensor insulating layer ISL2 may be positioned on the sensor base layer ISL1. The first sensor insulating layer ISL2 may cover the first sensor conductive layer MTL1. The second sensor conductive layer MTL2 may be positioned on the first sensor insulating layer ISL2 and overlap the non-emission area NPXA. The second sensor conductive layer MTL2 may be connected to the first sensor conductive layer MTL1 through a contact hole passing through the first sensor insulating layer ISL2. The second sensor insulating layer ISL3 may be positioned on the first sensor insulating layer ISL2. The second sensor insulating layer ISL3 may cover the second sensor conductive layer MTL2.

[0128] Figure 7 is a plan view of an input sensor ISP according to some embodiments of the present disclosure.

[0129] Reference Figure 7 , the input sensor ISP may include a detection area AA-S and a non-detection area NAA-S adjacent to the detection area AA-S. The detection area AA-S may be adjacent to the display device DD (see Figure 2 ) effective area AA (see Figure 2 ) corresponds. The detection area AA-S may be a detection electrode TE on which the input sensor ISP is arranged to detect the external input TC (see Figure 1 The non-detection area NAA-S can be connected to the display device DD (see Figure 2 ) of the peripheral region NAA (see Figure 2 The non-detection area NAA-S may be an area on which lines or elements for driving the detection electrodes TE positioned in the detection area AA-S are disposed.

[0130] The input sensor ISP may include a detection electrode TE positioned on a sensor base layer ISL1 , a trace TL (or a signal line), and a sensing controller TC.

[0131] The sensing electrodes TE may include first and second sensing electrodes TE1 and TE2 crossing each other on a plane (or in a plan view) and electrically insulated from each other. The input sensor ISP may obtain information of external input through a capacitance change between the first and second sensing electrodes TE1 and TE2.

[0132] Each of the first detection electrodes TE1 may extend in the first direction DR1, and the first detection electrodes TE1 may be arranged in the second direction DR2. The first detection electrodes TE1 may be provided in a plurality of rows arranged in the second direction DR2. Figure 7Ten first sensing electrodes TE1 are shown as an example, but the number of first sensing electrodes TE1 included in the input sensor ISP is not limited thereto.

[0133] Each of the second detection electrodes TE2 may extend in the second direction DR2, and the second detection electrodes TE2 may be arranged in the first direction DR1. The second detection electrodes TE2 may be provided in a plurality of columns arranged in the first direction DR1. Figure 7 Eight second sensing electrodes TE2 are shown as an example, but the number of second sensing electrodes TE2 included in the input sensor ISP is not limited thereto.

[0134] Each of the first sensing electrodes TE1 may include a first sensing pattern SP1 and a first connection pattern BP1 (or a bridge pattern). The first sensing patterns SP1 may be arranged in the first direction DR1. Each of the first connection patterns BP1 may electrically connect the first sensing patterns SP1 adjacent thereto in the first direction DR1 to each other. The first connection pattern BP1 may be positioned at a different layer from the first sensing pattern SP1 and connected to the first sensing pattern SP1 corresponding to the first connection pattern BP1 through a contact hole. The first sensing patterns SP1 spaced apart from each other in the first direction DR1 may be electrically connected to each other through the first connection pattern BP1. The first connection pattern BP1 positioned at a different layer from the first sensing pattern SP1 to electrically connect the first sensing patterns SP1 to each other may be defined as a bridge pattern.

[0135] Each of the second sensing electrodes TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. The second sensing patterns SP2 may be arranged in the second direction DR2. Each of the second connection patterns BP2 may electrically connect the second sensing patterns SP2 adjacent thereto in the second direction DR2 to each other. The second connection pattern BP2 may be positioned at the same layer as the second sensing pattern SP2 and extend from the second sensing pattern SP2 to have an integral shape on a plane (or in a plan view). The second sensing pattern SP2 and the second connection pattern BP2 may be patterns formed by patterning the same conductive layer through the same process. However, the embodiments according to the present disclosure are not limited thereto, as long as each of the second connection patterns BP2 electrically connects the second sensing patterns SP2 adjacent thereto in the second direction DR2 to each other.

[0136] According to some embodiments, the first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern BP2 may be positioned at the same layer. The first connection pattern BP1 may be positioned at a different layer from the first sensing pattern SP1. For example, the first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern BP2 may be included in the second sensor conductive layer MTL2 (see Figure 4C), the first connection pattern BP1 may include in the first sensor conductive layer MTL1 (see Figure 4C However, the first sensing pattern SP1, the second sensing pattern SP2 and the second connection pattern BP2 may be included in the first sensor conductive layer MTL1 (see Figure 4C ), the first connection pattern BP1 may include in the second sensor conductive layer MTL2 (see Figure 4C )middle.

[0137] Figure 7 An aspect of an embodiment in which the first connection pattern BP1 is positioned at a different layer from the first sensing pattern SP1 , the second sensing pattern SP2 , and the second connection pattern BP2 is shown. However, embodiments according to the present disclosure are not limited thereto.

[0138] For example, the second connection pattern BP2 may be positioned at a different layer from the second sensing pattern SP2, and connected to the second sensing pattern SP2 corresponding to the second connection pattern BP2 through a contact hole. The first connection pattern BP1 may be positioned at the same layer as the first sensing pattern SP1, and may extend from the first sensing pattern SP1 to have an integral shape on a plane (or in a plan view). Here, the second connection pattern BP2 may be positioned at a different layer from each of the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2. Optionally, according to some embodiments, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be positioned at the same layer, and the second connection pattern BP2 may be positioned at a different layer from the second sensing pattern SP2.

[0139] The trace TL may be positioned in the non-detection area NAA-S. The trace TL may include a first trace TL1 and a second trace TL2. The first traces TL1 may be connected to the first detection electrodes TE1, respectively. Each of the first traces TL1 may be connected to the first detection electrodes TE1, which are arranged in a row corresponding to the first trace TL1, among the first detection electrodes TE1 arranged in a plurality of rows. The second traces TL2 may be connected to the second detection electrodes TE2, respectively. Each of the second traces TL2 may be connected to the second detection electrodes TE2, which are arranged in a column corresponding to the second trace TL2, among the second detection electrodes TE2 arranged in a plurality of columns.

[0140] The second traces TL2 may be respectively connected to lower ends of the second detection electrodes TE2 adjacent to the sensing controller TC. Each of the second traces TL2 may extend from a lower end of the second detection electrode TE2 corresponding thereto in the non-detection area NAA-S to be connected to the sensing controller TC.

[0141] Each of the first traces TL1 may be connected to the left end or the right end of each of the first detection electrodes TE1. For example, each of the first traces TL1 connected to the first detection electrodes TE1 disposed in odd rows may be connected to the left end of the first detection electrodes TE1 corresponding to the first trace TL1 among the first detection electrodes TE1 disposed in odd rows. Each of the first traces TL1 connected to the first detection electrodes TE1 disposed in even rows may be connected to the right end of the first detection electrodes TE1 corresponding to the first trace TL1 among the first detection electrodes TE1 disposed in even rows. Each of the first traces TL1 may extend from the left end or the right end of the first detection electrode TE1 corresponding to the first trace TL1 in the non-detection area NAA-S in the second direction DR2, so that the first trace TL1 is connected to the sensing controller TC.

[0142] The first trace TL1 may be positioned at a different layer from at least some of the second sensing patterns SP2. For example, the first trace TL1 may be positioned at a different layer from the second sensing patterns SP2. According to some embodiments, the first trace TL1 may include a first sensor conductive layer MTL1 (see Figure 4C ), the second sensing pattern SP2 may include in the second sensor conductive layer MTL2 (see Figure 4C However, the embodiments according to the present disclosure are not necessarily limited thereto.

[0143] The sensing controller TC may be positioned in the non-detection area NAA-S. The sensing controller TC may be arranged adjacent to the lower end of the sensor base layer ISL1. The sensing controller TC may be electrically connected to the trace TL. The sensing controller TC may apply a signal to the detection electrode TE through the trace TL, or receive a signal provided from the detection electrode TE. The sensing controller TC may include a controller, and may generate a coordinate value provided with information of an external input based on the signal received from the detection electrode TE. However, embodiments according to the present disclosure are not limited thereto. For example, the sensing controller TC may include sensing pads arranged to be spaced apart from each other and respectively connected to the trace TL, and the sensing pads may be portions of a circuit board electrically connected to provide a drive signal.

[0144] A driving signal for driving the first detection electrode TE1 and the second detection electrode TE2 may be applied from the sensing controller TC to the first detection electrode TE1 and the second detection electrode TE2 through the second trace TL2. A signal including information detected in the first detection electrode TE1 and the second detection electrode TE2 may be output through the first trace TL1. However, embodiments according to the present disclosure are not necessarily limited thereto.

[0145] Figure 8is an enlarged plan view of the first detection electrode TE1 and the second detection electrode TE2 according to some embodiments of the present disclosure.

[0146] Reference Figure 8 , each of the first sensing patterns SP1 may be a mesh pattern in which a first mesh opening portion M-OP1 is defined. The first mesh opening portion M-OP1 may be aligned with the emission area PXA (see FIG. 1 ) in plane (or in plan view). Figure 6 ). The first sensing pattern SP1 may overlap the non-emission area NPXA (see Figure 6 ). Each of the second sensing patterns SP2 may be a mesh pattern in which a second mesh opening portion M-OP2 is defined. The second mesh opening portion M-OP2 may overlap the emission area PXA (see FIG. 1 ) on a plane (or in a plan view). Figure 6 ). The second sensing pattern SP2 may overlap with the non-emission area NPXA (see Figure 6 ) overlap.

[0147] Each of the first connection patterns BP1 may connect the first sensing patterns SP1 adjacent thereto to each other. The first connection pattern BP1 may be connected to the first sensing pattern SP1 through a contact hole CNT. The first connection pattern BP1 may overlap the second sensing pattern SP2 on a plane (or in a plan view). The first connection pattern BP1 may be positioned at a different layer from the first sensing pattern SP1. The second connection pattern BP2 may be positioned at the same layer as the second sensing pattern SP2.

[0148] Figure 8 The case where the first connection pattern BP1 is positioned at a different layer from the first sensing pattern SP1 and is connected to the first sensing pattern SP1 through the contact hole CNT and the second connection pattern BP2 is positioned at the same layer as the second sensing pattern SP2 is shown. However, the embodiments according to the present disclosure are not limited thereto. For example, the second connection pattern BP2 may be positioned at a different layer from the second sensing pattern SP2 and is connected to the second sensing pattern SP2 through the contact hole, and the first connection pattern BP1 may be positioned at the same layer as the first sensing pattern SP1.

[0149] Hereinafter, the same structure as the first connection pattern BP1 and the first sensing pattern SP1 connected by the contact hole CNT described herein may be applied to the second connection pattern BP2 and the second sensing pattern SP2. Figure 8 A description is provided of the structure shown in FIG.

[0150] Fig. 9 According to some embodiments of the present disclosure Figure 8In the present disclosure, the fourth direction DR4 may be a direction crossing each of the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The fifth direction DR5 may be a direction crossing each of the first direction DR1, the second direction DR2, and the fourth direction DR4 on a plane defined by the first direction DR1 and the second direction DR2.

[0151] Reference Fig. 9 , the emission region PXA may include a first emission region PXA1, a second emission region PXA2, and a third emission region PXA3. Each of the first emission region PXA1, the second emission region PXA2, and the third emission region PXA3 may be provided in plural. The first emission region PXA1 and the second emission region PXA2 may be alternately arranged in each of the first direction DR1 and the second direction DR2. The first emission region PXA1 and the third emission region PXA3 extending in the fifth direction DR5 may be alternately arranged in the fourth direction DR4, and the first emission region PXA1 and the third emission region PXA3 extending in the fourth direction DR4 may be alternately arranged in the fifth direction DR5. The second emission region PXA2 and the third emission region PXA3 extending in the fourth direction DR4 may be alternately arranged in the fifth direction DR5, and the second emission region PXA2 and the third emission region PXA3 extending in the fifth direction DR5 may be alternately arranged in the fourth direction DR4.

[0152] The first emission region PXA1, the second emission region PXA2, and the third emission region PXA3 may emit light having different colors from each other. The surface area of ​​the first emission region PXA1 on a plane (or in a plan view) may be larger than the surface area of ​​the second emission region PXA2 on a plane (or in a plan view). The surface area of ​​the second emission region PXA2 on a plane (or in a plan view) may be larger than the surface area of ​​the third emission region PXA3 on a plane (or in a plan view). The first emission region PXA1 may emit light having a first color, the second emission region PXA2 may emit light having a second color, and the third emission region PXA3 may emit light having a third color. Here, the light having the first color may be blue light, the light having the second color may be red light, and the light having the third color may be green light. However, here, the colors of the light having the first color to the third color may be changed.

[0153] The launch area PXA is not limited to Fig. 9 The arrangement of the emission regions PXA shown in FIG. 1 and can be arranged differently. For example, the emission regions PXA1, PXA2, and PXA3 may have a pentile (PENTILE ®) shape, or diamond (DiamondPixel TM ) Arrange the shapes.

[0154] The first sensing pattern SP1 may include a mesh pattern MP. The mesh pattern MP may include a first line portion P1 and a second line portion P2. The first line portion P1 and the second line portion P2 may be connected to each other to have an integral shape and define a first mesh opening portion M-OP1 overlapping the first emission area PXA1, the second emission area PXA2, and the third emission area PXA3, respectively. The first line portion P1 and the second line portion P2 may be portions provided by patterning a conductive layer provided in an integral form using the first mesh opening portion M-OP1. The first line portion P1 and the second line portion P2 may be positioned in the non-emission area NPXA to have a shape surrounding the first emission area PXA1, the second emission area PXA2, and the third emission area PXA3.

[0155] The first line portion P1 may correspond to a portion of the mesh pattern MP extending in the fourth direction DR4. The second line portion P2 may correspond to a portion of the mesh pattern MP extending in the fifth direction DR5. The first line portion P1 and the second line portion P2 may be arranged on a plane (or in a plan view) to cross each other.

[0156] The first line portion P1 and the second line portion P2 may intersect each other at the intersection CP on a plane (or in a plan view). The first width TH-CP1 of the intersection CP in the fourth direction DR4 may be greater than the line width TH2 of the second line portion P2 in the fourth direction DR4. The second width TH-CP2 of the intersection CP in the fifth direction DR5 may be greater than the line width TH1 of the first line portion P1 in the fifth direction DR5. The contact hole CNT may be positioned in the intersection CP on a plane (or in a plan view). Since the contact hole CNT is positioned in the intersection CP having a relatively large surface area compared to the first line portion P1 and the second line portion P2, the contact hole CNT may be set to be as large as possible in surface area. In addition, since the contact hole CNT is positioned in the intersection CP having a large surface area, damage to another layer may not be caused even when the mask is misaligned during the formation of the contact hole CNT.

[0157] The shape of each of the first opening portion OP-1 and the second opening portion OP-2 on a plane (or in a plan view) may correspond to the shape of the contact hole CNT on a plane (or in a plan view). Fig.11 The first opening portion OP-1 and the second opening portion OP-2 are described in more detail.

[0158] The shape of the first mesh opening portion M-OP1 on a plane (or in a plan view) may correspond to the shape of each of the first emission region PXA1, the second emission region PXA2, and the third emission region PXA3 on a plane (or in a plan view). The shape of the first mesh opening portion M-OP1 on a plane (or in a plan view) may be larger than the corresponding shape of each of the first emission region PXA1, the second emission region PXA2, and the third emission region PXA3 on a plane (or in a plan view). One side surface of the first mesh opening portion M-OP1 may be spaced apart from one side surface of the emission region PXA corresponding to the first mesh opening portion M-OP1 on a plane (or in a plan view) by a gap (e.g., a set or predetermined gap).

[0159] Fig.10 According to some embodiments of the present disclosure Figure 8 The cross-sectional view corresponding to the line II-II'.

[0160] Reference Fig.10 , the first connection pattern BP1 may be positioned on the sensor base layer ISL1. The first sensing pattern SP1 and the second sensing pattern SP2 may be positioned on the first sensor insulating layer ISL2. The second sensor insulating layer ISL3 may cover the first sensing pattern SP1 and the second sensing pattern SP2.

[0161] The first sensing pattern SP1 may be electrically connected to the first connection pattern BP1 through a contact hole CNT penetrating the first sensor insulating layer ISL2. A portion of the first connection pattern BP1 may overlap the second sensing pattern SP2 on a plane (or in a plan view). The first connection pattern BP1 positioned on the sensor base layer ISL1 may be a first sensor conductive layer MTL1 (see Figure 6 ). The first sensing patterns SP1 and the second sensing patterns SP2 positioned on the first sensor insulating layer ISL2 may be the second sensor conductive layer MTL2 (see Figure 6 ).However, Fig.10 The layer structure shown in FIG. 1 is an example, and the layer structure is not limited thereto. For example, the first connection pattern BP1 may be positioned on the first sensor insulating layer ISL2, and the first sensing pattern SP1 and the second sensing pattern SP2 may be positioned on the sensor base layer ISL1. Here, the first connection pattern BP1 may be the second sensor conductive layer MTL2 (see FIG. 1 ). Figure 6 ), the first sensing pattern SP1 and the second sensing pattern SP2 may be the first sensor conductive layer MTL1 (see Figure 6 ).

[0162] Fig.11 According to some embodiments of the present disclosure Fig.10 A cross-sectional view of area BB' in FIG. Fig.11 The layer structure and connection structure of the first sensing patterns SP1 and the first connection patterns BP1 are shown.

[0163] Reference Fig.11 , the first connection pattern BP1 may include a 1-1 conductive layer CL1-1, a 1-2 conductive layer CL1-2, and a 1-3 conductive layer CL1-3. The 1-2 conductive layer CL1-2 may be directly positioned on one surface of the 1-1 conductive layer CL1-1, and the 1-3 conductive layer CL1-3 may be directly positioned on the other surface of the 1-1 conductive layer CL1-1. The 1-2 conductive layer CL1-2 may be directly positioned on the top surface of the 1-1 conductive layer CL1-1, and the 1-3 conductive layer CL1-3 may be directly positioned on the bottom surface of the 1-1 conductive layer CL1-1. The first connection pattern BP1 may have a three-layer structure in which the 1-3 conductive layer CL1-3, the 1-1 conductive layer CL1-1, and the 1-2 conductive layer CL1-2 are sequentially stacked.

[0164] The first sensing pattern SP1 may include a 2-1 conductive layer CL2-1, a 2-2 conductive layer CL2-2, and a 2-3 conductive layer CL2-3. The 2-2 conductive layer CL2-2 may be directly positioned on one surface of the 2-1 conductive layer CL2-1, and the 2-3 conductive layer CL2-3 may be directly positioned on the other surface of the 2-1 conductive layer CL2-1. The 2-2 conductive layer CL2-2 may be directly positioned on the bottom surface of the 2-1 conductive layer CL2-1, and the 2-3 conductive layer CL2-3 may be directly positioned on the top surface of the 2-1 conductive layer CL2-1. The first sensing pattern SP1 may have a three-layer structure in which the 2-2 conductive layer CL2-2, the 2-1 conductive layer CL2-1, and the 2-3 conductive layer CL2-3 are sequentially stacked.

[0165] The contact hole CNT may be defined in the inner surface of the first sensor insulating layer ISL2. The first opening portion OP-1 exposing the top surface of the 1-1 conductive layer CL1-1 may be defined in the 1-2 conductive layer CL1-2. The second opening portion OP-2 exposing the bottom surface of the 2-1 conductive layer CL2-1 may be defined in the 2-2 conductive layer CL2-2. The contact hole CNT and the first opening portion OP-1 and the second opening portion OP-2 may be provided using the same mask. The first opening portion OP-1 and the second opening portion OP-2 may be formed simultaneously by the same process. This will be described later with reference to FIG. 13A to FIG. 13J to describe.

[0166] Each of the first opening portion OP-1 and the second opening portion OP-2 may overlap on the contact hole CNT on a plane (or in a plan view). The shape of the first opening portion OP-1 on a plane (or in a plan view) may correspond to the shape of the second opening portion OP-2 on a plane (or in a plan view). The shape of each of the first opening portion OP-1 and the second opening portion OP-2 on a plane (or in a plan view) may correspond to the shape of the contact hole CNT on a plane (or in a plan view). This is because the contact hole CNT and the first opening portion OP-1 and the second opening portion OP-2 are provided using the same mask.

[0167] A surface of the 1-1 conductive layer CL1-1 overlapping with the first opening portion OP-1 and the second opening portion OP-2 and a surface of the 2-1 conductive layer CL2-1 overlapping with the first opening portion OP-1 and the second opening portion OP-2 may be in direct contact with each other. The bottom surface of the 2-1 conductive layer CL2-1 exposed by the second opening portion OP-2 may be in direct contact with the top surface of the 1-1 conductive layer CL1-1 exposed by the first opening portion OP-1. Here, the resistance value of the 1-1 conductive layer CL1-1 may be smaller than the resistance value of the 1-2 conductive layer CL1-2. The resistance value of the 2-1 conductive layer CL2-1 may be smaller than the resistance value of the 2-2 conductive layer CL2-2. For example, each of the 1-1 conductive layer CL1-1 and the 2-1 conductive layer CL2-1 may include aluminum or copper. The 1-2nd conductive layer CL1-2, the 1-3rd conductive layer CL1-3, the 2-2nd conductive layer CL2-2, and the 2-3rd conductive layer CL2-3 may include titanium.

[0168] When the first sensing pattern SP1 is connected to the first connection pattern BP1, the 1-1 conductive layer CL1-1 and the 2-1 conductive layer CL2-1, both having low resistance, can directly contact each other without passing through the 1-2 conductive layer CL1-2 or the 2-2 conductive layer CL2-2, both having high resistance. Therefore, when the first sensing pattern SP1 and the first connection pattern BP1 are connected through the contact hole CNT, the resistance can be greatly reduced. Therefore, the input sensor ISP (see Figure 7 ) can relatively reduce signal delay and relatively improve sensing performance.

[0169] Fig.12 is an enlarged plan view of the first detection electrode TE1 and the second detection electrode TE2 according to some embodiments of the present disclosure. Figure 8 The same / similar components as those described are denoted by the same / similar reference numerals, and description thereof will be simplified or omitted.

[0170] Reference Fig.12The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. The first sensing pattern SP1 and the first connection pattern BP1 may be positioned at the same layer and provided in an integrated form.

[0171] The second sensing electrode TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. The second connection pattern BP2 may be positioned at a different layer from the second sensing pattern SP2. The second connection pattern BP2 may be electrically connected to the second sensing pattern SP2 through a contact hole CNT. The second connection pattern BP2 may be positioned at a different layer from the first sensing pattern SP1, and some of the second connection patterns BP2 may overlap with the first sensing pattern SP1 on a plane (or in a plan view).

[0172] FIG. 13A to FIG. 13J Each is a cross-sectional view illustrating a portion of a method for manufacturing a display device according to some embodiments of the present disclosure. Hereinafter, components identical / similar to those described above will be omitted.

[0173] Reference Fig.13A and Fig. 13B , a 1-3 conductive layer CL1-3, a 1-1 conductive layer CL1-1, and a 1-2 conductive layer CL1-2 may be sequentially formed on the sensor base layer ISL1.

[0174] Reference Fig. 13C , the 1-1 conductive layer CL1-1 to the 1-3 conductive layer CL1-3 may be etched to form a first connection pattern BP1 (or a first sensor conductive layer) including the 1-1 conductive layer CL1-1 to the 1-3 conductive layer CL1-3. Fig.13D , a first sensor insulating layer ISL2 covering the first connection patterns BP1 may be formed.

[0175] Reference Fig.13E , a contact hole CNT exposing a portion of the 1-2 th conductive layer CL1-2 may be formed in the first sensor insulating layer ISL2. Here, a mask MK in which a mask opening portion MK-OP corresponding to the contact hole CNT is defined may be used.

[0176] Reference Fig.13F , a 2-2 th conductive layer CL2 - 2 may be formed on the exposed top surfaces of the first sensor insulating layer ISL2 and the 1-2 th conductive layer CL1 - 2 .

[0177] Reference Figure 13G , a first opening portion OP-1 overlapping with the contact hole CNT may be formed in the 1-2 conductive layer CL1-2. A second opening portion OP-2 overlapping with the contact hole CNT may be formed in the 2-2 conductive layer CL2-2. Here, the same reference may be used. Fig.13E The mask MK described above is used to form the first opening portion OP-1 and the second opening portion OP-2, and the mask opening portion MK-OP is defined in the mask MK. Fig.13E and 13G The same mask is used in the etching process, so the mask cost can be relatively reduced.

[0178] Reference Fig.13H and Fig.13I , a 2-1 conductive layer CL2-1 may be formed on the exposed top surfaces of the 2-2 conductive layer CL2-2 and the 1-1 conductive layer CL1-1. A top surface of the 1-1 conductive layer CL1-1 overlapping with the first opening portion OP-1 and the second opening portion OP-2 and a bottom surface of the 2-1 conductive layer CL2-1 overlapping with the first opening portion OP-1 and the second opening portion OP-2 may contact each other. A 2-3 conductive layer CL2-3 directly positioned on the 2-1 conductive layer CL2-1 may be formed. Thereafter, the 2-1 conductive layer CL2-1 and the 2-3 conductive layer CL2-3 may be etched to form a first sensing pattern SP1 (or a second sensor conductive layer).

[0179] Reference Fig.13J , a second sensor insulating layer ISL3 covering the first sensing pattern SP1 may be formed to form the input sensor ISP.

[0180] In the display device according to some embodiments of the present disclosure, when the detection pattern is connected by the bridge, the conductive layer with high resistance can be arranged to contact the conductive layer with low resistance. Therefore, the total resistance of the input sensor can be relatively reduced, and the sensing performance of the input sensor can be relatively improved.

[0181] In the method for manufacturing a display device according to some embodiments of the present disclosure, when forming an opening portion in a conductive layer, the same mask as that which has been previously used to form a contact hole may be used to simplify the manufacturing process.

[0182] Although the embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments, but can be variously changed and modified by those of ordinary skill in the art within the spirit and scope of the present invention. Therefore, the technical scope of the inventive concept is not limited to the contents described in the specific embodiments of the specification, but should be determined by the attached claims and their equivalents.

Claims

1. A display device, comprising: A display panel comprising an emission area and a non-emission area adjacent to the emission area; as well as The input sensor includes a detection area and a non-detection area adjacent to the detection area, and on the display panel, The input sensor includes a first detection electrode overlapping the detection area, the first detection electrode including: a first detection pattern; and a bridge pattern, which is in a different layer from the first detection pattern and is electrically connected to the first detection pattern through a contact hole passing through the sensor insulation layer, wherein the bridge pattern includes a 1-1 conductive layer and a 1-2 conductive layer directly on one surface of the 1-1 conductive layer, and The first detection pattern includes a 2-1 conductive layer and a 2-2 conductive layer directly on one surface of the 2-1 conductive layer, wherein a first opening portion exposing the one surface of the 1-1 conductive layer is defined in the 1-2 conductive layer, and a second opening portion exposing the one surface of the 2-1 conductive layer is defined in the 2-2 conductive layer, The one surface of the 1-1 conductive layer overlapping the first opening portion and the one surface of the 2-1 conductive layer overlapping the second opening portion are in contact with each other.

2. The display device according to claim 1, wherein: Each of the first opening portion and the second opening portion overlaps the contact hole in a plan view.

3. The display device according to claim 1, wherein: A shape of the first opening portion in a plane corresponds to a shape of the second opening portion in a plan view.

4. The display device according to claim 1, wherein: The first sensing pattern includes a grid pattern in which a grid opening portion overlapping the emission area is defined.

5. The display device according to claim 4, wherein: The grid pattern comprises: a first line portion extending in a first direction; and a second line portion extending in a second direction intersecting the first direction, wherein the contact hole is in a point where the first line portion and the second line portion cross each other.

6. The display device according to claim 1, wherein: The resistance value of the 1-1 conductive layer is smaller than the resistance value of the 1-2 conductive layer, and The resistance value of the 2-1 conductive layer is smaller than the resistance value of the 2-2 conductive layer.

7. The display device according to claim 1, wherein: Each of the 1-1 conductive layer and the 2-1 conductive layer includes aluminum, and Each of the 1-2 conductive layer and the 2-2 conductive layer includes titanium.

8. The display device according to claim 1, wherein: The input sensor further includes a second detection electrode insulated from the first detection electrode and crossing the first detection electrode. Wherein, the second detection electrodes are formed as a whole on the same layer.

9. The display device according to claim 8, wherein: The input sensor further includes a signal line in the non-detection area, Wherein, each of one end of the first detection electrode and one end of the second detection electrode is electrically connected to the signal line corresponding thereto.

10. The display device according to claim 8, wherein: The bridge pattern overlaps the second detection electrode and is on a different layer from the second detection electrode.

11. The display device according to claim 8, wherein: The second detection electrodes are on the same layer as the first detection patterns.

12. The display device according to claim 1, wherein: In a plan view, a shape of each of the first opening portion and the second opening portion corresponds to a shape of the contact hole.

13. The display device according to claim 1, wherein: The display panel comprises: A substrate layer including a display area and a non-display area; A transistor, on the base layer and overlapping the display area; a light emitting element overlapping the display area and electrically connected to the transistor; and An encapsulation layer, on the light emitting element, Wherein, the adhesive layer is not between the packaging layer and the input sensor.

14. The display device according to claim 1, wherein: The bridge pattern further includes a 1-3 conductive layer directly on the other surface of the 1-1 conductive layer, and The first sensing pattern further includes a 2-3 conductive layer directly on the other surface of the 2-1 conductive layer.

15. A display device, comprising: Display panel; as well as Input sensor, directly on the display panel, The input sensor comprises: a sensor base layer; a first sensor conductive layer on the sensor base layer; a sensor insulating layer on the sensor base layer and covering the first sensor conductive layer; and a second sensor conductive layer on the sensor insulating layer and electrically connected to the first sensor conductive layer through a contact hole passing through the sensor insulating layer. wherein the first sensor conductive layer includes a 1-1 conductive layer, a 1-2 conductive layer directly on one surface of the 1-1 conductive layer, and a 1-3 conductive layer directly on the other surface of the 1-1 conductive layer, and The second sensor conductive layer includes a 2-1 conductive layer, a 2-2 conductive layer directly on one surface of the 2-1 conductive layer, and a 2-3 conductive layer directly on the other surface of the 2-1 conductive layer, wherein a first opening portion exposing the one surface of the 1-1 conductive layer is defined in the 1-2 conductive layer, and a second opening portion exposing the one surface of the 2-1 conductive layer is defined in the 2-2 conductive layer, The one surface of the 1-1 conductive layer overlapping the first opening portion and the one surface of the 2-1 conductive layer overlapping the second opening portion are in contact with each other.

16. The display device according to claim 15, wherein: Each of the first opening portion and the second opening portion overlaps the contact hole in a plan view.

17. The display device according to claim 15, wherein: The resistance value of the 1-1 conductive layer is smaller than the resistance value of the 1-2 conductive layer, and The resistance value of the 2-1 conductive layer is smaller than the resistance value of the 2-2 conductive layer.

18. A method for manufacturing a display device, the method comprising: forming a first sensor conductive layer on the sensor base layer, wherein the first sensor conductive layer includes a 1-1 conductive layer and a 1-2 conductive layer directly on one surface of the 1-1 conductive layer; forming a sensor insulating layer to cover the first sensor conductive layer; forming a contact hole in the sensor insulating layer by using a mask; forming a 2-2 conductive layer on the sensor insulating layer; forming a first opening portion overlapping the contact hole in the 1-2 conductive layer, and forming a second opening portion overlapping the contact hole in the 2-2 conductive layer; as well as forming a 2-1 conductive layer on the 2-2 conductive layer to form a second sensor conductive layer including the 2-1 conductive layer and the 2-2 conductive layer, The one surface of the 1-1 conductive layer overlapping the first opening portion and the second opening portion and the one surface of the 2-1 conductive layer overlapping the first opening portion and the second opening portion are in contact with each other.

19. The method according to claim 18, wherein: In the step of forming the first opening portion and the second opening portion, the 1-2 conductive layer and the 2-2 conductive layer are etched using the same mask as that used in the step of forming the contact hole.

20. The method according to claim 18, wherein: In a plan view, a shape of each of the first opening portion and the second opening portion corresponds to a shape of the contact hole.

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