Dynamic stress assessment and parameter detection method, system and device, storage medium and program product

Abstract

The invention relates to a dynamic stress evaluation and parameter detection method, system and device, a storage medium and a program product, applied to a dynamic stress evaluation and parameter detection system, the dynamic stress evaluation and parameter detection system comprises an upper computer, a test circuit board and a signal collector, and a tested power device is deployed on the test circuit board; the method comprises the steps of sending a test loop access instruction to a test circuit board through an upper computer under the condition that stress application time corresponding to gate stress applied to a tested power device is exhausted; controlling the tested power device to be in a corresponding first stress test loop through the test circuit board based on the test loop access instruction; collecting a grid test signal of the tested power device under the first stress test loop through a signal collector; and detecting electrical performance parameters of the tested power device through the upper computer based on the grid test signal. By adopting the method, the detection accuracy of dynamic stress evaluation and parameter detection is improved.

Description

Technical Field

[0001] The present application relates to the technical field of power device detection, and in particular to a dynamic stress assessment and parameter detection method, system, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] Compared with power devices based on silicon, power devices based on gallium nitride and silicon carbide have higher breakdown voltage, faster switching speed, lower on-resistance and better stability. The above characteristics make gallium nitride and silicon carbide power devices have broad application prospects in electric vehicles, renewable energy systems, high-efficiency power converters and smart grids. Since gallium nitride and silicon carbide power devices have been subjected to gate stress for a long time, in order to accurately evaluate the performance and reliability of power devices under gate stress, it is essential to test the electrical performance parameters of power devices.

[0003] At present, in the process of testing the electrical performance parameters of power devices, traditional gate stress testing equipment is usually used to perform the test through fixed gate stress, such as applying a constant gate voltage or current as a stress source. However, since the gate stress of the power device under actual working conditions changes in real time, the stress source given by the gate stress testing equipment cannot simulate the dynamic gate stress to which the power device is subjected under actual working conditions, which makes it easy for the electrical performance parameters obtained by the test to be not the actual electrical performance parameters of the power device when it is working. Therefore, the current detection accuracy of dynamic stress evaluation and parameter detection is low. Summary of the invention

[0004] Based on this, it is necessary to provide a dynamic stress assessment and parameter detection method, system, computer equipment, computer-readable storage medium and computer program product to improve the detection accuracy of dynamic stress assessment and parameter detection in response to the above technical problems.

[0005] In a first aspect, the present application provides a dynamic stress assessment and parameter detection method, which is applied to a dynamic stress assessment and parameter detection system, wherein the dynamic stress assessment and parameter detection system includes a host computer, a test circuit board, and a signal collector, wherein a power device under test is deployed on the test circuit board; the method includes:

[0006] When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, sending a test loop access instruction to the test circuit board through the host computer;

[0007] Controlling the power device under test to be in a corresponding first stress test loop based on the test loop access instruction through the test circuit board;

[0008] Collecting the gate test signal of the power device under test in the first stress test loop by the signal collector;

[0009] The upper computer detects the electrical performance parameters of the power device under test based on the gate test signal.

[0010] In one of the embodiments, the dynamic stress assessment and parameter detection system includes a source meter and a programmable power supply, the test circuit board includes a coaxial shunt and a clamping circuit, the gate test signal includes a first gate test voltage and a second gate test voltage, and the electrical performance parameters include a threshold voltage and an on-resistance;

[0011] The detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer includes one of the following items:

[0012] Based on the voltage pulse signal sent by the programmable power supply to the power circuit of the test circuit board, the first gate test voltage collected by the signal collector is received by the host computer, and the first gate test voltage is used as a trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; according to the shunt current and the clamping voltage, the on-resistance of the power device under test is detected;

[0013] Based on the current pulse signal emitted by the source meter, the second gate test voltage collected by the signal collector is received by the host computer, and based on the second gate test voltage, the threshold voltage of the power device under test is detected.

[0014] In one of the embodiments, the test circuit board includes a pulse generator and a gate driver;

[0015] In the case where the stress application time corresponding to the gate stress applied to the power device under test is exhausted, before the host computer sends a test loop access instruction to the test circuit board, the method further includes:

[0016] Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal;

[0017] Based on the target pulse control signal, gate stress is applied to the power device under test through the gate driver.

[0018] In one embodiment, the adjusting the initial pulse signal to obtain the target pulse control signal includes at least one of the following:

[0019] Adjusting the amplitude of the initial pulse signal to obtain the target pulse control signal;

[0020] Adjusting the frequency of the initial pulse signal to obtain the target pulse control signal;

[0021] The duty cycle of the initial pulse signal is adjusted to obtain the target pulse control signal.

[0022] In one embodiment, after detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer, the method further includes:

[0023] If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has not failed;

[0024] If the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has failed, wherein the first preset electrical performance parameter threshold is less than the second preset electrical performance parameter threshold.

[0025] In one of the embodiments, the test circuit board includes a recovery test loop and a second stress test loop;

[0026] After the upper computer detects the electrical performance parameters of the power device under test based on the gate test signal, the method further includes at least one of the following items:

[0027] Performing recovery processing on the power device under test by connecting the power device under test to the recovery test loop;

[0028] The electrical performance parameters of the power device under test are detected by connecting the power device under test to the second stress test loop, wherein the gate stresses of the first stress test loop and the second stress test loop are different.

[0029] In a second aspect, the present application further provides a dynamic stress assessment and parameter detection system, the system comprising a host computer, a test circuit board and a signal collector, wherein a power device to be tested is deployed on the test circuit board;

[0030] The host computer is used to send a test access instruction to the test circuit board when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, and detect the electrical performance parameters of the power device under test based on the gate test signal transmitted by the signal collector;

[0031] The test circuit board is used to control the power device under test to be in the corresponding first stress test loop based on the test loop access instruction;

[0032] The signal collector is used to collect the gate test signal of the power device under test in the first stress test loop through the signal collector.

[0033] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0034] When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in the corresponding first stress test loop based on the test loop access instruction; the signal collector collects the gate test signal of the power device under test in the first stress test loop; and the host computer detects the electrical performance parameters of the power device under test based on the gate test signal.

[0035] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0036] When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in the corresponding first stress test loop based on the test loop access instruction; the signal collector collects the gate test signal of the power device under test in the first stress test loop; and the host computer detects the electrical performance parameters of the power device under test based on the gate test signal.

[0037] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0038] When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, the host computer sends a test loop access instruction to the test circuit board; the test circuit board controls the power device under test to be in the corresponding first stress test loop based on the test loop access instruction; the signal collector collects the gate test signal of the power device under test in the first stress test loop; and the host computer detects the electrical performance parameters of the power device under test based on the gate test signal.

[0039] The above-mentioned dynamic stress evaluation and parameter detection method, system, computer equipment, computer-readable storage medium and computer program product are applied to a dynamic stress evaluation and parameter detection system, which includes a host computer, a test circuit board and a signal collector, wherein a power device under test is deployed on the test circuit board. First, when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, a test circuit access instruction is sent to the test circuit board through the host computer, and then the test circuit board controls the power device under test to be in the corresponding first stress test circuit based on the test circuit access instruction, and the signal collector collects the gate test signal of the power device under test in the first stress test circuit, and finally the host computer detects the electrical performance parameters of the power device under test based on the gate test signal, thereby realizing the power device under test in actual working conditions. The invention can realize a real simulation of the dynamic gate stress to which the device is subjected, and complete the accurate detection of the electrical performance parameters of the power device under test under the real simulation of the gate stress applied to the power device under test, that is, by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the purpose of detecting and obtaining the actual electrical performance parameters of the power device is achieved, instead of only using the traditional gate stress test equipment to detect the actual electrical performance parameters of the power device through the fixed gate stress. Therefore, the technical defect that the gate stress of the power device under actual working conditions changes in real time, resulting in the stress source given by the gate stress test equipment being unable to simulate the dynamic gate stress to which the power device is subjected in actual working conditions, and thus making it easy for the electrical performance parameters detected to be not the actual electrical performance parameters of the power device, is overcome. Therefore, the detection accuracy of dynamic stress evaluation and parameter detection is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic diagram of a flow chart of a dynamic stress assessment and parameter detection method in one embodiment;

[0042] Figure 2 A schematic diagram of a test circuit board of a dynamic stress assessment and parameter detection method in one embodiment;

[0043] Figure 3 An overall schematic diagram of a dynamic stress assessment and parameter detection system of a dynamic stress assessment and parameter detection method in one embodiment;

[0044] Figure 4 is a structural block diagram of a dynamic stress evaluation and parameter detection system in one embodiment;

[0045] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] First of all, it should be understood that power devices using gallium nitride and silicon carbide materials as substrates may show unstable threshold voltage (VTH) and dynamic changes in on-resistance under gate stress, thereby affecting the performance and long-term reliability of power devices. For example, during the fast switching process of gallium nitride high electron mobility transistor (GaN HEMT), the threshold voltage drift will affect the switching characteristics and efficiency of the power device. It is understandable that under positive gate stress, electron capture and hole injection cause the threshold voltage of p-GaN gate HEMT devices to change significantly, which is different from that of silicon-based metal oxide semiconductor field effect transistors (Si MOSFET). Similarly, compared with Si MOSFET, SiC MOSFET exhibits more significant VTH drift. The instability of VTH is mainly affected by the capture and emission of positive and negative charges in the gate oxide layer. In addition, the dynamic change of on-resistance (RON) is also an important indicator for evaluating device reliability. The change of RON is not only closely related to the instability of VTH, but may also be coupled with drain stress, thus showing more complex change behavior. Based on the above, it can be seen that since the electrical performance parameters such as threshold voltage and on-resistance of power devices based on silicon carbide and gallium nitride will show rapid recovery characteristics, the threshold voltage obtained by the traditional threshold voltage scanning method will be seriously misestimated. It has been proven to be more accurate and effective to capture VTH changes on a microsecond time scale through fast measurement technology. However, the conventional gate stress test equipment is used to perform the test through fixed gate stress, which results in that the stress source given by the gate stress test equipment cannot simulate the dynamic gate stress to which the power device is subjected in actual working conditions, and thus makes it easy for the electrical performance parameters detected to be not the actual electrical performance parameters of the power device. That is, there is currently a lack of effective means for detecting the electrical performance parameters of the power device under dynamic gate stress. Therefore, how to comprehensively evaluate the reliability of the device in actual applications and how to quickly and accurately measure the threshold voltage and on-resistance while simulating the dynamic gate stress in actual working conditions are difficult problems to be solved in this field. That is, there is currently an urgent need for a dynamic stress evaluation and parameter detection method that can improve the detection accuracy of dynamic stress evaluation and parameter detection.

[0048] In one embodiment, Figure 1 As shown, a dynamic stress assessment and parameter detection method is provided. This embodiment takes the method applied to a dynamic stress assessment and parameter detection system as an example. The dynamic stress assessment and parameter detection system includes a host computer, a test circuit board and a signal collector, wherein a power device to be tested is deployed on the test board. It can be understood that the host computer includes but is not limited to a personal computer, a laptop computer, a smart phone and a tablet computer, etc., the signal collector includes but is not limited to an oscilloscope, a digital signal collector and a general data collector, etc., the test circuit board includes but is not limited to an aluminum substrate, a ceramic substrate or a polyimide (PI) board, etc., the host computer, the test circuit board and the signal collector are electrically connected to each other, wherein a power device to be tested is deployed on the test circuit board, for example, in an implementable manner, the power device to be tested is welded on an aluminum substrate with high thermal conductivity, and the gate, drain and source pins are led out and connected to the dynamic stress assessment and parameter detection system, the back of the aluminum substrate is in close contact with the constant temperature heating plate, wherein the host computer The machine is used to send a test circuit access instruction to the test circuit board through the host computer when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, and detect the electrical performance parameters of the power device under test based on the gate test signal transmitted by the signal collector. The test circuit board controls the gate test signal of the power device under test based on the test circuit access instruction, and the signal collector collects the gate test signal of the power device under test under the first stress test circuit. Through the signal interaction between the host computer, the test circuit board and the signal collector, the real simulation of the dynamic gate stress on the power device under test in the actual working condition can be achieved, and the electrical performance parameters of the power device under test can be accurately detected under the real simulation of the gate stress applied to the power device under test. That is, by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the purpose of detecting the actual electrical performance parameters of the power device is achieved, so the detection accuracy of dynamic stress evaluation and parameter detection is improved. In this embodiment, the method includes the following steps 202 to 208. Among them:

[0049] Step 202: When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, a test loop access instruction is sent to the test circuit board through the host computer.

[0050] It should be noted that the power device under test deployed on the test circuit board is connected to the dynamic stress evaluation and parameter detection system through the lead-out pins. For example, in an implementable manner, the lead-out pin spacing of the power device under test is 2.54 mm, compatible with TO220 packaging, and the pin order can be GDS. The power device under test refers to a power device waiting for electrical performance parameter detection, and can specifically be a power device with silicon carbide as a substrate or a power device with gallium nitride as a substrate, etc. In order to evaluate the performance change of the power device under test after a period of gate stress, the stress type, stress magnitude and stress time can be set through the host computer control program, wherein the stress type includes stress in a constant voltage mode (static stress mode) or a dynamic stress mode. If the stress type is stress in a dynamic stress mode, the frequency and duty cycle need to be specified. For example, in an implementable manner, the drain and source of the power device under test are short-circuited, thereby applying gate stress to the power device under test, wherein the voltage magnitude of the gate stress applied to the power device under test can be controlled by a low voltage difference line regulator and an adjustable potentiometer.

[0051] It should be noted that the test loop access instruction is triggered by the host computer, that is, the test loop access instruction is issued by the host computer program logic control. For example, in an implementable manner, the stress application time can be set in the host computer program, and when it is detected that the stress application time has been exhausted, the host computer sends a circuit switching instruction to the test circuit board, that is, the test loop access instruction is sent to the test circuit board by the host computer, and after receiving the instruction, the MCU sends a control signal to the high-speed switch to open or close the high-speed switch of the test circuit board. Based on the different instruction types of the test loop access instruction, the test circuit board can be in the first stress test loop for detecting the threshold voltage, in the first stress test loop for detecting the on-resistance, or end the electrical performance parameter detection process based on the test loop access instruction. It can be understood that the stress application time is pre-set based on the recovery characteristics of the power device under test.

[0052] It should be noted that in order to avoid the deviation of the detection results caused by temperature changes, the dynamic stress assessment and parameter detection system can also be provided with a temperature control device, which is electrically connected to the test circuit board, and the temperature of the power device under test is controlled by the temperature control device. It should be emphasized that in the process of temperature control of the power device under test, it can be achieved by locally heating the test circuit board. For example, in one feasible method, the device is welded on an aluminum substrate with high thermal conductivity, and the gate, drain and source pins are led out and connected to the test system. The back of the aluminum substrate is close to a constant temperature heating plate, and the constant temperature heating plate contains thermocouple feedback. The temperature is controlled by a PID algorithm. The chip can be welded on an aluminum-based adapter circuit board, and the pins are led out by the adapter board. A socket is arranged on the test circuit board, so that the adapter board can be plugged into the socket of the test circuit board to achieve connection. It can be understood that the aluminum substrate has better thermal conductivity than other materials, which is convenient for temperature control, so that the temperature remains unchanged during the detection process.

[0053] As an example, step 202 includes: applying gate stress to the power device under test, and sending a test loop access instruction to the test circuit board through the host computer when it is detected that the actual time of applying the gate stress reaches the stress application time.

[0054] Step 204 : Control the power device under test to be in the corresponding first stress test loop based on the test loop access instruction through the test circuit board.

[0055] It should be noted that, under the action of the test loop access instruction, the test circuit board quickly switches to the first stress test loop through a high-speed switch, so that the subsequent signal collector can collect the gate test signal under the first stress test loop, wherein the first stress test loop can specifically be a threshold voltage test loop or an on-resistance test loop, etc.

[0056] As an example, step 204 includes: controlling the power device under test to be in the corresponding first stress test loop based on the test loop access instruction through the test circuit board.

[0057] Step 206: Collect the gate test signal of the power device under test in the first stress test loop through the signal collector.

[0058] As an example, step 206 includes: collecting a gate test signal of the power device under test in the first stress test loop through an oscilloscope.

[0059] Step 208: The upper computer detects the electrical performance parameters of the power device under test based on the gate test signal.

[0060] It should be noted that the conversion of the gate test signal to the electrical performance parameters of the power device under test can be completed by the host computer. For example, in one feasible method, assuming that the signal collector is an oscilloscope, after the oscilloscope extracts the test voltage signal, it obtains the electrical performance parameters of the power device under test by analyzing the test voltage signal.

[0061] Specifically, when the electrical performance parameter being measured is the threshold voltage, the clamping voltage and the coaxial shunt current are invalid waveforms and do not need to be collected. Therefore, the signal collector only needs to collect the gate voltage signal waveform; when the electrical performance parameter being measured is the on-resistance, it is necessary to collect the clamping voltage and the coaxial shunt current. At this time, the gate signal is only used to trigger the oscilloscope (i.e., to tell the oscilloscope to collect data), and does not participate in the direct calculation of the on-resistance.

[0062] As an example, step 208 includes: detecting the electrical performance parameters of the power device under test according to the gate test signal by the host computer.

[0063] The above-mentioned dynamic stress evaluation and parameter detection method is applied to a dynamic stress evaluation and parameter detection system, which includes a host computer, a test circuit board and a signal collector, wherein a power device under test is deployed on the test circuit board. First, when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, a test circuit access instruction is sent to the test circuit board through the host computer, and then the test circuit board controls the power device under test to be in the corresponding first stress test circuit based on the test circuit access instruction, and the signal collector collects the gate test signal of the power device under test in the first stress test circuit, and finally the host computer detects the electrical performance parameters of the power device under test based on the gate test signal, thereby realizing the real simulation of the dynamic gate stress to which the power device under test is subjected in the actual working condition. The method can simulate and accurately detect the electrical performance parameters of the power device under test under the gate stress of the real simulation. That is, by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the purpose of detecting the actual electrical performance parameters of the power device is achieved, rather than only using the traditional gate stress test equipment to detect the actual electrical performance parameters of the power device through the fixed gate stress. Therefore, the technical defect that the gate stress of the power device under actual working conditions changes in real time, resulting in the stress source given by the gate stress test equipment being unable to simulate the dynamic gate stress to which the power device is subjected in actual working conditions, and thus making it easy for the electrical performance parameters detected to be not the actual electrical performance parameters of the power device, is overcome. Therefore, the detection accuracy of dynamic stress evaluation and parameter detection is improved.

[0064] In one embodiment, a dynamic stress assessment and parameter detection system includes a source meter and a programmable power supply, a test circuit board includes a coaxial shunt and a clamping circuit, a gate test signal includes a first gate test voltage and a second gate test voltage, and an electrical performance parameter includes a threshold voltage and an on-resistance;

[0065] The host computer detects the electrical performance parameters of the power device under test based on the gate test signal, including one of the following:

[0066] Step 302, based on the voltage pulse signal sent by the programmable power supply to the power circuit of the test circuit board, the first gate test voltage collected by the signal collector is received by the upper computer, and the first gate test voltage is used as the trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; according to the shunt current and the clamping voltage, the on-resistance of the power device under test is detected.

[0067] It should be noted that the electrical performance parameters include threshold voltage and on-resistance. It is understandable that the detection of threshold voltage and on-resistance can be realized based on the same dynamic stress evaluation and parameter detection system, but there are differences in the specific detection logic. In the process of detecting the on-resistance of the power device under test, the first gate test voltage is measured by the probe of the first channel of the oscilloscope. (GS means gate G to source S), and use the first gate test voltage as the oscilloscope trigger signal to measure the clamping voltage on the clamping circuit through the probe of the second channel of the oscilloscope , where M stands for Measure, i.e., measurement, and the shunt current on the coaxial shunt is measured through the third channel of the oscilloscope. (DS means drain D to source S), based on the above, the on-resistance can be solved, where the expression for solving the on-resistance is as follows:

[0068]

[0069] in, is a constant associated with the clamping circuit, is the contact resistance of K1 in the test circuit board, which is a constant. is the clamping voltage, is the shunt current.

[0070] As an example, step 302 includes: a voltage pulse signal emitted by a programmable power supply is used to receive a first gate test voltage collected by an oscilloscope by a host computer, and the first gate test voltage is used as a trigger signal of the oscilloscope. After the oscilloscope is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; and the on-resistance of the power device under test is detected based on the shunt current and the clamping voltage.

[0071] Step 304 : Based on the current pulse signal emitted by the source meter, the host computer receives the second gate test voltage collected by the signal collector, and based on the second gate test voltage, detects the threshold voltage of the power device under test.

[0072] It should be noted that the capture of the threshold voltage can also be completed by a signal collector. For example, in one feasible method, when the first stress test loop is switched to a stress test loop for detecting the threshold voltage, the SMU is made to send a current pulse signal of a specified size, thereby triggering the oscilloscope to perform a second gate test voltage. Specifically, the stable segment of the second gate test voltage can be extracted as the second gate test voltage, wherein the current pulse signal can specifically be a 1mA current pulse.

[0073] As an example, step 304 includes: according to the current pulse signal emitted by the source meter, receiving the second gate test voltage collected by the signal collector through the host computer, and selecting the voltage in the stable section of the second gate test voltage as the target gate test voltage; using the target gate test voltage as the threshold voltage of the power device under test.

[0074] In this embodiment, in the process of detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer, different detection methods are adopted for detection based on the different electrical performance parameters to be detected, that is, when detecting the on-resistance of the power device under test, the voltage pulse signal emitted by the programmable power supply triggers the collection of the first gate test voltage, the shunt current and the clamping voltage, and finally the on-resistance of the power device under test is detected by fusing the first gate test voltage, the shunt current and the clamping voltage, and when detecting the threshold voltage of the power device under test, the current pulse signal emitted by the source meter triggers the collection of the second gate test voltage, and finally the threshold voltage of the power device under test is detected by the second gate test voltage, thereby achieving the purpose of quickly capturing the threshold voltage and on-resistance of the power device under test by the host computer in cooperation with the source meter, the programmable power supply and the oscilloscope, thereby improving the detection accuracy of the threshold voltage and on-resistance of the power device under test.

[0075] In one embodiment, a test circuit board includes a pulse generator and a gate driver;

[0076] When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, before the host computer sends a test circuit access instruction to the test circuit board, the method further includes:

[0077] Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain the target pulse control signal; based on the target pulse control signal, gate stress is applied to the power device under test through the gate drive.

[0078] It should be noted that the actual gate stress can be sent to the power device under test through the gate drive, that is, providing a correct control signal to the gate drive can make the gate drive send out the waveform correctly. The frequency and duty cycle of the above control signal also determine the frequency and duty cycle of the gate stress waveform sent by the gate drive. By regarding the gate drive as an amplifier, the low level (0V) of the control signal can be amplified to VGS (OFF), and the high level (>2V) of the control signal can be amplified to VGS (ON), wherein VGS (OFF) and VGS (ON) are the low level and high level of dynamic stress, and their sizes are adjustable. It can be understood that the gate drive control signal can be given by any form of pulse generator, such as microcontroller unit MCU (single-chip microcomputer), field programmable gate array FPGA, function signal generator, etc. By integrating MCU on the test circuit board, it can be used to send a pulse waveform to the gate drive, and the MCU is connected to the host computer at the same time. According to the test loop access instruction sent by the host computer to the test circuit board, refer to Figure 3 , Figure 3 This is a schematic diagram of the test circuit board. The test circuit board will control the MCU to open or close the five high-speed switches K1 to K5 according to the test loop access instruction, so that the power device under test is in the first stress test loop in the corresponding mode. At the same time, the test circuit board can also modify the control signals of different frequencies and duty cycles sent to the gate drive according to the instructions of the host computer, thereby realizing the adjustment of dynamic gate stress.

[0079] As an example, based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted to the target pulse control signal through the pulse generator; under the action of the target pulse control signal, gate stress is applied to the power device under test through the gate drive. In this embodiment, a pulse generator and a gate drive are deployed on the test circuit board, so that before the test loop access instruction is sent to the test circuit board through the host computer, the initial pulse signal is adjusted to the target pulse control signal through the pulse generator based on the signal adjustment instruction sent by the host computer, and then under the action of the target pulse control signal, gate stress is applied to the power device under test through the gate drive, so that the purpose of dynamically adjusting the gate stress applied to the power device under test can be achieved, so as to lay a foundation for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0080] In one embodiment, the initial pulse signal is adjusted to obtain a target pulse control signal, which includes at least one of the following:

[0081] The amplitude of the initial pulse signal is adjusted to obtain a target pulse control signal; the frequency of the initial pulse signal is adjusted to obtain a target pulse control signal; the duty cycle of the initial pulse signal is adjusted to obtain a target pulse control signal.

[0082] It should be noted that in the process of adjusting the initial pulse signal through the pulse generator, different adjustment methods can be adopted to adjust the initial pulse signal based on different signal adjustment instructions. Specifically, the size (amplitude), frequency and duty cycle of the initial pulse signal can be adjusted synchronously, or the size, frequency and duty cycle of the initial pulse signal can be adjusted separately.

[0083] As an example, the target pulse control signal is obtained by adjusting the amplitude of the initial pulse signal; the target pulse control signal is obtained by adjusting the frequency of the initial pulse signal; and the target pulse control signal is obtained by adjusting the duty cycle of the initial pulse signal.

[0084] In this embodiment, by adjusting the amplitude, frequency and / or duty cycle of the initial pulse signal, a target pulse control signal for applying gate stress to the power device under test is obtained, so that different types of dynamic gate stress can be flexibly provided for detecting the electrical performance parameters of the power device under test, thereby laying a foundation for improving the detection accuracy of dynamic stress evaluation and parameter detection.

[0085] In one embodiment, after detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer, the method further includes:

[0086] If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has not failed; if the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has failed, wherein the first preset electrical performance parameter threshold is less than the second preset electrical performance parameter threshold.

[0087] It should be noted that after completing the electrical performance parameters of the power device under test, the performance of the power device under test can be further identified based on the electrical performance parameters obtained by detection. For example, in one implementable method, assuming that the electrical performance parameter is a threshold voltage, a first preset voltage threshold and a second preset voltage threshold can be set simultaneously, wherein the first preset voltage threshold is 1.6V and the second preset voltage threshold is 2.4V. When it is detected that the threshold voltage of the power device under test before stress is applied is 2V (between the first preset voltage threshold and the second preset voltage threshold), it is determined that the power device under test has not failed, and when it is detected that the threshold voltage of the power device under test is 2.6V (>2.4V) or 1.2V (<1.6V), it is determined that the power device under test has failed.

[0088] As an example, the test circuit board includes a recovery test loop and a second stress test loop;

[0089] After the upper computer detects the electrical performance parameters of the power device under test based on the gate test signal, the method further includes at least one of the following items:

[0090] The power device under test is restored by connecting it to a recovery test loop; the electrical performance parameters of the power device under test are detected by connecting it to a second stress test loop, wherein the gate stresses of the first stress test loop and the second stress test loop are different.

[0091] It should be noted that after completing the detection of the electrical performance parameters of the power device under test, the recovery process of the power device under test can be tracked by connecting to the recovery test loop, and the gate stress of the device can continue to be applied by connecting to the second stress test loop, so as to evaluate the impact of the cumulative stress on the power device under test. For example, in one feasible method, assuming that the electrical performance parameter is the threshold voltage, in order to capture the curve of the threshold voltage drifting over time, the first stress can be applied for a given period of time, and then the threshold voltage can be quickly measured and then the second stress can be applied for a given period of time. The impact of the stress is accumulated through the cycle until the stress application time is reached, that is, until the stress application time is exhausted, and then the recovery mode is entered, wherein the first stress and the second stress are different stresses, and the power device under test is connected to the recovery test loop in the same way. The specific process can be recovery-measurement-recovery-measurement, and this cycle is repeated until the stress application time is exhausted and the program exits.

[0092] As an example, the power device under test is connected to a recovery test circuit to recover the power device under test; the electrical performance parameters of the power device under test are detected by connecting the power device under test to a second stress test circuit, wherein the gate stresses of the first stress test circuit and the second stress test circuit are different.

[0093] In this embodiment, after the electrical performance parameters of the power device under test are detected, a circuit can be switched for the power device under test. For example, the power device under test can be connected to a recovery test circuit or a second stress test circuit, thereby achieving an in-depth exploration of the relationship between the electrical performance parameters and the on-resistance during the degradation process, and providing a new perspective and data support for the reliability analysis and life prediction of the power device under test. Therefore, while improving the detection accuracy of dynamic stress evaluation and parameter detection, the detection effect of dynamic stress evaluation and parameter detection is also improved simultaneously.

[0094] In one practicable manner, referring to Figure 3 , Figure 3The figure is an overall schematic diagram of a dynamic stress assessment and parameter detection system, wherein the dynamic stress assessment and parameter detection system includes a programmable power supply, an oscilloscope, a source meter, a temperature control device, a host computer and a test circuit board, wherein the connection relationship of the above devices is shown in the figure. First, the dynamic stress assessment and parameter detection system switches to the first stress test loop, and the stress type, stress magnitude and stress time are set by the host computer control program, wherein the stress magnitude can be controlled by a low-dropout linear regulator and an adjustable potentiometer, and the stress is applied. After the stress application time is exhausted, the high-speed switch is used to quickly switch to the first stress test loop for detecting the threshold voltage and the first stress test loop for detecting the on-resistance, and the data is measured and collected, wherein the high-speed switch The speed can be preset. The greater the switching delay of the high-speed switch, the longer the recovery time of the device (leaving the stress loop means removing the stress, and the device begins to recover), which makes the measured device threshold voltage lower. Therefore, the smaller the switching delay, the better. The speed of the high-speed switch can be set to about 10ms. Preferably, the speed of the high-speed switch can be <1ms. After the measurement and data collection are completed, the failure of the device can be judged according to the parameters. If it fails, the process can be exited in advance. In the threshold voltage measurement loop and the on-resistance measurement loop (the first stress test loop), the oscilloscope and the source meter share the same ground with the source of the device. In the threshold voltage measurement loop, the gate and drain of the device are short-circuited, and the source meter and the oscilloscope are connected to the gate. In the threshold voltage measurement loop, The source meter outputs a precise constant current, and the oscilloscope captures the gate voltage waveform and transmits it back to the host computer to analyze the threshold voltage; in the on-resistance measurement loop, the gate of the device is connected to the double pulse generation circuit, the drain of the device is connected to the inductive load and the clamping circuit, the other end of the inductive load is connected to the positive pole of the programmable power supply, the source of the device is connected to the coaxial shunt, the other end of the coaxial shunt is connected to the negative pole of the programmable power supply, and the oscilloscope is connected to the gate, the clamping circuit and the coaxial shunt; in the on-resistance measurement loop, the programmable power supply outputs a constant voltage, and at the same time, a double pulse is applied to the gate of the power device under test through the pulse generator. The oscilloscope captures the double pulse test waveform and transmits it back to the host computer for analysis to obtain the on-resistance; optionally, after the measurement, the device can be connected to a recovery loop or a stress loop; recovery The retest circuit is a short circuit of the gate, source and drain, that is, the three terminals are grounded; the second stress test circuit is the same as the first stress test circuit; the recovery test circuit is similar to the first stress test circuit, and it can still switch to the first stress test circuit after the recovery time is exhausted to monitor the recovery process of the device; according to the upper computer program settings, the above steps are repeated until the program exit conditions are met or manually exited. It can be understood that repetition is not a simple mechanical repetition. This step allows the type, intensity and duration of stress parameters to be flexibly adjusted according to the specific needs of the experiment; the measurement parameter options can be changed according to the test purpose, and the threshold voltage measurement circuit or the on-resistance measurement circuit can be selectively connected to achieve alternating measurement of threshold voltage and on-resistance.

[0095] The above-mentioned dynamic stress evaluation and parameter detection method can realize the real simulation of the dynamic gate stress to which the power device under test is subjected in the actual working condition, and complete the accurate detection of the electrical performance parameters of the power device under test under the real simulation of the gate stress applied to the power device under test. That is, by greatly reducing the stress interference in the measurement process and significantly shortening the measurement response time, the purpose of detecting and obtaining the actual electrical performance parameters of the power device is achieved, rather than only being able to use the traditional gate stress test equipment to detect the actual electrical performance parameters of the power device through the fixed gate stress. Therefore, the technical defect that the gate stress of the power device under the actual working condition changes in real time, resulting in the stress source given by the gate stress test equipment being unable to simulate the dynamic gate stress to which the power device is subjected in the actual working condition, and thus making it easy for the electrical performance parameters detected to be not the actual electrical performance parameters of the power device, is overcome. Therefore, the detection accuracy of dynamic stress evaluation and parameter detection is improved.

[0096] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0097] Based on the same inventive concept, the embodiment of the present application also provides a dynamic stress assessment and parameter detection system for implementing the dynamic stress assessment and parameter detection method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more dynamic stress assessment and parameter detection system embodiments provided below can refer to the limitations of the dynamic stress assessment and parameter detection method above, and will not be repeated here.

[0098] In an exemplary embodiment, Figure 4 As shown, a dynamic stress evaluation and parameter detection system is provided, the system includes a host computer 401, a test circuit board 402 and a signal collector 403, wherein a power device to be tested is deployed on the test circuit board;

[0099] The host computer 401 is used to send a test access instruction to the test circuit board when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, and detect the electrical performance parameters of the power device under test based on the gate test signal transmitted by the signal collector;

[0100] The test circuit board 402 is used to control the power device under test to be in the corresponding first stress test loop based on the test loop access instruction;

[0101] The signal collector 403 is used to collect the gate test signal of the power device under test in the first stress test loop through the signal collector.

[0102] In one embodiment, the dynamic stress evaluation and parameter detection system includes a source meter and a programmable power supply, the test circuit board includes a coaxial shunt and a clamping circuit, the gate test signal includes a first gate test voltage and a second gate test voltage, and the electrical performance parameters include a threshold voltage and an on-resistance; the host computer 401 is also used to:

[0103] Based on the voltage pulse signal emitted by the programmable power supply to the power circuit of the test circuit board, the first gate test voltage collected by the signal collector is received by the host computer, and the first gate test voltage is used as a trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; the on-resistance of the power device under test is detected according to the shunt current and the clamping voltage; based on the current pulse signal emitted by the source meter, the second gate test voltage collected by the signal collector is received by the host computer, and based on the second gate test voltage, the threshold voltage of the power device under test is detected.

[0104] In one embodiment, the test circuit board includes a pulse generator and a gate driver; the dynamic stress evaluation and parameter detection system is also used for:

[0105] Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal; based on the target pulse control signal, gate stress is applied to the power device under test by the gate driver.

[0106] In one embodiment, the dynamic stress assessment and parameter detection system is also used for:

[0107] The amplitude of the initial pulse signal is adjusted to obtain the target pulse control signal; the frequency of the initial pulse signal is adjusted to obtain the target pulse control signal; the duty cycle of the initial pulse signal is adjusted to obtain the target pulse control signal.

[0108] In one embodiment, the dynamic stress assessment and parameter detection system is also used for:

[0109] If the electrical performance parameter is between a first preset electrical performance parameter threshold and a second preset electrical performance parameter threshold, it is determined that the power device under test has not failed; if the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has failed, wherein the first preset electrical performance parameter threshold is less than the second preset electrical performance parameter threshold.

[0110] In one embodiment, the test circuit board includes a recovery test loop and a second stress test loop; the dynamic stress evaluation and parameter detection system is further used for:

[0111] After the upper computer detects the electrical performance parameters of the power device under test based on the gate test signal, the method further includes at least one of the following items: recovering the power device under test by connecting the power device under test to the recovery test circuit; detecting the electrical performance parameters of the power device under test by connecting the power device under test to the second stress test circuit, wherein the gate stresses of the first stress test circuit and the second stress test circuit are different.

[0112] Each module in the above-mentioned dynamic stress assessment and parameter detection system can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0113] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 5As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface, the display unit and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a dynamic stress assessment and parameter detection method is implemented. Those skilled in the art can understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0114] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0115] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0116] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0117] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0118] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A dynamic stress assessment and parameter detection method, characterized in that: Applied to a dynamic stress assessment and parameter detection system, the dynamic stress assessment and parameter detection system comprises a host computer, a test circuit board and a signal collector, wherein a power device to be tested is deployed on the test circuit board; the method comprises: When the stress application time corresponding to the gate stress applied to the power device under test is exhausted, sending a test loop access instruction to the test circuit board through the host computer; Controlling the power device under test to be in a corresponding first stress test loop based on the test loop access instruction through the test circuit board; Collecting the gate test signal of the power device under test in the first stress test loop by the signal collector; The upper computer detects the electrical performance parameters of the power device under test based on the gate test signal.

2. The method according to claim 1, characterized in that The dynamic stress evaluation and parameter detection system includes a source meter and a programmable power supply, the test circuit board includes a coaxial shunt and a clamping circuit, the gate test signal includes a first gate test voltage and a second gate test voltage, and the electrical performance parameters include a threshold voltage and an on-resistance; The detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer includes one of the following items: Based on the voltage pulse signal sent by the programmable power supply to the power circuit of the test circuit board, the first gate test voltage collected by the signal collector is received by the host computer, and the first gate test voltage is used as a trigger signal of the signal collector. After the signal collector is triggered by the first gate test voltage, the shunt current on the coaxial shunt and the clamping voltage on the clamping circuit are received; according to the shunt current and the clamping voltage, the on-resistance of the power device under test is detected; Based on the current pulse signal emitted by the source meter, the second gate test voltage collected by the signal collector is received by the host computer, and based on the second gate test voltage, the threshold voltage of the power device under test is detected.

3. The method according to claim 1, characterized in that The test circuit board includes a pulse generator and a gate driver; In the case where the stress application time corresponding to the gate stress applied to the power device under test is exhausted, before the host computer sends a test loop access instruction to the test circuit board, the method further includes: Based on the signal adjustment instruction sent by the host computer, the initial pulse signal is adjusted by the pulse generator to obtain a target pulse control signal; Based on the target pulse control signal, gate stress is applied to the power device under test through the gate driver.

4. The method according to claim 3, characterized in that The adjusting of the initial pulse signal to obtain the target pulse control signal includes at least one of the following: Adjusting the amplitude of the initial pulse signal to obtain the target pulse control signal; Adjusting the frequency of the initial pulse signal to obtain the target pulse control signal; The duty cycle of the initial pulse signal is adjusted to obtain the target pulse control signal.

5. The method according to claim 1, characterized in that: After detecting the electrical performance parameters of the power device under test based on the gate test signal by the host computer, the method further includes: If the electrical performance parameter is between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has not failed; If the electrical performance parameter is not between the first preset electrical performance parameter threshold and the second preset electrical performance parameter threshold, it is determined that the power device under test has failed, wherein the first preset electrical performance parameter threshold is less than the second preset electrical performance parameter threshold.

6. The method according to claim 1, characterized in that The test circuit board comprises a recovery test circuit and a second stress test circuit; After the upper computer detects the electrical performance parameters of the power device under test based on the gate test signal, the method further includes at least one of the following items: Performing recovery processing on the power device under test by connecting the power device under test to the recovery test loop; The electrical performance parameters of the power device under test are detected by connecting the power device under test to the second stress test loop, wherein the gate stresses of the first stress test loop and the second stress test loop are different.

7. A dynamic stress assessment and parameter detection system, the system comprising a host computer, a test circuit board and a signal collector, wherein: The test circuit board is provided with a power device to be tested; The host computer is used to send a test access instruction to the test circuit board when the stress application time corresponding to the gate stress applied to the power device under test is exhausted, and detect the electrical performance parameters of the power device under test based on the gate test signal transmitted by the signal collector; The test circuit board is used to control the power device under test to be in the corresponding first stress test loop based on the test loop access instruction; The signal collector is used to collect the gate test signal of the power device under test in the first stress test loop through the signal collector.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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