Reset processing method, system, electronic device and storage medium based on multiple reset sources

Abstract

The present disclosure provides a reset processing method, system, electronic device, and storage medium based on multiple reset sources. The method includes: a reset state machine generates a reset request for each reset source according to the reset signal and reset type corresponding to each reset source; a round-robin scheduling module performs round-robin scheduling on each reset request to generate a reset scheduling response signal; the reset state machine generates a reset release request for each reset source according to the reset scheduling response signal and reset type; the round-robin scheduling performs round-robin scheduling on each reset release request, generates a reset release scheduling response signal for each reset release request, and sends each reset release scheduling response signal to the reset state machine; the reset state machine clears the reset request of each reset source and unlocks the reset signal according to each reset release scheduling response signal, and the reset state machine generates a reset request corresponding to each reset source according to the reset type with a higher priority and the reset signal of each reset source corresponding to that type.

Description

Technical Field

[0001] The present disclosure relates to the field of computer science, and in particular to a reset processing method, system, electronic device, and storage medium based on multiple reset sources. Background Art

[0002] The PCIe (Peripheral Component Interconnect Express) system is primarily used to expand computer system bus data throughput and improve device communication speeds. The architecture of a PCIe system generally includes an RC (root complex), a switch, and an EP (endpoint).

[0003] In existing PCIe switch designs, reset signal processing is relatively simple and lacks flexibility. Specifically, traditional PCIe switches often only support a single type of reset source, which means they cannot selectively respond to multiple reset requests based on the needs of different scenarios.

[0004] This limitation not only restricts the flexibility of the PCIe system, but can also cause reliability and stability issues during the reset process.

[0005] Therefore, it is necessary to propose a reset processing method based on multiple reset sources to solve at least one of the above technical problems. Summary of the Invention

[0006] Embodiments of the present disclosure provide a reset processing method, system, electronic device, and storage medium based on multiple reset sources.

[0007] In a first aspect, the present disclosure provides a reset processing method based on multiple reset sources, comprising:

[0008] The reset state machine receives a reset signal from at least one reset source and latches each of the reset signals;

[0009] The reset state machine generates a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, and sends each reset request to the round-robin scheduling module;

[0010] The round-robin scheduling module receives each of the reset applications, performs round-robin scheduling on each of the reset applications, generates a reset scheduling response signal for each of the reset applications, and sends each of the reset scheduling response signals to the reset state machine;

[0011] The reset state machine receives each of the reset scheduling response signals, generates a reset release request for each of the reset sources according to each of the reset scheduling response signals and the reset type of each of the reset sources, and sends each of the reset release requests to the round-robin scheduling module;

[0012] The round-robin scheduling module receives each of the reset release applications, performs round-robin scheduling on each of the reset release applications, generates a reset release scheduling response signal corresponding to each of the reset release applications, and sends each of the reset release scheduling response signals to the reset state machine;

[0013] The reset state machine receives each of the reset release scheduling response signals, clears the reset request of each of the reset sources and unlocks the reset signal according to each of the reset release scheduling response signals.

[0014] In some optional implementations, after the round-robin scheduling module receives each reset request, the method further includes:

[0015] The round-robin scheduling module generates a physical layer reset signal of each reset source according to each reset application and the linkage physical layer reset control signal, and sends each physical layer reset signal to the physical layer module;

[0016] The physical layer module receives each of the physical layer reset signals, and resets the physical layer of the corresponding reset source according to each of the physical layer reset signals.

[0017] In some optional implementations, after the round-robin scheduling module receives each reset release request, the method further includes:

[0018] The round-robin scheduling module generates a physical layer reset release signal of each reset source according to each reset release application and the linkage physical layer reset release control signal, and sends each physical layer reset release signal to the physical layer module;

[0019] The physical layer module receives each of the physical layer reset release signals, and resets and releases the physical layer of the corresponding reset source according to each of the physical layer reset release signals.

[0020] In some optional implementations, the reset state machine generates a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, including:

[0021] The reset state machine updates a reset source mapping table according to the reset signal and the reset type of each reset source and generates a reset port vector of each reset source;

[0022] The reset state machine generates the reset request for each of the reset sources according to the updated reset source mapping table and each of the reset port vectors, wherein the reset request includes the reset port vector of the reset source.

[0023] In some optional implementations, the reset type of the reset source includes basic reset and warm reset.

[0024] In some optional implementations, the reset state machine generates a reset port vector for each reset source according to the reset signal and the reset type of each reset source, including:

[0025] The reset state machine generates a basic reset port vector according to the reset signal of the reset source and the basic reset;

[0026] The reset state machine generates a warm reset port vector according to the reset signal of the reset source and the warm reset.

[0027] In some optional implementations, when the basic reset and the hot reset conflict, the reset state machine sends each reset request to the round-robin scheduling module, including:

[0028] The reset state machine generates a reset request corresponding to each reset source according to a reset type with a higher priority among the basic reset and the hot reset and a reset signal of each reset source corresponding to the type.

[0029] In some optional implementations, the reset state machine clears the reset request of each reset source and unlocks the reset signal according to each reset release scheduling response signal, including:

[0030] The reset state machine clears the reset request of each reset source according to each reset release scheduling response signal, and after the reset state machine clears the reset requests corresponding to all reset sources, the reset state machine generates a reset completion mapping table;

[0031] The reset state machine unlocks the reset signal of each reset source according to the reset completion mapping table.

[0032] In a second aspect, the present disclosure provides a reset processing system based on multiple reset sources, comprising:

[0033] A reset state machine, configured to receive a reset signal from at least one reset source and latch each of the reset signals;

[0034] The reset state machine is further configured to generate a reset request for each reset source according to the reset signal and reset type corresponding to each reset source, and send each reset request to the round-robin scheduling module;

[0035] The round-robin scheduling module is configured to receive each of the reset applications, perform round-robin scheduling on each of the reset applications, generate a reset scheduling response signal for each of the reset applications, and send each of the reset scheduling response signals to the reset state machine;

[0036] The reset state machine is further configured to receive each of the reset scheduling response signals, generate a reset release request for each of the reset sources according to each of the reset scheduling response signals and the reset type of each of the reset sources, and send each of the reset release requests to the round-robin scheduling module;

[0037] The round-robin scheduling module is further configured to receive each of the reset release applications, perform round-robin scheduling on each of the reset release applications, generate a reset release scheduling response signal corresponding to each of the reset release applications, and send each of the reset release scheduling response signals to the reset state machine;

[0038] The reset state machine is further configured to clear the reset application corresponding to each reset source and unlock the reset signal according to each reset release scheduling response signal.

[0039] In a third aspect, the present disclosure provides an electronic device, comprising:

[0040] one or more processors;

[0041] a storage device having one or more programs stored thereon,

[0042] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in the embodiment of the first aspect of the present disclosure.

[0043] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by one or more processors, implements the method described in the embodiment of the first aspect of the present disclosure.

[0044] In a fifth aspect, the present disclosure provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the method described in the embodiment of the first aspect of the present disclosure.

[0045] Embodiments of the present disclosure provide a reset processing method, system, electronic device, and storage medium based on multiple reset sources, wherein a reset state machine receives a reset signal from at least one reset source and latches each reset signal; the reset state machine generates a reset application corresponding to each reset source based on the reset signal and reset type of each reset source, and sends each reset application to a round-robin scheduling module; the round-robin scheduling module receives each reset application, schedules each reset application, generates a reset scheduling response signal for each reset application, and sends each reset scheduling response signal to the reset state machine; the reset state machine receives each reset scheduling response signal, generates a reset release application for each reset source based on each reset scheduling response signal and the reset type of each reset source, and sends each reset release application to the round-robin scheduling module; the round-robin scheduling module receives each reset release application, schedules each reset release application, generates a reset release scheduling response signal corresponding to each reset release application, and sends each reset release scheduling response signal to the reset state machine; the reset state machine clears the reset application of each reset source and unlocks the reset signal based on each reset release scheduling response signal. The present disclosure receives and latches reset signals from different reset sources through a reset state machine, ensuring that each reset request can be accurately captured and processed, and then sends the reset application corresponding to each reset source to the round-robin scheduling module for scheduling, thereby realizing orderly processing of reset signals of multiple reset sources. Then, after the reset state machine receives the reset scheduling response signal, it will generate a reset release application and send it to the round-robin scheduling module again. The round-robin scheduling module schedules these reset release applications and generates a reset release scheduling response signal and sends it to the reset state machine. Finally, the reset state machine will clear the corresponding reset application according to the reset release scheduling response signal and unlock the corresponding reset signal, realizing selective response to multiple reset requests according to the needs of different scenarios, and can process multiple reset requests in an orderly and fair manner, thereby improving the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other features, objects, and advantages of the present disclosure will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are for illustration purposes only and are not to be considered as limiting the present invention. In the drawings:

[0047] Figure 1 is a system architecture diagram of an embodiment of a reset processing system based on multiple reset sources according to the present disclosure;

[0048] Figure 2 is a flowchart of an embodiment of a reset processing method based on multiple reset sources according to the present disclosure;

[0049] Figure 3 1 is a structural diagram of an embodiment of a reset processing system based on multiple reset sources according to the present disclosure. DETAILED DESCRIPTION

[0050] The present disclosure will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0051] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0052] Figure 1 An exemplary system architecture diagram 100 is shown to which embodiments of the reset processing method, apparatus, terminal device, and storage medium based on multiple reset sources of the present disclosure can be applied.

[0053] like Figure 1 As shown, the system architecture diagram 100 may include a reset state machine 101 , a round-robin scheduling module 102 and a physical layer module 103 .

[0054] The reset state machine 101 may be configured to receive and process reset signals from multiple reset sources, latch each reset signal, and generate corresponding reset requests and reset release requests according to the reset type of the reset source.

[0055] The round-robin scheduling module 102 may be used to perform round-robin scheduling on reset requests and generate corresponding scheduling response signals.

[0056] The physical layer module 103 may be configured to generate a physical layer reset signal, etc.

[0057] The reset state machine 101 , the round-robin scheduling module 102 , and the physical layer module 103 can communicate with each other via a PCIe link.

[0058] Through the coordinated work of the reset state machine 101, the round-robin scheduling module 102 and the physical layer module 103, latching, scheduling and releasing of the reset signal can be completed.

[0059] In some cases, the reset processing method based on multiple reset sources provided by the present disclosure can be jointly executed by the reset state machine 101 and the round-robin scheduling module 102. For example, the step of "receiving a reset signal from at least one reset source and latching each of the reset signals" can be executed by the reset state machine 101, and the step of "receiving each of the reset applications, scheduling each of the reset applications, generating a reset scheduling response signal corresponding to each of the reset applications, and sending each of the reset scheduling response signals to the reset state machine" can be executed by the round-robin scheduling module 102.

[0060] It should be understood that Figure 1 The number of reset state machines 101, round-robin scheduling modules 102, and physical layer modules 103 in the embodiment is merely illustrative. Any number of reset state machines 101, round-robin scheduling modules 102, and physical layer modules 103 may be provided according to implementation requirements.

[0061] Continue to refer Figure 2 , Figure 2 200 shows a flowchart of an embodiment of a reset processing method based on multiple reset sources according to the present disclosure. Figure 2 The reset processing method based on multiple reset sources shown can be applied to Figure 1 The reset state machine and round-robin scheduling module shown in FIG. The flowchart 200 may include the following steps:

[0062] Step 201: The reset state machine receives a reset signal from at least one reset source and latches each reset signal.

[0063] In this embodiment, the reset state machine is a finite state machine for managing and controlling reset operations in an electronic system or a computer system.

[0064] In a PCIe system, a reset source refers to the specific reason or source that triggers a reset operation on a device or the entire system.

[0065] In some optional embodiments, the reset source may include PERST# reset (low-level valid PCIe reset signal), upstream port hot reset, upstream port secondary bus reset, downstream port secondary bus reset, downstream port downstream link reset, virtual switch basic reset, non-transparent bridge link port reset, etc., which are not specifically limited here.

[0066] The upstream port hot reset may refer to a local reset mechanism for resetting an upstream port connected to a root complex.

[0067] Resetting the upstream port secondary bus may refer to resetting all devices on the secondary bus connected to the upstream port.

[0068] Resetting the downstream port secondary bus may refer to resetting all devices on the secondary bus connected to the downstream port.

[0069] Resetting the downstream link of the downstream port may refer to resetting all devices on the link connected to the downstream port.

[0070] Resetting the virtual switch infrastructure may refer to resetting the infrastructure of the virtual switch.

[0071] Resetting a non-transparent bridge link port may refer to resetting a specific link port of a non-transparent bridge.

[0072] A reset signal can be sent by a reset source. It is an electrical signal used to initialize or reinitialize a hardware device, circuit, or system. It is usually triggered when the system starts or when errors and failures are detected to ensure that the system can return to a known, stable state.

[0073] The reset state machine latches each reset signal after receiving a reset signal sent by at least one reset source.

[0074] In this embodiment, multiple reset sources may need to be reset at the same time. For example, the reset state machine may receive reset signals of the upstream port hot reset and the downstream port secondary bus reset, and latch the reset signals of the upstream port hot reset and the downstream port secondary bus reset.

[0075] The reset signal may include a reset source identifier of the reset source. Each reset source has a unique reset source identifier, which is used to identify the identity of each reset source.

[0076] Latching refers to saving the state of the reset signal. Even if the reset signal itself subsequently disappears or changes, the reset state machine can remember and process the reset signal. This helps to accurately manage and respond to different reset requests in complex systems.

[0077] Step 202: The reset state machine generates a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, and sends each reset request to the round-robin scheduling module.

[0078] In some optional implementations, each reset source corresponds to a reset type, and the corresponding relationship between each reset source and reset type can be preset and stored.

[0079] The reset state machine can identify the reset identifier of the reset source through the reset signal, determine the reset source corresponding to each reset signal, and generate a reset request corresponding to each reset source through the correspondence between the reset source and the reset type, and send each reset request to the round-robin scheduling module.

[0080] Four types of reset are defined in the PCIe system: cold reset, warm reset, hot reset, and functional layer reset.

[0081] Among them, cold reset and warm reset are also called basic reset. Basic reset is automatically handled by hardware and will reset the devices on the entire PCIe system, initialize all hardware logic related to the reset state machine, port status, and configuration registers in the configuration space.

[0082] A warm reset is performed by sending a TS1 (Training Sequence 1) ordered set over the PCIe link layer protocol. It resets a single PCIe device or link without affecting other devices or links.

[0083] Function-level resets are triggered by writing specific values ​​to the device's configuration space registers, allowing a single PCIe function to be reset without affecting other functions of the device.

[0084] The reset type of the reset source may include basic reset and warm reset.

[0085] For example, PERST# reset and virtual switch basic reset may belong to basic reset, and upstream port hot reset, upstream port secondary bus reset, downstream port secondary bus reset, downstream port downstream link reset and non-transparent bridge link port reset may belong to hot reset.

[0086] In some optional implementations, the reset type of the reset source further includes a function layer reset, and the function layer reset can directly locate the target function through a function identifier to achieve reset.

[0087] For basic reset and hot reset, the reset state machine generates a reset request corresponding to the basic reset of the virtual switch based on the reset signal and reset type of the basic reset of the virtual switch. The reset state machine generates a reset request corresponding to the upstream port hot reset based on the reset signal and reset type of the upstream port hot reset. The reset state machine generates a reset request corresponding to the downstream port secondary bus reset based on the reset signal and reset type of the downstream port secondary bus reset, and sends each reset request to the round-robin scheduling module.

[0088] In some optional embodiments, the reset state machine generates a reset request corresponding to each reset source based on the reset signal and reset type of each reset source. Specifically, the reset state machine can update the reset source mapping table and the reset port vector corresponding to each reset source based on the reset signal and reset type corresponding to each reset source, and then generate a reset request for each reset source based on the updated reset source mapping table and reset port vector, and send each reset request to the round-robin scheduling module, wherein the reset request includes the reset port vector of the reset source.

[0089] Here, the reset source mapping table may be used to represent the correspondence between reset sources and reset bits. In the reset mapping, each reset source corresponds to one bit.

[0090] For example, if there are 7 reset sources, the reset source mapping table may include 7 bits, wherein each bit corresponds to a reset source, and the initial state of the reset mapping table may be that each bit is set to 0, indicating that no reset source triggers a reset.

[0091] When the reset state machine receives a reset signal, the reset source that sends the reset signal can be determined based on the reset signals of each reset source to update the reset source mapping table. That is, the bit corresponding to the reset source that sends the reset signal can be set to 1 in the reset source mapping table to indicate that the reset source is to trigger a reset.

[0092] For example, the initial state of the reset mapping table may be 0000000, wherein the virtual switch basic reset, upstream port hot reset, and downstream port secondary bus reset correspond to bits 1, 2, and 4 of the reset mapping, respectively.

[0093] Then, the reset state machine may update the reset mapping table, and the updated reset source mapping table may be: 1101000.

[0094] The reset port vector can be used to indicate the port that needs to be reset corresponding to the reset source, that is, the reset port vector can be used to indicate which ports in the PCIe system need to be reset. The number of bits of the reset port vector depends on the number of ports in the PCIe system.

[0095] For example, if there are n ports in a PCIe system, the reset port vector may be an n-dimensional vector, where each component corresponds to a port in the PCIe system. If the port needs to be reset, the component corresponding to the port may be set to 1; if the port does not need to be reset, the component corresponding to the port may be set to 0.

[0096] For example, if there are 8 ports in a PCIe system, the reset port vector will be an 8-dimensional vector.

[0097] When ports 1, 3, and 5 need to be reset, the reset port vector can be represented as {01010100}, numbered from right to left, with the lowest bit being the first port.

[0098] It is understandable that the ports that need to be reset by each reset source are different, and the reset state machine can generate a reset port vector of each reset source according to the reset signal of each reset source.

[0099] In some optional implementations, according to the reset type of the reset source, the reset state machine may generate a reset port vector corresponding to the reset type.

[0100] In some optional implementations, the reset state machine generates a basic reset port vector according to the reset signal of the reset source and the basic reset. The reset state machine generates a warm reset port vector according to the reset signal of the reset source and the warm reset.

[0101] In this way, different reset port vectors are generated according to the reset type, which can clearly divide the scope of different reset types and facilitate management and maintenance by system administrators.

[0102] In this embodiment, the reset signal of the reset source also includes the port that needs to be reset by the reset source.

[0103] The basic reset vector may be used to indicate which ports need to be basic reset, and the warm reset port vector may be used to indicate which ports need to be warm reset.

[0104] The reset state machine generates a reset request for each reset source according to the reset source mapping table and the generated basic reset port vector and / or hot reset port vector, and sends each reset request to the round-robin scheduling module, wherein the reset request includes the reset port vector of the reset source.

[0105] In some optional embodiments, when a conflict occurs between a port basic reset and a hot reset, the reset state machine sends each reset request to the round-robin scheduling module. Specifically, the reset state machine generates a reset request corresponding to each reset source based on the reset type with a higher priority among the port basic reset and the hot reset and the reset signal of each reset source corresponding to the type.

[0106] Here, the priority of the basic port reset can be higher than the priority of the hot reset port. Therefore, when the port basic reset and hot reset exist at the same time, the reset state machine can only send the reset request of the reset source corresponding to the basic reset with a higher priority to the round-robin scheduling module, and then generate the reset request corresponding to each reset source according to the reset signal of each reset source corresponding to the basic reset.

[0107] Step 203 : The round-robin scheduling module receives each reset application, performs round-robin scheduling on each reset application, generates a reset scheduling response signal corresponding to each reset application, and sends each reset scheduling response signal to the reset state machine.

[0108] Here, the round-robin scheduling module may include a task scheduling algorithm. The round-robin scheduling module may cyclically allocate resources to each reset application in a certain order to achieve the reset of each reset source.

[0109] The round-robin scheduling module allocates a fixed time slice to each reset request. During this time slice, the CPU will be fully allocated to the reset request to perform the reset of the reset source. When the time slice is exhausted, the CPU will be allocated to the next reset request to perform the reset of the next reset source, and so on, forming a cycle. All waiting reset requests are placed in the ready queue and scheduled in a round-robin manner according to the first-in-first-out principle.

[0110] Here, the time slice of the round-robin scheduling module is configured as needed.

[0111] The round-robin scheduling module receives each reset application, performs round-robin scheduling on each reset application, generates a port reset signal to reset the port required to be reset by each reset source, and after the reset is completed, generates a reset scheduling response signal for each reset application and sends each reset scheduling response signal to the reset state machine.

[0112] The reset scheduling response signal can be used to confirm to the reset state machine that the reset request has been processed by the round-robin scheduling module, which means that the round-robin scheduling module has arranged the reset operation of the reset source and the reset state machine can continue with the next operation.

[0113] Step 204 : The reset state machine receives each reset scheduling response signal, generates a reset release request for each reset source according to each reset scheduling response signal and the reset type corresponding to each reset source, and sends each reset release request to the round-robin scheduling module.

[0114] Here, the reset release request can be used to inform the round-robin scheduling module that the reset request can be released. Its main function is to restore the normal working state of the system and ensure that each port in the PCIe system safely exits the reset state so that normal operation can resume.

[0115] Here, if it is a basic reset, you can wait for the reset source to fail to generate a reset source reset release request. If it is a hot reset, you can directly generate a reset source reset release request.

[0116] Without an appropriate reset release mechanism, different reset operations may conflict with each other, causing system instability. By using reset release requests, the reset and startup sequence of each reset source can be coordinated to avoid conflicts.

[0117] Through an orderly reset and reset release process, the overall reliability of the system can be improved.

[0118] Step 205 : The round-robin scheduling module receives each reset release application, performs round-robin scheduling on each reset release application, generates a reset release scheduling response signal corresponding to each reset release application, and sends each reset release scheduling response signal to the reset state machine.

[0119] Similarly, after receiving each reset release application, the round-robin scheduling module may cyclically allocate resources to each reset release application in a certain order to implement reset release of each reset source.

[0120] The round-robin scheduling module allocates a fixed time slice to each reset release request. During this time slice, the CPU will be fully allocated to the reset release request to execute the reset release of the reset source. When the time slice is exhausted, the CPU will be allocated to the next reset release request to execute the reset release request of the next reset source, and so on, forming a cycle. All waiting reset release requests are placed in the ready queue and scheduled in a round-robin manner according to the first-in-first-out principle.

[0121] The round-robin scheduling module receives each reset release application, performs round-robin scheduling on each reset release application, generates a port reset release signal to reset and release the ports reset by each reset source, and after the reset release is completed, generates a reset release scheduling response signal corresponding to each reset release application, and sends each reset release scheduling response signal to the reset state machine.

[0122] Step 206 : The reset state machine receives each reset release scheduling response signal, clears the reset request of each reset source and unlocks the reset signal according to each reset release scheduling response signal.

[0123] Here, when the reset state machine receives the reset release scheduling response signal from the reset source, it means that the ports corresponding to the reset source have been allowed to recover from the reset state. At this time, the reset state machine will update its internal status record, remove or mark the reset application of the reset source as completed or invalid, so as to clear the reset requests corresponding to each reset source and unlock the latched reset signal. The ports corresponding to the reset source can then return to normal working state.

[0124] In some optional embodiments, the reset state machine clears the reset request corresponding to each reset source and unlocks the reset signal according to each reset release scheduling response signal. Specifically, the reset state machine can clear the reset application corresponding to each reset source according to each reset release scheduling response signal, and after the reset state machine clears the reset application corresponding to all reset sources, the reset state machine generates a reset completion mapping table. Further, the reset state machine unlocks the reset signal of each reset source according to the reset completion mapping table.

[0125] Here, the reset completion mapping table may be used to indicate which reset source has completed the reset. In the reset completion mapping, each reset source corresponds to a bit.

[0126] For example, if there are 7 reset sources in the PCIe system, the reset completion map may include 7 bits, where each bit corresponds to a reset source.

[0127] In some optional implementations, the reset completion mapping table may refer to a state after the reset operation of each reset source is completed and the reset source mapping table is reset.

[0128] For example, the initial state of the reset source mapping table can be 0000000, where the virtual switch basic reset, upstream port hot reset, and downstream port secondary bus reset correspond to bits 1, 2, and 4 of the reset map, respectively. Then, the reset state machine can generate the reset source mapping table 1101000 based on the reset signals corresponding to each reset source.

[0129] After the reset state machine clears the reset requests corresponding to all reset sources, the reset state machine generates a reset completion mapping table, which may be to restore the reset source mapping table 1101000 to the initial state 0000000 of the reset source mapping table to indicate that each reset source has completed the reset.

[0130] In some optional implementations, the reset completion mapping table may also be an independent mapping table.

[0131] For example, the initial state of the reset completion mapping table may be 0000000, wherein the upstream port hot reset and the downstream port secondary bus reset require reset, and correspond to the 2nd and 4th bits of the reset completion mapping table respectively.

[0132] Then, after the upstream port hot reset and the downstream port secondary bus reset are completed, a reset completion mapping table 0101000 may be generated to indicate that both the upstream port hot reset and the downstream port secondary bus reset have been completed.

[0133] In some optional implementations, after the round-robin scheduling module receives each of the reset requests, steps 207 and 208 may be further included.

[0134] Step 207: The round-robin scheduling module generates a physical layer reset signal of each reset source according to each reset request and the linked physical layer reset control signal, and sends each physical layer reset signal to the physical layer module.

[0135] Here, the linked physical layer reset control signal may be used to indicate which physical layers need to be reset.

[0136] Here, the round-robin scheduling module can determine which physical layers need to be reset under the reset source based on the reset application of each reset source and the linkage physical layer reset control signal, generate corresponding physical layer reset signals, and then send the physical layer reset signals to the physical layer module.

[0137] Step 208: The physical layer module receives each physical layer reset signal, and resets the physical layer of the corresponding reset source according to each physical layer reset signal.

[0138] After receiving the physical layer reset signal sent by the round-robin scheduling module, the physical layer module processes the physical layer reset signal received from the round-robin scheduling module. Each physical layer reset signal corresponds to a specific reset source, that is, the hardware that needs to be reset under this reset source. The physical layer module performs the corresponding reset operation based on the physical layer reset signal to ensure that each physical layer that needs to be reset can correctly enter the initial state.

[0139] In some optional implementations, after the round-robin scheduling module receives each reset release request, step 209 and step 210 may be further included.

[0140] Step 209: The round-robin scheduling module generates a physical layer reset release signal of each reset source according to each reset release request and the linked physical layer reset release control signal, and sends each physical layer reset release signal to the physical layer module.

[0141] Here, the linked physical layer reset control release signal may be used to indicate which physical layers need to be reset and released.

[0142] The round-robin scheduling module can determine which physical layers need to be reset under the reset source based on the reset application of each reset source and the linkage physical layer reset control signal, generate the corresponding physical layer reset signal, and then send the physical layer reset signal to the physical layer module.

[0143] Here, after receiving the reset release request, the round-robin scheduling module can determine which physical layers need to be reset released under the reset source based on the reset release request and the linked physical layer reset release control signal, and generate the corresponding physical layer reset release signal. Then, the physical layer reset release signal is sent to the physical layer module.

[0144] Step 210: The physical layer module receives each physical layer reset release signal, and resets and releases the physical layer of the corresponding reset source according to each physical layer reset release signal.

[0145] After receiving the reset release signals from each physical layer, the physical layer module processes the reset release signals received from the round-robin scheduling module and performs the corresponding reset release operation. This allows the corresponding physical layer to return to normal operation mode from the reset state, allowing the previously reset physical layer to resume operation.

[0146] The following describes each step in conjunction with the state of the reset state machine:

[0147] The reset state machine can receive a reset signal from at least one reset source, latch each reset signal, and enter a reset application state.

[0148] The reset state machine generates a reset request for each reset source according to the reset signal and reset type corresponding to each reset source in the reset application state, and sends each reset request to the round-robin scheduling module.

[0149] The round-robin scheduling module receives each reset application, performs round-robin scheduling on each reset application, generates a reset scheduling response signal corresponding to each reset application, and sends each reset scheduling response signal to the reset state machine.

[0150] The reset state machine receives each reset scheduling response signal in the reset application state. When all reset applications are fully responded to, the reset state machine enters the reset release waiting state. In the reset waiting state, the reset state machine generates a reset release application for each reset source according to each reset scheduling response signal and the reset type corresponding to each reset source, and sends each reset release application to the round-robin scheduling module.

[0151] The round-robin scheduling module receives each reset release application, performs round-robin scheduling on each reset release application, generates a reset release scheduling response signal corresponding to each reset release application, and sends each reset release scheduling response signal to the reset state machine.

[0152] The reset state machine receives each reset release scheduling response signal in the reset release state. When all reset release requests are responded to, the reset state machine enters the reset completion state. In the reset completion state, the reset state machine clears the reset request corresponding to each reset source and unlocks the reset signal according to each reset release scheduling response signal.

[0153] An embodiment of the present disclosure provides a reset processing method based on multiple reset sources, wherein a reset state machine receives a reset signal from at least one reset source and latches each reset signal; the reset state machine generates a reset application corresponding to each reset source according to the reset signal and reset type corresponding to each reset source, and sends each reset application to a round-robin scheduling module; the round-robin scheduling module receives each reset application, schedules each reset application, generates a reset scheduling response signal corresponding to each reset application, and sends each reset scheduling response signal to the reset state machine; the reset state machine receives each reset scheduling response signal, generates a reset release application for each reset source according to each reset scheduling response signal and the reset type corresponding to each reset source, and sends each reset release application to the round-robin scheduling module; the round-robin scheduling module receives each reset release application, schedules each reset release application, generates a reset release scheduling response signal corresponding to each reset release application, and sends each reset release scheduling response signal to the reset state machine; the reset state machine clears the reset request corresponding to each reset source and unlocks the reset signal according to each reset release scheduling response signal. The present disclosure receives and latches reset signals from different reset sources through a reset state machine, ensuring that each reset request can be accurately captured and processed, and then sends the reset application corresponding to each reset source to the round-robin scheduling module for scheduling, thereby realizing orderly processing of reset signals of multiple reset sources. Then, after the reset state machine receives the reset scheduling response signal, it will generate a reset release application and send it to the round-robin scheduling module again. The round-robin scheduling module schedules these reset release applications and generates a reset release scheduling response signal and sends it to the reset state machine. Finally, the reset state machine will clear the corresponding reset application according to the reset release scheduling response signal and unlock the corresponding reset signal, realizing selective response to multiple reset requests according to the needs of different scenarios, and can process multiple reset requests in an orderly and fair manner, thereby improving the reliability and stability of the system.

[0154] The present disclosure can be applied to FPGA (Field-Programmable Gate Array), has good performance and a simple structure, can be used in a single chip, and can also be applied to large-scale chip configuration design, not limited to PCIe switch reset design.

[0155] Further references Figure 3 As an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a reset processing system based on multiple reset sources. Figure 2 Corresponding to the method embodiment shown, the system may specifically include a reset state machine and a round-robin scheduling module.

[0156] like Figure 3As shown, the reset processing system based on multiple reset sources of this embodiment, the system 300 includes: a reset state machine 301 and a round-robin scheduling module 302, wherein the reset state machine 301 is used to receive the reset signal of at least one reset source and latch each reset signal; the reset state machine 301 is also used to generate a reset application corresponding to each reset source according to the reset signal and reset type of each reset source, and send each reset application to the round-robin scheduling module; the round-robin scheduling module 302 receives each reset application, performs round-robin scheduling on each reset application, generates a reset scheduling response signal for each reset application, and sends each reset scheduling response signal to Reset state machine; the reset state machine 301 is also used to receive each reset scheduling response signal, generate a reset release application for each reset source according to each reset scheduling response signal and the reset type of each reset source, and send each reset release application to the round-robin scheduling module; the round-robin scheduling module 302 is also used to receive each reset release application, perform round-robin scheduling on each reset release application, generate a reset release scheduling response signal corresponding to each reset release application, and send each reset release scheduling response signal to the reset state machine; the reset state machine 301 is also used to clear the reset request of each reset source and unlock the reset signal according to each reset release scheduling response signal.

[0157] In this embodiment, the specific processing of the reset state machine 301 and the round-robin scheduling module 302 and the technical effects thereof can be referred to in Figure 2 The relevant descriptions of steps 201 to 210 in the corresponding embodiment are not repeated here.

[0158] In some optional implementations, after the round-robin scheduling module receives each reset request, the reset processing system based on multiple reset sources of this embodiment further includes a physical layer module 303. The round-robin scheduling module 302 and the physical layer module 303 may be further configured as follows:

[0159] The round-robin scheduling module 302 is further configured to generate a physical layer reset signal of each reset source according to each reset request and the linkage physical layer reset control signal, and send each physical layer reset signal to the physical layer module;

[0160] The physical layer module 303 is configured to receive each physical layer reset signal and reset the physical layer of the corresponding reset source according to each physical layer reset signal.

[0161] In some optional implementations, after the round-robin scheduling module receives each reset release request, the round-robin scheduling module 302 and the physical layer module 303 may be further configured to:

[0162] The round-robin scheduling module 302 is further configured to generate a physical layer reset release signal for each reset source according to each reset release request and the linked physical layer reset release control signal, and send each physical layer reset release signal to the physical layer module;

[0163] The physical layer module 303 is further configured to receive each physical layer reset release signal, and reset and release the physical layer of the corresponding reset source according to each physical layer reset release signal.

[0164] In some optional implementations, the reset state machine 301 may be further configured as follows:

[0165] The reset state machine 301 is further configured to update the reset source mapping table according to the reset signal and reset type of each reset source and generate a reset port vector corresponding to each reset source;

[0166] The reset state machine 301 is further configured to generate a reset request for each reset source according to the updated reset source mapping table and each reset port vector, wherein the reset request includes the reset port vector of the reset source.

[0167] In some optional implementations, the reset type of the reset source includes a basic reset and a warm reset.

[0168] In some optional implementations, the reset state machine 301 may be further configured as follows:

[0169] The reset state machine 301 is further configured to generate a basic reset port vector according to the reset signal of the reset source and the basic reset;

[0170] The reset state machine 301 is further configured to generate a hot reset port vector according to the reset signal of the reset source and the hot reset.

[0171] In some optional implementations, the reset state machine 301 may be further configured as follows:

[0172] The reset state machine 301 is further configured to generate a reset request corresponding to each reset source according to a reset type with a higher priority among the port basic reset and the hot reset and the reset signal of each reset source corresponding to the type.

[0173] In some optional implementations, the reset state machine 301 may be further configured as follows:

[0174] The reset state machine 301 is further configured to clear the reset application of each reset source according to each reset release scheduling response signal and generate a reset completion map after the reset state machine clears the reset application corresponding to all reset sources;

[0175] The reset state machine 301 is further configured to unlock the reset signal of each reset source according to the reset completion mapping table.

[0176] It should be noted that the implementation details and technical effects of each unit in the reset processing system based on multiple reset sources provided by the embodiments of the present disclosure can be referred to the description of other embodiments in the present disclosure and will not be repeated here.

[0177] It should be noted that the computer-readable medium mentioned in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable storage media may include, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such a propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wire, optical cable, RF (radio frequency), or any suitable combination thereof.

[0178] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0179] The computer readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device can realize the following operation: Figure 3 The illustrated embodiment and its optional implementations illustrate a reset processing method based on multiple reset sources.

[0180] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0181] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0182] The units involved in the embodiments described in this disclosure may be implemented in software or hardware. In some cases, the name of a unit does not limit the unit itself. For example, an acquisition unit may also be described as a "unit for acquiring configuration information."

[0183] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the scope of the above disclosure. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A reset processing method based on multiple reset sources, characterized in that: The method comprises: The reset state machine receives a reset signal from at least one reset source and latches each of the reset signals; The reset state machine generates a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, and sends each reset request to the round-robin scheduling module; The round-robin scheduling module receives each of the reset applications, performs round-robin scheduling on each of the reset applications, generates a reset scheduling response signal for each of the reset applications, and sends each of the reset scheduling response signals to the reset state machine; The reset state machine receives each of the reset scheduling response signals, generates a reset release request for each of the reset sources according to each of the reset scheduling response signals and the reset type of each of the reset sources, and sends each of the reset release requests to the round-robin scheduling module; The round-robin scheduling module receives each of the reset release applications, performs round-robin scheduling on each of the reset release applications, generates a reset release scheduling response signal corresponding to each of the reset release applications, and sends each of the reset release scheduling response signals to the reset state machine; The reset state machine receives each of the reset release scheduling response signals, clears the reset request of each of the reset sources and unlocks the reset signal according to each of the reset release scheduling response signals.

2. The method according to claim 1, characterized in that After the round-robin scheduling module receives each of the reset requests, the method further includes: The round-robin scheduling module generates a physical layer reset signal of each reset source according to each reset application and the linkage physical layer reset control signal, and sends each physical layer reset signal to the physical layer module; The physical layer module receives each of the physical layer reset signals, and resets the physical layer of the corresponding reset source according to each of the physical layer reset signals.

3. The method according to claim 1, characterized in that After the round-robin scheduling module receives each reset release request, the method further includes: The round-robin scheduling module generates a physical layer reset release signal of each reset source according to each reset release application and the linkage physical layer reset release control signal, and sends each physical layer reset release signal to the physical layer module; The physical layer module receives each of the physical layer reset release signals, and resets and releases the physical layer of the corresponding reset source according to each of the physical layer reset release signals.

4. The method according to claim 1, wherein The reset state machine generates a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, including: The reset state machine updates a reset source mapping table according to the reset signal and the reset type of each reset source and generates a reset port vector of each reset source; The reset state machine generates the reset request for each of the reset sources according to the updated reset source mapping table and each of the reset port vectors, wherein the reset request includes the reset port vector of the reset source.

5. The method according to claim 4, characterized in that The reset type of the reset source includes a basic reset and a warm reset.

6. The method according to claim 5, characterized in that The reset state machine generates a reset port vector of each reset source according to the reset signal and the reset type of each reset source, including: The reset state machine generates a basic reset port vector according to the reset signal of the reset source and the basic reset; The reset state machine generates a warm reset port vector according to the reset signal of the reset source and the warm reset.

7. The method according to claim 6, characterized in that When the basic reset and the hot reset conflict, the reset state machine sends each reset request to the round-robin scheduling module, including: The reset state machine generates a reset request corresponding to each reset source according to a reset type with a higher priority among the basic reset and the hot reset and a reset signal of each reset source corresponding to the type.

8. The method according to claim 1, characterized in that The reset state machine clears the reset application of each reset source and unlocks the reset signal according to each reset release scheduling response signal, including: The reset state machine clears the reset request of each reset source according to each reset release scheduling response signal, and after the reset state machine clears the reset requests corresponding to all reset sources, the reset state machine generates a reset completion mapping table; The reset state machine unlocks the reset signal of each reset source according to the reset completion mapping table.

9. A reset processing system based on multiple reset sources, characterized in that: The system comprises: A reset state machine, configured to receive a reset signal from at least one reset source and latch each of the reset signals; The reset state machine is further configured to generate a reset request corresponding to each reset source according to the reset signal and reset type of each reset source, and send each reset request to the round-robin scheduling module; The round-robin scheduling module is configured to receive each of the reset applications, perform round-robin scheduling on each of the reset applications, generate a reset scheduling response signal for each of the reset applications, and send each of the reset scheduling response signals to the reset state machine; The reset state machine is further configured to receive each of the reset scheduling response signals, generate a reset release request for each of the reset sources according to each of the reset scheduling response signals and the reset type of each of the reset sources, and send each of the reset release requests to the round-robin scheduling module; The round-robin scheduling module is further configured to receive each of the reset release applications, perform round-robin scheduling on each of the reset release applications, generate a reset release scheduling response signal corresponding to each of the reset release applications, and send each of the reset release scheduling response signals to the reset state machine; The reset state machine is further configured to receive each of the reset release scheduling response signals, clear the reset application of each of the reset sources and unlock the reset signal according to each of the reset release scheduling response signals.

10. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon, When one or more programs are executed by one or more processors, the one or more processors are caused to implement the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by one or more processors, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product, characterized in that The method comprises a computer program / instruction, which implements the method according to any one of claims 1 to 8 when the computer program / instruction is executed by a processor.

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