Electrophysiological signal processing device and processing method

Abstract

The present application relates to the field of brain-computer interface technology, and in particular to an electrophysiological signal processing device and processing method. The device includes a multi-channel time series signal bus, including multiple segmented processing nodes, which are used to unidirectionally transmit electrophysiological signals with the electrophysiological signal sampling time point as the stream synchronization signal; an electrophysiological signal processing unit, including an electrophysiological analog-to-digital converter interface, which is used to obtain electrophysiological signals at each segmented processing node and pre-process the electrophysiological signals; the pre-processed electrophysiological signals are unidirectionally transmitted to the subsequent segmented processing nodes through the multi-channel time series signal bus for electrophysiological state analysis; an event synchronization unit receives an external trigger event signal through its own trigger line and encoding line, determines the electrophysiological signal sampling point corresponding to the time point of the trigger event, and is used to mark and synchronously process the electrophysiological signals, so as to provide an integrated acquisition, storage and calculation system to improve the real-time performance and synchronization accuracy of data processing.

Description

Technical Field

[0001] The present application relates to the field of brain-computer interface technology, and more specifically, to an electrophysiological signal processing device and processing method. Background Art

[0002] Brain-computer interfaces encompass all means of acquiring brain activity, but currently the only mature, inexpensive, and practically applicable approach is the EEG-based BCI. EEG acquisition devices are essential, and BCIs are inherently computationally intensive, requiring stable data collection from electrodes on the human head, along with relatively complex algorithmic calculations and command classification, in order to output useful control commands or obtain brain status monitoring data.

[0003] Various technologies related to brain-computer interfaces (BCIs) are rapidly developing. Currently, a major pain point in their practical application is real-time performance. Due to their intense research focus, nearly all reported BCI systems are typically based on a high-performance EEG machine coupled with a high-performance PC. The EEG machine is solely responsible for amplifying and collecting EEG signals, while the PC handles all remaining data processing. This involves large amounts of data, and machine learning algorithms may require the assistance of expensive and energy-intensive GPUs. This approach has proven scalable, offering the advantage of flexible software algorithms. However, PC-based systems inevitably suffer from poor real-time performance.

[0004] Real-time data processing is a crucial primary metric for brain-computer interface (BCI) applications, contributing significantly to the ultimate brain-computer information transfer rate (ITR). It is also a key performance factor in BCIs with real-time feedback and human error warnings. However, due to the non-real-time nature of the operating system and the complexity of hardware and software driver interfaces, PCs often require delayed synchronization and are unable to perform tasks requiring precise synchronous triggering.

[0005] Furthermore, if a brain-computer interface requires a high-performance computer, its practical application and widespread adoption are severely limited. Therefore, the technical challenge of providing a comprehensive system capable of performing all the brain-computer interface acquisition, storage, and computation processes, achieving integrated acquisition, storage, and computation, has become a pressing issue. Summary of the Invention

[0006] In view of this, the present application provides an electrophysiological signal processing device and processing method to provide an integrated acquisition, storage and computing system to improve the real-time performance and synchronization accuracy of data processing.

[0007] In a first aspect, the present application provides an electrophysiological signal processing device, comprising a multi-channel time series signal bus, an electrophysiological signal processing unit mounted on the multi-channel time series signal bus, and an event synchronization unit;

[0008] The multi-channel time series signal bus includes a plurality of segmented processing nodes for unidirectionally transmitting electrophysiological signals using electrophysiological signal sampling time points as stream synchronization signals;

[0009] The electrophysiological signal processing unit includes an electrophysiological analog-to-digital converter interface for acquiring electrophysiological signals at each segmented processing node and preprocessing the electrophysiological signals; the preprocessed electrophysiological signals are unidirectionally transmitted via the multi-channel time series signal bus to one or more subsequent segmented processing nodes for electrophysiological state analysis;

[0010] The event synchronization unit is connected to the electrophysiological analog-to-digital converter interface, receives an external trigger event signal through its own trigger line and encoding line, and determines the electrophysiological signal sampling point corresponding to the time point when the trigger event occurs.

[0011] In one possible implementation, the electrophysiological signal processing unit further includes an electrode module, a preamplifier conditioning circuit, and a multi-channel analog-to-digital converter;

[0012] The electrode module is used to collect electrophysiological signals;

[0013] The preamplifier conditioning circuit is used to amplify and filter the collected electrophysiological signals;

[0014] The multi-channel analog-to-digital converter is used to convert the collected electrophysiological signals into digital signals at a preset sampling rate, and transmit the converted electrophysiological signals to the electrophysiological analog-to-digital converter interface through the analog-to-digital converter data output bus interface.

[0015] One possible implementation manner further includes a data storage unit for intercepting and storing electrophysiological signals at any segment processing node.

[0016] In one possible implementation, the multi-channel time series signal bus is based on programmable logic, and the transmission of electrophysiological signals between adjacent segmented processing nodes is accomplished through high-speed synchronous FIFO logic.

[0017] In one possible implementation, the event synchronization unit includes a trigger line and an external encoding line for triggering the input of an electrophysiological signal, and classifying event types through the trigger line, the external encoding line or the event synchronization unit itself.

[0018] One possible implementation method for classifying event types through a trigger line, an external encoding line, or the event synchronization unit itself includes:

[0019] Classify events by corresponding predefined event codes to different trigger lines; or,

[0020] Input the event type through the external encoding line and use a trigger line to latch the event type;

[0021] The event synchronization unit is directly connected to the electrophysiological analog-to-digital converter interface block, and the acquired event information is used as a data channel for transmission and processing.

[0022] In a second aspect, the present application provides an electrophysiological signal processing method, applied to the electrophysiological signal processing device as described in any one of the first aspects, comprising:

[0023] Using the sampling time point of the electrophysiological signal as a stream synchronization signal, and using a multi-channel time series signal bus to transmit the electrophysiological signal in segments;

[0024] At each segment processing node, the input electrophysiological signal is pre-processed and unidirectionally transmitted to one or more segment processing nodes at the subsequent stage through the multi-channel time series signal bus for electrophysiological state analysis;

[0025] An external trigger event signal is received, an electrophysiological signal sampling point corresponding to the time point of the trigger event is determined, and the electrophysiological signal is marked and synchronously processed based on the electrophysiological signal sampling point.

[0026] In one possible implementation, preprocessing the input electrophysiological signal includes amplifying and filtering the collected electrophysiological signal; and converting the collected electrophysiological signal into a digital signal at a preset sampling rate based on a multi-channel analog-to-digital converter.

[0027] Compared with the existing technology, the technical solution provided by this application has the following beneficial effects:

[0028] 1. Achieving theoretically optimal real-time data processing, improving the response and control speed of biofeedback / control-based brain-computer interface paradigms. Because a dedicated physical bus is designed based on sequential data processing principles, and the effective spectrum of the electrophysiological signal itself is relatively narrow, large-scale circuit computing or parallel processors (clusters) with sufficient frequency can theoretically achieve output of a data processing result via the bus within a single data sampling interval. The delay from the actual sampling point to the time that data is used to output the processing result is determined solely by the number of sequential signal processing links mounted on the bus. This can theoretically be calculated using the following formula: Delay = Sampling Interval * Number of Signal Processing Links.

[0029] Since the entire data processing link does not involve data encoding and decoding, packaging and unpacking operations, and all data processing is done in a streaming manner, a large amount of communication overhead is saved; and the pure hardware design directly avoids the delay caused by the weak processing result / control information output link of the traditional brain-computer interface system, thereby improving the response and control speed.

[0030] Second, the synchronized recording of external events achieves theoretically the highest accuracy. Because the synchronized recording module utilizes pure digital logic circuitry, with a reserved direct-connect trigger line node, and is directly connected to the electrophysiological analog-to-digital converter interface module and synchronized with the bus's sampling clock signal, it achieves the theoretically most accurate synchronized recording of external events. Even under the most unfavorable circumstances, the timing error will not exceed one sampling interval.

[0031] 3. It can achieve low-power, high-energy-efficiency, and portable data processing. Since the signal acquisition, processing, and storage systems all use a fully hardware-embedded processing solution, most of the digital logic circuits and acceleration processing cores are developed and selected to adapt to electrophysiological signals. Compared with general PCs, its power consumption is extremely low. Under the premise of achieving the same computational complexity of the brain-computer interface algorithm, the system energy efficiency can be greatly improved. In addition, its small size makes it easy to design into portable or wearable products. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a structural diagram of an electrophysiological signal processing device provided in Example 1 of the present application.

[0033] Figure 2 This is a flowchart of an electrophysiological signal processing method provided in Example 2 of the present application. DETAILED DESCRIPTION

[0034] The following will combine the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0035] This application addresses the limitations of existing brain-computer interface technology and, with a large-scale modular system-level programmable logic array chip as its core, constructs an embedded system that integrates data storage and computing with the brain-computer interface. This system achieves data processing capabilities comparable to those of a PC in a wearable form factor. The technical solutions provided by this application are described in detail below, with reference to specific embodiments.

[0036] Example 1

[0037] See also Figure 1 , is a structural diagram of an electrophysiological signal processing device provided in Example 1 of this application. Figure 1As shown in FIG, the electrophysiological signal processing device includes a channel time series signal bus 1, an electrophysiological signal processing unit 2, and an event synchronization unit 3. Based on the entire processing flow of the electrophysiological signal processing device, the electrophysiological signal processing unit 2 performs a series of preprocessing and intermediate processing on the input electrophysiological signal, and finally transmits it to the corresponding segmented processing node for signal feature interpretation and classification, and outputs the processing results of the electrophysiological signal, forming a unidirectional transmission hardware pipeline.

[0038] The entire pipeline is governed by the aforementioned multi-channel time series signal bus 1, with the sampling time of the electrophysiological signals serving as the pipeline's tick. To achieve theoretically optimal real-time performance within each tick formed by the sampling interval, each segmented processing node must complete an output update of the multi-channel data processing results for signal interpretation and classification, ultimately producing the final analysis results.

[0039] Specifically, the multi-channel time series signal bus 1 is composed of multiple segmented processing nodes, each of which is responsible for a specific signal processing task, aiming to provide an efficient hardware-based sequential processing architecture for electrophysiological signal processing. Its core lies in using the sampling time point of the electrophysiological signal as the synchronization signal of the entire bus to ensure the real-time and accuracy of data processing. The conflict-free transmission of intermediate data is achieved through a sequential arbitrator. Each processing node only contains one input and one output, and the data transmission direction is unidirectional, which simplifies the system design and improves the reliability of data transmission. In addition, the master node of the bus is controlled by a processor core, but the data flow does not necessarily pass through the core, which provides greater flexibility and scalability for the system. The multi-transmission capability of the segmented processing node allows the digital signal storage module to intercept the signal at any node for storage, which facilitates the subsequent analysis and processing of the data.

[0040] During the transmission of electrophysiological signals, the sampling time point is used as the synchronization signal to ensure the synchronization of the signal between various nodes. For example, in brain wave monitoring, the electrical activity signals of different brain regions need to be precisely synchronized in order to analyze the overall functional state of the brain. In addition, the multi-channel time series signal bus 1 is based on programmable logic. The bandwidth of electrophysiological signals is limited and only one-way transmission is required. The signal transmission between adjacent segmented processing nodes is completed through high-speed synchronous FIFO logic, which has low delay, high throughput and low resource consumption, thereby greatly improving the speed and stability of signal transmission, reducing delays and errors in data transmission, and meeting the needs of real-time monitoring.

[0041] Further, if Figure 1As shown in , each segmented processing node includes an input and an output. The output allows for multiple transmissions in one direction, meaning it can be sent to one or more subsequent segmented processing nodes. This allows for algorithmic implementation using different analysis processes starting at a specific segmented processing node, ultimately converging and merging the output to improve result quality. In one implementation, to address the needs of multi-channel electrophysiological signal processing, this solution achieves efficient EEG data processing by integrating various types of digital logic circuits, DSP circuit modules, dedicated DSP cores (clusters), and high-performance general-purpose processor cores on a physical bus. This design allows for the selection of the most appropriate processing circuit module or dedicated processor based on specific processing requirements, thereby improving data processing efficiency and accuracy. For example, algorithms such as filtering and waveform segmentation can be implemented using a multi-core, multi-transmit sequential hard DSP core; while machine learning-based interpretation models can utilize a hard NPU core for result output. This flexible modular design enables the system to adapt to various real-time processing algorithms and methods, meeting the needs of diverse application scenarios.

[0042] At the same time, the unidirectional multi-transmit structure can directly output to data storage unit 4. Data storage unit 4 can arbitrarily select the output results of a segmented processing node for storage. In this embodiment, data storage unit 4 utilizes hardware logic and uses a standard SDIO interface to mount a large-capacity MicroSD card (TF card) for selective data storage and writing. Data storage unit 4 is connected to the multi-channel time series signal bus 1 and can intercept and store electrophysiological signals at any segmented processing node, providing a rich data source for later analysis and processing.

[0043] The electrophysiological signal processing unit 2 is responsible for preprocessing and analyzing the collected electrophysiological signals. Figure 1 As shown in FIG, the unit includes an electrode module 21, a preamplifier conditioning circuit 22, a multi-channel analog-to-digital converter 23 and an electrophysiological analog-to-digital converter interface module 24.

[0044] The electrode module 21 is specifically used to collect EEG signals from the cerebral cortex. The collected weak EEG signals are first transmitted to the preamplifier and conditioning circuit 22. The collected EEG signals are initially amplified and filtered by the preamplifier and conditioning circuit 22 to improve the quality and strength of the EEG signals, ensuring that the collected EEG signals have sufficient amplitude and low noise level, thereby improving the signal processing accuracy and reliability of the entire system.

[0045] The preamplifier conditioning circuit 22 is connected to the multi-channel analog-to-digital converter 23 to send the processed EEG signal to the next stage for analog-to-digital conversion.

[0046] The multi-channel analog-to-digital converter 23 is specifically used to convert the pre-amplified and conditioned EEG signals into digital signals at a set sampling rate, and transmit the digitized EEG signals via a specific data output bus interface. Optionally, the specific data output bus interface can be an SPI serial bus. Of course, other data output buses can be configured according to actual circumstances, and this embodiment of the present application does not specifically limit this.

[0047] The electrophysiological analog-to-digital converter interface module 24 is connected to the data output bus interface of the multi-channel analog-to-digital converter 23 and is used to receive the digitized EEG signals from the multi-channel analog-to-digital converter 23. The digitized EEG signals are introduced into the system-on-chip for further processing, and event synchronization information is combined with the EEG signals to provide a basis for accurate event-related analysis.

[0048] The above-mentioned event synchronization recording module 3 is specifically used to determine the electrophysiological signal sampling point corresponding to the time point of the event by receiving the external trigger event signal, thereby realizing the marking and synchronous processing of the electrophysiological signal. The unit includes a trigger line and a coding line, which can classify events according to different trigger signals and codes. Specifically, the event synchronization recording module 3 is connected to the external input trigger signal buffer module through its own trigger line and coding line, thereby receiving the external trigger event signal, recording the electrophysiological signal sampling point corresponding to the time point of the trigger event, and transmitting and processing the event information as a special data channel. Figure 1 As shown in , the event synchronization recording module is connected to the electrophysiological analog-to-digital converter interface 24 to achieve the most accurate event synchronization time point recording in theory, and provide accurate time point channel data flow and event type information for subsequent processing. Specifically, the event type can be encoded and input, or the event type can be judged through different trigger lines. There are three methods for distinguishing the type of trigger events in the trigger electrical signal input unit, and all three can exist at the same time: one is to classify events by directly corresponding to predefined event codes through different trigger lines; the second is to input the event type through an external encoding line and use a specific trigger line to latch the event type; the third is to directly connect the event synchronization recording module to the electrophysiological analog-to-digital converter interface module, and the output data is transmitted and processed as a special data channel, and the recording frequency is consistent with the signal sampling rate, thereby ensuring the accuracy and real-time performance of event synchronization recording.

[0049] This solution focuses on recording the electrophysiological signal sampling points corresponding to the time of the trigger event with the highest accuracy. The event synchronization recording module is implemented using pure logic circuits, featuring high efficiency and low latency. The module is directly connected to the trigger electrical signal input via several trigger lines, enabling rapid response to trigger events. The trigger electrical signal input provides three methods for distinguishing the type of trigger event: using predefined event codes corresponding to non-trigger lines, inputting event types via external coding lines, and using the event recording module's own logical judgment. These methods can be used individually or in combination to meet event classification requirements in different scenarios.

[0050] Compared with the prior art, the technical solution provided in Example 1 of the present application has the following beneficial effects:

[0051] 1. Achieving theoretically optimal real-time data processing, improving the response and control speed of biofeedback / control-based brain-computer interface paradigms. Because a dedicated physical bus is designed based on sequential data processing principles, and the effective spectrum of the electrophysiological signal itself is relatively narrow, large-scale circuit computing or parallel processors (clusters) with sufficient frequency can theoretically achieve output of a data processing result via the bus within a single data sampling interval. The delay from the actual sampling point to the time that data is used to output the processing result is determined solely by the number of sequential signal processing links mounted on the bus. This can theoretically be calculated using the following formula: Delay = Sampling Interval * Number of Signal Processing Links.

[0052] Since the entire data processing link does not involve data encoding and decoding, packaging and unpacking operations, and all data processing is done in a streaming manner, a large amount of communication overhead is saved; and the pure hardware design directly avoids the delay caused by the weak processing result / control information output link of the traditional brain-computer interface system, thereby improving the response and control speed.

[0053] Second, the synchronized recording of external events achieves theoretically the highest accuracy. Because the synchronized recording module utilizes pure digital logic circuitry, with a reserved direct-connect trigger line node, and is directly connected to the electrophysiological analog-to-digital converter interface module and synchronized with the bus's sampling clock signal, it achieves the theoretically most accurate synchronized recording of external events. Even under the most unfavorable circumstances, the timing error will not exceed one sampling interval.

[0054] 3. It can achieve low-power, high-energy-efficiency, and portable data processing. Since the signal acquisition, processing, and storage systems all use a fully hardware-embedded processing solution, most of the digital logic circuits and acceleration processing cores are developed and selected to adapt to electrophysiological signals. Compared with general PCs, its power consumption is extremely low. Under the premise of achieving the same computational complexity of the brain-computer interface algorithm, the system energy efficiency can be greatly improved. In addition, its small size makes it easy to design into portable or wearable products.

[0055] Example 2

[0056] See also Figure 2 , is a flow chart of an electrophysiological signal processing method provided in Example 2 of this application. Figure 2 As shown in , the specific implementation steps of the above method include:

[0057] Step 101: Using the sampling time points of the electrophysiological signals as stream synchronization signals, the electrophysiological signals are segmented and transmitted using a multi-channel time series signal bus.

[0058] Specifically, the sampling time point of the electrophysiological signal is used as the synchronization signal source of the bus, so that each processing node can accurately complete the data processing task within each sampling interval, avoiding waiting and delays in the data processing process. The advantage of this synchronization mechanism is that it can ensure that the entire process from signal acquisition to final result output is carried out under strict time control, thereby achieving theoretically optimal real-time performance. In addition, since data transmission is unidirectional and data transfer between adjacent processing nodes is completed through high-speed synchronous FIFO logic, this design not only reduces latency, but also improves data throughput, enabling the system to efficiently process large-scale EEG data. In practical applications, this means that the system can complete the analysis and processing of a large number of EEG signals in a relatively short period of time, providing strong support for real-time monitoring of brain status or output of control instructions.

[0059] Step 102: At each segment processing node, pre-process the input electrophysiological signal and transmit it unidirectionally to one or more segment processing nodes at the subsequent stage through a multi-channel time series signal bus for electrophysiological state analysis.

[0060] The preprocessing includes amplification, filtering, and analog-to-digital conversion of electrophysiological signals to facilitate subsequent electrophysiological state analysis, which includes but is not limited to feature extraction, pattern recognition, and state monitoring and assessment.

[0061] Step 103: Receive an external trigger event signal, determine the electrophysiological signal sampling point corresponding to the time when the trigger event occurs, and mark and synchronize the electrophysiological signal based on the electrophysiological signal sampling point.

[0062] Specifically, receiving event signals is a critical step in achieving precise labeling and synchronization of electrophysiological signals. Its accuracy directly impacts the reliability and effectiveness of subsequent signal analysis. As the primary channels for receiving event signals, the design and implementation of trigger and encoding lines are crucial. The trigger line receives external trigger event signals, such as experimental stimulus signals or subject response signals. Its design must ensure rapid signal transmission and accurate identification. The encoding line inputs event type information and classifies and encodes different event signals. The encoding line design must meet the requirements of diversity and flexibility to accommodate the changing event types under different experimental conditions. Multiple encoding lines can be configured, each corresponding to a specific event code, or multi-level encoding can be used to transmit multiple event codes on a single encoding line. For example, in cognitive neuroscience experiments, encoding lines can be used to distinguish different cognitive tasks or stimulus types. Through different encoding combinations, event signals can be associated with corresponding cognitive processes, providing important reference information for subsequent signal analysis.

[0063] Compared with the prior art, the technical solution provided in Example 2 of the present application has the following beneficial effects:

[0064] Based on the electrophysiological signal processing method provided by this application, the sampling time point of the electrophysiological signal is used as the stream synchronization signal, and the multi-channel time series signal bus is used to realize the segmented transmission of the electrophysiological signal, ensuring the efficient and accurate transmission of the signal between multiple processing nodes, reducing data delay and distortion. Each segmented processing node can independently pre-process the input electrophysiological signal, including operations such as amplification, filtering and analog-to-digital conversion, which not only improves the quality of the signal, but also enhances the parallel processing capability of the system, thereby speeding up the overall analysis speed. In addition, by receiving and parsing the external trigger event signal, the electrophysiological signal sampling point corresponding to the time point of the trigger event is accurately determined, and the electrophysiological signal is marked and synchronously processed accordingly, so that the system can accurately capture key physiological events in a complex experimental environment, providing reliable data support for subsequent research. This method significantly improves the accuracy and efficiency of electrophysiological signal processing, and is suitable for real-time monitoring and analysis scenarios of various electrophysiological signals such as electrocardiograms and electroencephalograms that require high time resolution and accuracy.

[0065] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. An electrophysiological signal processing device, characterized in that: It includes a multi-channel time series signal bus, an electrophysiological signal processing unit mounted on the multi-channel time series signal bus, and an event synchronization unit; The multi-channel time series signal bus includes a plurality of segmented processing nodes for unidirectionally transmitting electrophysiological signals using electrophysiological signal sampling time points as stream synchronization signals; The electrophysiological signal processing unit includes an electrophysiological analog-to-digital converter interface, which is used to obtain electrophysiological signals at each segment processing node and pre-process the electrophysiological signals; The pre-processed electrophysiological signal is unidirectionally transmitted through the multi-channel time series signal bus to one or more segmented processing nodes of the subsequent stage for electrophysiological state analysis; The event synchronization unit is connected to the electrophysiological analog-to-digital converter interface, receives the external trigger event signal through its own trigger line and encoding line, determines the electrophysiological signal sampling point corresponding to the time when the trigger event occurs, and is used to mark and synchronize the electrophysiological signal.

2. The electrophysiological signal processing device according to claim 1, characterized in that: The electrophysiological signal processing unit also includes an electrode module, a preamplifier conditioning circuit and a multi-channel analog-to-digital converter; The electrode module is used to collect electrophysiological signals; The preamplifier conditioning circuit is used to amplify and filter the collected electrophysiological signals; The multi-channel analog-to-digital converter is used to convert the collected electrophysiological signals into digital signals at a preset sampling rate, and transmit the converted electrophysiological signals to the electrophysiological analog-to-digital converter interface through the analog-to-digital converter data output bus interface.

3. The electrophysiological signal processing device according to claim 1, characterized in that: It also includes a data storage unit for intercepting the electrophysiological signal at any segment processing node for storage.

4. The electrophysiological signal acquisition device according to claim 1, characterized in that: The multi-channel time series signal bus is based on programmable logic, and the transmission of electrophysiological signals between adjacent segmented processing nodes is completed through high-speed synchronous FIFO logic.

5. The electrophysiological signal acquisition device according to claim 1, characterized in that: The event synchronization unit includes a trigger line and an external encoding line, which are used to trigger the input of electrophysiological signals, and classify event types through the trigger line, the external encoding line or the event synchronization unit itself.

6. The electrophysiological signal acquisition device according to claim 5, characterized in that: Event types are classified by trigger line, external encoding line or event synchronization unit itself, including: Classify events by corresponding predefined event codes to different trigger lines; or, Input the event type through the external encoding line and use a trigger line to latch the event type; The event synchronization unit is directly connected to the electrophysiological analog-to-digital converter interface block, and the acquired event information is used as a data channel for transmission and processing.

7. A method for processing electrophysiological signals, characterized in that: Applied to the electrophysiological signal processing device according to any one of claims 1 to 5, the method comprises: Using the sampling time point of the electrophysiological signal as a stream synchronization signal, and using a multi-channel time series signal bus to transmit the electrophysiological signal in segments; At each segment processing node, the input electrophysiological signal is pre-processed and unidirectionally transmitted to one or more segment processing nodes at the subsequent stage through the multi-channel time series signal bus for electrophysiological state analysis; An external trigger event signal is received, an electrophysiological signal sampling point corresponding to the time point of the trigger event is determined, and the electrophysiological signal is marked and synchronously processed based on the electrophysiological signal sampling point.

8. The electrophysiological signal processing method according to claim 7, characterized in that: The preprocessing of the input electrophysiological signal includes amplifying and filtering the collected electrophysiological signal; and converting the collected electrophysiological signal into a digital signal according to a preset sampling rate based on a multi-channel analog-to-digital converter.

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