Electronic device

Abstract

The invention discloses an electronic device. The electronic device comprises a substrate layer; the first sensing electrode is arranged on the substrate layer; the second sensing electrode is arranged on the substrate layer and is adjacent to the first sensing electrode; the first wire is arranged on the substrate layer; the insulating layer is located between the first sensing electrode and the first wire and comprises at least three first through holes. The first wire is electrically connected with the first sensing electrode through the at least three first through holes, and the first wire crosses the second sensing electrode and is not electrically connected with the second sensing electrode.

Description

[0001] This application is a divisional application of the invention patent application with application date of September 18, 2020, application number 202010989165.1, and invention name “Electronic Device”. Technical Field

[0002] The present disclosure relates to an electronic device, and more particularly to an electronic device with a wiring design. Background Art

[0003] In recent years, as users have higher and higher requirements for electronic devices, components in electronic devices such as sensors can be set under the screen to improve the screen-to-body ratio in electronic devices. In addition, as the resolution of the sensor increases, it can be used as a fingerprint recognition component in electronic devices. However, when the resolution of the sensor increases, the number of wires electrically connected to the sensor also increases. Therefore, how to adjust the design of the wires to improve the space configuration in the electronic device has become an important issue in the electronics industry. Summary of the invention

[0004] One of the objectives of the present disclosure is to provide an electronic device, which may include a plurality of sensing elements and a plurality of traces electrically connected to the sensing elements, wherein the traces may be arranged in at least two conductive layers, thereby improving the spatial configuration in the electronic device.

[0005] In some embodiments, the present disclosure provides an electronic device. The electronic device includes a substrate layer; a first sensing electrode disposed on the substrate layer; a second sensing electrode disposed on the substrate layer and adjacent to the first sensing electrode; a first wire disposed on the substrate layer; and an insulating layer located between the first sensing electrode and the first wire and including at least three first through holes. The first wire is electrically connected to the first sensing electrode through the at least three first through holes, and the first wire passes over the second sensing electrode and is not electrically connected to the second sensing electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic top view of an electronic device according to a first embodiment of the present disclosure.

[0007] Figure 2 It is a cross-sectional schematic diagram of the electronic device along the sectional line AA′ according to the first embodiment of the present disclosure.

[0008] Figure 3 It is a top view schematic diagram of an electronic device according to a second embodiment of the present disclosure.

[0009] Figure 4 It is a schematic cross-sectional view of the electronic device along the cutting line BB′ according to the second embodiment of the present disclosure.

[0010] Figure 5 It is a top view schematic diagram of an electronic device according to a third embodiment of the present disclosure.

[0011] Figure 6 It is a schematic cross-sectional view of the electronic device along the cutting line CC' according to the third embodiment of the present disclosure.

[0012] Figure 7 It is a schematic cross-sectional view of the electronic device along the cutting line DD′ according to the third embodiment of the present disclosure.

[0013] Figure 8 It is a schematic top view of an electronic device according to a fourth embodiment of the present disclosure.

[0014] Fig. 9 It is a schematic cross-sectional view of the electronic device along the cutting line EE' according to the fourth embodiment of the present disclosure.

[0015] Fig.10 It is a schematic cross-sectional view of the electronic device according to the fourth embodiment of the present disclosure along the cutting line FF'.

[0016] Fig.11 It is a top view schematic diagram of an electronic device according to a fifth embodiment of the present disclosure.

[0017] Fig.12 It is a schematic cross-sectional view of the electronic device according to the fifth embodiment of the present disclosure along the cutting line GG'.

[0018] Fig.13 It is a top view schematic diagram of an electronic device according to a sixth embodiment of the present disclosure.

[0019] Fig.14 It is a schematic cross-sectional view of the electronic device according to the sixth embodiment of the present disclosure along the cutting line HH'.

[0020] Fig.15 It is a top view schematic diagram of an electronic device according to a seventh embodiment of the present disclosure.

[0021] Fig.16 It is a schematic cross-sectional view of the electronic device according to the seventh embodiment of the present disclosure along the cutting line II'.

[0022] Fig.17 It is a schematic top view of an electronic device according to an eighth embodiment of the present disclosure.

[0023] Fig.18 It is a partial enlarged cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present disclosure.

[0024] Explanation of reference numerals: A1-part; BA-base layer; BF, BF2-buffer layer; C1-semiconductor layer; CL-circuit layer; CO-covering layer; COL1, COL2-conductive layer; CT, CT2-contact; D1-direction; DD-display driver; DL-display layer; DR-display region; DR1-drain; DS-display substrate; DU-light-emitting unit; E1-first electrode; E2-second electrode; ED-electronic device; EN-encapsulation layer; G1-gate; GI-gate insulating layer; IL1, IL2, IL3, IL4, IL5-insulating layer; ILD-interlayer dielectric layer; L-length; L1, L2, L3-line segment; LL-tangent; LM-light-emitting layer; M0-shielding layer; NTP-non-turning part; OP-opening ; P1-spacer; PDL-pixel definition layer; PR-peripheral region; RE-region; S1-source; SB-substrate; SC, SC1, SC2, SC3, SC4-sensing circuit; SCL-sensing common line; SE, SE1, SE2, SE3, SE4, SE5, SE6-sensing electrode; SEL-sensing layer; SL, SL1, SL2, SL3, SL4, SL5, SL6-signal line; SOL-sensing output line; SP-sensing processor; SSL-sensing scan line; SW-driving element; T1, T2-thickness; TP-turning part; VH1, VH2, VH-through hole; A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I'-tangent. DETAILED DESCRIPTION

[0025] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present disclosure.

[0026] Certain words are used throughout this disclosure and in the appended claims to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names.

[0027] In the following description and claims, the words “including” and “comprising” are open-ended words and thus should be interpreted as meaning “including but not limited to…”.

[0028] It should be understood that when an element or film layer is referred to as being "on" another element or film layer, it can be directly on the other element or film layer, or there can be intervening elements or film layers between the two (indirect case). Conversely, when an element is referred to as being "directly" on another element or film layer, there can be no intervening elements or film layers between the two. Electrical connections can be direct electrical connections or indirect electrical connections through other elements.

[0029] Although the terms first, second, third, etc. can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third, etc. according to the order in which the components are declared in the claims. Therefore, in the following description, the first component may be the second component in the claims.

[0030] It should be noted that the following embodiments may be implemented by replacing, reorganizing, or mixing the technical features in several different embodiments without departing from the spirit of the present disclosure to implement other embodiments.

[0031] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view schematic diagram of an electronic device according to a first embodiment of the present disclosure, Figure 2 FIG. 1 is a cross-sectional view of the electronic device according to the first embodiment of the present disclosure along the tangent line AA'. Figure 1 As shown, in this embodiment, the electronic device ED may include a display device, which may display static or dynamic images or pictures according to the needs and operations of the user, but is not limited thereto. The display device may be applied to, for example, a notebook computer, a public display, a spliced ​​display, a car display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, or an electronic device applied to the above products, but is not limited thereto. Figure 2As shown, the electronic device ED may include a base layer BA, wherein the base layer BA in this embodiment may include any suitable display panel, for example, including a self-luminous display panel, but not limited thereto. In some embodiments, the base layer BA may be a non-self-luminous display panel. In addition, the base layer BA may be a flexible display panel or a rigid display panel. In detail, the base layer BA may include a substrate SB, a circuit layer CL, a light-emitting unit DU, a buffer layer BF, a pixel definition layer PDL, and an encapsulation layer EN, but not limited thereto. The substrate SB may include a flexible substrate, a rigid substrate, or a combination of the above substrates. The material of the flexible substrate may, for example, include polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or a combination of the above materials. The material of the rigid substrate may, for example, include glass, ceramic, quartz, sapphire, or a combination of the above materials. In addition, although Figure 2 The substrate SB shown in the figure is a single-layer structure, but the present disclosure is not limited thereto. In some embodiments, the substrate SB may include a multi-layer structure. The circuit layer CL is disposed on the substrate SB, for example, between the substrate SB and the light-emitting unit DU. The circuit layer CL may include various wires, circuits and / or electronic components. For example, Figure 2 As shown, the circuit layer CL may include a driving element SW, wherein the driving element SW may include, for example, a thin film transistor (TFT), but the present disclosure is not limited thereto. The driving element SW may include a gate G1, a source S1, a drain DR1, a semiconductor layer C1, and a gate insulating layer GI, wherein the gate insulating layer GI may be located between the gate G1 and the semiconductor layer C1, but the disclosure is not limited thereto. The material of the semiconductor layer C1 may include, for example, amorphous silicon, polycrystalline silicon, metal oxide (for example, indium gallium zinc oxide (IGZO)), other suitable materials, or a combination of the above materials, but the disclosure is not limited thereto. The gate G1 may include, for example, a metal material, other suitable conductive material, or a combination of the above materials, but the disclosure is not limited thereto. The source S1 and the drain DR1 may include, for example, doped amorphous material, doped polycrystalline material, metal oxide, metal material, other suitable conductive material, or a combination of the above materials, but the disclosure is not limited thereto. The gate insulating layer GI may include, for example, silicon nitride, silicon oxide, other suitable insulating materials, dielectric materials, or a combination of the above materials, but is not limited thereto. Figure 2The driving element SW shown is a top gate thin film transistor, but the present disclosure is not limited thereto. In some embodiments, the driving element SW may include, for example, a bottom gate thin film transistor or a multi-gate thin film transistor (e.g., a dual gate / double gate transistor). According to the present embodiment, the light emitting unit DU may be disposed on the circuit layer CL, and may include, for example, a light emitting diode, but is not limited thereto. In some embodiments, when the base layer BA includes a non-self-luminous display panel, such as a liquid crystal panel, the electronic device ED may include, for example, a dimming unit (e.g., a liquid crystal layer, but not limited thereto) located on the circuit layer CL, but does not include the light emitting unit DU disposed on the circuit layer CL, and the electronic device ED may also include a backlight module disposed below the substrate SB, but is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (OLED), a quantum dot diode (QLED or QDLED), an inorganic light emitting diode (LED), any other suitable light emitting element, or a combination thereof. The inorganic light emitting diode may include, for example, a sub-millimeter light emitting diode (mini LED) or a micro light emitting diode (micro LED), but is not limited thereto. In some embodiments, the chip size of the light emitting diode is about 300 micrometers (μm) to 10 millimeters (mm), the chip size of the sub-millimeter light emitting diode (mini LED) is about 100 micrometers to 300 micrometers, and the chip size of the micro light emitting diode (micro LED) is about 1 micrometer to 100 micrometers, but is not limited thereto. Figure 2 As shown, the light-emitting unit DU may include a first electrode E1, a second electrode E2 and a light-emitting layer LM, wherein the light-emitting layer LM is disposed between the first electrode E1 and the second electrode E2, but not limited thereto. The first electrode E1 and the second electrode E2 may, for example, include metal oxides, metal materials, other suitable conductive materials or a combination of the above materials, but not limited thereto. For example, the first electrode E1 and the second electrode E2 may include a transparent conductive material, such as indium tin oxide (ITO), but not limited thereto. In some embodiments, the electrode of the light-emitting unit DU on the non-display side (such as but not limited to the first electrode E1) may include a metal material or be composed of a metal layer, but not limited thereto. According to this embodiment, at least one of the light-emitting units DU may be electrically connected to at least one element in the circuit layer CL, for example, such as Figure 2As shown, the drain DR1 of the driving element SW in the circuit layer CL can be electrically connected to the first electrode E1 of the light-emitting unit DU through the contact CT, but the present invention is not limited thereto. In some embodiments, each of the plurality of driving elements SW can be electrically connected to one of the plurality of light-emitting units DU. In addition, the source S1 of the driving element SW can be electrically connected to the working voltage source (VDD) or the shared voltage source ( Figure 2 The gate electrode G1 of the driving element SW may be electrically connected to a switching element ( Figure 2 The switch element may be, for example, a thin film transistor, but not limited thereto. The encapsulation layer EN may be disposed on the light emitting unit DU and cover the light emitting unit DU and the film layer thereunder to protect the light emitting unit DU. The encapsulation layer EN may include any appropriate insulating material, for example, an organic insulating material, an inorganic insulating material, or a combination of the above materials, but not limited thereto. In addition, although Figure 2 The encapsulation layer EN in the embodiment is a single-layer structure, but the present embodiment is not limited thereto. In some embodiments, the encapsulation layer EN may include a three-layer structure of an inorganic layer, an organic layer and an inorganic layer.

[0032] In some embodiments, the base layer BA may further include, for example, a buffer layer BF, a light shielding layer M0, and a pixel definition layer PDL, but is not limited thereto. The buffer layer BF may be disposed between the substrate SB and the circuit layer CL. The light shielding layer M0 may be disposed on the substrate SB, and may be located between the circuit layer CL and the substrate SB in a top-view direction (e.g., direction D1) of the electronic device ED. In detail, the light shielding layer M0 may, for example, be disposed between the substrate SB and the driving element SW to block light entering from the side of the substrate SB to reduce the effect of ambient light on the driving element SW, but is not limited thereto. The pixel definition layer PDL may include at least one opening OP, and the light-emitting layer LM of the light-emitting unit DU may be disposed in the opening OP. In some embodiments, since the light-emitting layer LM may be disposed in the opening OP, the opening OP of the pixel definition layer PDL may define the light-emitting region or light-emitting area of ​​each light-emitting unit DU, but is not limited thereto. In addition, in some embodiments, the base layer BA may further include an interlayer dielectric layer ILD disposed on the gate insulating layer GI, an insulating layer IL1 disposed between the circuit layer CL and the light-emitting unit DU, and an insulating layer IL2 disposed between the circuit layer CL and the substrate SB, but the present invention is not limited thereto. The buffer layer BF, the insulating layer IL1, the insulating layer IL2, and the interlayer dielectric layer ILD may include, for example, an inorganic insulating material, an organic insulating material, or a combination of the above materials, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, but the present invention is not limited thereto. It should be noted that, Figure 2The structure of the base layer BA shown is only exemplary, and the present disclosure is not limited thereto. In some embodiments, the base layer BA may have any suitable structure or include any suitable element or film layer according to different design requirements. In addition, the base layer BA in the following embodiments of the present disclosure may refer to the contents of this embodiment, so it will not be repeated hereafter.

[0033] According to this embodiment, Figure 1 As shown, the electronic device ED may include a display region DR and a peripheral region PR, wherein the display region DR may be defined, for example, by a region where a plurality of pixels (pixels) in the electronic device ED are distributed. Figure 2 The display area DR is defined by the pixel definition layer PDL, wherein each of the multiple pixels may, for example, correspond to a light-emitting unit DU and its corresponding driving element SW and other related elements, but is not limited to this. In some embodiments, when the base layer BA includes a non-self-luminous display panel, a single pixel may, for example, correspond to a dimming unit and its corresponding driving element SW and other related elements. In the present embodiment, the display area DR may, for example, be defined as the area surrounded by the outer edges of the outermost pixels among the multiple pixels, and the area outside the display area DR may be defined as the peripheral area PR, but is not limited to this. The display area DR may, for example, correspond to the light-emitting area of ​​the electronic device ED, and the peripheral area PR may, for example, be used to set peripheral elements and / or peripheral circuits, but is not limited to this. The above-mentioned definitions of the display area DR and the peripheral area PR can be applied to each embodiment and variant embodiment of the present disclosure, and will not be repeated hereafter. In addition, Figure 1 The sizes of the display region DR and the peripheral region PR shown are merely exemplary, and the present disclosure is not limited thereto.

[0034] According to this embodiment, the electronic device ED may further include a sensing layer in addition to the above-mentioned elements or film layers. Figure 2 As shown, the electronic device ED may include a sensing layer SEL, wherein the sensing layer SEL may be disposed on the base layer BA, but is not limited thereto. It should be noted that the above-mentioned “the sensing layer is disposed on the base layer BA” may mean that the sensing layer SEL is directly disposed on the base layer BA, or there may be an intermediate film layer between the sensing layer SEL and the base layer BA, and the present disclosure is not limited thereto. In this embodiment, if Figure 1 and Figure 2As shown, the sensing layer SEL includes a plurality of sensing electrodes SE (e.g., sensing electrode SE1, sensing electrode SE2, sensing electrode SE3, and sensing electrode SE4), wherein the sensing electrodes SE may be, for example, disposed in the display region DR, but not limited thereto. An insulating layer IL5 may be disposed on the sensing layer SEL, wherein the insulating layer IL5 may cover the sensing layer SEL, but not limited thereto. The sensing electrode SE may, for example, include a transparent electrode, wherein the material of the transparent electrode may, for example, include indium tin oxide, indium zinc oxide (IZO), or a combination of the above materials, but not limited thereto. According to this embodiment, the sensing electrode SE in the electronic device ED may, for example, be used as a touch element, but not limited thereto. For example, the sensing electrode SE may be used as a capacitive touch element, and when an object (e.g., a finger) contacts the surface of the electronic device ED, the sensing electrode SE corresponding to the contact position of the object may detect a change in the capacitance value, thereby obtaining the touch position of the object on the surface of the electronic device ED, but not limited thereto. In some embodiments, when the sensing electrodes SE have a higher density and / or resolution, the peaks and troughs in the human finger will have different degrees of influence on the capacitance value, thereby causing the sensing electrodes SE to output different signals. Therefore, fingerprint identification can be performed through the sensing electrodes SE. In other words, the sensing electrodes SE can be used as a capacitive fingerprint identification element, for example, but not limited to this. In some embodiments, the sensing electrodes SE of the electronic device ED can have different densities in different areas, wherein a portion of the sensing electrodes SE with a larger density can be used as a fingerprint identification element, and another portion of the sensing electrodes SE can be used as a touch element, but not limited to this. The above-mentioned "density of the sensing electrodes SE" can be defined, for example, as the number of sensing electrodes SE per unit area, but not limited to this. It should be noted that, Figure 1 The pattern and arrangement of the sensing electrodes SE shown are merely exemplary, and the present disclosure is not limited thereto.

[0035] According to this embodiment, the electronic device ED may further include a plurality of signal lines SL, wherein each of the plurality of signal lines SL may be connected to one of the sensing electrodes SE, for example, but not limited thereto. Figure 1 As shown, the signal line SL1 can be electrically connected to the sensing electrode SE1, the signal line SL2 can be electrically connected to the sensing electrode SE2, the signal line SL3 can be electrically connected to the sensing electrode SE3, and the signal line SL4 can be electrically connected to the sensing electrode SE4, but it is not limited thereto. Figure 1 As shown, in order to electrically connect the signal line SL to the corresponding sensing electrode SE, the signal line SL can be extended to any suitable position in the corresponding sensing electrode SE in the top view direction (direction D1) of the electronic device ED, and can be connected through a through hole ( Figure 1The signal line SL in the present embodiment may be, for example, copper, silver, gold, aluminum, other suitable conductive materials or a combination of the above materials, but is not limited thereto. As described above, the sensing electrode SE in the present embodiment may, for example, be used as a touch element or a fingerprint recognition element, and the signal line SL electrically connected to the sensing electrode SE may transmit the signal detected by the sensing electrode SE to the sensing circuit, and the sensing processor may process the output signal from the sensing circuit and perform signal processing to identify the touch position or obtain the fingerprint pattern, but is not limited thereto. For example, if Figure 1 As shown, the electronic device ED may further include a sensing circuit SC and a sensing processor SP, wherein the sensing circuit SC and the sensing processor SP may be disposed in a peripheral region PR of the electronic device ED, but not limited thereto. In the present embodiment, the signal line SL1, the signal line SL2, the signal line SL3, and the signal line SL4, which are electrically connected to the sensing electrode SE1, the sensing electrode SE2, the sensing electrode SE3, and the sensing electrode SE4, respectively, may be electrically connected to the sensing circuit SC1, the sensing circuit SC2, the sensing circuit SC3, and the sensing circuit SC4, respectively, and transmit the signal detected by the sensing electrode SE to the sensing circuit SC. For example, when the sensing electrode SE is used as a capacitive touch element or a capacitive fingerprint recognition element, the signal line SL may transmit the capacitance signal from the sensing electrode SE to the sensing circuit SC, but not limited thereto. In addition, in the present embodiment, the sensing circuit SC may be electrically connected to the sensing processor SP ( Figure 1 (not shown), so that the sensing circuit SC can output a corresponding signal to the sensing processor SP after receiving the signal from the sensing electrode SE, but not limited to this. The sensing processor SP can process the output signal from the sensing circuit SC and process the signal to identify the touch position or obtain the fingerprint pattern, but not limited to this. It should be noted that although Figure 1 The sensing circuit SC in the following figures is shown in a checkered pattern, but the present disclosure is not limited thereto. In some embodiments, the sensing circuit SC may include a circuit formed by any suitable traces or wires.

[0036] In this embodiment, the peripheral region PR of the electronic device ED may include a display driver DD in addition to the sensing circuit SC and the sensing processor SP, wherein the display driver DD may be used, for example, to control the driving element SW and the driving light emitting unit DU to control the display function of the electronic device ED, but is not limited thereto. Figure 1As shown, the display driver DD and the sensing circuit SC and the sensing processor SP can be arranged on opposite sides of the display region DR to improve the spatial configuration in the electronic device ED, but the disclosure is not limited thereto. In some embodiments, the display driver DD, the sensing circuit SC and the sensing processor SP can have any suitable arrangement according to design requirements. In some embodiments, the peripheral region PR of the electronic device ED can include any peripheral components suitable for application in the electronic device ED in addition to the above components.

[0037] As described above, each of the sensing electrodes SE may be electrically connected to one of the signal lines SL, and the signal detected by the sensing electrode SE is transmitted to the sensing circuit SC and the sensing processor SP through the signal line SL. When the number and / or density of the sensing electrodes SE is large, the number and / or density of the signal lines SL in the electronic device (for example, defined as the number of signal lines SL per unit area, but not limited thereto) will increase accordingly. For example, when some or all of the sensing electrodes SE in the electronic device ED are used as fingerprint recognition elements, these sensing electrodes SE may have a larger resolution and / or density, and the number and / or density of the signal lines SL electrically connected to these sensing electrodes SE will increase accordingly. In this case, if the signal lines SL are arranged in the same layer, the signal lines SL may interfere with each other (for example, generate parasitic capacitance, but not limited thereto) due to the small spacing between them, thereby affecting the performance of the electronic device ED, or the signal lines SL may occupy a larger part of the space in the peripheral area PR, thereby limiting the spatial configuration in the electronic device ED, or the electronic device ED may not have enough space to arrange the signal lines SL corresponding to the number of sensing electrodes SE. Therefore, according to this embodiment, the electronic device ED includes at least two conductive layers, for example, a conductive layer COL1 and a conductive layer COL2, the conductive layer COL1 may include a portion of the signal line SL electrically connected to a portion of the sensing electrodes SE, and the conductive layer COL2 may include another portion of the signal line SL electrically connected to another portion of the sensing electrodes SE, so as to improve the space utilization rate of the electronic device ED and / or reduce the interference phenomenon between the signal lines SL. For example, Figure 2As shown, the conductive layer COL1 and the conductive layer COL2 can be disposed on the base layer BA. It should be noted that the above-mentioned "the conductive layer is disposed on the base layer BA" may mean that one of the conductive layers is directly disposed on the base layer BA and is in direct contact with the base layer BA, or there may be an intermediate film layer between the conductive layer and the base layer BA, and the present disclosure is not limited thereto. In addition, in the present embodiment, the conductive layer COL1 and the conductive layer COL2 may be located on different planes (for example, a plane perpendicular to the direction D1, but not limited thereto) or may be layers with different formation orders, but not limited thereto. According to the present embodiment, the sensing layer SEL may be disposed above the conductive layer COL1 and the conductive layer COL2, in other words, the conductive layer COL1 and the conductive layer COL2 are located between the sensing layer SEL and the base layer BA, but not limited thereto. An insulating layer IL3 may also be disposed between the conductive layer COL1 and the conductive layer COL2, wherein the insulating layer IL3 covers the conductive layer COL1 and separates the conductive layer COL1 from the conductive layer COL2. An insulating layer IL4 may be further disposed between the sensing layer SEL and the conductive layer COL2 to cover the conductive layer COL2 and separate the conductive layer COL2 from the sensing layer SEL. In some embodiments, the sensing layer SEL, the conductive layer COL1, and the conductive layer COL2 may have different arrangement orders according to design requirements. Figure 2As shown, a plurality of signal lines SL in the electronic device ED may be respectively included in the conductive layer COL1 and the conductive layer COL2, or in other words, some signal lines SL are formed by the conductive layer COL1, and other signal lines SL are formed by the conductive layer COL2, and the conductive layer COL1 and the conductive layer COL2 are the layers where the signal lines SL are located, but the disclosure is not limited thereto. For example, the signal line SL1 and the signal line SL3 electrically connected to the sensing electrode SE1 and the sensing electrode SE3, respectively, may be disposed in the conductive layer COL1, and the signal line SL2 and the signal line SL4 electrically connected to the sensing electrode SE2 and the sensing electrode SE4, respectively, may be disposed in the conductive layer COL2, but the disclosure is not limited thereto. In some embodiments, the signal line SL1 and the signal line SL3 may be disposed in the conductive layer COL2, and the signal line SL2 and the signal line SL4 may be disposed in the conductive layer COL1. Since the signal line SL in this embodiment can be arranged in at least two conductive layers (conductive layer COL1 and conductive layer COL2) located on different planes, even if the interval between adjacent (or corresponding) signal lines SL in the top-view direction becomes smaller, because they are located in different layers, the interference between the signal lines SL can still be reduced, making the spatial configuration of the electronic device ED more flexible. According to this embodiment, the signal line SL located in one of the conductive layers can have a spacing with the corresponding signal line SL in another conductive layer in the top-view direction (for example, direction D1), wherein the spacing can be, for example, less than or equal to 2 micrometers (micrometer), but is not limited thereto. It should be noted that the above-mentioned "the signal line SL in one of the conductive layers and the corresponding signal line SL in another conductive layer" means that the two signal lines SL are adjacent to each other, and no other signal lines SL may be included between the two signal lines SL, that is, the above-mentioned spacing refers to the shortest spacing between two adjacent signal lines SL in the top-view direction, and the measurement direction of this spacing is, for example, perpendicular to the extension direction of the signal line SL, but is not limited thereto. For example, Figure 2 The signal line SL2 in the conductive layer COL2 may correspond to the nearest signal line SL in the conductive layer COL1, such as the signal line SL1 (or the signal line SL3), and the signal line SL4 may correspond to the signal line SL3, but is not limited thereto. It should be noted that when the signal line SL and another corresponding signal line SL are mentioned below, the definition of "correspondence" can refer to the above content, so it will not be repeated hereafter. Figure 2As shown, there may be a spacing P1 between the signal line SL2 and the corresponding signal line SL1, and there may also be a spacing P1 between the signal line SL4 and the corresponding signal line SL3, but the present invention is not limited thereto. According to the present embodiment, as described above, the spacing P1 may be less than or equal to 2 microns, but the present invention is not limited thereto. In some embodiments, the spacing between the signal line SL2 and the corresponding signal line SL1 may be different from the spacing between the signal line SL4 and the corresponding signal line SL3. In some embodiments, the signal line SL2 may correspond to the signal line SL3, and there may be a spacing P1 between the signal line SL2 and the signal line SL3, which is less than or equal to 2 microns, but the present invention is not limited thereto. In addition, in the present embodiment, the thickness of the insulating layer IL3 may be designed to increase the vertical distance (the distance along the direction D1) between two adjacent or corresponding signal lines SL, thereby reducing the interference between the two signal lines SL, but the present invention is not limited thereto. For example, if Figure 2 As shown, the insulating layer IL3 may have a thickness T1, wherein as the thickness T1 increases, the vertical distance between the signal lines SL (e.g., the signal line SL1 and the signal line SL2 and / or the signal line SL3 and the signal line SL4) may increase accordingly. According to this embodiment, the thickness T1 of the insulating layer IL3 may range, for example, from To 4000 angstroms, but not limited thereto, the thickness T1 mentioned above refers to the distance between the bottom surface and the top surface of the insulating layer IL3, which will not be described in detail below. In some embodiments, the thickness T1 of the insulating layer IL3 may range from It should be noted that in this embodiment, the thickness of the insulating layer IL4 can be the same as or different from the thickness of the insulating layer IL3, and the present disclosure is not limited thereto. Figure 2 Only an electronic device ED including two conductive layers is shown, but the present disclosure is not limited to this. In some embodiments, the electronic device ED may include three or more conductive layers, and the signal lines SL may be arranged in the conductive layers in any suitable manner according to design requirements. In some embodiments, each conductive layer may be provided with an insulating layer, but this is not limited to this. The above-mentioned features regarding the number of conductive layers that may be included in the electronic device ED may be applied to each embodiment and variant embodiment of the present disclosure, and will not be described in detail hereinafter. According to this embodiment, since the signal lines SL in the electronic device ED may be arranged in different conductive layers, the vertical distance between adjacent or corresponding signal lines SL may be adjusted by adjusting the insulating layer between the conductive layers (for example Figure 2 Therefore, compared with the case where the signal lines SL are arranged in the same layer, the signal lines SL in the present embodiment may have a smaller interval (for example, interval P1) in the lateral direction D2, so as to improve the spatial configuration of the electronic device ED while reducing mutual interference between the signal lines SL.

[0038] More embodiments of the present disclosure will be described below. To simplify the description, the same film layers or components in the following embodiments will use the same reference numerals, and their features will not be repeated, while the differences between the embodiments will be described in detail below.

[0039] Please refer to Figure 3 and Figure 4 , Figure 3 is a top view schematic diagram of an electronic device according to a second embodiment of the present disclosure, Figure 4 This is a cross-sectional view of the electronic device of the second embodiment of the present disclosure along the sectional line BB'. Figure 3 Only the signal lines SL and the touch electrodes SE are shown, and the remaining elements and film layers are omitted. Figure 4 The base layer BA is only shown as a single layer, and the components and film layers included in the base layer BA can refer to the contents of the first embodiment above, so they are not repeated. The materials of the signal lines SL and the touch electrodes SE in this embodiment can refer to the contents of the first embodiment above, so they are not repeated. Figure 3 The structure shown is Figure 1 One of the main differences of the structure of the first embodiment shown is the design of the signal line SL. According to this embodiment, the signal line SL can be arranged in at least two conductive layers, and the signal line SL located in one of the at least two conductive layers can overlap with the corresponding signal line SL in another layer of the at least two conductive layers in the top view direction, for example, but not limited to this. In detail, as Figure 3 and Figure 4 As shown, the electronic device ED of this embodiment may include two conductive layers COL1 and COL2, and the two conductive layers include signal lines SL1, SL2, SL3, SL4, SL5, and SL6 electrically connected to sensing electrodes SE1, SE2, SE3, SE4, SE5, and SE6, respectively, wherein the signal lines SL1, SL3, and SL5 may be included in the conductive layer COL1, and the signal lines SL2, SL4, and SL6 may be included in the conductive layer COL2, but the present invention is not limited thereto. In addition, as Figure 3 and 4As shown, the signal line SL1 may overlap with its corresponding signal line SL2 in direction D1, the signal line SL3 may overlap with its corresponding signal line SL4 in direction D1, and the signal line SL5 may overlap with its corresponding signal line SL6 in direction D1, but the present invention is not limited thereto. Since the signal lines SL in the present embodiment may be arranged in different conductive layers, the signal lines SL in different conductive layers may overlap with each other, thereby improving the spatial configuration of the electronic device ED, such as saving the configuration space of the signal lines SL, or increasing the number of signal lines SL arranged in the electronic device ED, but the present invention is not limited thereto. In addition, in the present embodiment, the interference between the signal lines SL may be reduced by adjusting the thickness of the insulating layer between the conductive layers. For example, if Figure 4 As shown, in this embodiment, the insulating layer IL3 may have a thickness T2, wherein the thickness T2 may range from, for example, 5000 angstroms to 25000 angstroms, but is not limited thereto. In this embodiment, the thickness of the insulating layer IL3 may be, for example, greater than the thickness of the insulating layer IL4, but is not limited thereto. Since the insulating layer IL3 may have a greater thickness in this embodiment, the interference between the two overlapping signal lines SL may be reduced, thereby improving the performance of the electronic device ED. It should be noted that although in Figure 4 In the structure shown, the signal line SL1 completely overlaps the signal line SL2, the signal line SL3 completely overlaps the signal line SL4, and the signal line SL5 completely overlaps the signal line SL6, but the disclosure is not limited thereto. In some embodiments, the signal line SL1 may partially overlap the corresponding signal line SL2, the signal line SL3 may partially overlap the corresponding signal line SL4, and the signal line SL5 may partially overlap the corresponding signal line SL6. In addition, in some embodiments, Figure 4 As shown, a buffer layer BF2 may be included between the base layer BA and the conductive layer COL1, but the present disclosure is not limited thereto. The material of the buffer layer BF2 may refer to the buffer layer BF of the first embodiment, so it will not be described in detail.

[0040] Please refer to Figures 5 to 7 , Figure 5 is a top view schematic diagram of an electronic device according to a third embodiment of the present disclosure, Figure 6 This is a cross-sectional view of the electronic device along the cut line CC' of the third embodiment of the present disclosure. Figure 7 This is a cross-sectional view of the electronic device along the sectional line DD' of the third embodiment of the present disclosure. Figure 5 Only the signal lines SL and the touch electrodes SE are shown, and the remaining elements and film layers are omitted. Figure 6 and Figure 7The base layer BA is shown as a single layer, and the components and film layers included in the base layer BA can refer to the contents of the first embodiment, so they are not repeated. The materials of the signal lines SL and the touch electrodes SE in this embodiment can refer to the contents of the first embodiment, so they are not repeated. Figures 5 to 7 The structure shown is Figure 1 One of the main differences of the structure of the first embodiment shown is the location of the conductive layer and the sensing layer. According to this embodiment, the electronic device ED may include at least two conductive layers, and at least one of the at least two conductive layers may be disposed on the sensing layer SEL, but is not limited thereto. For example, Figures 5 to 7 As shown, the electronic device ED may include a conductive layer COL1, a conductive layer COL2 and a sensing layer SEL, wherein the sensing layer SEL includes sensing electrodes SE1, SE2, SE3 and SE4, and the conductive layers COL1 and COL2 include signal lines SL1, SL2, SL3 and SL4 electrically connected to the sensing electrodes SE1, SE2, SE3 and SE4, respectively. Figure 6 , Figure 7 As shown, in this embodiment, the conductive layer COL2 may be disposed on the sensing layer SEL, and the sensing layer SEL may be disposed on the conductive layer COL1, or in other words, the sensing layer SEL may be disposed between the conductive layer COL1 and the conductive layer COL2, but the present invention is not limited thereto. In this embodiment, the signal line SL1 and the signal line SL3 may be included in the conductive layer COL1, and the signal line SL2 and the signal line SL4 may be included in the conductive layer COL2, but the present invention is not limited thereto. That is, the signal line SL1 and the signal line SL3 in this example embodiment may be located below the sensing electrode SE, and the signal line SL2 and the signal line SL4 may be located above the sensing electrode SE, but the present invention is not limited thereto. Therefore, as Figure 6 As shown, the signal line SL1 is located below the sensing electrode SE1, and the insulating layer IL3 may include a through hole VH1, and the sensing electrode SE1 may be filled in the through hole VH1 and electrically connected to the signal line SL1, but the present invention is not limited thereto. Figure 7As shown, the signal line SL2 is located above the sensing electrode SE2, and the insulating layer IL5 may include, for example, a through hole VH2, and the signal line SL2 may be filled in the through hole VH2 and electrically connected to the sensing electrode SE2, but is not limited thereto. Although not shown in the figure, the signal line SL3 and the signal line SL4 in this embodiment can be electrically connected to the sensing electrode SE3 and the sensing electrode SE4, respectively, in the same manner as described above, so they will not be repeated here. The above-mentioned electrical connection method between the signal line SL and the sensing electrode SE can be applied to each embodiment and variant embodiment of the present disclosure, so they will not be repeated here. In addition, the method of electrically connecting the signal line SL to the sensing electrode SE through the through hole in the present embodiment is only exemplary, and the present disclosure is not limited thereto. In some embodiments, the signal line SL can be electrically connected to the sensing electrode SE in any suitable manner according to design requirements.

[0041] In this embodiment, since the signal lines SL can be arranged in different conductive layers, the interference between the signal lines SL caused by the reduced spacing in the planar direction can be reduced, thereby increasing the spatial configuration flexibility of the electronic device ED. Figure 6 and Figure 7 As shown, the signal line SL1 in the conductive layer COL1 may have a spacing P1 with the corresponding signal line SL2 in the conductive layer COL2 in the top view direction (direction D1), wherein the spacing P1 may be less than or equal to 2 micrometers, but is not limited thereto. That is, compared with the case where the signal lines SL are arranged in the same conductive layer, the signal lines SL in this embodiment may have a smaller lateral spacing in the top view direction (direction D1), so as to improve the spatial configuration of the electronic device ED while reducing the mutual interference of the signal lines SL, or, the number of signal lines SL arranged in the electronic device ED may be increased, but is not limited thereto.

[0042] Please refer to Figures 8 to 10 , Figure 8 is a top view schematic diagram of an electronic device according to a fourth embodiment of the present disclosure, Fig. 9 This is a cross-sectional view of the electronic device along the tangent line EE' of the fourth embodiment of the present disclosure. Fig.10 This is a cross-sectional view of the electronic device of the fourth embodiment of the present disclosure along the sectional line FF'. To simplify the drawings, Figure 8 Only the signal lines SL and the touch electrodes SE are shown, and the remaining elements and film layers are omitted. Fig. 9 and Fig.10 The base layer BA is shown as a single layer, and the components and film layers included in the base layer BA can refer to the contents of the first embodiment, so they are not repeated. The materials of the signal lines SL and the touch electrodes SE in this embodiment can refer to the contents of the first embodiment, so they are not repeated. Figures 8 to 10 The structure shown is Figure 3One of the main differences of the structure of the second embodiment shown is the location of the conductive layer and the sensing layer. Figures 8 to 10 As shown, the electronic device ED may include a conductive layer COL1, a conductive layer COL2 and a sensing layer SEL, the sensing layer SEL includes sensing electrodes SE1, SE2, SE3, SE4, SE5 and SE6, and the conductive layers COL1 and COL2 include signal lines SL1, SL2, SL3, SL4, SL5 and SL6 electrically connected to the sensing electrodes SE1, SE2, SE3, SE4, SE5 and SE6, respectively. Fig. 9 , Fig.10 As shown, in this embodiment, the conductive layer COL2 may be disposed on the sensing layer SEL, and the sensing layer SEL may be disposed on the conductive layer COL1, but the present invention is not limited thereto. In this embodiment, the conductive layer COL1 includes a signal line SL1, a signal line SL3, and a signal line SL5, and the conductive layer COL2 includes a signal line SL2, a signal line SL4, and a signal line SL6, but the present invention is not limited thereto. That is, in this embodiment, the signal line SL1, the signal line SL3, and the signal line SL5 may be located below the sensing electrode SE, and the signal line SL2, the signal line SL4, and the signal line SL6 may be located above the sensing electrode SE, but the present invention is not limited thereto. Fig. 9 As shown, the insulating layer IL3 may include a through hole VH1, and the sensing electrode SE1 may be filled in the through hole VH1 to directly contact the signal line SL1 to be electrically connected to the signal line SL1, but the present invention is not limited thereto. Fig.10 As shown, the insulating layer IL5 may include a through hole VH2 , and the signal line SL2 may be filled in the through hole VH2 to directly contact the sensing electrode SE2 to be electrically connected to the sensing electrode SE2 , but the present invention is not limited thereto.

[0043] According to this embodiment, since the signal lines SL can be arranged in different conductive layers, the signal lines SL in different conductive layers can overlap with another corresponding signal line SL, thereby improving the spatial configuration of the electronic device ED. Fig. 9 and Fig.10 As shown, the signal line SL1 can overlap with the corresponding signal line SL2, the signal line SL3 can overlap with the corresponding signal line SL4, and the signal line SL5 can overlap with the corresponding signal line SL6, but the present invention is not limited thereto. Compared with the case where the signal lines SL are arranged on the same layer, the arrangement of the signal lines SL in this embodiment can increase the space utilization rate of the electronic device ED, thereby improving the space configuration of the electronic device ED. It should be noted that Fig. 9 and Fig.10The structure shown is only exemplary, and the present disclosure is not limited thereto. In some embodiments, a signal line SL located in different conductive layers may partially overlap another corresponding signal line SL.

[0044] Please refer to Figure 11 to Figure 12 , Fig.11 This is a top view of an electronic device according to a fifth embodiment of the present disclosure. Fig.12 This is a cross-sectional view of the electronic device of the fifth embodiment of the present disclosure along the tangent line G-G'. To simplify the drawings, Fig.11 Only the signal line SL and the display unit DU are shown, and the remaining elements and film layers are omitted. Fig.12 The sensing layer SEL is omitted, and the base layer BA of the electronic device ED is simply shown as a three-layer structure, wherein Fig.12 The base layer BA may include a display substrate DS, a display layer DL, and a cover layer CO. The display substrate DS may, for example, include any suitable film layer or element located below the display unit DU, such as the substrate SB and the circuit layer CL described above, but not limited thereto. The display layer DL may, for example, include the display unit DU, but not limited thereto. The cover layer CO may, for example, include any suitable film layer or element located above the display unit DU, such as the encapsulation layer EN described above, but not limited thereto. The elements or film layers in the base layer BA described above may refer to the contents in the first embodiment, so they will not be described in detail. Fig.11 and Fig.12 The structure shown is Figure 1 One of the main differences of the structure of the first embodiment shown is the design of the signal line. According to this embodiment, the signal line SL in the electronic device ED may have a non-linear pattern, such as a zigzag pattern, but is not limited thereto. Fig.11 and Fig.12 As shown, the electronic device ED may include a signal line SL1, a signal line SL2, a signal line SL3 and a signal line SL4, wherein the signal line SL1 and the signal line SL3 may be included in the conductive layer COL1, and the signal line SL2 and the signal line SL4 may be included in the conductive layer COL2, but the present invention is not limited thereto. Fig.12The sensing layer is not shown in the figure, but the electronic device ED in this embodiment may include a sensing layer, wherein the arrangement relationship between the sensing layer, the conductive layer COL1 and the conductive layer COL2 may refer to the above-mentioned embodiments and variant embodiments. For example, the sensing layer in this embodiment may be arranged between the conductive layer COL1 and the conductive layer COL2, or the sensing layer may be arranged on the conductive layer COL1 and the conductive layer COL2, but the invention is not limited thereto. The signal line SL1, the signal line SL2, the signal line SL3 and the signal line SL4 may be electrically connected to a plurality of sensing electrodes arranged in the sensing layer, respectively, but the invention is not limited thereto. According to this embodiment, the signal line SL1, the signal line SL2, the signal line SL3 and the signal line SL4 may, for example, have a sawtooth pattern, but the invention is not limited thereto. In some embodiments, the signal line SL may include other suitable non-straight line graphics, such as an arc, an irregular shape or a combination of the above shapes, but the invention is not limited thereto. In this embodiment, since the signal lines SL can be arranged in different conductive layers, the signal lines SL in different conductive layers can overlap each other, or in other words, the signal lines in one of the conductive layers COL1 and COL2 can overlap the corresponding signal lines SL in the other of the conductive layers COL1 and COL2, but the present invention is not limited thereto. Fig.11 As shown, in this embodiment, each of the signal lines SL may include a turning portion TP and a non-turning portion NTP, and the turning portion TP may be arc-shaped or sharp-angled. In the direction D1 (i.e., the top view direction), the signal line SL1 and / or the signal line SL3 located in the conductive layer COL1 may overlap or intersect with the signal line SL2 and / or the signal line SL4 located in the conductive layer COL2 at the non-turning portion NTP, or in other words, the non-turning portion NTP of the signal line SL1 and / or the signal line SL3 may overlap or intersect with the non-turning portion NTP of the signal line SL2 and / or the signal line SL4, but is not limited thereto. In addition, as Fig.11 As shown in FIG. 1 , the turning portion TP of any one of the signal lines SL may not overlap the turning portions TP of other signal lines SL, but the present invention is not limited thereto. It should be noted that, in the present embodiment, the above-mentioned “turning portion TP and non-turning portion NTP of the signal line SL” may be defined, for example, by the line segment length and position of the signal line SL. Specifically, Fig.11 As shown, each of the signal lines SL may include a plurality of turning points, wherein a line segment of the signal line SL may be included between two adjacent turning points (for example, Fig.11 As shown, the signal line SL2 may include line segments L1, L2, and L3, and the length of a line segment may be defined as the distance between the centers of two line segments adjacent to the line segment, for example, Fig.11The length L of the middle line segment L2 may be the distance from the center of the line segment L3 adjacent to the line segment L2 to the center of the line segment L1, but is not limited thereto. In some embodiments, different line segments in a signal line SL may have the same line segment length, but is not limited thereto. In some embodiments, different line segments in a signal line SL may have different line segment lengths. After defining the line segment length, the turning portion TP and the non-turning portion NTP in the signal line SL may be further defined. In detail, in the present embodiment, the two ends of the turning portion TP may respectively have a distance of one quarter of the line segment length from the center of the line segment to define the positions of the two ends of the turning portion TP, and further define the range of the turning portion TP, but is not limited thereto. For example, if Fig.11 As shown, one end (e.g., end E1) of the turning portion TP in the signal line SL2 may be, for example, a quarter of the length L of the line segment L2 from the center of the line segment L3, and the other end (e.g., end E2) of the turning portion TP may be a quarter of the length L of the line segment L2 from the center of the line segment L3. Fig.11 The portion of the signal line SL2 between the end E1 and the end E2 may be defined as a turning portion TP of the signal line SL2, but the present invention is not limited thereto. In the present embodiment, the length of the conversion portion TP and the non-turning portion NTP in each line segment of the signal line SL may be, for example, half the length of the line segment. Fig.11 As shown, in the line segment L2, the length of the turning portion TP (L / 4+L / 4) may be the same as the length of the non-turning portion NTP (L / 2), but is not limited thereto.

[0045] In addition, in this embodiment, the signal line SL located in one layer of the conductive layer may not overlap the signal line SL located in another layer of the conductive layer but may be aligned with the signal line SL, but the present invention is not limited thereto. Fig.11 and Fig.12 As shown, the signal line SL2 in the conductive layer COL2 may not overlap the signal line SL3 in the conductive layer COL1 in the direction D1, and the signal line SL2 may be aligned with the signal line SL3 in the direction D1, for example, aligned with Fig.12 The tangent line LL in the diagram is not limited to this. Fig.11 and Fig.12It can be seen that the signal line SL3 and the signal line SL2 are aligned at the turning portion TP of the two, but the present invention is not limited thereto. In some embodiments, the signal line SL2 and the signal line SL3 may not be aligned in the direction D1 and have a gap, wherein the size of the gap may, for example, refer to the gap P1 of the first embodiment described above, but the present invention is not limited thereto. As described above, since the signal lines SL in the present embodiment may be arranged in different conductive layers, the signal lines SL in different conductive layers may overlap, align or have a smaller gap with each other to increase the space utilization rate of the electronic device ED, thereby improving the space configuration of the electronic device ED or increasing the number of signal lines SL that can be arranged in the electronic device ED. In addition, since the signal lines SL that overlap or align with each other in the present embodiment may be arranged in different conductive layers, the interference phenomenon caused by the reduction in the distance between the signal lines may be reduced, but the present invention is not limited thereto.

[0046] In addition, in this embodiment, the signal line SL in the electronic device ED may not overlap with the display unit DU in the top view direction, but the present invention is not limited thereto. Fig.11 As shown, in the present embodiment, the light-emitting units DU may be arranged, for example, in a pentile matrix, and the signal lines SL may be arranged, for example, in the top-view direction (direction D1) of the electronic device ED to form a plurality of regions RE, wherein each of the light-emitting units DU may be, for example, disposed in the region RE, so that the signal line SL may not overlap with the display unit DU in the top-view direction (direction D1) of the electronic device ED, but the invention is not limited thereto. Since the signal line SL of the present embodiment does not overlap with the display unit DU in the direction D1, the influence of the signal line SL on the display of the electronic device ED may be reduced, but the invention is not limited thereto. It should be noted that the concept of preventing the signal line SL from overlapping with the display unit DU in the top-view direction in the present embodiment may be applied to the various embodiments and variant embodiments of the present disclosure, and therefore will not be described in detail hereinafter. For example, although the location of the display unit is not shown in the above-mentioned embodiments and related drawings, the signal line SL in the electronic device ED may not overlap with the display unit DU in the top-view direction of the electronic device ED. In addition, Fig.11 The arrangement of the display units DU and the signal lines SL shown in the figure is only exemplary, and the present disclosure is not limited thereto. In some embodiments, the display units DU and the signal lines SL may have any suitable arrangement, so that the signal lines SL may not overlap the display units DU in the direction D1.

[0047] It should be noted that although the signal lines SL in this embodiment and the above-mentioned embodiments all have the same shape, the present disclosure is not limited thereto. In some embodiments, one of the signal lines SL may have a different shape from another of the signal lines SL. For example, when one of the signal lines SL includes Fig.11 When the meander pattern shown, another signal line SL may include, for example Figure 1 The straight line graph shown is not limited to the present disclosure. The above-mentioned concept that the signal line SL can have different shapes can be applied to each embodiment and variant embodiment of the present disclosure, so it will not be repeated hereafter.

[0048] Please refer to Fig.13 and Fig.14 , Fig.13 This is a top view of an electronic device according to a sixth embodiment of the present disclosure. Fig.14 This is a cross-sectional view of the electronic device of the sixth embodiment of the present disclosure along the tangent line H-H'. To simplify the drawings, Fig.13 Only the signal line SL and the display unit DU are shown, and the remaining elements and film layers are omitted. Fig.14 The sensing layer SEL is omitted, and the base layer BA of the electronic device ED is simply shown as a three-layer structure. Fig.14 The elements or film layers included in the base layer BA can be referred to Fig.13 The description of the first embodiment and the content of the above-mentioned first embodiment are not repeated here. Fig.13 and Fig.14 The structure shown is Fig.11 and Fig.12 One of the main differences in the structure of the fifth embodiment shown is the design of the signal line. Fig.13 and Fig.14 As shown, the electronic device ED may include, for example, a conductive layer COL1 and a conductive layer COL2, and the conductive layers COL1 and COL2 may include a signal line SL1, a signal line SL2, a signal line SL3, a signal line SL4, a signal line SL5, and a signal line SL6, wherein the signal line SL1, the signal line SL3, and the signal line SL5 may be included in the conductive layer COL1, and the signal line SL2, the signal line SL4, and the signal line SL6 may be included in the conductive layer COL2, but the present invention is not limited thereto. According to the present embodiment, the electronic device ED may include at least two conductive layers, and the signal line SL in one of the conductive layers may overlap with the corresponding signal line SL in the other conductive layer at the turning portion TP of the signal line SL, but the present invention is not limited thereto. Specifically, in the top view direction (direction D1) of the electronic device ED, the signal line SL in the conductive layer COL2 may, for example, extend through the turning portion TP of the signal line SL in the conductive layer COL1, so that the signal line SL in the conductive layer COL2 may overlap or intersect with the signal line SL in the conductive layer COL1 at the turning portion TP, or in other words, the turning portion TP of the signal line SL in the conductive layer COL2 may overlap with the turning portion TP of the signal line SL in the conductive layer COL1, but the present invention is not limited thereto. For example, if Fig.13As shown, the signal line SL4 in the conductive layer COL2 can extend through the turning portion TP of the signal line SL1 in the conductive layer COL1, so that the signal line SL4 and the signal line SL1 can overlap each other at the turning portion TP, but the present invention is not limited thereto. It should be noted that in this embodiment, the signal line SL in the conductive layer COL1 can also overlap the signal line SL in the conductive layer COL2 at the non-turning portion NTP. For example, Fig.13 As shown, the signal line SL1 located in the conductive layer COL1 may overlap with the signal line SL2 located in the conductive layer COL2 in the non-turning portion NTP, but the present invention is not limited thereto. According to the present embodiment, since the signal lines SL in the electronic device ED may be arranged in different conductive layers, the signal lines SL in different conductive layers may overlap with each other to increase the space utilization rate of the electronic device ED, thereby improving the space configuration of the electronic device ED or increasing the number of signal lines SL that can be arranged in the electronic device ED. In addition, since the signal lines SL that overlap with each other in the present embodiment may be arranged in different conductive layers, the interference phenomenon caused by the reduction in the distance between the signal lines may be reduced.

[0049] Please refer to Fig.15 and Fig.16 , Fig.15 is a top view schematic diagram of an electronic device according to a seventh embodiment of the present disclosure, Fig.16 This is a cross-sectional view of the electronic device of the seventh embodiment of the present disclosure along the tangent line II'. To simplify the drawings, Fig.15 Only the signal line SL and the sensing electrode SE are shown, and the remaining elements and film layers are omitted. Fig.16 The base layer BA is shown as a single layer, and the elements or film layers included in the base layer BA can refer to the above embodiments and variant embodiments, so they are not described again. According to this embodiment, the signal lines SL in the electronic device ED can be electrically connected to the corresponding sensing electrodes SE through a plurality of through holes, but this is not limited to this. For example, Fig.15 and Fig.16 As shown, the electronic device ED of this embodiment may include, for example, a sensing electrode SE1, a sensing electrode SE2, a sensing electrode SE3, a sensing electrode SE4, and a signal line SL1, a signal line SL2, a signal line SL3, and a signal line SL4 electrically connected to the sensing electrode SE1, the sensing electrode SE2, the sensing electrode SE3, and the sensing electrode SE4, respectively, wherein the signal line SL1 may be electrically connected to the sensing electrode SE1 through three through holes VH, but the present invention is not limited thereto. Fig.16As shown, in this embodiment, since the signal line SL1 is disposed in the conductive layer COL1, and the conductive layer COL1 is disposed below the sensing layer SEL, the through hole VH may be disposed in the insulating layer IL3, for example, and the sensing electrode SE1 located in the sensing layer SEL may be filled in the three through holes VH and electrically connected to the signal line SL1, but the present invention is not limited thereto. According to this embodiment, since the signal line SL may be electrically connected to the corresponding sensing electrode SE through more than one through hole, the contact impedance between the signal line SL and the sensing electrode SE may be reduced, thereby improving the performance of the electronic device ED, but the present invention is not limited thereto. In addition, in this embodiment, different signal lines SL may be electrically connected to the corresponding sensing electrode SE through different numbers of through holes, for example, Fig.15 As shown, Fig.15 The signal line on the left side in the figure can be electrically connected to the corresponding sensing electrode through two through holes, but the present invention is not limited thereto. The concept of electrically connecting the signal line SL and the sensing electrode SE through multiple through holes in the present embodiment can be applied to various embodiments and variant embodiments of the present disclosure. It should be noted that the number of through holes between the signal line SL and the sensing electrode SE in the present disclosure is not limited to one through hole. Fig.15 The number shown is limited, and any suitable number can be provided according to design requirements.

[0050] Please refer to Fig.17 and Fig.18 , Fig.17 is a top view schematic diagram of an electronic device according to an eighth embodiment of the present disclosure, Fig.18 This is an enlarged cross-sectional view of a portion A1 of the electronic device of the eighth embodiment of the present disclosure. To simplify the drawings, Fig.17 Only a part of the electronic device ED is shown (for example Figure 1 In addition, Fig.18 The sensing layer is omitted, and the base layer BA is illustrated as a single layer, but the present invention is not limited thereto. Fig.17 and Fig.18 As shown, the electronic device ED may include, for example, a sensing electrode SE1, a sensing electrode SE2, a signal line SL1 and a signal line SL2 electrically connected to the sensing electrode SE1 and the sensing electrode SE2, respectively, and a sensing circuit SC1 and a sensing circuit SC2 electrically connected to the signal line SL1 and the signal line SL2, respectively, wherein the sensing electrode SE1 and the sensing electrode SE2 may be arranged on a sensing layer ( Fig.17 and Fig.18 (not shown), the signal line SL1 may be included in the conductive layer COL1 ( Fig.18(not shown), and the signal line SL2 may be included in the conductive layer COL2, but is not limited thereto. As described above, the sensing electrode SE in this embodiment may be, for example, a touch element or a fingerprint recognition element, such as a capacitive touch element or a capacitive fingerprint recognition element, and the signal line SL electrically connected to the sensing electrode SE may, for example, transmit the signal detected by the sensing electrode SE to the sensing circuit SC located in the peripheral area PR, and the sensing circuit SC may output a corresponding signal to the sensing processor SP based on the received signal and perform signal processing to obtain information on the touch position or the pattern of the fingerprint, but is not limited thereto. For example, if Fig.17 As shown, the sensing circuit SC may include a sensing scan line SSL, a sensing common line SCL, and a sensing output line SOL, wherein the sensing common line SCL may be electrically connected to a reference voltage or a common voltage, but is not limited thereto. The sensing scan line SSL, the sensing common line SCL, and the sensing output line SOL may, for example, include any suitable conductive material, such as a metal material, but is not limited thereto. According to this embodiment, the sensing electrode SE may transmit a capacitive signal to the corresponding sensing circuit SC through the signal line SL, and the corresponding sensing circuit SC may transmit a corresponding output signal to the sensing processor SP through the sensing output line SOL after receiving the signal from the sensing electrode SE and perform signal processing. For example, when the object does not touch the surface of the electronic device ED, the sensing electrode SE may transmit a fixed signal to the corresponding sensing circuit SC through the signal line SL, so that the sensing circuit SC may output a fixed corresponding signal to the sensing processor SP through the sensing output line SOL, and when the object touches the surface of the electronic device ED, the capacitance value detected by the sensing electrode SE corresponding to the contact position of the object may change, causing the capacitance signal transmitted to the corresponding sensing circuit SC to change accordingly, thereby changing the signal transmitted to the sensing processor SP, and the information of the touch position may be obtained after signal processing, but not limited to this. In addition, when the sensing electrode SE has high resolution and / or density, the peaks and valleys of the fingerprint may cause the capacitance values ​​detected by the sensing electrode SE to be different, so that the signals transmitted to the sensing circuit SC and the sensing processor SP are different, so the fingerprint pattern can be analyzed by the sensing processor SP, for example, to achieve the function of identifying the fingerprint, but not limited to this.

[0051] According to this embodiment, the signal lines SL electrically connected to the sensing electrodes SE in the electronic device ED may be arranged in different conductive layers, and the signal lines SL arranged in one of the conductive layers may be transferred to other conductive layers before being electrically connected to the corresponding sensing circuits SC, so that all the signal lines SL may be located in the same conductive layer, for example, but not limited thereto. Fig.18As shown, the signal line SL2 electrically connected to the sensing electrode SE2 and the sensing circuit SC2 may be arranged in the conductive layer COL2, wherein the conductive layer COL2 may be located on the conductive layer COL1 on which the signal line SL1 is arranged, and before the signal line SL2 is electrically connected to the sensing circuit SC2, it may be transferred to the conductive layer COL1, so that both the signal line SL1 and the signal line SL2 may be located in the conductive layer COL1, but the present invention is not limited thereto. For example, the signal line SL2 may be transferred to the conductive layer COL1 through the through hole VH, but the present invention is not limited thereto. Since the signal lines SL arranged in different conductive layers may be located in the same conductive layer (e.g., the conductive layer COL1) before being electrically connected to the sensing circuit SC, for example, through a transfer process, the routing design and / or layout of the signal line SL electrically connected to the sensing circuit SC may be simplified. In other words, although the signal line SL may be arranged in the conductive layer COL1 and the conductive layer COL2 in the present embodiment, the routing of the signal line SL electrically connected to the sensing circuit SC may, for example, be arranged only in the conductive layer COL1, but the present invention is not limited thereto. It should be noted that the concept of switching the signal lines in this embodiment so that the signal lines SL can be located in the same conductive layer can be applied to each embodiment and variant embodiment of the present disclosure.

[0052] In summary, the present disclosure provides an electronic device, which includes a plurality of sensing electrodes and a plurality of signal lines electrically connected to the corresponding sensing electrodes. When the resolution and / or density of the sensing electrodes in the electronic device increases, the number of required signal lines may increase accordingly, making it more difficult to arrange the signal lines in the electronic device in a general manner, or the signal lines may interfere with each other due to the small spacing. However, since the signal lines in the electronic device of the present disclosure can be arranged in different conductive layers, the spacing of the signal lines in the top view direction of the electronic device can be reduced, so as to improve the spatial configuration of the electronic device ED while reducing the mutual interference of the signal lines.

[0053] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic device, characterized in that: include: a basal layer; a first sensing electrode, disposed on the base layer; a second sensing electrode, disposed on the base layer and adjacent to the first sensing electrode; A first conductive line, disposed on the base layer; as well as an insulating layer, located between the first sensing electrode and the first wire and comprising at least three first through holes; The first wire is electrically connected to the first sensing electrode through the at least three first through holes, and the first wire passes over the second sensing electrode and is not electrically connected to the second sensing electrode.

2. The electronic device according to claim 1, characterized in that: The at least three first through holes overlap the first conductive line and the first sensing electrode.

3. The electronic device according to claim 1, characterized in that: Two first through holes among the at least three first through holes are arranged along a first direction.

4. The electronic device according to claim 3, characterized in that: A third sensing electrode is also included, wherein the third sensing electrode and the first sensing electrode are arranged along the first direction, and the second sensing electrode is arranged between the first sensing electrode and the third sensing electrode.

5. The electronic device according to claim 4, characterized in that: The first conductive line overlaps the third sensing electrode.

6. The electronic device according to claim 4, characterized in that: A second conductive line is also included, wherein the insulating layer further includes at least three second through holes, and the second conductive line is electrically connected to the third sensing electrode through the at least three second through holes.

7. The electronic device according to claim 6, characterized in that: Two second through holes among the at least three second through holes are arranged along the first direction.

8. The electronic device according to claim 6, characterized in that: The second conductive line does not cross the first sensing electrode.

9. The electronic device according to claim 1, characterized in that: The first conductive line includes a turning portion, and the turning portion has an arc shape.

10. The electronic device according to claim 1, characterized in that: The base layer includes a light-emitting unit, and in a top view of the electronic device, the first conductive line does not overlap the light-emitting unit.

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