Flash memory unit erasing method and device for reducing threshold voltage distribution and storage medium

Abstract

The invention discloses a flash memory unit erasing method and device for reducing threshold voltage distribution and a storage medium, and the method comprises the steps: obtaining a programming flash memory unit and an erasing flash memory unit of a to-be-erased storage block according to an erasing instruction; performing suppression processing on the programming flash memory unit and performing pre-programming processing on the erasing flash memory unit to obtain a processed storage block to be erased; and performing erasing operation work on the processed storage block to be erased. According to the method, the programming flash memory unit is subjected to suppression processing, and then the erasing flash memory unit is subjected to pre-programming processing; therefore, the programming flash memory unit is not influenced by the erasing process, and the threshold voltage of the programming flash memory unit is not changed, so that the threshold voltage distribution range is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a flash memory unit erasing method, device and storage medium for reducing threshold voltage distribution. Background Art

[0002] NAND FLASH (flash memory) is a common non-volatile memory. With the growing demand for memory capacity and performance in embedded systems and electronic devices, NAND FLASH, as a low-cost, easy-to-integrate memory, has become the first choice for solutions. NAND FLASH is widely used in embedded systems and electronic devices. However, in the use of embedded systems and electronic devices, data erasure operations are often faced. When performing data erasure operations, the flash memory cells in the storage block of NAND FLASH are erased. However, there are multiple flash memory cells in the storage block, and flash memory cells in the programming state and the erased state exist at the same time. During the erase operation, the flash memory cells in the programming state will be affected by the erase pulse stress generated by the flash memory cells in the erased state, causing the flash memory cells in the programming state to be over-erased, thereby making the threshold voltage distribution range of the flash memory cells in the storage block larger. Therefore, when performing an erase operation on NAND FLASH, it is necessary to reduce the influence of the erase pulse stress generated by the flash memory cells in the erased state.

[0003] However, the existing flash memory cell erasing method usually performs programming operations on all flash memory cells in a storage block, so as to convert the flash memory cells in the erased state in the storage block into the programmed state. However, in the process of programming the flash memory cells in the erased state, the flash memory cells in the programmed state will also be programmed. In this way, the flash memory cells in the programmed state will be over-programmed, so that the threshold voltage distribution range of the flash memory cells in the storage block is larger, causing the problem of NAND FLASH performance degradation.

[0004] Therefore, there is still an urgent need for a flash memory cell erasing method that can reduce threshold voltage distribution and improve NAND FLASH performance. Summary of the invention

[0005] The main purpose of the present invention is to propose a flash memory cell erasing method, device and storage medium with reduced threshold voltage distribution, so as to solve the problem that when the existing defective NAND FLASH is erased, the threshold voltage distribution range of the flash memory cell in the storage block is large, thereby reducing the performance of the NAND FLASH.

[0006] To achieve the above object, the present invention provides a flash memory cell erasing method for reducing threshold voltage distribution, the flash memory cell erasing method for reducing threshold voltage distribution comprising:

[0007] According to the erase instruction, the program flash memory unit and the erase flash memory unit of the storage block to be erased are obtained;

[0008] Performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased;

[0009] An erasing operation is performed on the processed storage block to be erased.

[0010] In some embodiments, the step of obtaining the programming flash memory unit and the erasing flash memory unit of the storage block to be erased includes:

[0011] Reading the current state of each flash memory cell in the storage block to be erased, wherein the current state includes a programming state and an erasing state;

[0012] If the current state of the flash memory cell is the programming state, determining that the flash memory cell is a programming flash memory cell;

[0013] If the current state of the flash memory unit is the erase state, it is determined that the flash memory unit is an erased flash memory unit.

[0014] In some embodiments, the inhibiting process on the program flash memory unit and the pre-programming process on the erase flash memory unit include:

[0015] performing the suppression process on the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed;

[0016] The pre-programming process is performed on the erased state of the erased flash memory unit to change the erased flash memory unit from the erased state to the programmed state.

[0017] In some embodiments, before reading the current state of each flash memory cell in the storage block to be erased, the method further includes:

[0018] Get each storage block;

[0019] The storage block to be erased is determined from the storage blocks.

[0020] In some embodiments, before acquiring the program flash memory unit and the erase flash memory unit of the storage block to be erased according to the erase instruction, the method further includes:

[0021] Get the erasure information entered by the user;

[0022] The erasure instruction is generated according to the erasure information input by the user.

[0023] In some embodiments, it also includes:

[0024] Respectively acquiring a threshold voltage of the programming flash memory cell and a threshold voltage of the erasing flash memory cell during an erasing operation;

[0025] Determining a threshold voltage distribution value according to a distance between a threshold voltage of the programming flash memory cell and a threshold voltage of the erasing flash memory cell;

[0026] Determining whether the threshold voltage distribution value is less than a preset distribution value;

[0027] If the threshold voltage distribution value is less than the preset distribution value, it is determined that the inhibition process and the pre-programming process are successful.

[0028] In some embodiments, after performing the erasing operation on the processed storage block to be erased, the method further includes:

[0029] Determining whether the erasing operation is successful;

[0030] If the erasing operation is successful, the erasing operation is terminated.

[0031] In some embodiments, after the erasing operation is ended, the method further includes:

[0032] Acquire the programming flash memory cell in the inhibition process;

[0033] The inhibit process of the program flash memory cell is ended.

[0034] The present invention also provides a flash memory cell erasing device for reducing threshold voltage distribution, comprising:

[0035] at least one processor; and,

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0038] The present invention also provides a storage medium storing a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0039] The present invention suppresses the programming flash memory unit and then performs pre-programming processing on the erasing flash memory unit; the programming flash memory unit is not affected whether in the pre-programming processing stage of the erasing flash memory unit or in the erasing operation of the storage block to be erased; the threshold voltage of the programming flash memory unit remains unchanged, so that when the NANDFLASH performs the erasing operation, the threshold voltage distribution range between the flash memory units in the storage block is reduced, and the performance of the NANDFLASH is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic flow chart of a flash memory cell erasing method for reducing threshold voltage distribution in an embodiment of the present invention;

[0041] Figure 2 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0042] Figure 3 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0043] Figure 4 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0044] Figure 5 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0045] Figure 6 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0046] Figure 7 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0047] Figure 8 Another schematic diagram of the process of erasing a flash memory cell for reducing threshold voltage distribution according to an embodiment of the present invention;

[0048] Fig. 9 It is a schematic structural diagram of a flash memory cell erasing device for reducing threshold voltage distribution according to an embodiment of the present invention;

[0049] Fig.10 A schematic diagram of a threshold voltage of a programming flash memory cell and a threshold voltage of an erasing flash memory cell according to an embodiment of the present invention;

[0050] Fig.11Another schematic diagram of the threshold voltage of programming a flash memory cell and the threshold voltage of erasing a flash memory cell according to an embodiment of the present invention;

[0051] Fig.12 Another schematic diagram of the threshold voltage of programming a flash memory cell and the threshold voltage of erasing a flash memory cell according to an embodiment of the present invention;

[0052] Fig.13 Another schematic diagram of a threshold voltage for programming a flash memory cell and a threshold voltage for erasing a flash memory cell according to an embodiment of the present invention.

[0053] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0054] The scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0057] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0058] To achieve the above object, the present invention provides a flash memory cell erasing method for reducing threshold voltage distribution. The flash memory cell erasing method for reducing threshold voltage distribution includes:

[0059] Step S110, obtaining the programming flash memory unit and the erasing flash memory unit of the storage block to be erased according to the erase instruction;

[0060] Step S120, performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased;

[0061] Step S130, performing an erasing operation on the processed storage block to be erased.

[0062] In this embodiment, refer to Figure 1 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 , the flash memory cell erasing method with reduced threshold voltage distribution can be applied to the flash memory cell erasing device with reduced threshold voltage distribution. The flash memory cell erasing device with reduced threshold voltage distribution can be configured inside the NAND FLASH (flash memory) so that the NAND FLASH can execute the flash memory cell erasing method with reduced threshold voltage distribution. Among them, the NAND FLASH can be an SPI NAND FLASH (Serial Peripheral Interface NAND FLASH, flash memory with serial peripheral interface) or a PPI NAND FLASH (Parallel Pin Interface NAND FLASH, flash memory with parallel peripheral interface). The NAND FLASH can reduce the threshold voltage distribution between the flash memory cells when performing the erasing operation through the flash memory cell erasing device with reduced threshold voltage distribution. In this embodiment, the execution subject of the method steps is the NAND FLASH configured with the flash memory cell erasing device with reduced threshold voltage distribution.

[0063] It can be understood that NAND FLASH includes multiple storage blocks, each storage block includes multiple flash memory cells, and the storage block to be erased is a storage block waiting to be erased; some flash memory cells in the storage block are in a programming state, and some flash memory cells are in an erasing state; so that when NAND FLASH performs an erase operation on any storage block, the programming flash memory cells and the erasing flash memory cells in the storage block coexist.

[0064] exist Figures 10 to 13 The graph shown in is a graph showing the changes in the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell as the flash memory cell erasing method of reducing the threshold voltage distribution is performed. Figures 10 to 13In the table, erase refers to erasing the threshold voltage of the flash memory cell, program refers to programming the threshold voltage of the flash memory cell, VT(V) refers to the threshold voltage (in volts), Bit refers to the number of erase pulses, and the coordinate axis can be understood as the threshold voltage changing with the number of erase pulses. Fig.10 A schematic diagram of the threshold voltage when executing the erase instruction step; Fig.11 A schematic diagram of the threshold voltage after performing the inhibition process on the program flash memory cell and the pre-programming process on the erase flash memory cell; Fig.12 A schematic diagram of the threshold voltage during the process of performing an erasing operation on a processed storage block to be erased; Fig.13 A schematic diagram of the threshold voltage after performing an erase operation on a processed storage block to be erased.

[0065] When the user needs to erase the NAND FLASH, the user can input an erase command to the NAND FLASH, and then the NAND FLASH can receive the erase command. The NAND FLASH can obtain the programming flash memory cells and the erasing flash memory cells of the storage block to be erased according to the erase command. The flash memory cells in the storage block to be erased are distinguished, thereby obtaining the programming flash memory cells and the erasing flash memory cells.

[0066] At this time, by detecting the threshold voltage of the programming flash memory cell and the erasing flash memory cell, we can get Fig.10 As shown in the schematic diagram, since the programming or erasing operation of the storage block is realized through different threshold voltages, the threshold voltage of erasing the flash memory cell and the threshold voltage of programming the flash memory cell are respectively on the two sides of the coordinate axis.

[0067] NAND FLASH distinguishes each flash memory cell in the storage block to be erased, and obtains the programming flash memory cell and the erasing flash memory cell; NAND FLASH first suppresses the programming flash memory cell, and then performs pre-programming on the erasing flash memory cell. Thus, the processed storage block to be erased is obtained. Since NAND FLASH first suppresses the programming flash memory cell, NAND FLASH then performs pre-programming on the erasing flash memory cell, and does not perform programming operation on the programming flash memory cell together, thus preventing over-programming of the programming flash memory cell.

[0068] At this time, by detecting the threshold voltage of the programming flash memory cell and the erasing flash memory cell, we can get Fig.11Schematic diagram shown. Since the programming flash memory cell is suppressed, when NAND FLASH performs pre-programming on the erased flash memory cell, the programming flash memory cell will not be programmed together, so that the threshold voltage of the programming flash memory cell will not change; since the erased flash memory cell is pre-programmed, the threshold voltage of the erased flash memory cell will shift to the right, thereby approaching the threshold voltage of the programming flash memory cell. If the programming flash memory cell is not suppressed first, then when the erased flash memory cell is pre-programmed, the programming flash memory cell will also be programmed together; at this time, the threshold voltage of the programming flash memory cell will also shift to the right, so that the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programming flash memory cell will not be significantly reduced, that is, the threshold voltage distribution is not significantly reduced. However, by suppressing the programming flash memory cell first in this embodiment and then pre-programming the erased flash memory cell, the threshold voltage of the programming flash memory cell remains unchanged, and the threshold voltage of the erased flash memory cell shifts to the right, which will shorten the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programming flash memory cell, that is, the threshold voltage distribution is reduced.

[0069] Since the flash memory cells can be directly operated when reading, writing, programming and other operations are performed in NAND FLASH, while the storage blocks can only be operated when erasing. Therefore, when NAND FLASH performs an erase operation, it is performed on the storage blocks. After NAND FLASH performs suppression processing and pre-programming processing on the storage blocks to be erased to obtain the processed storage blocks to be erased, the erase operation can be performed on the processed storage blocks to be erased.

[0070] Since the erase operation is performed on the processed memory block to be erased, at this time, the threshold voltages of the programming flash memory cell and the erasing flash memory cell are detected, and the Fig.12 The programming flash memory cell and the erasing flash memory cell are both affected in the same way, so that the threshold voltage of the erasing flash memory cell and the threshold voltage of the programming flash memory cell are shifted to the left at the same time. At this time, the distance between the threshold voltage of the erasing flash memory cell and the threshold voltage of the programming flash memory cell does not change. After the erasing operation is completed on the processed storage block to be erased, it can be obtained Fig.13 As shown in the schematic diagram, the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell has not changed; therefore, after the threshold voltage distribution is reduced as mentioned above, when the erase operation is performed on the processed storage block to be erased, the threshold voltage distribution has not changed, so that before the NAND FLASH performs the erase operation, the programmed flash memory cell is first suppressed, and then the erased flash memory cell is pre-programmed, and then the erase operation is performed, which can reduce the threshold voltage distribution between the flash memory cells during and after the erase operation.

[0071] Similarly, if the erasing operation is performed directly without performing the suppression process and pre-programming process on the storage block to be erased, the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell are as follows: Fig.10 As shown, they shift to the left at the same time. At this time, the distance between the threshold voltage of the erased flash memory cell and the threshold voltage of the programmed flash memory cell is very large, that is, the threshold voltage distribution is large.

[0072] Through this embodiment, the programming flash memory unit is suppressed and the erasing flash memory unit is pre-programmed; the programming flash memory unit is not affected whether it is in the pre-programming processing stage of the erasing flash memory unit or in the erasing operation of the storage block to be erased; the threshold voltage of the programming flash memory unit remains unchanged, so that when the NAND FLASH performs an erasing operation, the threshold voltage distribution range between the flash memory units in the storage block is reduced, and the performance of the NAND FLASH is improved.

[0073] In some embodiments, the aforementioned obtaining of the programming flash memory unit and the erasing flash memory unit of the storage block to be erased includes:

[0074] Step S140, reading the current state of each flash memory cell in the storage block to be erased, wherein the current state includes a programming state and an erasing state;

[0075] Step S141, if the current state of the flash memory cell is a programming state, determining that the flash memory cell is a programming flash memory cell;

[0076] Step S142: if the current state of the flash memory unit is the erase state, determine that the flash memory unit is an erase flash memory unit.

[0077] In this embodiment, refer to Figure 2 When NAND FLASH executes step S110, it distinguishes the flash memory cells according to the current state. Wherein, NAND FLASH includes multiple storage blocks, and the storage block includes multiple flash memory cells. The storage block to be erased is the storage block to be erased. NAND FLASH first reads each flash memory cell in the storage block to be erased, so as to obtain the current state of each flash memory cell in each flash memory cell; wherein, the current state includes a programming state and an erase state.

[0078] If NAND FLASH determines that the current state of the flash memory cell is a programming state, the flash memory cell may be determined as a programming flash memory cell.

[0079] If NAND FLASH determines that the current state of the flash memory cell is an erase state, the flash memory cell may be determined as an erased flash memory cell.

[0080] NAND FLASH divides each flash memory cell into a programming flash memory cell and an erasing flash memory cell according to the current state of the flash memory cell.

[0081] In some embodiments, the aforementioned inhibiting process for programming flash memory cells and pre-programming process for erasing flash memory cells include:

[0082] Step S150, suppressing the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed;

[0083] Step S151, pre-programming the erased state of the erased flash memory unit to change the erased flash memory unit from the erased state to the programmed state.

[0084] In this embodiment, refer to Figure 3 When NAND FLASH executes step S120, it first performs suppression processing and then performs pre-programming processing. NAND FLASH first performs suppression processing on the programming state of the programming flash memory cell, so that the programming state of the programming flash memory cell is suppressed; then, it performs pre-programming processing on the erasing state of the erasing flash memory cell, so that the erasing flash memory cell is changed from the erasing state to the programming state. After the suppression processing is performed on the programming state of the programming flash memory cell, when the pre-programming processing is performed on the erasing state of the erasing flash memory cell, the programming flash memory cell will not be programmed together, thereby preventing the programming flash memory cell from being over-programmed.

[0085] In some embodiments, before reading the current state of each flash memory cell in the storage block to be erased, the method further includes:

[0086] Step S160, obtaining each storage block;

[0087] Step S161, determining a storage block to be erased from each storage block.

[0088] In this embodiment, refer to Figure 4 Before executing step S140, NAND FLASH needs to obtain the storage block to be erased. NAND FLASH includes multiple storage blocks, and the storage block to be erased is the storage block waiting to be erased. NAND FLASH first obtains each internal storage block, and then finds the storage block that needs to be erased from each storage block, that is, determines the storage block to be erased from each storage block. For example: NAND FLASH can determine the data to be erased according to the erase instruction, and then determine which storage block the data to be erased is stored in. After finding the storage block storing the data to be erased, the storage block can be determined as the storage block to be erased.

[0089] In some embodiments, before obtaining the programming flash memory unit and the erasing flash memory unit of the storage block to be erased according to the erase instruction, the method further includes:

[0090] Step S100, obtaining erasure information input by a user;

[0091] Step S101, generating an erasure instruction according to the erasure information input by the user.

[0092] In this embodiment, refer to Figure 5 Before executing step S110, NAND FLASH may also generate instructions based on the information input by the user. NAND FLASH obtains the erasure information input by the user, and then generates an erasure instruction based on the erasure information input by the user. For example, when a user wants to delete a part of the files in a folder in NAND FLASH, the erasure information input may be to select the part of the files and then confirm the deletion; at this time, NAND FLASH may receive the erasure information and then generate an erasure instruction for the part of the files based on the erasure information.

[0093] In some embodiments, the aforementioned flash memory cell erasing method for reducing threshold voltage distribution further includes:

[0094] Step S170, respectively obtaining a threshold voltage of a programming flash memory cell and a threshold voltage of an erasing flash memory cell during an erasing operation;

[0095] Step S171, determining a threshold voltage distribution value according to a distance between a threshold voltage of a programming flash memory cell and a threshold voltage of an erasing flash memory cell;

[0096] Step S172, determining whether the threshold voltage distribution value is less than a preset distribution value;

[0097] Step S173: if the threshold voltage distribution value is less than the preset distribution value, it is determined that the suppression process and the pre-programming process are successful.

[0098] In this embodiment, refer to Figure 6 , Fig.10 , Fig.11 , Fig.12 and Fig.13 , NAND FLASH can also obtain the threshold voltage of each flash memory cell during the execution of step S130. NAND FLASH obtains the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell during the erase operation respectively; then determines the threshold voltage distribution value according to the distance between the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell. Then NAND FLASH compares the threshold voltage distribution value with the preset distribution value; wherein the preset distribution value is customized by the user according to the actual test requirements.

[0099] If the NAND FLASH determines that the threshold voltage distribution value is less than the preset distribution value, it determines that the inhibition process and the pre-programming process are successful.

[0100] If the NAND FLASH determines that the threshold voltage distribution value is greater than the preset distribution value, it determines that the inhibition process and the pre-programming process have failed. At this time, the NAND FLASH will perform the steps of inhibiting the programming flash memory cell and pre-programming the erasing flash memory cell for a second time.

[0101] Of course, NAND FLASH can obtain the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell in any period of the erasing operation after executing the steps of inhibiting the programming flash memory cell and pre-programming the erasing flash memory cell for judgment. For example, the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell after the erasing operation can be obtained respectively; Fig.13 As shown, the threshold voltage distribution value is determined according to the distance between the threshold voltage of the programming flash memory cell and the threshold voltage of the erasing flash memory cell, and then it is determined whether the threshold voltage distribution value is less than the preset distribution value.

[0102] In some embodiments, after performing an erase operation on the processed storage block to be erased in the foregoing, the method further includes:

[0103] Step S180, determining whether the erase operation is successful;

[0104] Step S181: if the erasing operation is successful, the erasing operation is terminated.

[0105] In this embodiment, refer to Figure 7 After executing step S130, NAND FLASH can also determine whether the erasing operation is successful. After NAND FLASH performs the erasing operation on the processed storage block to be erased, it can determine whether the erasing operation on the storage block to be erased is successful. If NAND FLASH determines that the erasing operation on the storage block to be erased is successful, NAND FLASH can end the erasing operation. If NAND FLASH determines that the erasing operation on the storage block to be erased fails, NAND FLASH will execute the step of performing the erasing operation on the processed storage block to be erased again.

[0106] In some embodiments, after the erasing operation is finished, the method further includes:

[0107] Step S190, obtaining a program flash memory cell in the inhibition process;

[0108] Step S191, ending the inhibition process of programming the flash memory cell.

[0109] In this embodiment, refer to Figure 8 After NAND FLASH executes step S181, it also ends the inhibition process. After NAND FLASH ends the erase operation, NAND FLASH acquires the programming flash memory cell that is in the inhibition process, and then ends the inhibition process of the programming flash memory cell, so that the programming flash memory cell can continue the programming operation.

[0110] The present invention suppresses the programming flash memory unit and then performs pre-programming processing on the erasing flash memory unit; the programming flash memory unit is not affected whether in the pre-programming processing stage of the erasing flash memory unit or in the erasing operation of the storage block to be erased; the threshold voltage of the programming flash memory unit remains unchanged, so that when the NANDFLASH performs the erasing operation, the threshold voltage distribution range between the flash memory units in the storage block is reduced, and the performance of the NANDFLASH is improved.

[0111] The flash memory cell erasing device with reduced threshold voltage distribution according to the embodiment of the present invention may be a controller capable of executing the flash memory cell erasing method with reduced threshold voltage distribution; the controller has at least one. Fig. 9 As shown, the flash memory cell erasing device for reducing the threshold voltage distribution may include: a controller 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned controller 1001.

[0112] Those skilled in the art will understand that Fig. 9 The structure of the flash memory cell erasing device with reduced threshold voltage distribution shown in the figure does not constitute a limitation on the flash memory cell erasing device with reduced threshold voltage distribution, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0113] like Fig. 9 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0114] exist Fig. 9In the flash memory cell erasing device with reduced threshold voltage distribution shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the controller 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the controller 1001, the steps of the flash memory cell erasing method with reduced threshold voltage distribution are implemented.

[0115] The present invention also provides a storage medium storing a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes any one of the above-mentioned flash memory cell erasing methods for reducing threshold voltage distribution.

[0116] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A flash memory cell erasing method for reducing threshold voltage distribution, characterized in that: The flash memory cell erasing method for reducing threshold voltage distribution comprises: According to the erase instruction, the program flash memory unit and the erase flash memory unit of the storage block to be erased are obtained; Performing suppression processing on the program flash memory unit and pre-programming processing on the erase flash memory unit to obtain a processed storage block to be erased; An erasing operation is performed on the processed storage block to be erased.

2. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, characterized in that: The step of obtaining a programming flash memory unit and an erasing flash memory unit of a storage block to be erased comprises: Reading the current state of each flash memory cell in the storage block to be erased, wherein the current state includes a programming state and an erasing state; If the current state of the flash memory cell is the programming state, determining that the flash memory cell is a programming flash memory cell; If the current state of the flash memory unit is the erase state, it is determined that the flash memory unit is an erased flash memory unit.

3. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 2, characterized in that: The inhibiting process of the program flash memory unit and the pre-programming process of the erase flash memory unit include: Performing the suppression process on the programming state of the programming flash memory cell so that the programming state of the programming flash memory cell is suppressed; The pre-programming process is performed on the erased state of the erased flash memory unit to change the erased flash memory unit from the erased state to the programmed state.

4. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 2, characterized in that: Before reading the current state of each flash memory cell in the storage block to be erased, the method further includes: Get each storage block; The storage block to be erased is determined from the storage blocks.

5. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 4, characterized in that: Before obtaining the programming flash memory unit and the erasing flash memory unit of the storage block to be erased according to the erase instruction, the method further includes: Get the erasure information entered by the user; The erasure instruction is generated according to the erasure information input by the user.

6. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, characterized in that: Also includes: Respectively acquiring a threshold voltage of the programming flash memory cell and a threshold voltage of the erasing flash memory cell during an erasing operation; Determining a threshold voltage distribution value according to a distance between a threshold voltage of the programming flash memory cell and a threshold voltage of the erasing flash memory cell; Determining whether the threshold voltage distribution value is less than a preset distribution value; If the threshold voltage distribution value is less than the preset distribution value, it is determined that the inhibition process and the pre-programming process are successful.

7. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 1, characterized in that: After performing the erasing operation on the processed storage block to be erased, the method further includes: Determining whether the erasing operation is successful; If the erasing operation is successful, the erasing operation is terminated.

8. The flash memory cell erasing method for reducing threshold voltage distribution according to claim 7, characterized in that: After the erasing operation is finished, the method further includes: Acquire the programming flash memory cell in the inhibition process; The inhibit process of the program flash memory cell is ended.

9. A flash memory cell erasing device with reduced threshold voltage distribution, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executed by the at least one processor, wherein the instructions are executed by the at least one processor so as to enable the at least one processor to perform the flash memory cell erasing method for reducing threshold voltage distribution according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the flash memory cell erasing method for reducing threshold voltage distribution according to any one of claims 1 to 8.

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