Data processing method and device, electronic equipment, medium and program product

Abstract

The invention discloses a data processing method and device, electronic equipment, a medium and a program product, and belongs to the technical field of electronic equipment. The data processing method comprises the following steps: controlling a central processing unit (CPU) to send a data copying command to a universal flash memory (UFS); the data copying command is used for indicating a source address and a destination address of data copying; and controlling the UFS to copy the data of the source address to the destination address in response to the data copying command.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and in particular, relates to a data processing method, device, electronic equipment, medium and program product. Background Art

[0002] In the mobile phone user scenario, data copying is a very common operation. In the current data copying process, the central processing unit (CPU) sends a command to read the data from the universal flash storage (UFS) location 1 to the low power double data rate (LPDDR). The data itself is not modified and is only written back to the UFS location 2. This process actually causes redundant IO reading and writing processes, which leads to low data copying efficiency. Summary of the invention

[0003] The embodiments of the present application provide a data processing method, device, electronic device, medium and program product to improve data copying efficiency.

[0004] In order to solve the above technical problems, this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a data processing method, including:

[0006] Controlling the central processing unit CPU to send a data copy command to the universal flash storage UFS; the data copy command is used to indicate the source address and destination address of the data copy;

[0007] The UFS is controlled to copy the data at the source address to the destination address in response to the data copy command.

[0008] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0009] Optionally, the number of the source address information is one, and the number of the destination address information is one.

[0010] Optionally, the number of the source address information is one, and the number of the destination address information is at least two.

[0011] Optionally, the number of the source address information is at least two, and the number of the destination address information is one.

[0012] Optionally, the number of the source address information is at least two, and the at least two source address information include first source address information and second source address information;

[0013] The number of the destination address information is at least two, and the at least two destination address information include first destination address information and second destination address information;

[0014] There is a copy relationship between the first source address information and the first destination address information;

[0015] There is a copy relationship between the second source address information and the second destination address information.

[0016] Optionally, the source address information includes a source address and a data volume corresponding to the source address, the destination address information includes a destination address and a data volume corresponding to the destination address, and the sum of the data volumes corresponding to at least two of the source addresses is equal to the data volume corresponding to the destination address.

[0017] Optionally, the source address information includes the source address and the data volume corresponding to the source address, the destination address information includes the destination address and the data volume corresponding to the destination address, the data volume corresponding to the first source address information is equal to the data volume between the first destination address information, and the data volume corresponding to the second source address information is equal to the data volume between the second destination address information.

[0018] Optionally, the number of the source address is at least one, and the number of the destination address is at least one;

[0019] The controlling the UFS to copy the data at the source address to the destination address in response to the data copy command includes:

[0020] Controlling the UFS to read data from each of the source addresses in response to the data copy command;

[0021] The UFS is controlled to copy the data read from each source address to the corresponding destination address.

[0022] Optionally, before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes:

[0023] Controlling the CPU to perform validity check on the data copy command;

[0024] The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including:

[0025] When the data copy command is valid, the CPU is controlled to send the data copy command to the UFS controller.

[0026] Optionally, the control CPU performs validity verification on the data copy command, including:

[0027] Control the CPU to perform validity check on at least one of the following items in the data copy command:

[0028] Whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address;

[0029] whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information;

[0030] Whether the source address and the destination address are valid, the validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of UFS.

[0031] Optionally, the method further comprises:

[0032] Control the UFS to return the data copy result to the CPU;

[0033] In a case where the data copy result includes abnormal information, the CPU is controlled to execute an error processing operation corresponding to the abnormal information.

[0034] Optionally, in an incremental upgrade scenario, the controlling the CPU to perform an error handling operation corresponding to the exception information includes:

[0035] The CPU is controlled to remap the partitions, and the upgrade progress is synchronized to the kernel, so that the kernel performs the upgrade process.

[0036] Optionally, in the scenario of incremental upgrade, before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes:

[0037] Control the CPU to sort operations and arrange all data copy operations included in the incremental upgrade process after non-data copy operations;

[0038] The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including:

[0039] After executing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0040] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is used to read data from a source address of the data storage unit and write the read data to a target address of the data storage unit in response to the data copy command.

[0041] In a second aspect, an embodiment of the present application provides a data processing device, including:

[0042] A first control module is used to control the central processing unit CPU to send a data copy command to the universal flash storage UFS controller; the data copy command is used to indicate a source address and a destination address of the data copy;

[0043] The second control module is used to control the UFS controller to copy the data at the source address to the destination address in response to the data copy command.

[0044] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0045] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps described in the first aspect.

[0046] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps described in the first aspect are implemented.

[0047] In a fifth aspect, an embodiment of the present application further provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps described in the first aspect.

[0048] In a sixth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0049] In an embodiment of the present application, by controlling the CPU to send a copy command carrying a source address and a destination address to the UFS, the UFS is controlled to directly obtain data from the indicated source address and copy it to the location indicated by the destination address, thereby reducing the signaling interaction process in the data copy process and improving the data copy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a flowchart of a data processing method according to an embodiment of the present application;

[0051] Figure 2 It is a schematic diagram of the architecture of an embodiment of the present application;

[0052] Figure 3 It is a schematic diagram of the data copy process of an embodiment of the present application;

[0053] Figure 4 This is a schematic diagram of the entry format;

[0054] Figure 5 This is a command format diagram;

[0055] Figure 6 It is a detailed information diagram of the data copy command;

[0056] Figure 7 It is a schematic diagram of the reading and writing sequence;

[0057] Figure 8 This is a schematic diagram of the incremental upgrade process;

[0058] Fig. 9 This is a schematic diagram of the exception handling process during the incremental upgrade process;

[0059] Fig.10 is a module schematic diagram of a data processing device according to an embodiment of the present application;

[0060] Fig.11 It is one of the structural schematic diagrams of the electronic device according to the embodiment of the present application;

[0061] Fig.12 This is the second structural schematic diagram of the electronic device according to the embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0064] The relevant technologies of this application are described below.

[0065] The specific data copy process for the data copy scenario mainly includes:

[0066] 1. The central processing unit (CPU) in the phone's system-on-chip (SOC) sends a read command to the underlying universal flash storage (UFS) controller;

[0067] 2. The UFS controller reads data from data location 1;

[0068] 3. UFS returns data and saves it in low power double data rate (LPDDR) memory;

[0069] 4. Based on the data in memory, the CPU sends a write command to UFS location 1;

[0070] 5. The UFS controller receives the command and writes the data to location 2, completing the data copy from location 1 to location 2 (the NAND array is a data storage unit).

[0071] The data processing method, device, electronic device, medium and program product provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0072] like Figure 1 As shown, an embodiment of the present application provides a data processing method, which is applied to an electronic device, including:

[0073] Step 101, controlling the central processing unit CPU to send a data copy command to the universal flash storage UFS; the data copy command is used to indicate the source address and destination address of the data copy;

[0074] Step 102: Control the UFS to copy the data at the source address to the destination address in response to the data copy command.

[0075] It should be noted that the embodiment of the present application controls the CPU to send a copy command carrying the source address and the destination address to the UFS, so as to control the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This can reduce the signaling interaction process in the data copy process, save data copy time, improve data copy efficiency, and also reduce system power consumption.

[0076] Optionally, the CPU refers to a CPU located in a SOC.

[0077] Optionally, in one implementation, Figure 2 As shown, UFS200, including:

[0078] UFS controller 210, data storage unit 220;

[0079] The UFS controller 210 is used to receive the data copy command, and in response to the data copy command, read data from a source address of the data storage unit 220 , and write the read data to a target address of the data storage unit 220 .

[0080] It should be noted that, for CPU 100, it sends a data copy command to UFS 200; UFS 200 receives the data copy command, and in response to the data copy command, copies the data of the source address to the destination address; specifically, it is the UFS controller 210 that receives the data copy command, and the UFS controller 210 directly reads data from the corresponding position in the data storage unit 220 based on the received data copy command and copies the read data to a new position, thereby realizing that data is copied only within the UFS, avoiding the bit flipping problem that may be caused by reading data out to the outside, thereby improving the stability of the copied data.

[0081] Optionally, the plurality of data storage units 220 may be understood as a NAND array.

[0082] Optionally, in one implementation, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0083] It should be noted that the source address information mentioned in the embodiments of the present application can be understood as a source entry, each source entry includes a source address (usually corresponding to the starting address of the source address), or includes the source address and the amount of data corresponding to the source address (i.e., data size); the destination address information can be understood as a destination entry, which includes the destination address (usually corresponding to the starting address of the destination address), or includes the destination address and the amount of data corresponding to the destination address (i.e., data size).

[0084] Optionally, the source address and the destination address both refer to UFS addresses.

[0085] Optionally, the source address information and the destination address information may be implemented in the following ways:

[0086] Implementation situation 1: the number of the source address information is one, and the number of the destination address information is one.

[0087] Implementation situation 2: the number of the source address information is one, and the number of the destination address information is at least two.

[0088] Implementation situation three: the number of the source address information is at least two, and the number of the destination address information is one.

[0089] It should be noted that in this implementation, optionally, the source address information includes the source address and the data volume corresponding to the source address, the destination address information includes the destination address and the data volume corresponding to the destination address, and the sum of the data volumes corresponding to at least two of the source addresses is equal to the data volume corresponding to the destination address.

[0090] Implementation situation four: the number of the source address information is at least two, and the at least two source address information include the first source address information and the second source address information; the number of the destination address information is at least two, and the at least two destination address information include the first destination address information and the second destination address information; there is a copy relationship between the first source address information and the first destination address information; there is a copy relationship between the second source address information and the second destination address information.

[0091] Optionally, a copy relationship between the first source address information and the first destination address information can be understood as the data of the source address indicated in the first source address information is copied to the destination address indicated in the first destination address information; a copy relationship between the second source address information and the second destination address information can be understood as the data of the source address indicated in the second source address information is copied to the destination address indicated in the second destination address information.

[0092] Optionally, in this implementation, the source address information includes the source address and the data volume corresponding to the source address, the destination address information includes the destination address and the data volume corresponding to the destination address, the data volume corresponding to the first source address information is equal to the data volume between the first destination address information, and the data volume corresponding to the second source address information is equal to the data volume between the second destination address information.

[0093] Optionally, in an implementation manner, the number of the source address is at least one, and the number of the destination address is at least one; and the controlling the UFS to copy the data of the source address to the destination address in response to the data copy command includes:

[0094] Controlling the UFS to read data from each of the source addresses in response to the data copy command;

[0095] The UFS is controlled to copy the data read from each source address to the corresponding destination address.

[0096] For example, for implementation case two, UFS responds to the data copy command and reads data from the source address. The data read from the source address can be copied to each destination address, that is, each destination address corresponds to all the data read from the source address, or the data read from the source address can be copied in parts to all destination addresses, that is, each destination address corresponds to part of the data read from the source address.

[0097] Optionally, in one implementation, before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes:

[0098] Controlling the CPU to perform validity check on the data copy command;

[0099] The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including:

[0100] When the data copy command is valid, the CPU is controlled to send the data copy command to the UFS controller.

[0101] This situation can be understood as that before controlling the CPU to send a data copy command to the UFS, it is necessary to ensure that the copy command sent is accurate. Therefore, it is necessary to first perform a validity check on the information for constructing the data copy command. Only after the validity verification is passed can the CPU be controlled to send a data copy command to the UFS.

[0102] Optionally, in one implementation, the control CPU performs validity verification on the data copy command, including:

[0103] Control the CPU to perform validity check on at least one of the following items in the data copy command:

[0104] A11, whether the data volume corresponding to the source address is equal to the data volume corresponding to the destination address;

[0105] It should be noted here that if the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address, the validity verification passes, otherwise, the validity verification fails.

[0106] A12: Whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information;

[0107] It should be noted that since the system will pre-set the command format for each command, the command format will correspond to a specific total length (which can be understood as the bit length). In this case, it is to verify whether the information constituting the data copy command is equal to the total length corresponding to the pre-set command format. If they are equal, the validity verification passes, otherwise, the validity verification fails.

[0108] A13. Whether the source address and the destination address are valid. The validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of UFS.

[0109] Optionally, in one implementation, the method further includes:

[0110] Control the UFS to return the data copy result to the CPU;

[0111] In a case where the data copy result includes abnormal information, the CPU is controlled to execute an error processing operation corresponding to the abnormal information.

[0112] It should be noted that if UFS successfully completes the data copy, the data copy result fed back by UFS to the CPU indicates that the data copy is completed. If UFS does not successfully complete the data copy, the data copy result fed back by UFS to the CPU includes exception information. Optionally, the CPU side will store the error execution code corresponding to each exception information, and the CPU only needs to execute the corresponding error handling code according to the corresponding exception information.

[0113] For example, if the exception information is that the UFS is busy, the CPU can send a data copy command to the UFS again after receiving the exception information; for example, if the exception information is that the UFS fails to execute the copy command, the CPU will feedback a copy failure prompt to the user after receiving the exception information.

[0114] Taking the example that a user wants to copy the contents of file1 (UFS address 1, data length 1) and the contents of file2 (UFS address 2, data length 2) to file3 (UFS address 3) as an example, the specific implementation process of the embodiment of the present application is illustrated as follows.

[0115] like Figure 3 As shown in the figure, the specific implementation process includes:

[0116] Step 301: The CPU obtains the source address and destination address of the required data copy, and constructs the source entry and destination entry.

[0117] Among them, entry contains the starting UFS address and data volume, and its format is as follows Figure 4 Optionally, the source entry and the destination entry use the same format, and multiple entries are allowed for both.

[0118] Based on the user copy requirement of the example, a total of 1 destination entry and 2 source entries are required, where the destination entry contains information about UFS address 3, data length 1, and data length 2, source entry 1 includes information about UFS address 1 and data length 1, and source entry 2 includes information about UFS address 2 and data length 2.

[0119] Step 302, control the CPU to execute code to form data in command format (for being recognized by the UFS controller, Figure 5 is an example of the command format, which does not constitute a limitation on the command format), and performs a validity check on the copy command by sending a data copy command to the UFS.

[0120] The validity check of the copy command includes at least one of the following: whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address, whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information, and whether the source address and the destination address are valid (the validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of the UFS). After the check is passed, the CPU sends the data copy command to the UFS controller;

[0121] Optionally, based on the example user copy requirement, the CPU should transmit detailed information of the data copy command to the UFS controller such as Figure 6 As shown, there is 1 destination entry and 2 source entries, and the corresponding values ​​are assigned. The entry contents are from 1,…n (n≥1).

[0122] Step 303, control the UFS controller to receive the data copy command, and parse the information of the source entry and the destination entry. After the parsing is completed, control the UFS controller to read all the data from the source entry in the data storage unit inside the UFS, and then write it to each destination entry in turn. After completing the reading and writing, control the UFS controller to return the execution result to the CPU.

[0123] It should be noted that since there may be multiple entries, they need to be written in the order of the entries passed in. The order of reading and writing is as follows: Figure 7 shown.

[0124] Step 304: Control the UFS controller to return the data copy result to the CPU.

[0125] If the copy is completed successfully, the data copy result will indicate that the copy is completed; if the copy is not completed, the UFS controller will return exception information, the CPU will receive the exception information, and execute a pre-set error handling code. Different error handling can be performed for different error codes (for example, if the UFS returns busy, the CPU can resend the command after receiving it; if the UFS fails to execute the command, the CPU will inform the user of the copy failure after receiving it).

[0126] It should be noted that the data copy operation of the embodiment of the present application can reduce the path of the underlying UFS data flow in the copy scenario, and directly complete the data copy inside the UFS, thereby reducing the copy time and reducing power consumption, and improving the user experience; in addition, this data copy method makes it unnecessary to read the data from the UFS to the LPDDR, thereby avoiding the bit flipping problem that may exist in the LPDDR and improving the stability of the copied data; this data copy method will not destroy the source data position, so it will not cause damage to the user's source data; it should also be noted that the embodiment of the present application supports a single command to pass in multiple destination addresses and multiple source addresses to meet the complex copy scenarios where the written destination addresses are continuous and discontinuous.

[0127] Optionally, the above-mentioned data copy operation may also be introduced in an incremental upgrade scenario of an electronic device. Optionally, in this application scenario, the controlling the CPU to execute an error handling operation corresponding to the abnormal information includes:

[0128] The CPU is controlled to remap the partitions, and the upgrade progress is synchronized to the kernel, so that the kernel performs the upgrade process.

[0129] In this case, it can be understood that when the data copy method based on the embodiment of the present application fails to copy data normally, the CPU needs to remap the partition and then notify the kernel of the upgrade progress, and the kernel will perform the upgrade process.

[0130] Optionally, it should be noted that, in the incremental upgrade scenario, in the embodiment of the present application, before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes:

[0131] Control the CPU to sort operations and arrange all data copy operations included in the incremental upgrade process after non-data copy operations;

[0132] The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including:

[0133] After executing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0134] That is to say, in the incremental upgrade scenario, the non-data copy operation is performed first, and the data copy operation is performed after the non-data copy operation is completed, so as to prevent data confusion and ensure the accuracy of the incremental upgrade.

[0135] The following is an example of an incremental upgrade process of data copy using an embodiment of the present application.

[0136] like Figure 8 As shown in the figure, the specific implementation process includes:

[0137] Step 801, parse the incoming incremental upgrade package to obtain the source address and destination address and the corresponding amount of data to be written.

[0138] Optionally, the source address and destination address of the static partition are both from the upgrade package; the source address of the dynamic partition is from the upgrade package, and the destination address is provided by the global location variable maintained during the upgrade process, which is calculated from the virtual offset and the actual physical address mapping table of the destination device.

[0139] Step 802, execute all non-data copy operations in the upgrade.

[0140] This part requires that the data copy operation be placed last in the upgrade package. This is because when the kernel writes non-data copy operations, there is no order of precedence and it is likely to overwrite the data in the partition written in the data copy, thus causing data confusion. Therefore, the CPU needs to sort the operations first and place the data copy operations after the non-data copy operations, executing the non-data copy operations first and then the data copy operations uniformly.

[0141] Optionally, the upgrade operation can be performed normally for static partitions. For dynamic partitions, the location of the actual written destination address needs to be recorded in real time, and refreshed after writing to ensure that it is written to the disk. The subsequent data copy operation will continue to write data based on the above recorded location.

[0142] Step 803, executing the initialization operation in the data copy operation.

[0143] These initialization operations may include obtaining source partition and destination partition mapping tables and calculating start addresses, logical unit numbers of partitions corresponding to UFS, and the like.

[0144] Step 804: Select the destination entry.

[0145] The destination entry can include the starting UFS address and data size. Based on the factors of highest execution efficiency (minimum number of command issuances, maximum information carried by a single command), no lag in execution (command execution time), and input data copy operation data size, select the destination entry for single issuance.

[0146] Because the destination address of a dynamic partition during an upgrade is different from that of a static partition in that the entire physical address is continuous and does not require metadata to be recorded, the dynamic partition needs to consider the data format and physical address information of the destination address when selecting the destination entry for a single delivery.

[0147] Step 805: Select a matching source entry based on the destination entry.

[0148] For matching logic, static partitions and dynamic partitions are the same, and are matched in sequence according to the information in the upgrade package. For example, the destination entry and source entry are as follows:

[0149] 56: SOURCE_COPY

[0150] Source:4extent(800blocks)

[0151] (2832,500)(1618,100)(674,100)(874,100)

[0152] Destination:1extent(800blocks)

[0153] (2838,800)

[0154] In the example, for (A, B), A is the virtual address offset and B is the size of the data to be written. If the destination entry selected in step 804 is (2832, 512), based on the above example, the source entries are (2832, 500) and (1618, 12).

[0155] Step 806, the control CPU performs validity check on the data copy command formed, and after the check passes, the control CPU sends the data copy command to the UFS controller.

[0156] This part of the static partition is the same as the dynamic partition. The data sent to the UFS controller includes all the destination entry information, source entry information, total data length, etc.

[0157] It should be noted that the CPU allows multiple processes to send data copy operations simultaneously.

[0158] Step 807: After receiving the command sent by the system, the UFS controller parses the data and completes the data copy operation inside the device, and controls the UFS controller to return the data copy result to the CPU.

[0159] Step 808: The CPU receives the data copy result returned by the UFS and continues to perform operations required for the upgrade.

[0160] For example, writing metadata of the upgrade operation and executing the next upgrade operation.

[0161] Step 809: After all upgrade data copy operations are completed, the partitions are remapped to synchronize the progress of the new solution execution to the kernel.

[0162] Furthermore, the kernel will continue to perform verification and data merging. It should be noted that the kernel execution process is consistent with the prior art and will not be repeated here.

[0163] It should be noted that if UFS executes abnormally, the CPU will parse the exception information returned by UFS and follow the preset exception handling process, such as Fig. 9 As shown in the figure, the specific implementation process includes:

[0164] Step 901, data copy process;

[0165] The execution process of step 901 is similar to the above steps 805-807, and will not be described again;

[0166] Step 902, controlling the CPU to determine whether the data copy operation is executed abnormally;

[0167] If the execution is abnormal, execute step 903; if the execution is normal, return to step 901;

[0168] Step 903, control the CPU to remap all partitions and synchronize the upgrade progress to the kernel;

[0169] Step 904, the control kernel re-executes the current operation in a conventional manner and continues to execute based on the current upgrade.

[0170] It should be noted that this method can ensure that users will not directly cause upgrade failure due to failure of the copy command, and this solution will continue to perform the upgrade based on the previous progress, ensuring upgrade efficiency and users will not be aware of it.

[0171] It should be noted that the incremental upgrade solution of the embodiment of the present application can reduce the path of data copying in the underlying UFS data stream during the upgrade, directly complete the data copying within the UFS, allow the size of a single command to be issued to become larger, and remove the hash check. Based on the above three points, the user upgrade time can be reduced; at the same time, data does not need to be read from UFS to LPDDR, which can improve data copying efficiency, reduce user upgrade power consumption, and avoid possible bit flipping problems in LPDDR, thereby improving the stability of copied data.

[0172] It should be noted that the data processing method provided in the embodiment of the present application can be executed by a data processing device or a control module in the data processing device for executing the data processing method. In the embodiment of the present application, the data processing method provided in the embodiment of the present application is described by taking the data processing device executing the data processing method as an example.

[0173] like Fig.10 As shown, at least one embodiment of the present application further provides a data processing device 1000, which is applied to an electronic device, and the device includes:

[0174] The first control module 1001 is used to control the central processing unit CPU to send a data copy command to the universal flash storage UFS controller; the data copy command is used to indicate the source address and destination address of the data copy;

[0175] The second control module 1002 is used to control the UFS controller to copy the data at the source address to the destination address in response to the data copy command.

[0176] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0177] Optionally, the number of the source address information is one, and the number of the destination address information is one.

[0178] Optionally, the number of the source address information is one, and the number of the destination address information is at least two.

[0179] Optionally, the number of the source address information is at least two, and the number of the destination address information is one.

[0180] Optionally, the number of the source address information is at least two, and the at least two source address information include first source address information and second source address information;

[0181] The number of the destination address information is at least two, and the at least two destination address information include first destination address information and second destination address information;

[0182] There is a copy relationship between the first source address information and the first destination address information;

[0183] There is a copy relationship between the second source address information and the second destination address information.

[0184] Optionally, the source address information includes a source address and a data volume corresponding to the source address, the destination address information includes a destination address and a data volume corresponding to the destination address, and the sum of the data volumes corresponding to at least two of the source addresses is equal to the data volume corresponding to the destination address.

[0185] Optionally, the source address information includes the source address and the data volume corresponding to the source address, the destination address information includes the destination address and the data volume corresponding to the destination address, the data volume corresponding to the first source address information is equal to the data volume between the first destination address information, and the data volume corresponding to the second source address information is equal to the data volume between the second destination address information.

[0186] Optionally, the number of the source address is at least one, and the number of the destination address is at least one;

[0187] The second control module 1002 includes:

[0188] A first control unit, configured to control the UFS to read data from each of the source addresses in response to the data copy command;

[0189] The second control unit is used to control the UFS to copy the data read from each source address to the corresponding destination address.

[0190] Optionally, before the first control module 1001 controls the central processing unit CPU to send a data copy command to the universal flash storage UFS controller, the device further includes:

[0191] A third control module, used to control the CPU to perform validity check on the data copy command;

[0192] The first control module 1001 is used to:

[0193] When the data copy command is valid, the CPU is controlled to send the data copy command to the UFS controller.

[0194] Optionally, the third control module is used to:

[0195] Control the CPU to perform validity check on at least one of the following items in the data copy command:

[0196] Whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address;

[0197] whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information;

[0198] Whether the source address and the destination address are valid, the validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of UFS.

[0199] Optionally, the device further comprises:

[0200] A fourth control module, used for controlling the UFS to return a data copy result to the CPU;

[0201] The fifth control module is used to control the CPU to execute an error handling operation corresponding to the abnormal information when the data copy result includes abnormal information.

[0202] Optionally, in the scenario of incremental upgrade, the fifth control module is used to:

[0203] The CPU is controlled to remap the partitions, and the upgrade progress is synchronized to the kernel, so that the kernel performs the upgrade process.

[0204] Optionally, in the scenario of incremental upgrade, before the first control module 1001 controls the central processing unit CPU to send a data copy command to the universal flash storage UFS controller, the device further includes:

[0205] A sixth control module, used to control the CPU to perform operation sequencing, arranging all data copy operations included in the incremental upgrade process after non-data copy operations;

[0206] The first control module 1001 is used to:

[0207] After executing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0208] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is used to read data from a source address of the data storage unit and write the read data to a target address of the data storage unit in response to the data copy command.

[0209] It should be noted that the device embodiment corresponds to the above method, and all implementation methods in the above method embodiment are applicable to the device embodiment and can achieve the same technical effect.

[0210] The data processing device in the embodiment of the present application can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. The non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0211] The data processing device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0212] The data processing device provided in the embodiment of the present application can realize Figure 1 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0213] The device of the embodiment of the present application controls the CPU to send a copy command carrying the source address and the destination address to the UFS, and controls the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address, thereby reducing the signaling interaction process in the data copy process, saving data copy time, improving data copy efficiency, and also reducing system power consumption.

[0214] Optional, such as Fig.11 As shown, an embodiment of the present application also provides an electronic device 1100, including a processor 1101, a memory 1102, and a program or instruction stored in the memory 1102 and executable on the processor 1101. When the program or instruction is executed by the processor 1101, each process of the above-mentioned data processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0215] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0216] Fig.12 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0217] The electronic device 1200 includes but is not limited to: a radio frequency unit 1201, a network module 1202, an audio output unit 1203, an input unit 1204, a sensor 1205, a display unit 1206, a user input unit 1207, an interface unit 1208, a memory 1209, and a processor 1210 and other components.

[0218] Those skilled in the art will appreciate that the electronic device 1200 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1210 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.12 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0219] The processor 1210 is configured to:

[0220] Controlling the central processing unit CPU to send a data copy command to the universal flash storage UFS controller; the data copy command is used to indicate the source address and destination address of the data copy;

[0221] The UFS controller is controlled to copy the data at the source address to the destination address in response to the data copy command.

[0222] Optionally, the data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the amount of data corresponding to the source address; the destination address information includes the destination address, or the destination address and the amount of data corresponding to the destination address.

[0223] Optionally, the number of the source address information is one, and the number of the destination address information is one.

[0224] Optionally, the number of the source address information is one, and the number of the destination address information is at least two.

[0225] Optionally, the number of the source address information is at least two, and the number of the destination address information is one.

[0226] Optionally, the number of the source address information is at least two, and the at least two source address information include first source address information and second source address information;

[0227] The number of the destination address information is at least two, and the at least two destination address information include first destination address information and second destination address information;

[0228] There is a copy relationship between the first source address information and the first destination address information;

[0229] There is a copy relationship between the second source address information and the second destination address information.

[0230] Optionally, the source address information includes a source address and a data volume corresponding to the source address, the destination address information includes a destination address and a data volume corresponding to the destination address, and the sum of the data volumes corresponding to at least two of the source addresses is equal to the data volume corresponding to the destination address.

[0231] Optionally, the source address information includes the source address and the data volume corresponding to the source address, the destination address information includes the destination address and the data volume corresponding to the destination address, the data volume corresponding to the first source address information is equal to the data volume between the first destination address information, and the data volume corresponding to the second source address information is equal to the data volume between the second destination address information.

[0232] Optionally, the number of the source address is at least one, and the number of the destination address is at least one;

[0233] The processor 1210 is configured to:

[0234] Controlling the UFS to read data from each of the source addresses in response to the data copy command;

[0235] The UFS is controlled to copy the data read from each source address to the corresponding destination address.

[0236] Optionally, the processor 1210 is further configured to:

[0237] Controlling the CPU to perform validity check on the data copy command;

[0238] The processor 1210 is configured to:

[0239] When the data copy command is valid, the CPU is controlled to send the data copy command to the UFS controller.

[0240] Optionally, the processor 1210 is configured to:

[0241] Control the CPU to perform validity check on at least one of the following items in the data copy command:

[0242] Whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address;

[0243] whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information;

[0244] Whether the source address and the destination address are valid, the validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of UFS.

[0245] Optionally, the processor 1210 is further configured to:

[0246] Control the UFS to return the data copy result to the CPU;

[0247] In a case where the data copy result includes abnormal information, the CPU is controlled to execute an error processing operation corresponding to the abnormal information.

[0248] Optionally, in an incremental upgrade scenario, the processor 1210 is configured to:

[0249] The CPU is controlled to remap the partitions, and the upgrade progress is synchronized to the kernel, so that the kernel performs the upgrade process.

[0250] Optionally, in an incremental upgrade scenario, the processor 1210 is further configured to:

[0251] Control the CPU to sort operations and arrange all data copy operations included in the incremental upgrade process after non-data copy operations;

[0252] The processor 1210 is configured to:

[0253] After executing the non-data copy operation, the control CPU sends a data copy command to the UFS.

[0254] Optionally, the UFS includes a UFS controller and a data storage unit; wherein the UFS controller is used to read data from a source address of the data storage unit and write the read data to a target address of the data storage unit in response to the data copy command.

[0255] It should be noted that the embodiment of the present application controls the CPU to send a copy command carrying the source address and the destination address to the UFS, so as to control the UFS to directly obtain data from the indicated source address and copy it to the location indicated by the destination address. This can reduce the signaling interaction process in the data copy process, save data copy time, improve data copy efficiency, and also reduce system power consumption.

[0256] It should be understood that in the embodiment of the present application, the input unit 1204 may include a graphics processor (Graphics Processing Unit, GPU) 12041 and a microphone 12042, and the graphics processor 12041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1206 may include a display panel 12061, and the display panel 12061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1207 includes a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include two parts: a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, a physical keyboard, a function key (such as a volume control button, a switch button, etc.), a trackball, a mouse, and a joystick, which will not be repeated here. The memory 1209 can be used to store software programs and various data, including but not limited to applications and operating systems. The processor 1210 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor 1210.

[0257] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned data processing method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0258] The processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0259] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned data processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0260] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0261] The embodiments of the present application further provide a computer program / program product, which is stored in a storage medium and is executed by at least one processor to implement the various processes of the above-mentioned data processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0262] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0263] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0264] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A data processing method, characterized in that: include: Control the central processing unit CPU to send a data copy command to the universal flash storage UFS; The data copy command is used to indicate the source address and destination address of the data copy; The UFS is controlled to copy the data at the source address to the destination address in response to the data copy command.

2. The method according to claim 1, characterized in that: The data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the data volume corresponding to the source address; the destination address information includes the destination address, or the destination address and the data volume corresponding to the destination address.

3. The method according to claim 2, characterized in that The number of the source address information is one, and the number of the destination address information is one.

4. The method according to claim 2, characterized in that: The number of the source address information is one, and the number of the destination address information is at least two.

5. The method according to claim 2, characterized in that: The number of the source address information is at least two, and the number of the destination address information is one.

6. The method according to claim 2, characterized in that The number of the source address information is at least two, and the at least two source address information include first source address information and second source address information; The number of the destination address information is at least two, and the at least two destination address information include first destination address information and second destination address information; There is a copy relationship between the first source address information and the first destination address information; There is a copy relationship between the second source address information and the second destination address information.

7. The method according to claim 5, characterized in that The source address information includes a source address and a data volume corresponding to the source address, and the destination address information includes a destination address and a data volume corresponding to the destination address. The sum of the data volumes corresponding to at least two source addresses is equal to the data volume corresponding to the destination address.

8. The method according to claim 6, characterized in that The source address information includes the source address and the data volume corresponding to the source address, and the destination address information includes the destination address and the data volume corresponding to the destination address. The data volume corresponding to the first source address information is equal to the data volume between the first destination address information, and the data volume corresponding to the second source address information is equal to the data volume between the second destination address information.

9. The method according to claim 2, characterized in that: The number of the source address is at least one, and the number of the destination address is at least one; The controlling the UFS to copy the data at the source address to the destination address in response to the data copy command includes: Controlling the UFS to read data from each of the source addresses in response to the data copy command; The UFS is controlled to copy the data read from each source address to the corresponding destination address.

10. The method according to claim 2, characterized in that Before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes: Controlling the CPU to perform validity check on the data copy command; The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including: When the data copy command is valid, the CPU is controlled to send the data copy command to the UFS controller.

11. The method according to claim 10, characterized in that The control CPU performs validity verification on the data copy command, including: Control the CPU to perform validity check on at least one of the following items in the data copy command: Whether the amount of data corresponding to the source address is equal to the amount of data corresponding to the destination address; whether the total length of the command format corresponding to the data copy command is the same as the length of the command formed by the source address information and the destination address information; Whether the source address and the destination address are valid, the validity of the source address and the destination address includes at least one of the following: the address is not a negative number and does not exceed the maximum address range of UFS.

12. The method according to claim 1, characterized in that The method further comprises: Control the UFS to return the data copy result to the CPU; In a case where the data copy result includes abnormal information, the CPU is controlled to execute an error processing operation corresponding to the abnormal information.

13. The method according to claim 12, characterized in that In the incremental upgrade scenario, the controlling the CPU to perform an error handling operation corresponding to the exception information includes: The CPU is controlled to remap the partitions, and the upgrade progress is synchronized to the kernel, so that the kernel performs the upgrade process.

14. The method according to claim 1, characterized in that In the incremental upgrade scenario, before the control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, the method further includes: Control the CPU to sort operations and arrange all data copy operations included in the incremental upgrade process after non-data copy operations; The control central processing unit CPU sends a data copy command to the universal flash storage UFS controller, including: After executing the non-data copy operation, the control CPU sends a data copy command to the UFS.

15. The method according to claim 1, characterized in that The UFS includes a UFS controller and a data storage unit; wherein the UFS controller is used to read data from a source address of the data storage unit and write the read data to a target address of the data storage unit in response to the data copy command.

16. A data processing device, characterized in that: include: The first control module is used to control the central processing unit CPU to send a data copy command to the universal flash storage UFS controller; The data copy command is used to indicate the source address and destination address of the data copy; The second control module is used to control the UFS controller to copy the data at the source address to the destination address in response to the data copy command.

17. The device according to claim 16, characterized in that The data copy command includes source address information and destination address information; the source address information includes the source address, or the source address and the data volume corresponding to the source address; the destination address information includes the destination address, or the destination address and the data volume corresponding to the destination address.

18. An electronic device, characterized in that: It comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the data processing method as described in any one of claims 1 to 15.

19. A readable storage medium, characterized in that: The readable storage medium stores programs or instructions, and when the programs or instructions are executed by the processor, the steps of the data processing method according to any one of claims 1 to 15 are implemented.

20. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the data processing method according to any one of claims 1 to 15.

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