Heterogeneous virtualization platform virtual machine migration method and system

Abstract

The present application proposes a method and system for migrating virtual machines on a heterogeneous virtualization platform, wherein the method includes: intercepting a section from the binary code in the source architecture executable file to obtain partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine; translating and running the partial binary code for N heterogeneous chip systems of the heterogeneous virtualization platform to obtain N second running data of the partial binary code running on the N heterogeneous chip systems; based on the first running data and the N second running data, determining the target architecture base and the target translation process according to the architecture of the N heterogeneous chip systems; based on the target architecture base and the target translation process, translating the source architecture executable file through one or more of a static translator, a dynamic translation executor and an interpreter to obtain an executable file for running on the target architecture machine; thereby improving the virtual machine migration effect of the heterogeneous virtualization platform.

Description

Technical Field

[0001] The present application relates to the technical field of heterogeneous chip virtual machine migration, and in particular to a method and system for migrating virtual machines on a heterogeneous virtualization platform. Background Art

[0002] China Coal Technology and Engineering Mining Research Institute built a large number of digital systems during its digital transformation. In order to manage these systems as a whole, it built corresponding computer rooms and hardware equipment. On this basis, virtualization hyper-convergence technology was used to allocate corresponding virtual machine resources to these systems.

[0003] Previously, heterogeneous virtualization platforms primarily relied on the X86 and ARM architecture instruction sets. To support national policies on the creation of new information and innovation industries, domestic CPU chips such as Hygon, Kunpeng, Zhaoxin, Loongson, and Shenwei have been selected, encompassing instruction set architectures such as X86, ARM, LoognArch, MIPS, SW64, and RISC-V. Migrating virtual machines between different chip architectures within heterogeneous virtualization platforms is crucial for achieving optimal performance after migration. For example, automated migration technology from X86 to other domestic instruction set architectures is particularly important. Summary of the Invention

[0004] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0005] To this end, the first purpose of this application is to propose a method for migrating virtual machines on a heterogeneous virtualization platform, thereby improving the effect of virtual machine migration on a heterogeneous virtualization platform.

[0006] The second objective of this application is to provide a virtual machine migration system for a heterogeneous virtualization platform.

[0007] The third objective of this application is to provide an electronic device.

[0008] The fourth object of this application is to provide a computer-readable storage medium.

[0009] A fifth object of this application is to provide a computer program product.

[0010] To achieve the above objectives, the first embodiment of the present application proposes a method for migrating virtual machines on a heterogeneous virtualization platform, comprising:

[0011] intercepting a section of binary code from the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine;

[0012] For the N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the portion of binary code to obtain N second running data of the portion of binary code running on the N heterogeneous chip systems;

[0013] Based on the first operating data and the N second operating data, determining a target architecture base according to the architectures of the N heterogeneous chip systems and selecting a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by the static translator and a dynamic translation executor;

[0014] Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

[0015] To achieve the above objectives, the second embodiment of the present application proposes a heterogeneous virtualization platform virtual machine migration system, including:

[0016] The system includes an instruction selector, a static translator, a dynamic translation executor and an interpreter, wherein the instruction selector is configured to:

[0017] intercepting a section of binary code from the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine;

[0018] For the N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the portion of binary code to obtain N second running data of the portion of binary code running on the N heterogeneous chip systems;

[0019] Based on the first operating data and the N second operating data, determining a target architecture base according to the architectures of the N heterogeneous chip systems and selecting a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by the static translator and a dynamic translation executor;

[0020] Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

[0021] To achieve the above-mentioned purpose, the third aspect embodiment of the present application proposes an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method described in the first aspect.

[0022] To achieve the above-mentioned purpose, the fourth embodiment of the present application proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in the first aspect.

[0023] To achieve the above-mentioned purpose, the fifth embodiment of the present application proposes a computer program product, including a computer program, which implements the method described in the first aspect when executed by a processor.

[0024] The present application provides a method and system for migrating virtual machines on a heterogeneous virtualization platform. The method and system select a target architecture base and a target translation process based on the running data of a portion of the binary code of an intercepted source architecture executable file in each heterogeneous chip system. The source architecture executable file is translated based on the target architecture base and the target translation process. The method and system then determine whether the current target architecture base and the target translation process can obtain an ideal translation result based on the translation efficiency. If the translation result is not ideal, the target architecture base and the target translation process are adjusted and the translation is performed again to obtain the executable file of the target architecture system. This improves the effect of virtual machine migration on the heterogeneous virtualization platform.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in an embodiment of the present application;

[0028] Figure 2 A flowchart of a method for migrating virtual machines on a heterogeneous virtualization platform provided by another embodiment of the present application;

[0029] Figure 3 A flowchart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in another embodiment of the present application;

[0030] Figure 4A flowchart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in another embodiment of the present application;

[0031] Figure 5 A block diagram of a virtual machine migration system for a heterogeneous virtualization platform provided in an embodiment of the present application;

[0032] Figure 6 A block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0034] The following describes the heterogeneous virtualization platform virtual machine migration method, device and equipment of the embodiments of the present application with reference to the accompanying drawings.

[0035] Figure 1 A flow chart of a method for migrating virtual machines on a heterogeneous virtualization platform provided in an embodiment of the present application.

[0036] It should be noted that the executor of the heterogeneous virtualization platform virtual machine migration method in the embodiment of the present application is the heterogeneous virtualization platform virtual machine migration device in the embodiment of the present application. The heterogeneous virtualization platform virtual machine migration device can be configured in an electronic device so that the electronic device can perform the heterogeneous virtualization platform virtual machine migration function.

[0037] like Figure 1 As shown, the heterogeneous virtualization platform virtual machine migration method includes the following steps:

[0038] Step 101: intercept a section of binary code from a source architecture executable file to obtain a partial binary code; and obtain first running data of the partial binary code running on a source architecture machine;

[0039] In some embodiments, the first running data includes a first execution time of a portion of the binary code running on the source architecture machine.

[0040] Exemplarily, the source architecture executable file is an X86 executable file, a section of binary code is intercepted from the X86 binary code of the X86 executable file, and the section of binary code is run on an X86 machine to obtain first running data.

[0041] Step 102 : For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run a portion of the binary code to obtain N second running data of the portion of the binary code running on the N heterogeneous chip systems.

[0042] As an implementation method, for the N heterogeneous chip systems of the heterogeneous virtualization platform, part of the binary code is translated by a static translator to obtain N executable codes corresponding to the N heterogeneous chip systems respectively; the N executable codes are run on the N heterogeneous chip systems respectively to obtain N second running data of the part of the binary code running on the N heterogeneous chip systems.

[0043] In some embodiments, the second running data includes a second execution time, CPU resource occupancy, memory resource occupancy, and storage resource occupancy value of a portion of the binary code running on the nth heterogeneous chip system; wherein 1≤n≤N.

[0044] Exemplarily, the mining research institute includes N heterogeneous chip systems, such as LoognArch, MIPS, SW64, RISC-V, etc.

[0045] Step 103: Based on the first operating data and the N second operating data, determine the target architecture base according to the architecture of the N heterogeneous chip systems and select a target translation process from multiple translation processes; wherein the multiple translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor.

[0046] As a way to implement Figure 2 As shown, the method for determining the target architecture and the target translation process includes:

[0047] Step 201 : Obtain execution efficiency of a portion of binary code running on the nth heterogeneous chip system based on a first execution time and a second execution time of a portion of binary code running on the nth heterogeneous chip system.

[0048] Step 202 : Obtain resource values ​​of N heterogeneous chip systems based on the execution efficiency, CPU resource occupancy, memory resource occupancy, and storage resource occupancy of the partial binary code running on the nth heterogeneous chip system.

[0049] Step 203 : Based on the resource values ​​of the N heterogeneous chip systems and the architectures of the N heterogeneous chip systems, a target architecture system is determined and a target translation process is selected from a plurality of translation processes.

[0050] As an implementation method, the execution efficiency is obtained by the following formula:

[0051] 1-(t2-t1) / t1

[0052] Wherein, t1 is the first execution time, and t2 is the second execution time.

[0053] In some embodiments, the resource value of N heterogeneous chip systems is calculated using the following formula (1):

[0054]

[0055] Among them, Vn is the resource value of the nth heterogeneous chip system, λ1, λ2, and λ3 are all adjustment parameters, which are adjusted according to the actual situation and importance of the CPU, memory, and storage of the virtualization platform; En is the execution efficiency running on the nth heterogeneous chip system, Cn is the CPU resource occupancy running on the nth heterogeneous chip system, Mn is the memory resource occupancy running on the nth heterogeneous chip system, and Sn is the storage resource occupancy value running on the nth heterogeneous chip system.

[0056] In some embodiments, as Figure 3 As shown, based on the resource value of the nth heterogeneous chip system, a method for determining a target architecture base according to the architectures of N heterogeneous chip systems and selecting a target translation process from multiple translation processes includes:

[0057] Step 301: Based on the resource values ​​of N heterogeneous chip systems, determine a target heterogeneous chip system with the largest resource value.

[0058] Step 302: Determine the target architecture base based on the architecture of the target heterogeneous chip system.

[0059] Step 303: When the resource value of the target heterogeneous chip system is greater than the resource value upper limit threshold, a static translation process is selected as the target translation process.

[0060] Step 304 : When the resource value of the target heterogeneous chip system is less than or equal to the upper resource value threshold and greater than or equal to the lower resource value threshold, the dynamic translation process is selected as the target translation process.

[0061] It should be noted that the translation process also includes the interpreter translation process, and the interpreter translation process includes the interpreter direct running process.

[0062] For example, from V1...Vn, the heterogeneous chip system with Max(Vn) is prioritized for allocation. For example, if the Loongson architecture system has the highest V value, the x86 executable code is preferentially translated into Loongson binary code, using the Loongson binary as the target architecture binary. The upper resource value threshold is 1, and the lower resource value threshold is 0. When 0 < V of the target heterogeneous chip system <= 1, the dynamic translation process is selected; when V of the target heterogeneous chip system > 1, the static translation process is selected.

[0063] It should be noted here that when Vn is a negative number, it means that the heterogeneous chip system resources are exhausted and cannot be allocated.

[0064] Step 104, based on the target architecture binary and the target translation process, the source architecture executable file is translated through one or more of the static translator, dynamic translation executor and interpreter to obtain an executable file for running on the target architecture machine.

[0065] As a way to implement Figure 4 As shown, based on the target architecture binary and the target translation process, a method for translating a source architecture executable file through one or more of a static translator, a dynamic translation executor, and an interpreter to obtain an executable file for running on a target architecture machine includes:

[0066] Step 401: When the target translation process is a static translation process, a source architecture executable file is translated by a static translator to obtain a translated target executable file.

[0067] Step 402: When the target translation process is a dynamic translation process, the source architecture executable file is translated by a static translator and a dynamic translation executor in a static and dynamic combined manner to obtain a translated target executable file.

[0068] Step 403: Obtain the translation efficiency of the static translator.

[0069] Step 404, based on the translation efficiency and a preset threshold, determine a new target architecture base, a new target translation process, and whether to use the translated target executable file as one or more executable files for running on the target architecture machine.

[0070] As an implementation manner, a method for obtaining the translation efficiency of a static translator includes: obtaining the translation amount of the static translator as T, the total code amount as C, calculating T / C, and obtaining the translation efficiency.

[0071] In some embodiments, a method for translating a source architecture executable file in a static and dynamic combination manner using a static translator and a dynamic translation executor to obtain a translated target executable file includes: performing offline translation and deep optimization on the binary code in the source architecture executable file using a static translator to obtain a static translation result; and passing the static translation result to a dynamic translation executor; loading the binary code and the static translation result in the source architecture executable file through the dynamic translation executor; performing online translation and optimization on the untranslated part of the binary code in the source architecture executable file, and merging the online translation and optimization results into the static translation result to obtain a translated target executable file.

[0072] In some embodiments, the preset thresholds include a first efficiency threshold a1 and a second efficiency threshold a2. Based on the translation efficiency and the preset thresholds, a method for determining one or more of a new target architecture binary, a new target translation process, and whether to use the translated target executable file as an executable file for running on a target architecture machine includes:

[0073] When the translation efficiency is less than or equal to a first efficiency threshold, directly running the source architecture executable file through the interpreter to obtain an executable file for running on the target architecture machine;

[0074] When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a dynamic translation process, the source architecture executable file is re-translated by the static translator to obtain the translated target executable file and return to re-acquire the translation efficiency of the static translator;

[0075] When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a static translation process, returning to re-determine a new target architecture base and a target translation process from the N heterogeneous chip systems based on the first operation data and the second operation data;

[0076] When the translation efficiency is greater than the second efficiency threshold, the translated target executable file is used as an executable file for running on the target architecture machine.

[0077] It can be understood that when T / C < a1, it indicates that the currently selected target translation process has a very poor translation effect on the binary code of the source architecture. Most of the code translations fail, and the interpreter needs to be directly run to execute the binary code of the source architecture. When a1 < T / C <= a2, if the target translation process is a dynamic translation process, the binary code of the source architecture is re-translated directly through the static translator; if the target translation process is a static translation process, a higher system with a V value lower than the current target architecture system is returned to re-perform the target translation process. When T / C > a2, it indicates that the code obtained by the current target translation process is relatively ideal and can be migrated and used on the target machine.

[0078] The method for migrating virtual machines in a heterogeneous virtualization platform according to an embodiment of the present application selects the target architecture base and the target translation process according to the running data of a partial binary code of an executable file of the source architecture intercepted on different heterogeneous chip systems; based on the target architecture base and the target translation process, the executable file of the source architecture is translated; and then it is judged whether the current target architecture base and the target translation process can obtain an ideal translation result according to the translation efficiency. In the case where the translation result is not ideal, the target architecture base and the target translation process are adjusted to re-perform the translation to obtain an executable file of the target architecture system; thereby improving the effect of migrating virtual machines in the heterogeneous virtualization platform.

[0079] To clearly illustrate the above embodiments, specific examples are now used for illustration. Figure 5 It is a block diagram of a system for migrating virtual machines in a heterogeneous virtualization platform provided by an embodiment of the present application. As Figure 5 shown, the method for migrating virtual machines in the heterogeneous virtualization platform of the present application is applied to a system for migrating virtual machines in a heterogeneous virtualization platform. The system for migrating virtual machines in the heterogeneous virtualization platform includes an instruction selector 501, a static translator 502, a dynamic translation executor 503, and an interpreter 504. The instruction selector 501 is used for:

[0080] Intercept a segment from the binary code in the executable file of the source architecture to obtain partial binary code; and obtain the first running data of the partial binary code running on the source architecture machine;

[0081] For N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the partial binary code to obtain N second running data of the partial binary code running on the N heterogeneous chip systems;

[0082] Based on the first operating data and the N second operating data, determining a target architecture base according to the architectures of the N heterogeneous chip systems and selecting a target translation process from a plurality of translation processes; wherein the plurality of translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by the static translator 502, and the dynamic translation process includes a static and dynamic combined translation process implemented by the static translator 502 and the dynamic translation executor 503;

[0083] Based on the target architecture binary and the target translation process, the source architecture executable file is translated through one or more of the static translator 502, the dynamic translation executor 503 and the interpreter 504 to obtain an executable file for running on the target architecture machine.

[0084] The following description takes X86 source binary code as an example.

[0085] In order to combine the advantages of static translator 502 and dynamic translation executor 503 and avoid their shortcomings, a binary translation system combining dynamic and static is constructed. This binary translation system includes a static translator 502 and a dynamic translation executor 503. When working, the format of the target code of translation is first selected by instruction selector 501, and whether to translate through dynamic translation executor 503 or directly translate by static translator 502 is selected according to performance. Wherein, static translator 502 carries out off-line translation and depth optimization to X86 executable file, and then hands over the static translation result of translation to dynamic translation executor 503. Dynamic translation executor 503 loads X86 source file and static translation result together. If it is found that there is still X86 code that has not been translated during execution, dynamic translator is called to carry out online translation and optimization, and the result of online translation and optimization is merged into static translation result and utilized together.

[0086] Among them, the role of the static translator 502 is to translate and optimize the X86 source binary code, generate executable code on the target virtual machine, and store it in the form of a file. The static translator 502 can also choose to translate and optimize the X86 source binary code with the help of the dynamic translation information of the dynamic translation executor 503. The role of the static translator 502 is to translate the X86 binary before the program is executed and generate a static translation result. The static translation result includes the translated target binary code and some auxiliary information. The static translator 502 performs offline translation, and the time for offline translation does not take up runtime. The static translation result obtained by translation can be used multiple times by the dynamic translation executor 503; therefore, the static translator 502 can achieve some more powerful optimizations and generate more efficient target architecture code. However, the static translator 502 also has some limitations, such as the inability to recognize the targets of indirect jumps and indirect calls, and the inability to handle code self-modification programs, etc. These must be solved by the dynamic translation executor 503.

[0087] The main optimizations implemented by the static translator 502 include local register allocation (LRA), global register allocation (GRA) and extended basic block optimization (EBO), where local register allocation refers to the register allocation algorithm within a basic block; global register allocation refers to the register allocation algorithm across basic blocks; and extended basic block optimization refers to many compilation routine optimizations across basic blocks, such as constant propagation and dead code removal.

[0088] In order to solve the limitation of the static translator 502 that it cannot handle indirect jump targets, semantic enhancement can be used to successfully identify a class of indirect jump targets, which largely overcomes this limitation of the static translator 502 and improves the performance of system migration.

[0089] In some embodiments, the structure of the static translator 502 is as follows Figure 3 As shown, it includes a file loading unit, a translation unit, an optimization unit and a translation result output unit, wherein the file loading unit is used to load the X86 source binary code and the translation information generated by the dynamic translation executor 503 into the memory, and then the translation unit translates it. The intermediate result of the translation is handed over to the optimization unit for optimization (the translation unit will also perform certain optimization during the translation process). Finally, the translation result output unit outputs the output results of the translation unit and the optimization unit in a certain format to obtain a static translation result, which is passed to the dynamic translation executor 503 for use.

[0090] The dynamic translation executor 503 utilizes the static translation results of the static translator 502 to execute the target binary program through translation, native code execution, and interpretation. The program execution unit is a block, a linear set of X86 instruction codes that terminates when a jump instruction is encountered. Dynamic translation is performed during execution, and the dynamic translation information is recorded for use by the static translator 502. The dynamic part of the heterogeneous virtualization platform virtual machine migration system inputs the files generated by the static part and the X86 binary source code. The dynamic part interprets, translates, and executes the generated native code in units of source code blocks.

[0091] The function of the dynamic translation executor 503 is to fully utilize the translation results of the static translator 502 for the X86 source binary file, and assist in the interpretation and dynamic translation method to achieve the effect of correctly executing the X86 executable file on the target machine. The system structure of the dynamic translation executor 503 is shown in the figure

[0092] In some embodiments, the dynamic translation executor 503 includes a dynamic master control module, a file loading module, a command line parameter analysis module, a disassembly module, a native code execution environment module, an interpretation module, a translation module, and an optimization module. The dynamic master control module is responsible for coordinating the work of each module, the file loading module is responsible for loading the X86 executable file and the translation results of the static translator 502, the command line parameter analysis module is responsible for analyzing the command line parameters when the program is started and obtaining information about the translated program, the disassembly module is responsible for disassembling the X86 executable code and forming the basic unit of dynamic translation or interpretation, the native code execution environment module is responsible for constructing the context environment for native code execution, including register mapping, native code loading and execution, context switching, memory management, etc. The interpretation module is responsible for interpreting and executing the disassembled X86 executable code, the translation module is responsible for translating the disassembled X86 executable code, and the optimization module includes optimization measures taken to improve the performance of the binary translation system. The algorithms and implementations of the main modules are described in detail below.

[0093] The dynamic master control module is the master control module for dynamic execution, which controls the interpretation, translation and execution of the X86 Block and the native code. Starting from the X86 entry address, the module simulates the execution semantics of the X86 program. For basic blocks with native code, the native code is directly executed. For basic blocks without native code, the native code is first translated and then executed. This module ends when the simulated X86 program ends. The execution process of the dynamic execution master control module in the dynamic translation part of the binary translation system divides the master control module into four main sub-modules, namely the basic block division module, the interpreter 504 module, the dynamic translation module, and the native code execution module. The dynamic master control module includes the following implementation process:

[0094] 1) Assign the entry address to pc (pc is the program counter of the X86 code, which is also the virtual address of the X86 code, and the X86 address that this module will translate and execute). Construct information based on the contents of pc. (The contents of the information will be used during translation or interpretation).

[0095] 2) Determine whether native code already exists at the X86 address corresponding to the PC. If so, go to 7) to execute the native code.

[0096] 3) Build X86 Block (Block division).

[0097] 4) Determine whether the block with pc as its entry point needs to be interpreted or translated. If the block is interpreted, go to 5), otherwise go to 6) the local code translation submodule.

[0098] 5) The interpreter 504 simulates X86 instructions, updates the pc, and goes to 8).

[0099] 6) Translate the PC entry block and establish a link with the existing local code.

[0100] 7) The local code executes and returns some build information after execution, including updating the PC.

[0101] 8) Determine whether the X86 program has ended. If so, this module ends. Otherwise, record the indirect target address; go to 2).

[0102] The disassembly module is responsible for dividing blocks and disassembling them, recording the information in IR1. The instructions that end a block include: branch, jmp^indirect jump, indirect call, ret, and halt. The disassembly module implements the following process:

[0103] 1) Assign block->entry_vaddr to pc.

[0104] 2) Disassemble the instruction pointed to by pc.

[0105] 3) Fetch the next instruction.

[0106] 4) Determine whether the instruction type is a Block end instruction; otherwise, go to 2).

[0107] 5) Store the disassembled IR1 of the block into the irl cache of the block.

[0108] 6) Set the irl num of the block to the IR1 number, irl addr to the irl cache address, and mark the flag of the block as disassembled.

[0109] The disassembly module is mainly used to disassemble a given dynamic translation unit. It takes the entry point of the translation unit as a parameter, disassembles the translation unit, stores the disassembly result in IR1, and records the block information.

[0110] The instructions of the X86 file executed by the dynamic translation executor 503 are divided into basic blocks. The disassembly module needs to disassemble each instruction in the basic block one by one, and record the disassembly results in the intermediate representation of the X86 instruction until the last control transfer instruction of the basic block is identified. The execution process of the dynamic disassembly is completed.

[0111] The interpretation module consists of two parts. One is the execution part, which is executed after the disassembly module completes its operations and represents the X86 binary code as the IR1 intermediate representation. This module simulates the execution of X86 instructions one by one. The other is the initialization part, which initializes the virtual execution environment before interpreting the instructions. The execution part consists of a master control function and a series of instruction interpretation functions. The master control function is a general scheduler that interprets each instruction in a loop. The interpretation of a specific instruction calls each specific instruction interpretation function (almost all X86 instructions correspond to an instruction interpretation function). The interpretation of each instruction usually involves pre-analyzing the meaning of the instruction, then interpreting it with instructions of the same semantics and executing them simultaneously. The initialization part simply completes the initialization of the virtual execution environment.

[0112] The translation module has two submodules: the flag analysis module and the instruction translation module. The flag analysis module operates before instruction translation and significantly improves the efficiency of the translated IR2 instruction sequence. It translates the X86 source program generated by the disassembly module, generating an IR2 instruction sequence with the same semantics. Simultaneously, modules closely related to translation, such as dynamic register allocation and flag calculation, operate simultaneously. The module's most basic unit is a series of instruction translation functions, each corresponding to an X86 instruction with the same operational semantics. The module begins with the main entry point function, Translate(), and proceeds through steps such as conditional translation flags and the loading of related functions based on compilation options. Finally, it indirectly calls these X86 instruction translation functions to implement the source program's semantics. During the dynamic translation process, key related modules, such as flagpattern, flag calculation, and dynamic register allocation, operate simultaneously. The flag pattern module and flag calculation module effectively improve the efficiency of the translated IR2 instructions.

[0113] The native code execution environment module is responsible for constructing the context for native code execution. When the BT controller detects that a block has already been translated, it calls this module to initiate execution of that block. Both transitioning from the BT controller to native code execution and vice versa requires a context switch. Because native code chaining is used in translation, multiple blocks may be executed at once.

[0114] In order to implement the above embodiment, the present application also proposes an electronic device. Figure 6 , Figure 6 is a block diagram of an electronic device provided in an embodiment of the present application. Figure 6 As shown, the electronic device 600 includes: a processor 601, and a memory 602 communicatively connected to the processor 601; the memory 602 stores computer-executable instructions; the processor 601 executes the computer-executable instructions stored in the memory to implement the method provided in the aforementioned embodiment.

[0115] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the methods provided by the above embodiments.

[0116] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which implements the methods provided by the above embodiments when executed by a processor.

[0117] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this application are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0118] It is important to note that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold beyond these legitimate uses. Furthermore, such collection / sharing should be conducted only after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes the relevant user information before using the feature. Furthermore, any necessary steps must be taken to safeguard and secure access to such personal information and ensure that others with access to personal information comply with its privacy policy and procedures.

[0119] This application contemplates providing implementations that allow users to selectively block the use or access of personal information data. Specifically, this disclosure contemplates providing hardware and / or software to prevent or block access to such personal information data. Risks can be minimized by limiting data collection and deleting data once it is no longer needed. Furthermore, where applicable, such personal information can be de-identified to protect user privacy.

[0120] In the descriptions of the foregoing embodiments, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are mutually inconsistent.

[0121] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0122] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0123] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0124] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0125] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0126] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0127] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A method for migrating virtual machines on a heterogeneous virtualization platform, characterized in that: The method comprises the following steps: intercepting a section of binary code from the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine; For the N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the portion of binary code to obtain N second running data of the portion of binary code running on the N heterogeneous chip systems; Based on the first operating data and the N second operating data, the target architecture base is determined according to the architecture of the N heterogeneous chip systems and a target translation process is selected from multiple translation processes; wherein, the multiple translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor; the first operating data includes a first execution time of the part of the binary code running on the source architecture machine, and the second operating data includes a second execution time, CPU resource occupancy, memory resource occupancy and storage resource occupancy value of the part of the binary code running on the nth heterogeneous chip system; wherein, 1≤n≤N; the Based on the first operating data and the N second operating data, a target architecture base is determined according to the architecture of the N heterogeneous chip systems, and a target translation process is selected from a plurality of translation processes; including: based on the first execution time and the second execution time of the partial binary code running on the nth heterogeneous chip system, an execution efficiency of the partial binary code running on the nth heterogeneous chip system is obtained; based on the execution efficiency, CPU resource occupancy, memory resource occupancy and storage resource occupancy value of the partial binary code running on the nth heterogeneous chip system, a resource value of the N heterogeneous chip systems is obtained; based on the resource value of the N heterogeneous chip systems, a target architecture base is determined according to the architecture of the N heterogeneous chip systems, and a target translation process is selected from a plurality of translation processes; Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

2. The method according to claim 1, characterized in that The method of determining a target architecture base based on the resource value of the nth heterogeneous chip system and selecting a target translation process from a plurality of translation processes according to the architectures of the N heterogeneous chip systems comprises: Determine, based on the resource values ​​of the N heterogeneous chip systems, a target heterogeneous chip system with a maximum resource value; Determining a target architecture base according to the architecture of the target heterogeneous chip system; When the resource value of the target heterogeneous chip system is greater than the resource value upper limit threshold, selecting the static translation process as the target translation process; When the resource value of the target heterogeneous chip system is less than or equal to the upper threshold value of the resource value and greater than or equal to the lower threshold value of the resource value, the dynamic translation process is selected as the target translation process.

3. The method according to claim 1, characterized in that The method of obtaining resource values ​​of the N heterogeneous chip systems based on the execution efficiency, CPU resource occupancy, memory resource occupancy, and storage resource occupancy of the partial binary code running on the nth heterogeneous chip system includes obtaining resource values ​​of the N heterogeneous chip systems based on the execution efficiency, the CPU resource occupancy, the memory resource occupancy, and the storage resource occupancy using a first formula, wherein the first formula is expressed as follows: Among them, Vn is the resource value of the nth heterogeneous chip system, λ1, λ2, and λ3 are all adjustment parameters, which are adjusted according to the actual situation and importance of the CPU, memory, and storage of the virtualization platform; En is the execution efficiency running on the nth heterogeneous chip system, Cn is the CPU resource occupancy running on the nth heterogeneous chip system, Mn is the memory resource occupancy running on the nth heterogeneous chip system, and Sn is the storage resource occupancy value running on the nth heterogeneous chip system.

4. The method according to claim 1, wherein The translation process further includes an interpreter translation process, and the interpreter translation process includes a direct interpreter running process; based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine; including: When the target translation process is a static translation process, translating the source architecture executable file by the static translator to obtain a translated target executable file; When the target translation process is a dynamic translation process, the source architecture executable file is translated by the static translator and the dynamic translation executor in a dynamic and static combination manner to obtain a translated target executable file; Obtaining translation efficiency of the static translator; Based on the translation efficiency and a preset threshold, determine the new target architecture binary, the new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine.

5. The method according to claim 4, characterized in that The preset thresholds include a first efficiency threshold and a second efficiency threshold, and determining, based on the translation efficiency and the preset thresholds, a new target architecture binary, a new target translation process, and whether to use the translated target executable file as one or more of the executable files for running on the target architecture machine; including: When the translation efficiency is less than or equal to a first efficiency threshold, directly running the source architecture executable file through the interpreter to obtain an executable file for running on a target architecture machine; When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a dynamic translation process, the source architecture executable file is retranslated by the static translator to obtain a translated target executable file and the translation efficiency of the static translator is returned to be reacquired; When the translation efficiency is greater than the first efficiency threshold and less than the second efficiency threshold, and the target translation process is a static translation process, returning to re-determine a new target architecture base and a target translation process from the N heterogeneous chip systems based on the first operation data and the second operation data; When the translation efficiency is greater than the second efficiency threshold, the translated target executable file is used as the executable file for running on the target architecture machine.

6. The method according to claim 1, characterized in that The method of translating and running the portion of binary code on the N heterogeneous chip systems of the heterogeneous virtualization platform to obtain N second running data of the portion of binary code running on the N heterogeneous chip systems includes: For the N heterogeneous chip systems of the heterogeneous virtualization platform, translating the portion of binary code by the static translator to obtain N executable codes corresponding to the N heterogeneous chip systems respectively; The N executable codes are respectively run on the N heterogeneous chip systems to obtain N second running data of the partial binary code running on the N heterogeneous chip systems.

7. The method according to claim 4, characterized in that The method of translating the source architecture executable file by the static translator and the dynamic translation executor in a static and dynamic combination manner to obtain a translated target executable file comprises: Performing offline translation and deep optimization on the binary code in the source architecture executable file by the static translator to obtain a static translation result; and transmitting the static translation result to the dynamic translation executor; The binary code in the source architecture executable file and the static translation result are loaded through the dynamic translation executor; the untranslated part of the binary code in the source architecture executable file is translated and optimized online, and the results of the online translation and optimization are merged into the static translation result to obtain the translated target executable file.

8. A virtual machine migration system for a heterogeneous virtualization platform, characterized in that: The system includes an instruction selector, a static translator, a dynamic translation executor and an interpreter, wherein the instruction selector is configured to: intercepting a section of binary code from the source architecture executable file to obtain a partial binary code; and obtaining first running data of the partial binary code running on the source architecture machine; For the N heterogeneous chip systems of the heterogeneous virtualization platform, translate and run the portion of binary code to obtain N second running data of the portion of binary code running on the N heterogeneous chip systems; Based on the first operating data and the N second operating data, the target architecture base is determined according to the architecture of the N heterogeneous chip systems and a target translation process is selected from multiple translation processes; wherein, the multiple translation processes include a static translation process and a dynamic translation process, the static translation process includes a static translation process implemented by a static translator, and the dynamic translation process includes a static and dynamic combined translation process implemented by a static translator and a dynamic translation executor; the first operating data includes a first execution time of the part of the binary code running on the source architecture machine, and the second operating data includes a second execution time, CPU resource occupancy, memory resource occupancy and storage resource occupancy value of the part of the binary code running on the nth heterogeneous chip system; wherein, 1≤n≤N; the Based on the first operating data and the N second operating data, a target architecture base is determined according to the architecture of the N heterogeneous chip systems, and a target translation process is selected from a plurality of translation processes; including: based on the first execution time and the second execution time of the partial binary code running on the nth heterogeneous chip system, an execution efficiency of the partial binary code running on the nth heterogeneous chip system is obtained; based on the execution efficiency, CPU resource occupancy, memory resource occupancy and storage resource occupancy value of the partial binary code running on the nth heterogeneous chip system, a resource value of the N heterogeneous chip systems is obtained; based on the resource value of the N heterogeneous chip systems, a target architecture base is determined according to the architecture of the N heterogeneous chip systems, and a target translation process is selected from a plurality of translation processes; Based on the target architecture binary and the target translation process, the source architecture executable file is translated by one or more of the static translator, the dynamic translation executor and the interpreter to obtain an executable file for running on the target architecture machine.

9. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 7 when executed by a processor.

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