Data center multi-level de-aggregation memory system

Abstract

This invention proposes a multi-tiered de-aggregation memory system for data centers. The system includes: a host side comprising a CPU, local memory connected to the CPU, and an operating system connected to the CPU; a Data Processing Unit (DPU) connected to the host side, the DPU unit comprising a DPU control module and a DPU memory module connected to the DPU control module; and a remote memory pool connected to the DPU unit. The DPU control module controls the memory interaction between the DPU unit and the host side, and between the DPU unit and the remote memory pool. This system enables data interaction between the host side and the DPU, and between the DPU and the remote memory pool, allowing the host side to obtain expanded memory while maintaining lower memory access latency.

Description

Technical Field

[0001] This invention relates to the field of data centers, and more particularly to a multi-level de-aggregation memory system for data centers. Background Technology

[0002] The increasing popularity of tasks such as deep learning, graph computing, and key-value storage has led to a surge in memory demands in data centers. However, in many cases, data center memory resources suffer from low utilization and insufficient dynamism. Studies show that only about 50% of memory in a data center is actively used, while approximately 30% of total memory is allocated but unused. Furthermore, in current server architectures, the CPU-to-physical-memory ratio is fixed, making it difficult to dynamically expand the memory capacity of a single server to the required size. When the application's working set exceeds the main memory capacity, performance can suffer a significant decline. Therefore, reducing memory waste and providing additional extended memory for memory-intensive applications is a key factor in improving data center efficiency and reducing costs. Disaggregated memory systems can decouple CPU and memory resources, forming a memory pool that can be shared by multiple hosts. Hosts can request memory from the memory pool on demand, thereby reducing memory waste and dynamically providing extended memory to hosts. Therefore, building a disaggregated memory system can effectively solve the memory problem in data centers.

[0003] Currently, methods for constructing de-aggregation memory systems can be mainly divided into two categories. The first type prioritizes the use of local memory, using extended memory as the next level of storage after local memory, and only using extended memory when local memory is nearly exhausted, such as the TPP method. The second type treats local memory and extended memory as two independent spaces, with their use not affecting each other, and usually uses extended memory directly, such as Kona. The physical location of the extended memory provided by TPP is still local, and its efficiency is limited by the memory capacity of the extended memory nodes. However, the memory capacity that can be provided locally is often limited, and TPP faces the problem of poor scalability. In addition, extended memory nodes can only be accessed by the host connected to them and cannot be provided to other host nodes, which leads to the waste of memory resources. For example, due to different tasks being run by the hosts, some hosts may exhaust their extended memory, while others may still have free extended memory. The former cannot access the latter's extended memory, resulting in waste, because they cannot share extended memory nodes. Kona cannot use local memory when using extended memory, and the latency of accessing extended memory is greater than that of local memory, so Kona's overall memory access latency is relatively high. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a multi-level de-aggregation memory system for data centers, comprising:

[0005] On the host side, it includes: CPU, local memory connected to the CPU, and operating system connected to the CPU;

[0006] The DPU unit is connected to the host side, and the DPU unit includes: a DPU control module and a DPU memory module connected to the DPU control module;

[0007] A remote memory pool is connected to the DPU unit;

[0008] The DPU control module controls the memory interaction between the DPU unit and the host side, and between the DPU unit and the remote memory pool.

[0009] In one embodiment of the present invention, the memory capacity configured in the DPU unit includes the actual capacity of the DPU memory module and the capacity of the remote memory pool, wherein the portion of the actual capacity of the DPU memory module corresponds to the real physical address range; and the portion of the capacity of the remote memory pool corresponds to the virtual physical address range.

[0010] The host-side CPU accesses the DPU memory module via a virtual physical address;

[0011] The DPU control module receives memory access requests using VPA from the host-side CPU and translates the virtual physical address into a real physical address;

[0012] The DPU control module accesses the DPU memory module or the remote memory pool based on the actual physical address obtained from the translation.

[0013] In one embodiment of the present invention, the DPU unit is configured with a page table that records the mapping relationship between virtual physical addresses and real physical addresses. Each entry in the page table includes at least a virtual physical address number, a real physical address number, and a flag bit.

[0014] The flag bits include at least a present bit and a valid bit, wherein the present bit is used to indicate that the page exists in the DPU memory module or in the remote memory pool, and the valid bit is used to indicate whether the page table entry is valid.

[0015] In one embodiment of the present invention, a fast table is used to cache recently used page table entries;

[0016] The DPU control module first accesses the TLB to translate the virtual physical address into a real physical address. When the TLB is not hit, it accesses the page table and updates the TLB.

[0017] In one embodiment of the present invention, the local memory is configured with a bitmap, which is used to record the allocation status of the DPU memory module. Each bit of the bitmap is an idle state flag bit, corresponding to a page in the virtual physical address space. The idle state flag bit is used to identify the idle state of the corresponding page.

[0018] If a page migration request is received from the host side, the bitmap is queried, and a free page is found based on the free status flag. The page requested to be migrated from the host side local memory is allocated to the free page, wherein the page migration request is a request to migrate the page from the host side to the DPU memory module.

[0019] In one embodiment of the present invention, when querying the bitmap, the search starts from the page after the last free page that was allocated memory, and continues until a free page is found, at which point the page requested to be migrated from the host side is allocated to that free page.

[0020] In one embodiment of the present invention, when the page migration request is received from the host side, if the DPU memory module is found to be insufficient, the DPU control module selects the pages in the DPU memory module that need to be replaced to the remote memory pool, transmits the pages to the remote memory pool for storage through the network interface, and migrates the pages requesting migration from the host side to the DPU memory module.

[0021] In one embodiment of the present invention, the DPU unit is further configured with a local access count table to record the number of times the host-side CPU accesses each page of the DPU memory module;

[0022] The DPU control module records the number of times each page is accessed. If the number of times a page is accessed reaches a first threshold, it is identified as the first hot page.

[0023] The operating system on the host side accesses the local access count table at regular intervals via the CPU. When the operating system identifies a first hot page, it migrates the first hot page from the DPU memory module to the local memory on the host side for storage.

[0024] In one embodiment of the present invention, the DPU unit is further configured with a remote access count table to record the number of times the DPU unit accesses each page of the remote memory pool.

[0025] When the DPU control module detects that the number of times a page is accessed reaches a second threshold, it identifies it as a second hot page and migrates the second hot page from the remote memory pool to the DPU memory module for storage.

[0026] In one embodiment of the present invention, the DPU unit is further configured with a cache coherence interface, and the host side and the DPU unit are connected through the cache coherence interface.

[0027] As can be seen from the above solutions, the advantages of the present invention are:

[0028] This invention discloses a multi-layered de-aggregation memory system for data centers, which, in conjunction with a data interaction method between the host and the DPU unit, and between the DPU unit and the remote memory pool, enables the expansion of memory from local memory to DPU memory and then to remote memory. This allows the host to obtain expanded memory while maintaining lower memory access latency. The method enables the migration of memory pages in both directions—from host local memory to DPU memory and from DPU memory to host memory—reducing the impact of migrating pages to DPU memory on memory access latency. Furthermore, the method also enables the migration of memory pages in both directions—from DPU memory to remote memory and from remote memory to DPU memory—reducing the impact of migrating pages to remote memory on memory access latency. Attached Figure Description

[0029] Figure 1 is a structural diagram of a multi-level de-aggregation memory system for a data center disclosed in an embodiment of the present invention;

[0030] Figure 2 shows the data structure diagram of the page table;

[0031] Figure 3 shows the data structure diagram of the bitmap;

[0032] Figure 4 shows the data structure of the local access count table.

[0033] Figure label:

[0034] 10: Multi-level de-aggregation memory system for data centers;

[0035] 11: Host side;

[0036] 12: DPU unit;

[0037] 13: Remote memory pool;

[0038] 111: CPU;

[0039] 112: Local memory;

[0040] 113: Operating system;

[0041] 121: DPU control module;

[0042] 122: DPU memory module;

[0043] 123: Network interface;

[0044] 124: Cache consistency interface;

[0045] 125: Memory controller. Detailed Implementation

[0046] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0047] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] Please refer to Figure 1, which shows a structural diagram of a multi-level deaggregation memory system for a data center disclosed in an embodiment of the present invention.

[0049] The multi-layered de-aggregation memory system 10 for the data center specifically comprises three parts: a host side 11, a DPU (Data Processing Unit) unit 12, and a remote memory pool 13. The host side 11 is interconnected with the DPU unit 12, and the DPU unit 12 is interconnected with the remote memory pool 13. The host side 11 specifically includes a CPU 111, local memory 112, and an operating system 113. The local memory 112 is connected to the CPU (Central Processing Unit) 111, and the CPU 111 is connected to the operating system. In one embodiment, the host side is a server, and the data center application runs on the operating system and accesses local memory during runtime.

[0050] The DPU unit 12 includes a DPU control module 121, a DPU memory module 122, a network interface 123, a cache coherency interface 124, and a memory controller 125. The memory controller 125, network interface 123, and cache coherency interface 124 are all connected to the DPU control module 121, and the DPU memory module 122 is connected to the memory controller 125. In one embodiment, the DPU memory module 122 uses off-chip DRAM (Dynamic Random Access Memory). The remote memory pool 13 consists of a large number of memory units and can be accessed by multiple host-side platforms. The DPU control module 121 controls the memory interaction between the DPU unit 12 and the host-side platform 11, and between the DPU unit 12 and the remote memory pool 13. In one embodiment, local memory is used preferentially; when local memory is insufficient, pages are migrated to the DPU memory module; and when the DPU memory module is insufficient, pages are then migrated to the remote memory pool.

[0051] In one embodiment, the DPU unit 12 is connected to the host side 11 via the cache coherence interface 124, allowing the host-side CPU 111 to access the DPU memory module 122 via load / store instructions, just as if accessing the host-side local memory 112. The DPU control module 121 receives memory access requests sent from the host-side CPU via the cache coherence interface 124, and then accesses the DPU memory module via the DPU unit's memory controller 125. Simultaneously, the DPU control module 121 also returns the memory access result to the host-side CPU 111 via the cache coherence interface 124.

[0052] In one embodiment, the DPU unit 12 interconnects with the remote memory pool 13 via a network interface 123.

[0053] During the startup phase, the host-side CPU 111 identifies the memory capacity configured in the DPU unit 12 and allocates a physical address range for it, a process similar to the allocation of physical address ranges for local memory. In one embodiment, by modifying the relevant registers of the DPU unit 12 (through which the CPU 111 learns the memory capacity configured in the DPU unit 12), the actual physical memory capacity exposed by the DPU unit 12 to the host-side CPU 111 (i.e., the memory capacity configured in the DPU unit 12) is greater than the capacity of the DPU memory module 122 actually mounted on the DPU unit 12. For example, if the actual memory capacity mounted on the DPU memory module 122 is 4GB, by modifying the registers exposed by the DPU unit 12 to the host-side CPU 111, the memory capacity exposed by the DPU unit 12 to the host-side CPU 111 is changed to 8GB, allowing the host-side CPU 111 to use physical memory greater than the actual memory capacity of the DPU memory module 122, thus solving the problem of limited expandable memory capacity. Specifically, the memory capacity configured in the DPU unit 12 includes both the actual capacity of the DPU memory module 111 and the capacity of the remote memory pool 13. By combining the storage of the DPU unit 12 with the storage of the remote memory pool 13, the portion of physical memory exceeding the actual memory capacity of the DPU memory module 122 is transferred to the remote memory pool 13. The modified, larger physical address range is called the Virtual Physical Address (VPA), while the physical address range of the physical memory of the actual memory capacity of the DPU memory module is called the True Physical Address (TPA). The host-side CPU 111 accesses the DPU memory module 122 through the VPA, and the DPU control module 121 accesses the actual memory through the TPA. Since the memory access requests received by the DPU control module 121 from the host-side CPU 111 use VPA, the DPU control module 121 needs to perform address translation from VPA to TPA. Only after the DPU control module 121 obtains the corresponding TPA can it access the DPU memory. The address translation process is similar to the address translation process performed by the host-side CPU 111 when accessing local memory, namely, maintaining a page table that records the mapping relationship between the two. Each entry in the page table consists of a VPA number, a TPA number, and flag bits, as shown in Figure 2. Since 4KB page management is used, the page number is obtained by removing the lower 12 bits from the address.The flags include at least a present bit indicating whether the page is in the DPU memory module and a valid bit indicating whether the page table entry is valid. In one embodiment, a present bit of 1 indicates that the page is in DPU memory, and a present bit of 0 indicates that the page is currently in a remote memory pool. A valid bit of 1 indicates that the page table entry is valid, otherwise it is invalid. The complete page table is stored in a designated location in the DPU memory module. To speed up the lookup, a Translation Look-aside Buffer (TLB) is used to cache some recently used page table entries. The DPU control module 121 first accesses the TLB to convert the VPA to a TPA. If the page table is not found in the TLB, the complete page table is then accessed and the TLB is updated.

[0054] In one embodiment, when the local memory 112 on the host side is scarce, the operating system 113 initiates memory reclamation. Unlike the traditional practice of migrating reclaimed pages to the switching device, in this embodiment, the reclaimed pages are migrated to the DPU memory module 122 for storage. The memory migration operation can be implemented using the memory migration function built into the operating system kernel. Therefore, the migration process is much faster than migrating to the switching device, and thanks to the cache coherence interface, subsequent access to the pages migrated to the DPU memory module 122 by the host-side CPU 111 will not trigger a page fault interrupt. When migrating a page from local memory 112 to the DPU memory module 122, space needs to be allocated in the DPU memory module 122 for the page to be migrated out. Therefore, in one embodiment, the operating system kernel also maintains a data structure for recording the DPU memory allocation status. This data structure is a bitmap stored in local memory 112. As shown in Figure 3, each bit corresponds to a page in the VPA address space and is a page idle status flag. The idle status of the page can be identified through the page idle status flag. For example, if the corresponding idle status flag is 1, it means that the page has been allocated; if the corresponding idle status flag is 0, it means that the page is idle and can be allocated to a page to be migrated.

[0055] When the DPU unit 12 receives a page migration request from the host side, it queries the bitmap, searches for a free page based on the free status flag, and allocates the page requested for migration from the host side to that free page. In one embodiment, the next-fit algorithm is used when allocating memory, that is, the search starts from the page after the last free page allocated memory, until a free page is found for allocation. After the page is allocated, the corresponding VPA address can be obtained directly. For example, if the base address of the VPA is BASE_ADDR, and the allocated page is at bit N of the bitmap, then the corresponding page address is BASE_ADDR + N * 0x1000. After obtaining the VPA address, the page migration function can transfer the page to be migrated to the DPU memory module and modify the original mapping relationship of the page. Then, the host-side CPU 111 can access the page in the DPU memory module 122 through the normal address translation process. Subsequently, if these pages that have been migrated to the DPU memory module 122 are released by the application, the corresponding bit in the bitmap needs to be changed to 0 to participate in the subsequent allocation process. At the same time, the page table of the DPU unit needs to be modified so that the valid bit of the page table entry corresponding to the page is 0, indicating that the page table entry is invalid.

[0056] In one embodiment, the "hotness" or "coldness" of a page can represent the frequency of its access. The more times a page is accessed within a unit of time, the hotter it is, and according to the principle of temporal locality, the greater the likelihood that the page will continue to be accessed in the future. Through the process of migrating pages from the host-side local memory 112 to the DPU memory module 122, some pages that would otherwise be recycled can be moved to the DPU memory module 122. These pages stored in the DPU memory module 122 may also become hot pages due to frequent access by the host-side CPU 111. Although CPU access to the DPU memory module is faster than that of the switching device, it is still slower than access to local memory. Therefore, if hot pages reside in the DPU memory module for a long time, it may also lead to a decrease in system performance. Therefore, in one embodiment, it is considered to migrate hot pages in the DPU memory module 122 to the host-side local memory 112 for storage.

[0057] To address this, the first step is to determine the hotness or coldness of each page stored in the DPU memory module 122. Because of the use of the cache coherence interface 124, the DPU unit 12 can perceive the physical address of each memory access, unlike TPP and the operating system which rely on page fault interrupts. Therefore, a more accurate page promotion algorithm can be designed without the overhead of page faults.

[0058] After receiving a memory access request from the cache coherency interface 124, the DPU control module 121 obtains the physical address of the request and then converts it into a physical page number, i.e., a VPA number. The DPU unit 12 is also configured with a local access count table that records the access count for each VPA number. The specific structure of the local access count table is shown in Figure 4. Each entry in the local access count table consists of a VPA number, an access count, and a promotion flag. When the DPU control module 121 receives a memory access request, it parses the corresponding VPA number and then queries the local access count table. If the VPA number exists, the corresponding access count is incremented by 1; otherwise, the VPA number replaces an entry according to the LRU (Least Recently Used) algorithm. When the access count of a page reaches a first threshold, such as 4, it indicates that the page is highly popular. The page is identified as the first hot page, and the promotion flag is set to 1, indicating that it can be promoted to local memory. Since the host-side CPU 111 can access the DPU memory module 122 through the cache coherence interface 124, it can also access the local access count table. The host-side operating system 113 accesses the local access count table periodically through the CPU 111. When the operating system 113 detects that the promotion flag corresponding to a certain VPA number is 1, indicating that the first hot page is stored, it uses a page migration function to migrate the first hot page to local memory 112. Simultaneously, it modifies the page idle status flag corresponding to the VPA number in the bitmap managing the DPU memory module 122, changing it to indicate a page idle state (e.g., 0), and invalidates the corresponding page table entry in the DPU unit 12. When this hot page migration is complete, the corresponding promotion flag is changed to 0, indicating that the entry can be replaced from the local access count table.

[0059] In one embodiment, since the VPA address range is larger than the TPA, the number of pages downgraded from the host side 11 to the DPU unit 12 may exceed the actual memory of the DPU memory module 122. In this case, some pages need to be downgraded to the remote memory pool 13. Specifically, when it is detected that the actual memory of the DPU memory module 122 of the DPU unit is insufficient, if a page migration request (i.e., a request to migrate pages from the host side 11 to the DPU unit 12) is received, the DPU control module 121 uses the LRU algorithm to select the second page that needs to be replaced to the remote memory pool, and transmits the second page to the remote memory pool 13 for storage via the network interface 123. Furthermore, the present bit of the page table entry corresponding to this page is modified to 0, indicating that the page is now in the remote memory pool 13. Simultaneously, the DPU control module 121 migrates the first hot page requesting migration from the host side 11 to the DPU memory module 122, writing it into the space freed up by the second page in the DPU memory module 122. Afterwards, if the host-side CPU 11 needs to access the second page migrated to the remote memory pool 13, the DPU control module 121 searches the TLB or page table. If the present bit of the page table entry corresponding to the second page is 0, it indicates that the corresponding second page has been migrated to the remote memory pool 13. The DPU control module 121 then accesses the corresponding page in the remote memory pool 13 through the network interface 123, obtains the return result, and passes it to the host-side CPU 111.

[0060] In one embodiment, if the DPU unit 12 frequently accesses a page in the remote memory pool 13, it indicates that the page is highly popular and should be migrated to the DPU memory module 122, which has lower access latency, for storage. To this end, the DPU unit 12 also maintains a remote access count table, which records the access count of each page in the remote memory pool. When the DPU control module 121 detects that the access count of a page reaches a second threshold, it identifies it as a second hot page and promotes it to the DPU memory module 122 for storage. The structure of the remote access count table is consistent with the local access count table, as shown in Figure 4. When the DPU control module 121 accesses the remote memory pool 13 through the network interface 123, it increments the access count of the corresponding VPA number by 1. If the VPA number was not originally in the remote access count table, it is inserted according to the LRU algorithm. When the access count exceeds the second threshold, it is identified as a second hot page, and its promotion flag is set to 1. The DPU control module 121 periodically queries the remote access count table, filters out the second hot pages based on the promotion flag being 1, and promotes these pages from the remote memory pool 13 to the DPU memory module 122 via the network interface. After the migration is complete, the corresponding promotion flag is changed to 0, and the present bit of the corresponding entry in the TLB and page table is changed to 1, indicating that the page is now in the DPU memory module 122.

[0061] In summary, the multi-layered de-aggregation memory system for data centers disclosed in this invention, combined with a data interaction method between the host and DPU units, and between DPU units and remote memory pools, enables the expansion of memory from local memory to DPU memory and then to remote memory. This allows the host to obtain expanded memory while maintaining lower memory access latency. This method enables the migration of memory pages in both directions: from host local memory to DPU memory and from DPU memory to host memory, reducing the impact of migrating pages to DPU memory on memory access latency. Furthermore, this method enables the migration of memory pages in both directions: from DPU memory to remote memory and from remote memory to DPU memory, reducing the impact of migrating pages to remote memory on memory access latency. Compared to existing TPP systems, this invention can achieve memory migration at three levels: local memory, DPU memory, and remote memory, providing better scalability while avoiding memory resource waste. Compared to the Kona system, this invention can fully utilize local memory, resulting in lower memory access latency.

[0062] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A multi-level de-aggregation memory system for data centers, characterized in that, Include: On the host side, it includes: CPU, local memory connected to the CPU, and operating system connected to the CPU; A DPU unit is connected to the host side. The DPU unit includes a DPU control module and a DPU memory module connected to the DPU control module. A remote memory pool is connected to the DPU unit; The DPU control module controls the memory interaction between the DPU unit and the host side, and between the DPU unit and the remote memory pool. The memory capacity configured in the DPU unit includes the actual capacity of the DPU memory module and the capacity of the remote memory pool, wherein the portion of the actual capacity of the DPU memory module corresponds to the real physical address range; and the portion of the capacity of the remote memory pool corresponds to the virtual physical address range. The host-side CPU accesses the DPU memory module via a virtual physical address; The DPU control module receives memory access requests using VPA from the host-side CPU and translates the virtual physical address into a real physical address; The DPU control module accesses the DPU memory module or the remote memory pool based on the actual physical address obtained from the translation.

2. The system according to claim 1, characterized in that, The DPU unit is configured with a page table that records the mapping relationship between virtual physical addresses and real physical addresses. Each entry in the page table includes at least a virtual physical address number, a real physical address number, and a flag bit. The flag bits include at least a present bit and a valid bit, wherein the present bit is used to indicate that the page exists in the DPU memory module or in the remote memory pool, and the valid bit is used to indicate whether the page table entry is valid.

3. The system according to claim 2, characterized in that, Use a TLB to cache recently used page table entries; The DPU control module first accesses the TLB to translate the virtual physical address into a real physical address. When the TLB is not hit, it accesses the page table and updates the TLB.

4. The system according to claim 1, characterized in that, The DPU unit is configured with a bitmap, which is used to record the allocation of the DPU memory module. Each bit of the bitmap is an idle status flag, corresponding to a page in the virtual physical address space. The idle status flag is used to indicate the idle status of the corresponding page. If a page migration request is received from the host side, the bitmap is queried, and a free page is found according to the free status flag. The page requested to be migrated from the host side local memory is allocated to the free page, wherein the page migration request is a request to migrate the page from the host side to the DPU memory module.

5. The system according to claim 4, characterized in that, When querying the bitmap, the search begins from the page following the last free page that was previously allocated memory, and continues until a free page is found. In this case, the page requested to be migrated from the host side is allocated to that free page.

6. The system according to claim 4, characterized in that, Upon receiving the page migration request from the host side, If insufficient memory is detected in the DPU memory module, the DPU control module filters out the pages in the DPU memory module that need to be replaced to the remote memory pool, transmits the pages to the remote memory pool for storage via the network interface, and migrates the pages requesting migration from the host side to the DPU memory module.

7. The system according to claim 1, characterized in that, The DPU unit is also configured with a local access count table to record the number of times the host-side CPU accesses each page of the DPU memory module. The DPU control module records the number of times each page is accessed. If the number of times a page is accessed reaches a first threshold, it is identified as the first hot page. The operating system on the host side accesses the local access count table at regular intervals via the CPU. When the operating system identifies a first hot page, it migrates the first hot page from the DPU memory module to the local memory on the host side for storage.

8. The system according to claim 1, characterized in that, The DPU unit is also configured with a remote access count table to record the number of times the DPU unit accesses each page of the remote memory pool. When the DPU control module detects that the number of visits to a page reaches a second threshold, it identifies the page as a second hot page and migrates it from the remote memory pool to the DPU memory module for storage.

9. The system according to claim 1, characterized in that, The DPU unit is also configured with a cache coherence interface, and the host side is connected to the DPU unit through the cache coherence interface.

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