Method for automatically generating interval configuration diagram based on full-loop lookup logic

Abstract

The invention discloses a method for automatically generating an interval configuration diagram based on full-loop lookup logic. The method comprises the following steps: extracting a main transformer interval group and associated CT and PT from an SSD file; performing full-loop logic query of the CT and the CT winding, and then performing full-loop logic query of the PT and the PT winding; dividing the obtained secondary equipment into four levels according to equipment types; if the secondary equipment of the third level and the fourth level flows through the loop of the CT and the CT winding obtained in the step 2, the secondary equipment and the loop associated with the secondary equipment are reserved; according to the method, the workload and time of manual drawing are reduced through automatic processing, the accuracy and efficiency of drawing the interval configuration diagram are improved, and the workload of subsequent operation and maintenance is optimized.

Description

Technical Field

[0001] The present invention relates to the field of power system design and operation and maintenance, and in particular to a method for automatically generating an interval configuration diagram based on full-loop search logic. Technical Background

[0002] In the design and operation and maintenance of modern power systems, the bay configuration diagram is a vital tool. It shows in detail the connection relationship between the protection bays and related equipment in the power system, and plays a key role in circuit overview, fault location, operation and maintenance, etc.

[0003] However, the traditional method of drawing bay configuration diagrams mainly relies on manual modeling and configuration, which is prone to omissions due to the large number of devices involved, multiple types, and complex circuits. This method requires reading a large number of drawings and materials, which is not only inefficient, but also time-consuming and labor-intensive. In addition, each time the circuit is changed, multiple parts need to be redrawn, which requires a large maintenance workload. Summary of the invention

[0004] The purpose of the present invention is to provide a method for automatically generating an interval configuration diagram based on full-loop search logic in view of the above-mentioned deficiencies in the current prior art.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for automatically generating an interval configuration diagram based on full-loop search logic comprises the following steps:

[0007] Step 1: Extract the main transformer bay group and the associated CT and PT from the SSD file, and add the name, ratio and accuracy of the corresponding winding under the CT and PT. The main transformer bay group includes the main transformer high voltage side bay, medium voltage side bay, low voltage side bay and main transformer body bay;

[0008] Step 2: Perform full-loop logic query on the CT and its CT winding, and then perform full-loop logic query on the PT and its PT winding, to obtain the secondary devices and corresponding loops that have loop connection relationship between each CT winding and PT winding;

[0009] Step 3: Divide the secondary devices obtained in step 2 into 4 levels according to device type, with the level priority being: first level > second level > third level > fourth level;

[0010] Step 4: The secondary devices of the third and fourth levels are traversed. If the secondary devices of the third and fourth levels flow through step 2 to obtain the circuit of the CT and its CT winding, the secondary devices and their associated circuits are retained; if the secondary devices of the third and fourth levels do not flow through step 2 to obtain the circuit of the CT and its CT winding, the secondary devices and their associated circuits are deleted.

[0011] Performing a full-loop logic query of a CT and its CT winding as described above includes the following steps:

[0012] Step 2.1a: Parse the SSD file, extract the main transformer bay group and all current transformers CTs under the main transformer bay group and the secondary devices associated with their CT windings, and obtain the main transformer high-voltage side bay ID, medium-voltage side bay ID, low-voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file;

[0013] Step 2.2a: According to the CT windings under the main transformer bay group and the associated secondary devices extracted in the above step 2.1a, find all the loops passing through the associated secondary devices and the starting terminals and ending terminals of the loops in the SPD file;

[0014] Step 2.3a: traverse each loop description in the loop of the associated secondary device obtained in step 2.2a, and retain the loop whose loop description is associated with the CT winding name;

[0015] Step 2.4a: For the bay ID of the start terminal of the retained loop, if the same bay ID can be found in the main transformer high voltage side bay ID, medium voltage side bay ID, low voltage side bay ID and main transformer body bay ID under the main transformer bay group, the loop is retained, otherwise the loop is deleted;

[0016] Step 2.5a: Repeat steps 2.2a to 2.4a until all CTs and CT windings extracted in step 2.1 are traversed;

[0017] Step 2.6a: For the loops remaining after executing step 2.5a, if there are loops with duplicate loop IDs, only one of the loops is retained, and only one phase of the retained loop is retained.

[0018] Performing a full-loop logic query of a PT and its PT winding as described above includes the following steps:

[0019] Step 2.1b: Parse the SSD file, extract the main transformer bay group and all the voltage transformers PT and PT winding-related secondary devices under the main transformer bay group, and obtain the main transformer high-voltage side bay ID, medium-voltage side bay ID, low-voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file;

[0020] In the SSD file, find all the intervals with the same endpoints in the main transformer interval group, which are called associated intervals;

[0021] Step 2.2b: If the associated bay type is a bus bay, the associated bay is retained; if the associated bay type is not a bus bay, the associated bay is deleted; query the SSD file for all voltage transformers PT and their PT windings under the above bus bay, as well as the secondary equipment associated with the PT windings;

[0022] Step 2.3b: If the PT winding under the busbar interval is not the last zero-sequence winding: query the circuits through which the secondary equipment associated with the PT winding passes in the SPD file, and filter the queried circuits. If the circuit description contains "L%", the corresponding circuit is deleted. If it does not contain "L%", the corresponding circuit is retained. Query and filter all the starting terminals of the retained circuits based on the SPD file;

[0023] Step 2.4b: If the PT winding under the busbar interval is the last zero-sequence winding: query the circuits through which the secondary equipment associated with the PT winding passes in the SPD file, and filter the queried circuits. If the circuit description contains "L%", the corresponding circuit is retained. If not, the corresponding circuit is deleted. Query and filter all the starting terminals of the retained circuits based on the SPD file;

[0024] Step 2.5b: Based on the starting terminal queried in the above steps 2.3b and 2.4b, query all the circuits through which the starting terminal flows, as well as the starting terminals, ending terminals, and secondary devices passing through all the queried circuits;

[0025] Step 2.6b: Search the bay IDs of the starting terminals of all the loops queried in step 2.5b based on the SPD file. If the bay ID of the starting terminals of the loops queried in step 2.5b is consistent with any bay ID in the main transformer bay group, the loop is retained; if not, the loop is deleted.

[0026] Step 2.7b: Repeat steps 2.3b to 2.6b until all PTs and PT windings queried in step 2.2b are traversed;

[0027] Step 2.8b: After executing the above steps, for the remaining loops, if there are loops with duplicate loop IDs, only one of the loops is retained, and only one phase of the retained loop is retained.

[0028] As described above, the secondary device performs the level determination only once, and the secondary device performs the high priority level determination first.

[0029] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0030] A computer-readable storage medium stores a computer program, which implements the steps of the above method when executed by a processor.

[0031] A computer program product comprises a computer program, which implements the steps of the above method when executed by a processor.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. Improve efficiency and accuracy: Through automated processing and the use of SSD and SPD files, the interval configuration diagram can be quickly generated, significantly reducing the time and manpower input of manual operations.

[0034] 2. Improve accuracy: Through automatic screening and deduplication mechanism, the correct association between each winding and secondary device is ensured, avoiding the problems of wrong connection and missed connection in manual operation, and improving the accuracy of the overall drawing.

[0035] 3. Simplify maintenance work: The present invention only needs to update the SPD file for later maintenance and then generate the interval configuration diagram immediately, which reduces the maintenance workload and greatly alleviates the system maintenance burden. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is the process of the present invention.

[0037] Figure 2 This is a schematic diagram of the relationship between windings and secondary devices in the SSD file.

[0038] Figure 3 Define footprint for hierarchical placement. DETAILED DESCRIPTION

[0039] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. It should be understood that the implementation examples described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0040] Embodiment 1:

[0041] like Figure 1 As shown, a method for automatically generating an interval configuration diagram based on full-loop search logic, based on SSD files and SPD files, automatically generates an interval configuration diagram of the voltage and current of each secondary device and the connection relationship between the CT and PT windings of the corresponding primary main wiring diagram according to the loop search logic, and the method includes:

[0042] Exemplarily, it is assumed that the logic of generating the main transformer bay configuration diagram of a 220kV substation is taken as an example.

[0043] Step 1: According to the existing SSD file standard specifications, extract the main transformer high voltage side bay, medium voltage side bay, low voltage side bay, main transformer body bay, and the corresponding primary equipment associated with each bay: CT current transformer, PT voltage transformer.

[0044] Modify the SSD file according to the existing drawings. Add the name, ratio, accuracy and other parameters of the corresponding windings under the existing CT current transformer and PT voltage transformer. At the same time, associate each winding with a secondary device that passes through the winding loop according to the drawing information.

[0045] The high-voltage side bay, medium-voltage side bay, low-voltage side bay, and main transformer bay are defined as a main transformer bay group. The modified SSD file is as follows: Figure 2 shown.

[0046] The interval names in the SSD file are consistent with the interval names in the SPD file.

[0047] Step 2: First perform a full-loop logic query on the CT and its CT winding, and then perform a full-loop logic query on the PT and its PT winding, to form a loop connection relationship between the winding and all devices, and perform loop deduplication processing according to the logic.

[0048] The full circuit query logic of CT and its windings is as follows:

[0049] Step 2.1a: Parse the modified SSD file to extract the main transformer bay group and all current transformers CT and secondary devices associated with their CT windings under the main transformer bay group. At the same time, because the bay name in the SSD file is consistent with the bay name in the SPD model, the main transformer high voltage side bay ID, medium voltage side bay ID, low voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file are obtained.

[0050] Step 2.2a: Based on the CT windings under the main transformer bay group extracted in step 2.1a above and the associated secondary devices, perform loop query in the SPD file. Find all loops passing through the associated secondary devices and the start-pin and end-pin of the loops;

[0051] Step 2.3a: According to the current transformer CT and the CT winding name "T21-5", traverse each loop description in the loop of the associated secondary device obtained in step 2.2a, retain the loop description associated with the CT winding name (for example, the loop description is "%215%"), and delete the remaining loops;

[0052] Step 2.4a: According to the above step 2.3a, the start-pin of the retained loop and its bay ID are compared with the main transformer high voltage side bay ID, medium voltage side bay ID, low voltage side bay ID and main transformer body bay ID under the main transformer bay group. If the start-pin and its bay ID are consistent with any bay ID in the main transformer bay group, the loop is retained; if not, the loop is deleted, and the secondary equipment with loop connection relationship and the corresponding loop of the current traversed CT winding are obtained.

[0053] Step 2.5a: Repeat steps 2.2a to 2.4a, and query the windings of the remaining CTs in other intervals in sequence as described above, until all CTs and CT windings extracted in step 2.1 are traversed;

[0054] Step 2.6a: For the remaining loops after executing step 2.5a, if there are loops with duplicate loop IDs, delete the loops with duplicate loop IDs and keep only one loop. At the same time, determine the phase (A, B, C, N phase) according to the description or phase identification of the loop, and keep only one phase in the loop;

[0055] The full circuit query logic of PT and its winding is as follows:

[0056] Step 2.1b: Parse the modified SSD file to extract the main transformer bay group, as well as all the voltage transformers PT and secondary devices associated with the PT windings under the main transformer bay group. At the same time, because the bay name in the SSD file is consistent with the bay name in the SPD file, the main transformer high voltage side bay ID, medium voltage side bay ID, low voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file are obtained.

[0057] According to the SSD file, all the intervals with the same endpoints in the main transformer interval group can be found, which are called associated intervals;

[0058] Step 2.2b: Determine whether the associated bay type is a bus bay, and the bus bay is retained; at the same time, query all voltage transformers PT and their PT windings under the bus bay in the SSD file, as well as the secondary equipment associated with the PT winding;

[0059] Step 2.3b: Determine all the voltage transformers PT and their PT windings under the above busbar interval. If the PT winding under the busbar interval is not the last zero-sequence winding, query the circuits through which the secondary equipment associated with its PT winding passes based on the SPD file, and filter the circuit descriptions of the queried circuits. The filtering logic is whether the circuit description contains "L%". If it does, the corresponding circuit is deleted. If it does not, the corresponding circuit is retained. At the same time, query and filter all the start terminals start-pin of the retained circuits based on the SPD file;

[0060] Step 2.4b: Determine all the voltage transformers PT and their PT windings under the above busbar interval. If the PT winding under the busbar interval is the last zero-sequence winding, query the circuits through which the secondary equipment associated with its PT winding passes based on the SPD file, and filter the circuit descriptions of the queried circuits. The filtering logic is whether the circuit description contains "L%". If it does, the corresponding circuit is retained. If it does not, the corresponding circuit is deleted. At the same time, query and filter all the start terminals start-pin of the retained circuits based on the SPD file;

[0061] Pay special attention to one situation. When no circuit is found according to step 2.4b, the circuit through which the secondary equipment associated with the PT winding passes will be queried again based on the SPD file, and the starting terminal start-pin of the queried circuit will be queried based on the SPD file.

[0062] Step 2.5b: Based on the start terminal start-pin queried in the above steps 2.3b and 2.4b, query all the circuits through which the start terminal start-pin flows, as well as the start terminal start-pin, end terminal end-pin of all the queried circuits, and the secondary devices passing through all the queried circuits;

[0063] Step 2.6b: Filter the start-pin of all the loops queried in step 2.5b, find the bay ID to which the start-pin of all the loops queried in step 2.5b belongs based on the SPD file, and compare them one by one with the bay ID of the main transformer high-voltage side, the bay ID of the medium-voltage side, the bay ID of the low-voltage side, and the bay ID of the main transformer body under the main transformer bay group. If the start-pin of the loop queried in step 2.5b and its bay ID are consistent with any bay ID in the main transformer bay group, the loop is retained; if not, the loop is deleted, and the secondary equipment with loop connection relationship and the corresponding loop of the currently traversed PT winding are obtained.

[0064] Step 2.7b: Repeat steps 2.3b to 2.6b, and query the PT windings of the remaining PTs in other intervals in sequence as described above, until all PTs and PT windings queried in step 2.2b are traversed.

[0065] Step 2.8b: After executing the above step 2.7b, for the remaining loops, if there are loops with duplicate loop IDs, delete the loops with duplicate loop IDs and keep only one loop. At the same time, determine the phase (A, B, C, N phase) according to the description or phase identification of the loop, and keep only one phase in the loop.

[0066] After executing step 2, the CT winding and PT winding of the current transformer CT and the voltage transformer PT of the main transformer bay group, as well as the secondary equipment and corresponding circuits in which each CT winding and PT winding has a loop connection relationship can be obtained.

[0067] Step 3: Divide the secondary equipment obtained in step 2 into levels according to the equipment type, where the first level should be the merging unit / collection execution unit / integrated intelligent device involved; the second level should be the voltage switching device, protection device, and measurement and control device of the main transformer bay group; the third level should be busbar protection, standby automatic switching, power quality, and metering; the fourth level should be stabilization control, wave recording, traveling wave, PMU and other equipment.

[0068] The priority is set as follows: first level > second level > third level > fourth level. All secondary devices are judged only once, starting from the first level. Secondary devices are judged first at the high priority level. If the secondary device meets the first level conditions, there is no need to judge the subsequent levels; otherwise, the second, third, and fourth levels are judged in order.

[0069] Step 4: Finally, according to the secondary devices and corresponding loops with loop connection relationship of CT winding obtained in step 2, the secondary devices are screened once, and this screening is only for the secondary devices of the third and fourth levels. The judgment standard is: if the secondary devices of the third and fourth levels flow through the loop of the current transformer CT and its CT winding obtained in step 2, then the secondary devices and their associated ones are retained; if not, then the secondary devices and their associated loops are deleted.

[0070] Through the above logic and step results, i.e., CT, CT winding, PT, PT winding, and the remaining secondary devices and associated circuits after executing step 4, a complete bay configuration diagram of the main transformer bay group can be obtained.

[0071] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods.

[0072] Embodiment 2:

[0073] This embodiment provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above-mentioned embodiment 1 when executing the computer program.

[0074] Embodiment 3:

[0075] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned embodiment 1 are implemented.

[0076] Embodiment 4:

[0077] This embodiment provides a computer program product, including a computer program, which implements the steps in the above-mentioned embodiment 1 when executed by a processor.

[0078] The specific embodiments described herein are merely examples of the present invention. A person skilled in the art may make various modifications, additions or substitutions to the specific embodiments described, but will not deviate from the essence of the present invention or exceed the scope defined by the appended claims.

Claims

1. A method for automatically generating an interval configuration diagram based on full-loop search logic, characterized in that: The following steps are involved: Step 1: Extract the main transformer bay group and the associated CT and PT from the SSD file, and add the name, ratio and accuracy of the corresponding winding under the CT and PT. The main transformer bay group includes the main transformer high voltage side bay, medium voltage side bay, low voltage side bay and main transformer body bay; Step 2: Perform full-loop logic query on the CT and its CT winding, and then perform full-loop logic query on the PT and its PT winding, to obtain the secondary devices and corresponding loops that have loop connection relationship between each CT winding and PT winding; Step 3: Divide the secondary devices obtained in step 2 into 4 levels according to device type, with the level priority being: first level > second level > third level > fourth level; Step 4: The secondary devices of the third and fourth levels are traversed. If the secondary devices of the third and fourth levels flow through step 2 to obtain the circuit of the CT and its CT winding, the secondary devices and their associated circuits are retained; if the secondary devices of the third and fourth levels do not flow through step 2 to obtain the circuit of the CT and its CT winding, the secondary devices and their associated circuits are deleted.

2. According to claim 1, a method for automatically generating an interval configuration diagram based on full-loop search logic is characterized in that: The full-loop logic query of the CT and its CT winding comprises the following steps: Step 2.1a: Parse the SSD file, extract the main transformer bay group and all current transformers CTs under the main transformer bay group and the secondary devices associated with their CT windings, and obtain the main transformer high-voltage side bay ID, medium-voltage side bay ID, low-voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file; Step 2.2a: According to the CT windings under the main transformer bay group and the associated secondary devices extracted in the above step 2.1a, find all the loops passing through the associated secondary devices and the starting terminals and ending terminals of the loops in the SPD file; Step 2.3a: traverse each loop description in the loop of the associated secondary device obtained in step 2.2a, and retain the loop whose loop description is associated with the CT winding name; Step 2.4a: For the bay ID of the start terminal of the retained loop, if the same bay ID can be found in the main transformer high voltage side bay ID, medium voltage side bay ID, low voltage side bay ID and main transformer body bay ID under the main transformer bay group, the loop is retained, otherwise the loop is deleted; Step 2.5a: Repeat steps 2.2a to 2.4a until all CTs and CT windings extracted in step 2.1 are traversed; Step 2.6a: For the loops remaining after executing step 2.5a, if there are loops with duplicate loop IDs, only one of the loops is retained, and only one phase of the retained loop is retained.

3. The method for automatically generating an interval configuration diagram based on full-loop search logic according to claim 1, characterized in that: The full-loop logic query of the PT and its PT winding comprises the following steps: Step 2.1b: Parse the SSD file, extract the main transformer bay group and all the voltage transformers PT and PT winding-related secondary devices under the main transformer bay group, and obtain the main transformer high-voltage side bay ID, medium-voltage side bay ID, low-voltage side bay ID, and main transformer body bay ID under the main transformer bay group in the SPD file; In the SSD file, find all the intervals with the same endpoints in the main transformer interval group, which are called associated intervals; Step 2.2b: If the associated bay type is a bus bay, the associated bay is retained; if the associated bay type is not a bus bay, the associated bay is deleted; query the SSD file for all voltage transformers PT and their PT windings under the above bus bay, as well as the secondary equipment associated with the PT windings; Step 2.3b: If the PT winding under the busbar interval is not the last zero-sequence winding: query the circuits through which the secondary equipment associated with the PT winding passes in the SPD file, and filter the queried circuits. If the circuit description contains "L%", the corresponding circuit is deleted, and if it does not contain "L%, the corresponding circuit is retained. Query and filter all the starting terminals of the retained circuits based on the SPD file; Step 2.4b: If the PT winding under the busbar interval is the last zero-sequence winding: query the circuits through which the secondary equipment associated with the PT winding passes in the SPD file, and filter the queried circuits. If the circuit description contains "L%", the corresponding circuit is retained, and if it does not contain it, the corresponding circuit is deleted. Query and filter all the starting terminals of the retained circuits based on the SPD file; Step 2.5b: Based on the starting terminal queried in the above steps 2.3b and 2.4b, query all the circuits through which the starting terminal flows, as well as the starting terminals, ending terminals, and secondary devices passing through all the queried circuits; Step 2.6b: Search the bay IDs of the starting terminals of all the loops queried in step 2.5b based on the SPD file. If the bay ID of the starting terminals of the loops queried in step 2.5b is consistent with any bay ID in the main transformer bay group, the loop is retained; if not, the loop is deleted. Step 2.7b: Repeat steps 2.3b to 2.6b until all PTs and PT windings queried in step 2.2b are traversed; Step 2.8b: After executing the above steps, for the remaining loops, if there are loops with duplicate loop IDs, only one of the loops is retained, and only one phase of the retained loop is retained.

4. The method for automatically generating an interval configuration diagram based on full-loop search logic according to claim 1, characterized in that: The secondary device performs level determination only once, and the secondary device performs high priority level determination first.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

7. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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