A method for protecting sensitive information in a chip and a chip

Abstract

The application discloses a chip in-situ sensitive information protection method and chip, and aims at improving the security of sensitive data in the chip. The method divides the chip life cycle into four stages of testing, debugging, product running and life cycle end, and adopts different protection measures in different stages, such as disabling JTAG interface, OTP read-only locking and the like. The stage marker and register value are used to determine the stage and prevent the stage from backfolding, simplify the user protection private data flow, and the operation is simple and safe. The chip comprises a FLASH area and an OTP area, the FLASH area stores a boot loader, and the sensitive information protection method is executed. The application improves the security of the chip, prevents data leakage or tampering, and simplifies the operation flow.

Description

Technical Field

[0001] This invention relates to a method for protecting sensitive information within a chip, and also to a corresponding chip, belonging to the field of information security technology. Background Technology

[0002] The boot loader of a security chip has functions such as firmware signature verification, encryption, data anti-tampering, and secure storage to protect the data and firmware stored in the chip from unauthorized access and tampering, thus preventing losses to users.

[0003] The bootloader for existing security chips typically injects sensitive data via a host computer tool. The security chip then stores this sensitive data in its One-Time Programming (OTP) memory or internal FLASH memory. The OTP address is generally not publicly accessible to prevent unauthorized reading of sensitive data, such as software version numbers, hardware version numbers, and user data. Firmware and system data are stored within the FLASH chip. A signature verification method is typically used to prevent firmware data tampering. When downloading firmware, the host computer tool signs the firmware, and then the signed firmware is sent to the chip. Upon receiving the firmware, the chip verifies the signature; only after successful verification does the chip start the firmware.

[0004] However, although the bootloader of existing security chips stores sensitive data in an OTP area with a non-public address, this address can still be obtained through brute force, and the security cannot meet the increasingly high commercial requirements.

[0005] Furthermore, sensitive data includes chip manufacturer data and user data. However, current security chips do not separately protect chip manufacturer data and user data, nor do they differentiate security levels between firmware and data. Because sensitive data lacks a distinction between high, medium, and low security levels, some low-security sensitive data can be set to high security levels, hindering subsequent use. The complex structure of sensitive data requires users to understand the meaning of each data point for configuration, and sometimes even the storage address of sensitive data is necessary, which is inconvenient. Once sensitive data is attacked or tampered with, it can lead to security vulnerabilities in the chip, allowing the startup of unauthorized firmware. Summary of the Invention

[0006] The primary technical problem to be solved by this invention is to provide a method for protecting sensitive information within a chip.

[0007] Another technical problem to be solved by the present invention is to provide a chip employing the above-mentioned sensitive information protection method.

[0008] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0009] According to a first aspect of the present invention, a method for protecting sensitive information within a chip is provided, comprising the following steps:

[0010] Step 1: Power on and start up. Read from OTP and check if there is a marker in the Phase 3 check. If there is a marker, proceed to Step 2; otherwise, proceed to Step 3.

[0011] Step 2: Disable the chip's JTAG interface, and set gStage=Product Operation Stage and stage=3 for OTP, then proceed to Step 6;

[0012] Step 3: Check if the register REG_STAGE_FLAG = 01. If not, disable the JTAG interface and reset the chip. If yes, proceed to step 4.

[0013] Step 4: Set gStage=debug stage and stage=2, then proceed to step 5;

[0014] Step 5: Check the Stage 2 marker. If there is a marker, proceed to Step 6; otherwise, set gStage = Test Stage and stage = 1, then proceed to Step 6.

[0015] Step 6: Determine if stage≥2 is satisfied. If not, proceed to step 8; if satisfied, proceed to step 7.

[0016] Step 7: Recalculate the CRC value based on the parameters or data in the current stage OTP, and compare it with the CRC value in the injected stage 2 parameters to determine if they are consistent. If they are inconsistent, decrement stage by 1 and reset the chip; if they are consistent, proceed to the next step.

[0017] Step 8: Determine if stage≥3 is satisfied. If not, proceed to step 10; if satisfied, proceed to step 9.

[0018] Step 9: Recalculate the CRC value based on the parameters or data in the current stage OTP, and compare it with the CRC value in the injected stage 2 parameters to determine if they are consistent. If they are inconsistent, decrement stage by 1 (make stage = 2) and reset the chip; if they are consistent, proceed to the next step.

[0019] Step 10: Determine if one of the following conditions is met: gStage = Test Stage and stage! = 1, gStage = Debug Stage and stage! = 2, gStage = Product Operation Stage and stage! = 3. If it is met, reset the chip; if none of them are met, end the process and proceed to firmware download and startup.

[0020] Preferably, the chip is not protected during the testing phase; the chip's OTP is locked in read-only mode during the debugging phase; and the chip's OTP is made unreadable during the product operation phase, and JTAG debugging is prohibited, requiring firmware verification while maintaining the OTP read-only mode.

[0021] Preferably, during the testing and debugging phases, register REG_STAGE_FLAG = 01; during the product operation phase, register REG_STAGE_FLAG = 02.

[0022] Preferably, when upgrading from the testing phase to the debugging phase, the phase 2 flag is written into the OTP of the chip, and gStage is set to debug phase and stage = 2.

[0023] Preferably, when transitioning from the debugging phase to the product operation phase, a stage 3 marker is written into the chip's OTP, and gStage is set to product operation phase and stage = 3.

[0024] Preferably, the value of the REG_STAGE_FLAG register is set to 02.

[0025] Preferably, during the debugging phase, an RSA public key is injected into the chip's OTP for downloading authentication and signing.

[0026] According to a second aspect of the present invention, a chip is provided, including a FLASH area and an OTP area, wherein a bootloader is stored in the FLASH area for executing the sensitive information protection method within the chip as described above.

[0027] Preferably, the chip's OTP is not protected during the testing phase; during the debugging phase, the OTP is read-only locked; during the product operation phase, the OTP is made unreadable, and JTAG debugging is prohibited, requiring firmware verification, while maintaining the OTP read-only lock.

[0028] Compared with existing technologies, the present invention has the following advantages: 1) It divides the chip into four life cycle stages according to different usage scenarios, distinguishes the security level of external data according to different usage scenarios, and writes and protects it at different stages to prevent data leakage or tampering, thus balancing security and convenience; 2) It uses stage markers and register values ​​to determine different stages and prevent stage rollback; 3) It simplifies the process of protecting private data for users, and is simple and easy to use. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the bootloader startup process during the product's runtime phase.

[0030] Figure 2This is the classification of different security levels in the first embodiment of the present invention;

[0031] Figure 3 This is a flowchart illustrating a method for protecting sensitive information within a chip, as described in the first embodiment of the present invention.

[0032] Figure 4 This is an example diagram of the parameters or data injected into the chip in the first embodiment of the present invention. Detailed Implementation

[0033] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] The technical concept in this invention is as follows: By introducing a lifecycle maintenance mechanism into the chip's bootloader, sensitive data is divided into chip manufacturer sensitive data and user sensitive data. Device manufacturers or terminal manufacturers only need to be concerned with the use of user sensitive data and do not need to consider how the chip manufacturer's sensitive data is used, thus simplifying the operation process and greatly reducing the difficulty of using sensitive data during chip software development. Furthermore, all sensitive data is differentiated into low, medium, and high security levels based on their security severity, facilitating subsequent use. With the introduction of the lifecycle maintenance mechanism, once the lifecycle is upgraded, it cannot be rolled back. Even if sensitive data is attacked or tampered with, the lifecycle cannot be reversed, thereby avoiding security vulnerabilities and greatly improving chip security.

[0035] First Embodiment

[0036] like Figure 2 As shown, a System Microcontroller Unit (SMCU) typically undergoes testing, debugging, end-product manufacturing, and end-of-life processes after leaving the wafer. In this embodiment, the SMCU's bootloader divides the chip's lifecycle into four stages for these different usage processes. Each stage can only be upgraded to the next adjacent stage and cannot be rolled back (the upgrade parameters for each stage are written to the OTP and cannot be erased or rewritten).

[0037] Specifically, during the testing phase (used by the manufacturing process engineer to inspect the chip), the chip's memory (OTP, FLASH, RAM) is in its initial state (the bootloader detects no stage marker in the OTP, so it considers this phase equal to the testing phase and sets stage = 1). The chip manufacturer can then test the chip and its peripheral interfaces. This phase requires writing calibration parameter markers. After the chip passes calibration, the serial number (SN) is injected into the OTP and the calibration parameter markers are written, indicating that the chip calibration is successful. Furthermore, the parameters injected into the OTP during the upgrade from the testing phase to the debugging phase include... Figure 3It includes the Stage 2 flag, SN (serial number), calibration parameters, and CRC (CRC32 value of the parameter before Stage2_flag).

[0038] Write the Stage 2 flag to the OTP (for example, set the Stage 2 flag value to 1), set gStage = debug stage and stage = 2, and upgrade to the debug stage. In this stage, the REG_STAGE_FLAG register is equal to 01.

[0039] During the debugging phase (used by device manufacturers for hardware and software debugging of the chip), device manufacturers may frequently download debug firmware. Since the chip is not yet a mature product, only basic protection is provided for this phase (protecting chip identity information: SN, test flag). Once development is complete, the device manufacturer injects the RSA public key (used for downloading authentication and signing) and private data into the chip, and writes a Stage 3 flag into the OTP (e.g., setting the Stage 3 flag value to 1), sets gStage to the product operation phase and stage = 3, and the chip enters the product operation phase. Furthermore, the value of the REG_STAGE_FLAG register is set to 02.

[0040] The parameters injected during the transition from the debugging phase to the product operation phase are similar to those in the testing phase, including the Phase 3 flag, SN, calibration parameters, and CRC. During this phase, the value of the REG_STAGE_FLAG register remains 01.

[0041] During the product operation phase (when the chip is integrated with other hardware and software and provided to users as an end product), the chip operates in a real product environment with the highest security level. Some keys and private data require strict protection to prevent external reading and tampering. Device manufacturers can update and upgrade the chip firmware (signature verification is required). In this phase, if the device firmware fails to boot in phase 3, the chip is considered damaged and reaches phase 4, which marks the end of its life cycle.

[0042] When the chip reaches the end of its lifespan (the chip hardware reaches its service life and the chip cannot boot the firmware), the security level is the highest compared to the product's operating stage. Even when the lifespan ends, the security protection function remains effective. If the hardware supporting the security function is damaged, the firmware cannot be booted, and sensitive data inside the chip cannot be obtained from the outside.

[0043] As can be seen, in this embodiment, the upgrade at each stage must be carried out in accordance with... Figure 2As shown, the upgrade process cannot skip any stages. Each stage has a different security level, meaning different methods are used to protect sensitive data. The security level is highest at the end of the product lifecycle and during product operation, with the most stringent protection of sensitive data, strictly prohibiting its leakage. The security level is next highest during the debugging stage, and there is no security protection during the testing stage. This design prevents the chip from regressing from a high-security-level stage to a low-security-level stage, thus avoiding major security incidents caused by incorrect security levels, where sensitive data would not be protected.

[0044] Furthermore, this embodiment provides different levels of security protection (tiered protection) for each stage, enabling the chip to have different functions. Below is an example of a table showing the correspondence between each stage and its function. Those skilled in the art will understand that the content of this table can be adjusted according to actual needs, such as adding control over specific functions.

[0045] Table 1. Comparison of Stages and Functions

[0046]

[0047] Specifically, the graded protection mechanism includes: no protection during the testing phase; OTP read-only lock during the debugging phase; making OTP unreadable and prohibiting JTAG debugging during the product operation phase, requiring firmware verification while maintaining OTP read-only lock; and making OTP unreadable, prohibiting JTAG debugging, and prohibiting firmware startup during the end-of-life phase.

[0048] Based on the aforementioned tiered protection mechanism at each stage, such as Figure 3 As shown, the method for protecting sensitive information within a chip provided in the first embodiment of the present invention includes the following steps:

[0049] Step 1: Power on and start the machine. Read from the OTP and check if there is a marker in the Phase 3 check. If there is a marker, proceed to Step 2. If there is no marker, proceed to Step 3.

[0050] If the Phase 3 marker is present, it indicates that the chip is in the product operation phase (Phase 3). According to the reference table shown in Table 1, the chip's JTAG (Joint Tech Action Group) interface should be disabled to prevent unauthorized access and tampering. For chips without the Phase 3 marker, it indicates that the chip is not in Phase 3 (it may be in Phase 1 or Phase 2).

[0051] Step 2: Disable the chip's JTAG interface, and set gStage=Product Operation Stage and stage=3 for OTP, then proceed to Step 6.

[0052] As mentioned above, when the chip moves from the debugging stage (stage 2) to the product operation stage (stage 3), the equipment manufacturer writes a stage 3 mark in the chip's OTP. Therefore, in this step, since the stage 3 mark is already marked, it indicates that the chip has entered stage 3 and cannot be reversed.

[0053] Since the chip has entered the product operation stage, according to the settings in Table 1, disable the JTAG interface of the chip to prevent unauthorized access and tampering; and set gStage=product operation stage and stage=3 for OTP.

[0054] Step 3: Check if the register REG_STAGE_FLAG = 01. If not, disable the JTAG interface and reset the chip. If yes, proceed to step 4.

[0055] As mentioned earlier, when a chip enters the product operation phase, the value of the REG_STAGE_FLAG register is set to 02. In other words, during the testing phase (Phase 1) and debugging phase (Phase 2), the REG_STAGE_FLAG register is equal to 01. By checking the value of the REG_STAGE_FLAG register, chips in the product operation phase (Phase 3) and beyond can be distinguished. Since chips in the product operation phase (Phase 3) were already detected in step 1 based on the Phase 3 marker, this step uses the register value to distinguish chips in Phase 3 from chips in Phase 1 or Phase 2.

[0056] A Phase 4 chip will inevitably have a Phase 3 marker, and therefore possesses the security features of a Phase 3 chip. The only difference between a Phase 4 chip and a Phase 3 chip is that it cannot boot, so no further detection is needed.

[0057] Step 4: Set gStage=Debug stage and stage=2, then proceed to step 5.

[0058] As mentioned earlier, since register REG_STAGE_FLAG = 01, step 3 determines that the chip is in the testing phase (phase 1) and the debugging phase (phase 2). In this step, the chip is set to gStage = debugging phase and stage = 2.

[0059] Step 5: Check the Stage 2 marker. If there is a marker, proceed to Step 6; otherwise, set gStage = Test Stage and stage = 1, then proceed to Step 6.

[0060] Because the Phase 2 marker is injected into the OTP only when the test phase is upgraded to the debug phase, there is no marker in the chip during the test phase. Therefore, this step is used to distinguish the chips in the test phase (Phase 1) and the debug phase (Phase 2). In other words, the aforementioned steps are used to differentiate the chips in the three phases and process them separately.

[0061] Step 6: Determine if stage≥2 is satisfied. If not, proceed to step 8; if satisfied, proceed to step 7.

[0062] Step 7: Recalculate the CRC value based on the parameters or data in the current stage OTP, compare it with the CRC value in the injected stage 2 parameters, and determine if they are consistent. If they are inconsistent, decrement stage by 1 and reset the chip; if they are consistent, proceed to the next step.

[0063] The parameters or data structures injected into the chip when upgrading from one stage to the next stage according to the embodiments of the present invention. Figure 4 Each parameter or data segment contains its CRC value. When determining the stage size, the bootloader recalculates the CRC of the parameters or data in the current OTP and compares the newly calculated CRC value with the CRC value of the previously injected parameters or data. If the CRCs match, the verification passes; otherwise, it indicates that the current parameters or data have been tampered with and are unusable. The bootloader then decrements the stage size by 1 (or sets stage = 1) and resets the chip.

[0064] Specifically, in this step, since the chip has a stage value of 2 (obtained in step 4), subtracting 1 from stage gives stage = 1. Thus, in this step, the chip is set to gStage = debug stage and stage = 1. By making the values ​​of gStage and stage mismatched, chips whose parameters or data have been tampered with are identified.

[0065] Therefore, by using the CRC value within the parameters of the debugging phase (Phase 2) as a basis for consistency judgment, it is possible to determine whether the chip parameters or data in Phase 2 or Phase 3 have been tampered with. Using this design, terminal manufacturers do not need to know the OTP address to which these parameters are written, nor the meaning of the parameters injected during the testing phase, nor even whether the parameters injected during the testing phase exist. They only need to ensure that the parameters injected during the upgrade from the debugging phase to the product operation phase are correct, thus achieving firmware verification and balancing security and ease of use.

[0066] Step 8: Determine if stage≥3 is satisfied. If not, proceed to step 10; if satisfied, proceed to step 9.

[0067] Step 9: Recalculate the CRC value based on the parameters or data in the current stage OTP, compare it with the CRC value in the injected stage 2 parameters, and determine if they are consistent. If they are inconsistent, decrement stage by 1 (make stage = 2) and reset the chip; if they are consistent, proceed to the next step.

[0068] Step 10: Determine if one of the following conditions is met: gStage = Test Stage and stage! = 1, gStage = Debug Stage and stage! = 2, gStage = Product Operation Stage and stage! = 3. If it is met, reset the chip; if none of them are met, end the process and proceed to firmware download and startup.

[0069] As described above, in one embodiment of the present invention, the checks are performed sequentially from high to low stage (stage 3 to stage 1). If the current stage is the product operation stage (stage 3), then the following three conditions must be met simultaneously: the value of register REG_STAGE_FLAG is equal to 02, gStage = product operation stage, and stage = 3. If the current stage is the debugging stage, then the following three conditions must be met simultaneously: the value of register REG_STAGE_FLAG is equal to 01, gStage = debugging stage, and stage = 2. If the current stage is the testing stage, then the following three conditions must be met simultaneously: the value of register REG_STAGE_FLAG is equal to 1, gStage = testing stage, and stage = 1. If any of the above three stage conditions are not met, the chip is reset and the program cannot be started. Therefore, once the chip is attacked and the internal data of the OTP is tampered with, the bootloader can detect this situation after startup and refuse to start the firmware.

[0070] Furthermore, during the testing and debugging phases of the chip, the value of the REG_STAGE_FLAG register is 01 by default. Only when upgraded to the production running phase is the value of the REG_STAGE_FLAG register set to 02. Moreover, this register is designed so that once a value other than 01 is written to it, it cannot be changed back to 01, preventing tampering. During actual chip operation, in phase 2, the injected OTP parameters are read-only locked and cannot be read, so external attacks cannot tamper with the data; in phase 3, the injected OTP parameters are set to be unreadable, so external attacks also cannot tamper with the data. In summary, since the injected parameters cannot be modified at each stage, and the value of the REG_STAGE_FLAG register cannot be modified after being written once, the stages cannot be rolled back, thus achieving the goal of protecting data security.

[0071] Second Embodiment

[0072] The third embodiment of the present invention provides a method for protecting sensitive information within a chip, comprising the following steps:

[0073] Upon power-on, the chip's OTP check stage 3 flag is checked. If a flag is found, the JTAG interface is disabled and the chip is reset. If no flag is found, the process proceeds to the next step.

[0074] Check the Phase 2 marker. If there is a marker, it indicates that the chip is in the debugging phase; if there is no marker, it indicates that the chip is in the testing phase.

[0075] The CRC value is recalculated based on the parameters or data within the current OTP phase. This value is then compared with the CRC value in the injected Phase 2 parameters. If they match, the firmware is started; otherwise, the chip is reset.

[0076] When the chip moves from the testing phase to the debugging phase, it is marked with a phase 2 tag and injected with phase 2 parameters or data; when it moves from the debugging phase to the product operation phase, it is marked with a phase 3 tag and injected with phase 3 parameters or data.

[0077] Third Embodiment

[0078] A third embodiment of the present invention provides a chip. This chip has a FLASH memory and an OTP area. The FLASH memory stores a bootloader program, which is used to execute the sensitive information protection methods described in the above embodiments after power-on.

[0079] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of the various embodiments can be combined, and the order of the steps can be changed, all of which are within the scope of protection of this patent.

[0080] The above provides a detailed description of the method for protecting sensitive information within a chip and the chip provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A method for protecting sensitive information within a chip, characterized in that... Includes the following steps: Step 1: Power on and start up. Read from OTP and check if there is a marker in the Phase 3 check. If there is a marker, proceed to Step 2; otherwise, proceed to Step 3. Step 2: Disable the chip's JTAG interface, and set gStage=Product Operation Stage and stage=3, then proceed to Step 6; Step 3: Check if the register REG_STAGE_FLAG = 01. If not, disable the JTAG interface and reset the chip. If so, proceed to step 4; Step 4: Set gStage=debug stage and stage=2, then proceed to step 5; Step 5: Check the Stage 2 marker. If there is a marker, proceed to Step 6; if there is no marker, set gStage = test stage and stage = 1, then proceed to Step 6. Step 6: Determine if stage≥2 is satisfied. If not, proceed to step 8; if satisfied, proceed to step 7. Step 7: Recalculate the CRC value based on the parameters or data in the current stage OTP, and compare it with the CRC value in the injected stage 2 parameters to determine if they are consistent. If they are inconsistent, decrement stage by 1 and reset the chip; if they are consistent, proceed to the next step. Step 8: Determine if stage≥3 is satisfied. If not, proceed to step 10; if satisfied, proceed to step 9. Step 9: Recalculate the CRC value based on the parameters or data in the current stage OTP, and compare it with the CRC value in the injected stage 3 parameters to determine if they are consistent. If they are inconsistent, decrement stage by 1 and reset the chip; if they are consistent, proceed to the next step. Step 10: Determine if one of the following conditions is met: gStage = Test Stage and stage! = 1, gStage = Debug Stage and stage! = 2, gStage = Product Operation Stage and stage! = 3. If it is met, reset the chip; if none of the conditions are met, end the process and proceed to firmware download and startup. Specifically, the chip is not protected during the testing phase; the chip's OTP is locked in read-only mode during the debugging phase; and the chip's OTP is made unreadable and JTAG debugging is prohibited during the product operation phase, requiring firmware verification while maintaining the OTP read-only lock.

2. The sensitive information protection method as described in claim 1, characterized in that: During the testing and debugging phases, register REG_STAGE_FLAG = 01; during the product operation phase, register REG_STAGE_FLAG = 02.

3. The sensitive information protection method as described in claim 2, characterized in that: When upgrading from the testing phase to the debugging phase, the phase 2 flag is written into the chip's OTP, and gStage is set to debug phase and stage = 2.

4. The sensitive information protection method as described in claim 3, characterized in that: When transitioning from the debugging phase to the product operation phase, a stage 3 flag is written into the chip's OTP, and gStage is set to product operation phase and stage = 3.

5. The sensitive information protection method as described in claim 4, characterized in that: Set the value of the REG_STAGE_FLAG register to 02.

6. The sensitive information protection method as described in claim 5, characterized in that: During the debugging phase, an RSA public key is injected into the chip's OTP for downloading authentication and signing.

7. A chip comprising FLASH and OTP, characterized in that... The FLASH area stores a bootloader program for executing the sensitive information protection method according to any one of claims 1 to 6.

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