Vehicle-mounted chip calibration technology verification system and verification method

Abstract

The present application relates to a vehicle-mounted chip calibration technology verification system and a verification method, a SOC system verification environment is established based on a uvm universal verification methodology to simulate the real working environment of the vehicle-mounted chip during calibration, so that the verification of the calibration technology is more convincing, wherein the dynamic full random reference model created can enable verification engineers to meet the verification requirements without developing too many redundant directional use cases, and the functional coverage model created not only simplifies the verification process, but also comprehensively covers various possible combinations and boundary conditions of memory access between multiple cores and multiple memory blocks, and can simply and efficiently adapt to random mapping of any address, so that the verification is more efficient, comprehensive and accurate, and the quality and stability of the vehicle-mounted chip design are ensured.

Description

Technical Field

[0001] This invention belongs to the field of chip verification technology, and relates to a verification system and method for automotive chip calibration technology. Background Technology

[0002] In modern automotive intelligent systems, with the increasing complexity of chips, calibration technology, which can dynamically adjust parameters to optimize chip performance, has become one of the key technologies for automotive chips. Address remapping between inter-core memory (such as flash memory and SRAM (static random access memory)) is a commonly used technique in calibration design. Automotive chip calibration technology is a technique used to optimize and adjust the performance and parameters of automotive chips to achieve their best working state in specific vehicle environments and application scenarios.

[0003] Normally, program code is permanently burned into flash memory, and the CPU directly reads and executes the program code from flash memory. When code parameters need to be modified, the new program code must be burned into flash memory. However, with address remapping, a portion of the address space in flash memory can be dynamically mapped into SRAM. Since the contents of SRAM can be dynamically loaded and updated, the entire process of modifying code parameters does not require modification of flash memory, thus avoiding re-burning.

[0004] Therefore, accurate memory mapping management is crucial for the implementation of calibration technology. When data is exchanged between flash memory and SRAM, memory address remapping not only needs to handle dynamic allocation of different memory regions, but also must consider various combinations and boundary conditions of memory access across multiple memory blocks between multiple cores. However, traditional verification techniques often only cover conventional directional mapping cases, lacking sufficient verification capabilities for special boundary conditions, extreme memory combinations, and randomized address allocations, or they involve excessive redundancy in the verification process. Therefore, how to achieve efficient automotive chip calibration technology verification has become one of the technical problems to be solved. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a verification system and a verification method for automotive chip calibration technology, which can achieve efficient verification of automotive chip calibration technology.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On one hand, a verification system for automotive chip calibration technology is provided, including a top-level verification file created by the UVM general verification methodology. The top-level verification file is used to initialize the verification system, start test cases, and establish a SOC system verification environment. The verification system includes multiple Axi host agent components derived and instantiated based on base class test cases, and a system chip instantiated based on the design code of the automotive chip under test. Each Axi host agent component is used to create a SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host agent components corresponds to the number of cores. The Axi interface of each core is connected to the corresponding Axi host agent component through force syntax. The SOC system verification environment is connected to the system clock and reset signal. The driver and monitor of each Axi host agent component simulate the read and write operations initiated by the corresponding core as the host through the Axi interface drive signal.

[0008] The test cases call the initialization process function for address remapping established through registers in the base class test cases, configuring the enable switches of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; among them, a coverage model is created in the base class test cases to collect coverage of the initial address, memory block size, and memory boundary address of the memory block.

[0009] Test cases are used to call the proxy components of each AXI host to traverse each core, and random data is written to multiple memory blocks at the target address.

[0010] The test cases call the dynamic fully random reference model function for address remapping created in the SOC system verification environment, passing the target address, random data, and source address into the dynamic fully random reference model function.

[0011] After calculating the expected source address using the dynamic fully random reference model function, the expected source address is read through the axi interface to determine whether it is equal to the random data written to the target address.

[0012] If so, the test cases will call each AXI host proxy component to traverse each core until the set number of simulations is reached, at which point the simulation will end and the verification results will be output; otherwise, an error will be reported.

[0013] On the other hand, a verification method for automotive chip calibration technology is also provided, which is applied to a verification system for automotive chip calibration technology. The verification system includes a top-level verification file created by the UVM general verification methodology. The top-level verification file is used to initialize the verification system, start test cases, and the SOC system verification environment. The verification system includes multiple Axi host agent components derived and instantiated based on base class test cases, and a system chip instantiated based on the design code of the automotive chip under test. Each Axi host agent component is used to create a SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host agent components corresponds to the number of cores. The Axi interface of each core is connected to the corresponding Axi host agent component through force syntax. The SOC system verification environment is connected to the system clock and reset signal. The driver and monitor of each Axi host agent component simulate the read and write operations initiated by the corresponding core as the host through the Axi interface drive signal.

[0014] The verification method for the above-mentioned automotive chip calibration technology includes the following steps:

[0015] The test cases call the initialization process function for address remapping established through registers in the base class test cases, configuring the enable switches of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; among them, a coverage model is created in the base class test cases to collect coverage of the initial address, memory block size, and memory boundary address of the memory block.

[0016] Test cases are used to call the proxy components of each AXI host to traverse each core, and random data is written to multiple memory blocks at the target address.

[0017] The test cases call the dynamic fully random reference model function for address remapping created in the SOC system verification environment, passing the target address, random data, and source address into the dynamic fully random reference model function.

[0018] After calculating the expected source address using the dynamic fully random reference model function, the expected source address is read through the axi interface to determine whether it is equal to the random data written to the target address.

[0019] If so, the test cases will call each AXI host proxy component to traverse each core until the set number of simulations is reached, at which point the simulation will end and the verification results will be output; otherwise, an error will be reported.

[0020] One of the above technical solutions has the following advantages and beneficial effects:

[0021] The aforementioned verification system and method for automotive chip calibration technology establishes a SOC system verification environment based on the UVM general verification methodology to simulate the real working environment of the automotive chip during calibration, making the verification of the calibration technology more convincing. The created dynamic fully random reference model allows verification engineers to meet verification requirements without developing too many redundant directional test cases. Combined with the created functional coverage model, it not only simplifies the verification process but also comprehensively covers all possible combinations and boundary conditions of memory access between multiple memory blocks across multiple cores. Furthermore, it can easily and efficiently adapt to random mapping of arbitrary addresses, making the verification more efficient, comprehensive, and accurate, ensuring the quality and stability of the automotive chip design. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a structural block diagram of a verification system for vehicle-mounted chip calibration technology in one embodiment;

[0024] Figure 2 This is a schematic diagram illustrating the creation process of a verification system for vehicle-mounted chip calibration technology in one embodiment.

[0025] Figure 3 This is a schematic diagram illustrating the implementation principle of a dynamic fully random reference model in one embodiment;

[0026] Figure 4 This is a schematic diagram of the workflow of a verification system for vehicle-mounted chip calibration technology in one embodiment.

[0027] Figure 5 This is a flowchart illustrating a verification method for vehicle-mounted chip calibration technology in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0029] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in the specification and appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] In one embodiment, such as Figure 1 As shown, a verification system for automotive chip calibration technology is provided, including a top-level verification file created using the UVM general verification methodology. The top-level verification file is used to initialize the verification system, start test cases, and establish a SOC system verification environment. The verification system includes multiple Axi host agent components derived and instantiated based on base class test cases, and a system chip instantiated based on the design code of the automotive chip under test. Each Axi host agent component is used to create a SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host agent components corresponds to the number of cores. The Axi interface of each core is connected to the corresponding Axi host agent component through force syntax. The SOC system verification environment is connected to the system clock and reset signal. The driver and monitor of each Axi host agent component simulate the read and write operations initiated by the corresponding core as the host through the Axi interface drive signals.

[0032] The test cases invoke the address remapping initialization process function established via registers in the base class test cases. This configures the enable switches for each core, the initial address of the target address, the size of the memory block to be mapped, and the number of memory blocks to be opened. A coverage model is created in the base class test cases to collect coverage data for the initial address, memory block size, and memory boundary addresses of the memory blocks. The test cases then invoke each AXI host agent component to traverse each core, writing random data to multiple memory blocks at the target address. The test cases also invoke the dynamic fully random reference model function for address remapping created in the SOC system verification environment, passing the target address, random data, and source address to the dynamic fully random reference model function. After calculating the expected source address using the dynamic fully random reference model function, the expected source address is read through the AXI interface to determine if it equals the random data written to the target address. If so, the test cases invoke each AXI host agent component to traverse each core until the set number of simulations is reached, at which point the simulation ends and the verification result is output; otherwise, an error is reported.

[0033] It is understood that this embodiment utilizes the UVM general verification methodology to build a SOC system verification environment for automotive chips, develops a dynamic fully randomized verification reference model, and, in conjunction with the coverage model in the system, can comprehensively cover all possible combinations and boundary conditions of memory access to multiple memory blocks between multiple cores. Furthermore, it can easily and efficiently adapt to random mapping of arbitrary addresses. This not only significantly simplifies the development of targeted verification test cases but also improves the comprehensiveness and accuracy of verification, ensuring the quality and stability of automotive chip design and meeting the requirements of high-reliability and high-security automotive systems. The connection relationships between flash memory, SRAM, calibration modules, and multiple cores can be understood similarly to existing connection relationships in automotive chips in this field, and will not be elaborated upon further in this specification.

[0034] Specifically, such as Figure 2 As shown, the SOC system verification environment for the automotive chip is first established using the UVM general verification methodology. Figure 1As shown, the top-level verification file is used to initialize the entire verification system, start test cases, and establish the SOC system verification environment. This initialization process includes, but is not limited to, connecting the AXI (Advanced eXtensible Interface) interfaces of multiple cores (such as core 0, core 1, and core 2) of the SOC system chip in the vehicle chip to the top-level interface of the SOC system verification environment using force syntax. Then, the interfaces are connected to the corresponding AXI host agent components, and the system clock and reset signals are connected. The drivers and monitors of the AXI host agent components simulate read / write operations initiated by the corresponding core as the host using standard protocols (such as the AXI protocol) through the aforementioned AXI interface drive signals. Each corresponding AXI host agent component may include, for example, AXI host agent component 1 to AXI host agent component 3 derived from the base class test cases. Each AXI host agent component includes an AXI agent bus, a monitor, and a driver. The collaborative working principle of each module in the AXI host agent component can be understood similarly to the working principle of each module in the agent in the UVM general verification methodology, and is used to simulate the interactive functions required in this embodiment.

[0035] The `force` syntax is a statement in hardware description languages ​​(such as Verilog or VHDL) used to force signals to be assigned specific values. It can change the state of signals during simulation and is often used to apply special stimuli or constraints to signals in a design to verify the correctness of the design under various conditions. The SOC system verification environment is a software architecture used to functionally verify hardware designs. The top-level interface is the highest-level interface between the SOC system verification environment and the design being verified (such as a system-on-a-chip, especially its processor core). It defines the signal connections and communication protocols between the SOC system verification environment and the design being verified, serving as the channel for data transmission and interaction between them.

[0036] By connecting the AXI interfaces of each core to the top-level interface of the SOC system verification environment, a channel for data transmission and control signal interaction can be established between the cores and the environment. This allows the verification environment to send various stimulus signals, such as read / write requests and address information, to the cores, and to receive response signals, such as data outputs and status flags, from each core. This enables comprehensive verification of the calibration module's functionality. Using the `force` syntax to connect the interfaces allows for mandatory setting of signal values ​​on the AXI interfaces during verification, simulating various possible scenarios such as abnormal address access, data conflicts, or clock jitter. This tests the stability and correctness of each core under these extreme or special conditions, helping to identify potential problems and vulnerabilities in the design. Furthermore, it verifies the compatibility between the AXI interfaces of each core and the top-level interface of the SOC system verification environment, ensuring that they match in terms of signal levels, timing requirements, and protocol specifications. This guarantees the accuracy and reliability of data transmission, laying the foundation for the correct operation of the entire system.

[0037] In the base class test cases, instantiation and creation of constraint files such as memory address, core and memory block selection are completed. In the base class test cases, the initialization process function for address remapping is established through registers, including configuring the enable switches of the three cores, configuring the initial address of the target address (such as pfalsh and dflash), configuring the size of the memory block to be mapped, and configuring how many memory blocks to open.

[0038] In the SOC system verification environment, a dynamic fully random reference model function for address remapping was created, and a scoreboard component was added to compare the expected and actual test data. The implementation principle of the dynamic fully random reference model function is as follows: Figure 3 As shown, this dynamic fully random reference model function supports parameters such as target address, source address, and memory block size. It uses a foreach statement to iterate and evaluate addresses, then performs various address remapping checks. For example, if multiple cores access the same memory block simultaneously, the access is invalid. If it's a single-core access, when multiple memory blocks at the target address (flash) are mapped to the same source address (sram), the successfully mapped address when reading from that source address (sram) is the one with the higher target address block number. If it's a single-core access, when the same memory block at the target address (flash) is mapped to multiple source addresses (sram), reading from multiple source addresses (sram) will all map to the target address. If it's a single-core access and multiple memory blocks at the target address (flash) are completely nested, the remapped address is the larger target address - the smaller target address + the larger source address. If it's a single-core access and there's no overlap, when writing to a memory block at the target address, the remapped address is the memory block address corresponding to the source address (sram); otherwise, an error will occur.

[0039] Among them, there is a logical expression containing multiple conditions: target address A > B && the memory block size of target address A < B && the memory block boundary of A does not exceed B. The condition "target address A > B" means that the position of target address A in the memory address space is greater than target address B. The condition "the memory block size of target address A < B" refers to that the size of the memory block allocated to target address A is smaller than the size of the memory block allocated to target address B; the memory block size is a measurement unit such as the number of bytes of the continuous memory space allocated for storing data. This condition can be used to compare the capacity sizes of the memory regions corresponding to different addresses. The condition "the memory block boundary of A does not exceed B" means that the boundary of the memory block corresponding to target address A cannot exceed the range of the memory block corresponding to target address B; the memory block has a start address and an end address, forming a boundary range. This condition is to ensure that the memory block of A is completely contained within the memory block of B, or has a certain specific boundary relationship with the memory block of B, to prevent problems such as out-of-bounds memory access.

[0040] Among them, the foreach statement is a control structure existing in many programming languages, mainly used to traverse the elements in a collection or an array. The foreach statement will automatically iterate through each element in the collection or array, assign the current element to a specified variable, and then execute the code in the loop body. Each time it iterates, the variable will sequentially take each element in the collection until all elements are traversed.

[0041] Create a coverage model for the initial address, address block size, and memory boundary address of the address block in the base class test case, for collecting the coverage of the initial address, memory block size, and memory boundary address of the memory block, to further ensure comprehensive coverage and verification of various possible combinations and boundary cases of memory access to multiple memory blocks between multiple cores.

[0042] The above verification system for vehicle-mounted chip calibration technology establishes a verification environment for the SOC system based on the uvm general verification methodology to simulate the real working environment of the vehicle-mounted chip during calibration, making the verification of the calibration technology more persuasive. The created dynamic fully random reference model can enable verification engineers to meet the verification requirements without developing too many redundant directed test cases. Together with the created functional coverage model, it not only simplifies the verification process, but also can comprehensively cover various possible combinations and boundary cases of memory access to multiple memory blocks between multiple cores, and can simply and efficiently adapt to the random mapping of any address, making the verification more efficient, comprehensive, and accurate, and ensuring the quality and stability of the vehicle-mounted chip design.

[0043] In one embodiment, such as Figure 2As shown, a makefle file was also written, and the compilation tools, compilation macros, coverage collection items, etc. were selected. This makefle file is used to connect the file list of each digital module of the system chip and the file list of the SOC system verification environment. It can also be used to configure the automatic execution of test cases a specified number of times.

[0044] It is understandable that the verification system for the above-mentioned automotive chip calibration technology may also include a written makefle file. The makefle file is used to connect the file list of the design under test and the file list of the UVM verification environment. The makefle file includes compiler macros and coverage collection options.

[0045] It is understood that in this embodiment, a makefle file was also written and the corresponding compilation tool was selected to connect the file list of the design under test and the file list of the UVM verification environment. Compilation macros and coverage collection options were also added. Through this makefle file script, the test cases in the UVM verification environment can also be run automatically a specified number of times. The specific process of writing and running the makefle file script can be understood by referring to the relevant implementation process of existing makefle files in this field. It will not be elaborated in this specification.

[0046] In one embodiment, such as Figure 3 As shown, the Dynamic Fully Random Reference Model (DMR) function supports input parameters including target address, source address, and memory block size. After using a foreach statement to iterate through and compare the target and source addresses of multiple input memory blocks, the DMR function performs the following address remapping checks:

[0047] If it is determined that multiple cores are accessing the same memory block simultaneously, then the access is invalid.

[0048] When it is determined to be a single-core access, if there are two or more identical source addresses, after multiple target addresses are mapped to the same source address, an error will be reported if the source address is not the target address with the higher corresponding number.

[0049] When it is determined to be a single-core access, if there are two or more identical target addresses, and the same target address is mapped to multiple source addresses, an error will be reported if the data read from multiple source addresses is not the most recently written target address.

[0050] When it is determined to be a single-core access, if there are no overlapping memory blocks, an error will be reported if the data read from the source address of the memory block is not equal to the data at the corresponding target address.

[0051] When a single-core access is detected, if multiple memory blocks at the destination address are completely nested, the system reads the large target address (e.g., A) - the small target address (e.g., B) + the large source address (e.g., the source address corresponding to B). If the data written is not at the large target address (e.g., A), an error will be reported.

[0052] When a single-core access is detected, if multiple memory blocks at the destination address are partially nested, an error will occur if the source address of the memory block read is not equal to the corresponding destination address.

[0053] The dynamic fully random reference model can handle all combinations of memory block addresses, greatly simplifying the development of targeted test cases and improving verification efficiency.

[0054] In one embodiment, to more clearly and intuitively demonstrate the verification system for the aforementioned automotive chip calibration technology, such as... Figure 4 The diagram illustrates the operating principle of a SOC system verification environment. One example uses pflash as the target address, sram as the source address, and 16 configurable memory blocks.

[0055] After setting up the SOC system verification environment, the initialization process function is called. The initial memory address of the pflash boot remapping memory block 1 is 100_0000 and the memory block size is 64kb. The memory address of the pflash boot remapping memory block 2 is 100_4000 and the memory block size is 16kb with an offset address of 100. The initial memory address of the SRAM memory block 1 is 2100_0000 and the memory address of the SRAM memory block 2 is 2100_8000. Then, the system iterates through the 16 memory blocks of the three cores, writing data to memory blocks 1 and 2 of the pflash via the AXI bus function. If the data is 100_0100 and 100_4100 respectively, the dynamic fully random reference model determines that the address is fully covered based on the traversal result. At this point, the system reads the data at the initial address + offset address of memory block 2 in the SRAM, which is 2100_8100. If the data matches the address written to memory block 2 in the corresponding flash memory, an error is reported. If the data does not match the address 100_4100-100_0000+2100_0000 calculated by the dynamic fully random reference model, an error is reported.

[0056] Each component in the aforementioned verification system for vehicle-mounted chip calibration technology can be implemented entirely or partially through software, hardware, or a combination thereof. These components can be embedded in hardware or independently of a device with data processing capabilities, or stored in software within the memory of the aforementioned device, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of chip verification computers already existing in the art.

[0057] In one embodiment, a verification method for automotive chip calibration technology is provided, applied to a verification system for automotive chip calibration technology. The verification system includes a top-level verification file created using the UVM general verification methodology. The top-level verification file is used to initialize the verification system, start test cases, and establish a SOC system verification environment. The verification system includes multiple Axi host agent components derived and instantiated based on base class test cases, and a system chip instantiated based on the design code of the automotive chip under test. Each Axi host agent component is used to create a SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host agent components corresponds to the number of cores. The Axi interface of each core is connected to the corresponding Axi host agent component through force syntax. The SOC system verification environment is connected to a system clock and a reset signal. The driver and monitor of each Axi host agent component simulate read and write operations initiated by the corresponding core as the host through Axi interface drive signals.

[0058] like Figure 5 As shown, the verification method for automotive chip calibration technology includes the following steps S10 to S18:

[0059] S10: The test case calls the initialization process function for address remapping established through registers in the base class test case, configuring the enable switch of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; among them, a coverage model is created in the base class test case to collect the coverage of the initial address of the memory block, the size of the memory block, and the memory boundary address.

[0060] S12, through test cases, call each axi host proxy component to traverse each core, and write random data to multiple memory blocks at the target address;

[0061] S14, through the test case, call the dynamic fully random reference model function for address remapping created in the SOC system verification environment, and pass the target address, random data and source address into the dynamic fully random reference model function;

[0062] S16, after calculating the expected source address through the dynamic fully random reference model function, read the expected source address through the axi interface and determine whether it is equal to the random data written to the target address;

[0063] S18, if yes, then call each AXI host agent component through the test cases to traverse each core until the set number of simulations is reached, then end the simulation and output the verification result; otherwise, report an error.

[0064] The aforementioned verification method for automotive chip calibration technology establishes a SOC system verification environment based on the UVM general verification methodology to simulate the real working environment of the automotive chip during calibration, making the verification of the calibration technology more convincing. The created dynamic fully random reference model allows verification engineers to meet verification requirements without developing too many redundant targeted test cases. Combined with the created functional coverage model, it not only simplifies the verification process but also comprehensively covers all possible combinations and boundary conditions of memory access between multiple memory blocks across multiple cores. Furthermore, it can easily and efficiently adapt to random mapping of arbitrary addresses, making the verification more efficient, comprehensive, and accurate, ensuring the quality and stability of the automotive chip design.

[0065] In one embodiment, a makefle file is written, which includes compiler macros and coverage collection options; the makefle file is used to link the file lists of the various digital modules of the system chip and the file list of the SOC system verification environment.

[0066] In one embodiment, the dynamic fully random reference model function supports input parameters including target address, source address, and memory block size. After using a foreach statement to iterate and determine the target and source addresses of multiple input memory blocks, the dynamic fully random reference model function performs the following address remapping checks:

[0067] If it is determined that multiple cores are accessing the same memory block simultaneously, then the access is invalid.

[0068] When it is determined to be a single-core access, if there are two or more identical source addresses, after multiple target addresses are mapped to the same source address, an error will be reported if the source address is not the target address with the higher corresponding number.

[0069] When it is determined to be a single-core access, if there are two or more identical target addresses, and the same target address is mapped to multiple source addresses, an error will be reported if the data read from multiple source addresses is not the most recently written target address.

[0070] When it is determined to be a single-core access, if there are no overlapping memory blocks, an error will be reported if the data read from the source address of the memory block is not equal to the data at the corresponding target address.

[0071] When it is determined to be a single-core access, if there are multiple completely nested memory blocks at the destination address, then read the large target address - the small target address + the large source address. If the data written is not at the large target address, an error will be reported.

[0072] When a single-core access is detected, if multiple memory blocks at the destination address are partially nested, an error will occur if the source address of the memory block read is not equal to the corresponding destination address.

[0073] For specific limitations on the verification methods of automotive chip calibration technology, please refer to the corresponding limitations of the verification system for automotive chip calibration technology mentioned above, which will not be repeated here.

[0074] It should be understood that, although Figure 5 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 5 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0075] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A verification system for automotive chip calibration technology, characterized in that, The system includes a top-level verification file created using the UVM general verification methodology. This top-level verification file is used to initialize the verification system, start test cases, and establish the SOC system verification environment. The verification system includes multiple Axi host agent components derived and instantiated from base class test cases, and a system chip instantiated from the design code of the automotive chip under test. Each Axi host agent component is used to create the SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host agent components corresponds to the number of cores. The Axi interface of each core is connected to its corresponding Axi host agent component via force syntax. The SOC system verification environment is connected to a system clock and a reset signal. The drivers and monitors of each Axi host agent component simulate read and write operations initiated by the corresponding core as the host through the Axi interface drive signals. The test case calls the initialization process function for address remapping established through registers in the base class test case, configures the enable switch of each core, configures the initial address of the target address, configures the size of the memory block to be mapped, and configures the number of memory blocks to be opened; wherein, a coverage model is created in the base class test case to collect the coverage of the initial address, memory block size, and memory boundary address of the memory block; The test case calls each of the aforementioned AXI host proxy components to traverse each of the aforementioned cores, instructing each of the aforementioned AXI host proxy components to write the random data generated by the test case into multiple memory blocks at the target address according to the AXI protocol; The test case calls the dynamic fully random reference model function for address remapping created in the SOC system verification environment, and passes the target address, random data and source address to the dynamic fully random reference model function. After the dynamic fully random reference model function calculates the expected source address, it reads the expected source address through the axi interface and determines whether it is equal to the random data written to the target address. If so, the test case calls each of the aforementioned AXI host proxy components to traverse each of the aforementioned cores until the set number of simulations is reached, then the simulation ends and the verification result is output; otherwise, an error is reported.

2. The verification system for vehicle-mounted chip calibration technology according to claim 1, characterized in that, It also includes a written makefle file, which is used to link the list of various digital module files of the system chip and the list of files of the SOC system verification environment. The makefle file includes compiler macros and coverage collection options.

3. The verification system for vehicle-mounted chip calibration technology according to claim 1 or 2, characterized in that, The dynamic fully random reference model function supports input parameters including target address, source address, and memory block size. After using a foreach statement to iterate and determine the target and source addresses of multiple input memory blocks, the function performs the following address remapping checks: If it is determined that multiple cores are accessing the same memory block simultaneously, then the access is invalid. When it is determined to be a single-core access, if there are two or more identical source addresses, after multiple target addresses are mapped to the same source address, an error will be reported if the source address is not the target address with the higher corresponding number. When it is determined to be a single-core access, if there are two or more identical target addresses, and the same target address is mapped to multiple source addresses, an error will be reported if the data read from multiple source addresses is not the most recently written target address. When it is determined to be a single-core access, if there are no overlapping memory blocks, an error will be reported if the data read from the source address of the memory block is not equal to the data at the corresponding target address. When it is determined to be a single-core access, if there are multiple completely nested memory blocks at the destination address, then read the large target address - the small target address + the large source address. If the data written is not at the large target address, an error will be reported. When a single-core access is detected, if multiple memory blocks at the destination address are partially nested, an error will occur if the source address of the memory block read is not equal to the corresponding destination address.

4. A verification method for automotive chip calibration technology, characterized in that, A verification system for automotive chip calibration technology is provided. The verification system includes a top-level verification file created using the UVM general verification methodology. This top-level file is used to initialize the verification system, start test cases, and establish a System-on-Chip (SOC) system verification environment. The verification system includes multiple Axi host proxy components derived and instantiated from base class test cases, and a system chip instantiated from the design code of the automotive chip under test. Each Axi host proxy component is used to create the SOC system verification environment for the system chip. The system chip includes flash memory, SRAM, a calibration module, and multiple cores. The number of Axi host proxy components corresponds to the number of cores. The Axi interface of each core is connected to its corresponding Axi host proxy component via force syntax. The SOC system verification environment is connected to a system clock and a reset signal. The drivers and monitors of each Axi host proxy component simulate read / write operations initiated by the corresponding core as the host through the Axi interface drive signals. The verification method for the vehicle-mounted chip calibration technology includes the following steps: The test cases call the initialization process function for address remapping established through registers in the base class test cases, configuring the enable switch of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; wherein, a coverage model is created in the base class test cases to collect coverage of the initial address, memory block size, and memory boundary address of the memory block. The test cases call each of the axi host proxy components to traverse each of the cores, and instruct each of the axi host proxy components to write the random data generated by the test cases into multiple memory blocks at the target address according to the axi protocol; The test case calls the dynamic fully random reference model function for address remapping created in the SOC system verification environment, and passes the target address, random data and source address into the dynamic fully random reference model function. After calculating the expected source address using the dynamic fully random reference model function, the expected source address is read through the axi interface and it is determined whether it is equal to the random data written to the target address. If so, the test cases will be used to call each of the aforementioned AXI host proxy components to traverse each of the aforementioned cores until the set number of simulations is reached, at which point the simulation will end and the verification results will be output; otherwise, an error will be reported.

5. The verification method for vehicle-mounted chip calibration technology according to claim 4, characterized in that, Also includes: Write a makefle file, adding compiler macros and coverage collection options; The makefle file is used to link the file list of each digital module of the system chip and the file list of the SOC system verification environment.

6. The verification method for vehicle-mounted chip calibration technology according to claim 4 or 5, characterized in that, The dynamic fully random reference model function supports input parameters including target address, source address, and memory block size. After using a foreach statement to iterate and determine the target and source addresses of multiple input memory blocks, the function performs the following address remapping checks: If it is determined that multiple cores are accessing the same memory block simultaneously, then the access is invalid. When it is determined to be a single-core access, if there are two or more identical source addresses, after multiple target addresses are mapped to the same source address, an error will be reported if the source address is not the target address with the higher corresponding number. When it is determined to be a single-core access, if there are two or more identical target addresses, and the same target address is mapped to multiple source addresses, an error will be reported if the data read from multiple source addresses is not the most recently written target address. When it is determined to be a single-core access, if there are no overlapping memory blocks, an error will be reported if the data read from the source address of the memory block is not equal to the data at the corresponding target address. When it is determined to be a single-core access, if there are multiple completely nested memory blocks at the destination address, then read the large target address - the small target address + the large source address. If the data written is not at the large target address, an error will be reported. When a single-core access is detected, if multiple memory blocks at the destination address are partially nested, an error will occur if the source address of the memory block read is not equal to the corresponding destination address.

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