Equivalent model circuit of memory inductor

Abstract

The invention discloses a memory inductor equivalent model circuit, which belongs to the technical field of circuit design and is formed by cascading a Vi variable quantum circuit, a phi variable quantum circuit, a-rho variable quantum circuit and a Vo variable quantum circuit. The Vi variable quantum circuit is connected with the Vo variable quantum circuit through a port Vo; the phi variable quantum circuit is connected with the Vi variable quantum circuit through a port Vi; the-rho variable quantum circuit is connected with the phi variable quantum circuit through a port phi; the Vo variable quantum circuit is connected with the Vi variable quantum circuit through a port Vi, is connected with the phi variable quantum circuit through a port phi, and is connected with the-rho variable quantum circuit through a port-rho. The circuit model is clear and simple in structure and easy to realize, and is of great significance to design and research of the equivalent model circuit of the memory inductor.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and relates to a memory element model equivalent circuit structure, and specifically to the design and implementation of a physically realizable memsensor equivalent model with hysteresis curve characteristics. Background Art

[0002] In 1971, Professor Cai predicted and first proposed the fourth basic circuit element, the memristor, based on the completeness of the circuit, alongside resistors, capacitors and inductors. This innovative discovery opened up a new direction for building systems based on traditional circuits. The construction of system circuits will no longer be limited to traditional elements such as resistors, inductors and capacitors. In December 2008, at the "Memristor and Memristor System Seminar" held at the University of Berkeley, Professor Cai Shaotang once again pointed out that elements with memory characteristics should not be limited to memristors, but should also be extended to memristors and memristors. At the same time, he pointed out that although memristors and memristors are also memory devices, they are different from memristors in that they are energy storage elements. In 2009, he used the following two new variables s and r , extending the elements with memory characteristics from memristors to memristor systems, thus making the memory elements form a complete system like traditional circuit elements.

[0003] In the existing memory element system, some use chemical preparation to make memristors in memory elements, while others use equivalent replacement circuits to realize memory elements. Among them, the equivalent model of memristors has been relatively complete, but due to the particularity of the intrinsic variables of memristors and memcapacitors, there are still some deficiencies in the construction of equivalent circuits. Therefore, it is of great significance to design memristor models and build corresponding equivalent circuits. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention proposes a memsensor model equivalent circuit.

[0005] The technical solution adopted by the present invention to solve the technical problem is as follows: The device used in the present invention includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 11th resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 16th resistor R 16 17th resistor R 17, Eighteenth resistor R 18 , 19th resistor R 19 , a first capacitor C1, a second capacitor C2, a first diode D1, a second diode D2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8, a first signal source V1, and a second signal source V2. The memristor model is composed of V i Variable subcircuit, f Variable subcircuit, - r Variable subcircuit, V o It is composed of cascaded variable sub-circuits.

[0006] Said V i Variable subcircuit through port V o and V o The first operational amplifier U1 same-direction input terminal is used as the signal input port A, and the reverse input terminal is connected to its output terminal as the port V i ; One end of the first resistor R1 is connected to the input port V o The other end is connected to the non-inverting input end of the first operational amplifier U1.

[0007] Said f Variable subcircuit through port V i and V i The second operational amplifier U2 is connected to the variable sub-circuit; the same-direction input terminal is grounded, the reverse input terminal is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the input port V i One end of the third resistor R3 is connected to the reverse input terminal of the second operational amplifier U2, and the other end is connected to the output of the second operational amplifier U2 as a port - f The first capacitor C1 is connected in parallel with the third resistor R3; one end of the fourth resistor R4 is connected to the output end of the second operational amplifier U2, and the other end is connected to the reverse input end of the third operational amplifier U3; one end of the fifth resistor R5 is connected to the reverse input end of the third operational amplifier U3, and the other end is connected to the output end of the third operational amplifier U3 and serves as an output port f ; The same-direction input terminal of the third operational amplifier U3 is grounded.

[0008] Said- r Variable subcircuit through port f and f The variable subcircuit is connected; one end of the sixth resistor R6 is connected to the input port f The seventh resistor R7 is connected to the inverting input terminal of the fourth operational amplifier U4 and the inverting input terminal of the fifth operational amplifier U5, and the other end is connected to the input port f The eighth resistor R8 is connected at one end to the same-direction input terminal of the fifth operational amplifier U5, and the other end is connected to the ground; the ninth resistor R9 is connected at one end to the reverse input terminal of the fourth operational amplifier U4, and the other end is connected to the negative end of the second diode D2; the negative end of the first diode D1 is connected to the same-direction input terminal of the fourth operational amplifier U4, and the positive end is connected to the output terminal of the fifth operational amplifier U5; the positive end of the second diode D2 is connected to the output terminal of the fourth operational amplifier U4, and the negative end is connected to the ninth resistor R9; the tenth resistor R 10 One end is connected to the negative end of the second diode D2 as port | f |, the other end is connected to the inverting input terminal of the sixth operational amplifier; the eleventh resistor R 11 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the positive end of the DC current source V1; the twelfth resistor R 12 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the output end of the sixth operational amplifier U6 as an output port - r The second capacitor C2 and the twelfth resistor R 12 In parallel, the non-inverting input terminal of the sixth operational amplifier U6 is grounded.

[0009] Said V o Variable subcircuit through port V i and V i The variable subcircuits are connected through ports f and f The variable subcircuits are connected through ports- r and- r The variable sub-circuit is connected; the thirteenth resistor R 13 One end is connected to the inverting input terminal of the seventh operational amplifier U7, and the other end is connected to the input port V i The fourteenth resistor R 14 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the reverse input end of the seventh operational amplifier U7; the same-direction input end of the seventh operational amplifier U7 is grounded; the fifteenth resistor R 15One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the reverse input end of the eighth operational amplifier U8; the sixteenth resistor R 16 One end and input port f The other end is connected to the inverting input terminal of the eighth operational amplifier U8; the seventeenth resistor R 17 One end and input port - r The other end is connected to the inverting input end of the eighth operational amplifier U8; the eighteenth resistor R 18 One end is connected to the inverting input end of the eighth operational amplifier U8, and the other end is connected to the positive electrode of the DC voltage source V2; the nineteenth resistor R 19 One end is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the eighth operational amplifier U8 as an output port V o ; The same-direction input terminal of the eighth operational amplifier U8 is grounded.

[0010] The present invention has the following characteristics and beneficial effects: The above technical solution has a simple structure, uses fewer types of devices, and does not involve various integrated modules and complex calculation modules, which greatly reduces the complexity and cost of the circuit. The circuit model structure is clear and simple, easy to implement, and has great significance for the design and research of the equivalent model circuit of the memristor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of the present invention; Figure 2 is the equivalent model of the memristor of the present invention V i Circuit diagram of the variable; Figure 3 is the equivalent model of the memristor of the present invention f Circuit diagram of the variable; Figure 4 is the equivalent model of the memristor of the present invention - r Circuit diagram of the variable; Figure 5 is the equivalent model of the memristor of the present invention V o Circuit diagram of the variable; Figure 6 is the equivalent model of the memristor of the present invention f ( t )and i ( t ) Timing diagram; Figure 7 is the equivalent model of the memristor of the present invention f - i variable phase diagram; Figure 8 The equivalent hardware circuit of the memory sensor of the present invention is f ( t )and i ( t ) Timing diagram; Figure 9 The equivalent hardware circuit of the memory sensor of the present invention is f - i Variable phase diagram. DETAILED DESCRIPTION

[0012] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0013] The mathematical expression based on the memristor equivalent model circuit designed by the present invention is shown in formula (1): (1) in f , i are represented as the magnetic flux and current of the memristor respectively. They are the constitutive variables of the memristor and represent the input and output of the system. r pass f Integrate to get, In addition, in the above expression, the parameters are set as a =-1 / 10, b =5 / 3, c =0.5 and d =2.57. Magnetic flux f It can be obtained by integrating the input voltage.

[0014] The memristor equivalent model circuit designed by the present invention is composed of four sub-circuits connected in cascade. Figure 1 As shown, A The port is the signal input port of the memristor equivalent model. A Terminal input voltage V in , and the feedback output voltage V o Through the operational amplifier U 1 The additive voltage follower circuit is constructed to obtain the variable V i In the next stage, the second resistor R 2. The third resistor R 3. The first capacitor C 1 and the second operational amplifier U 2 composed of reverse integration circuit, its input is V i , through the second operational amplifier U After the integral operation of 2, a negative magnetic flux (- f ). The third operational amplifierU 3. The fourth resistor R 4 and 5th resistor R 5 constitutes a reverse proportional operation circuit, which f Perform calculations to obtain f In order to perform absolute value operation on the flux signal, in the next stage, the fourth operational amplifier U 4. Fifth operational amplifier U 5 and the sixth operational amplifier U 6. The first diode D 1 and the second diode D 2. The sixth resistor R 6. Seventh resistor R 7. Eighth resistor R 8 and 9 resistors R 9 forms an absolute value operation circuit. When the input is f When Similarly, the sixth operational amplifier U 6. Tenth resistor R 10 11th resistor R 11 and the twelfth resistor R 12 , the second capacitor C 2. First signal source V The reverse addition and integration circuit composed of 1 can obtain the variable - r Next, - r , V i , f and the second signal source V 2 Through the seventh operational amplifier U7 and the eighth operational amplifier U8, the thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 16th resistor R 16 17th resistor R 17 , Eighteenth resistor R 18 and the nineteenth resistor R 19 The reverse addition circuit composed of the memristor output voltage is added V o , finally, the output voltage V o Through the first resistor R 1Convert the voltage into current, and you can get the current flowing through the memristor i .

[0015] like Figure 2 As shown, Vi In the variable subcircuit, the first operational amplifier U1 non-inverting input terminal is used as the signal input port A , the reverse input end is connected to its output end as a port V i ; One end of the first resistor R1 and the input port V o The other end is connected to the non-inverting input end of the first operational amplifier U1.

[0016] like Figure 3 As shown, f In the variable subcircuit, the same-direction input terminal of the second operational amplifier U2 is grounded, the reverse input terminal is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the input port V i One end of the third resistor R3 is connected to the reverse input terminal of the second operational amplifier U2, and the other end is connected to the output of the second operational amplifier U2 as a port - f The first capacitor C1 is connected in parallel with the third resistor R3; one end of the fourth resistor R4 is connected to the output end of the second operational amplifier U2, and the other end is connected to the reverse input end of the third operational amplifier U3; one end of the fifth resistor R5 is connected to the reverse input end of the third operational amplifier U3, and the other end is connected to the output end of the third operational amplifier U3 and serves as an output port f ; The non-inverting input terminal of the third operational amplifier U3 is grounded.

[0017] like Figure 4 As shown, described - r In the variable subcircuit, one end of the sixth resistor R6 is connected to the input port f One end of the seventh resistor R7 is connected to the same-direction input terminal of the fourth operational amplifier U4 and the reverse input terminal of the fifth operational amplifier U5, and the other end is connected to the input port f One end of the eighth resistor R8 is connected to the same-direction input terminal of the fifth operational amplifier U5, and the other end is connected to the ground; one end of the ninth resistor R9 is connected to the reverse input terminal of the fourth operational amplifier U4, and the other end is connected to the negative end of the second diode D2; the negative end of the first diode D1 is connected to the same-direction input terminal of the fourth operational amplifier U4, and the positive end is connected to the output terminal of the fifth operational amplifier U5; the positive end of the second diode D2 is connected to the output terminal of the fourth operational amplifier U4, and the negative end is connected to the ninth resistor R9; the tenth resistor R 10 One end is connected to the negative end of the second diode D2 as port | f |, the other end is connected to the inverting input terminal of the sixth operational amplifier; the eleventh resistor R 11 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the positive end of the DC current source V1; the twelfth resistor R 12One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the output end of the sixth operational amplifier U6 as an output port - r ; The second capacitor C2 and the twelfth resistor R 12 In parallel, the same-direction input terminal of the sixth operational amplifier U6 is grounded.

[0018] like Figure 5 As shown, V o In the variable subcircuit, the thirteenth resistor R 13 One end is connected to the inverting input terminal of the seventh operational amplifier U7, and the other end is connected to the input port V i Connected; fourteenth resistor R 14 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the seventh operational amplifier U7; the same-inverting input end of the seventh operational amplifier U7 is grounded; the fifteenth resistor R 15 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the eighth operational amplifier U8; a sixteenth resistor R 16 One end and input port f The other end is connected to the inverting input terminal of the eighth operational amplifier U8; the seventeenth resistor R 17 One end and input port - r The other end is connected to the inverting input terminal of the eighth operational amplifier U8; the eighteenth resistor R 18 One end is connected to the inverting input terminal of the eighth operational amplifier U8, and the other end is connected to the positive electrode of the DC voltage source V2; the nineteenth resistor R 19 One end is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the eighth operational amplifier U8 as an output port V o ; The same-direction input terminal of the eighth operational amplifier U8 is grounded.

[0019] In order to verify the effectiveness of the memristor circuit model, the circuit was built in Multisim simulation software and magnetic flux excitation was applied to the circuit model. f ( t )= f 0cos(2π feet )( f 0=4V, f =100Hz). Figure 6 Shown f ( t )and i ( t )’s timing relationship, Figure 7 Shown f - iThe phase relationship between the variables shows the hysteresis curve waveform between the constitutive variables unique to the memristor circuit, indicating that it conforms to the definition of the memristor equivalent model. Furthermore, according to the memristor equivalent subcircuit structure and component parameters, a hardware circuit was built to further prove its feasibility and effectiveness. In the hardware circuit, the operational amplifier uses OP07C (U1 to U8) and its operating voltage is set to ±15V, the diode uses 1N4007 (D1 and D2), and the parameters of the remaining circuit components and DC voltage sources (V1 and V2) are consistent with the values ​​set in the subcircuit diagram. Figure 8 Shown f ( t )and i ( t ), Figure 9 Shown f - i The phase relationship between variables. The hardware circuit test results, simulation circuit results and theoretical analysis results are consistent, which fully verifies the feasibility and effectiveness of the memristor model circuit of the present invention.

[0020] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments including components are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A memristor equivalent model circuit, characterized in that: By V i Variable subcircuit, φ variable subcircuit, -ρ variable subcircuit, V o It is composed of variable subcircuits cascaded; The V i The variable subcircuit passes through port V o With V o The variable subcircuit is connected; the φ variable subcircuit is connected through the port V i With V i The -ρ variable subcircuit is connected to the φ variable subcircuit through the port φ; the V o The variable subcircuit passes through port V i With V i The variable subcircuit is connected to the φ variable subcircuit through the port φ, and is connected to the -ρ variable subcircuit through the port -ρ.

2. A memristor equivalent model circuit according to claim 1, characterized in that: The V i In the variable subcircuit, the first operational amplifier U1 has a non-inverting input terminal as a signal input port A, and a reverse input terminal connected to its output terminal as a port V i ; One end of the first resistor R1 is connected to the input port V o The other end is connected to the non-inverting input end of the first operational amplifier U1.

3. A memristor equivalent model circuit according to claim 2, characterized in that: In the φ variable subcircuit, the same-direction input terminal of the second operational amplifier U2 is grounded, the reverse input terminal is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the input port V i connected; one end of the third resistor R3 is connected to the reverse input terminal of the second operational amplifier U2, and the other end is connected to the output of the second operational amplifier U2 as port -φ; the first capacitor C1 is connected in parallel with the third resistor R3; one end of the fourth resistor R4 is connected to the output terminal of the second operational amplifier U2, and the other end is connected to the reverse input terminal of the third operational amplifier U3; one end of the fifth resistor R5 is connected to the reverse input terminal of the third operational amplifier U3, and the other end is connected to the output terminal of the third operational amplifier U3 and serves as the output port φ; the same-direction input terminal of the third operational amplifier U3 is grounded.

4. The memristor equivalent model circuit according to claim 3, characterized in that: In the -ρ variable sub-circuit, one end of the sixth resistor R6 is connected to the input port φ, and the other end is connected to the reverse input terminal of the fourth operational amplifier U4; one end of the seventh resistor R7 is connected to the non-inverting input terminal of the fourth operational amplifier U4 and the reverse input terminal of the fifth operational amplifier U5, and the other end is connected to the input port φ; one end of the eighth resistor R8 is connected to the non-inverting input terminal of the fifth operational amplifier U5, and the other end is connected to the ground; one end of the ninth resistor R9 is connected to the reverse input terminal of the fourth operational amplifier U4, and the other end is connected to the negative end of the second diode D2; the negative end of the first diode D1 is connected to the non-inverting input terminal of the fourth operational amplifier U4, and the positive end is connected to the output terminal of the fifth operational amplifier U5; the positive end of the second diode D2 is connected to the output terminal of the fourth operational amplifier U4, and the negative end is connected to the ninth resistor R9; the tenth resistor R 10 One end is connected to the negative end of the second diode D2 as the port |φ|, and the other end is connected to the reverse input end of the sixth operational amplifier; the eleventh resistor R 11 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the positive end of the DC current source V1; the twelfth resistor R 12 One end is connected to the inverting input end of the sixth operational amplifier U6, and the other end is connected to the output end of the sixth operational amplifier U6 as the output port -ρ; the second capacitor C2 is connected to the twelfth resistor R 12 In parallel, the same-direction input terminal of the sixth operational amplifier U6 is grounded.

5. The memristor equivalent model circuit according to claim 4, characterized in that: The V o In the variable subcircuit, the thirteenth resistor R 13 One end is connected to the inverting input terminal of the seventh operational amplifier U7, and the other end is connected to the input port V i Connected; fourteenth resistor R 14 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the seventh operational amplifier U7; the same-inverting input end of the seventh operational amplifier U7 is grounded; the fifteenth resistor R 15 One end is connected to the output end of the seventh operational amplifier U7, and the other end is connected to the inverting input end of the eighth operational amplifier U8; a sixteenth resistor R 16 One end is connected to the input port φ, and the other end is connected to the inverting input terminal of the eighth operational amplifier U8; the seventeenth resistor R 17 One end is connected to the input port -ρ, and the other end is connected to the inverting input terminal of the eighth operational amplifier U8; the eighteenth resistor R 18 One end is connected to the inverting input terminal of the eighth operational amplifier U8, and the other end is connected to the positive electrode of the DC voltage source V2; the nineteenth resistor R 19 One end is connected to the inverting input terminal of the operational amplifier U8, and the other end is connected to the output terminal of the eighth operational amplifier U8 as the output port V o ; The same-direction input terminal of the eighth operational amplifier U8 is grounded.

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