Transistor-level delay optimization method and system based on circuit topological structure

Abstract

The invention discloses a transistor-level delay optimization method and system based on a circuit topological structure. The method comprises the following steps: acquiring all units on a time sequence path to be optimized; performing transistor-level delay optimization on each unit to obtain a time sequence path after delay optimization; simulation is carried out on the time sequence path after time delay optimization to obtain optimized path time delay, n units with the maximum change relative to the original time sequence path time delay are selected in the path time delay to serve as n time delay sensitive units, and n is smaller than or equal to N; and redrawing the layout according to the modification corresponding to the delay optimization for the selected n delay sensitive units. The invention aims to solve the problem that the size of a delay sensitive unit on a path and the size of a transistor needing to be optimized in the unit are difficult to determine during path delay optimization of an integrated circuit, and transistor-level delay optimization based on a circuit topological structure is realized so as to quickly and efficiently optimize path delay.

Description

Technical Field

[0001] The invention relates to the field of very large scale integrated circuit timing optimization, and in particular to a transistor-level delay optimization method and system based on circuit topology structure. Background Art

[0002] With the rapid development of integrated circuit technology, the complexity of circuit design is increasing day by day, and the delay optimization of transistor-level paths has become an important task to improve circuit performance. The introduction of standard cells facilitates the design of circuits, but there is still a lot of room for optimization of the delay of specific circuits. Compared with full customization, which consumes a lot of human resources and time, partial full customization that only changes the delay-sensitive cells on the path will be more effective. There have been many achievements in the research of transistor-level path delay optimization, which can be mainly divided into two categories: optimization based on logic reorganization and optimization based on physical design. The former reduces delay by changing the logical structure of the circuit, while the latter optimizes the signal propagation path by adjusting the layout and routing. In order to meet the growing performance requirements, designers must effectively optimize the transistor-level paths. However, traditional methods for optimizing transistor-level paths often rely on the experience of designers and it is difficult to make full use of the topological structure information of the circuit. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a transistor-level delay optimization method and system based on circuit topology structure are provided. The present invention aims to solve the problem that it is difficult to determine the delay-sensitive units on the path and the size of the transistors that need to be optimized in the units when optimizing the path delay of an integrated circuit, and to realize transistor-level delay optimization based on circuit topology structure to quickly and efficiently optimize the path delay.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A transistor-level delay optimization method based on circuit topology structure comprises the following steps: 1) Obtain all N units on the timing path to be optimized; 2) Perform transistor-level delay optimization on each unit to obtain the timing path after delay optimization; 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N; 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization.

[0005] Optionally, step 2) includes: 2.1) Traverse N units to obtain a unit as the current unit. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the timing path after delay optimization has been obtained, and jump to step 3); 2.2) Find and calculate the number of gates gate_num of each transistor in the current unit, the number of fins Fin of each gate nfin and the total number of fins Fin all_fin_num; 2.3) Based on the number of gates gate_num in each transistor in the current unit, the number of fins Fin in each gate nfin and the total number of fins Fin all_fin_num, the number of gates in the transistor in the current unit is modified according to the unit type and circuit structure to achieve transistor-level delay optimization, and then jump to step 2.1).

[0006] Optionally, step 2.2) includes: 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell, if the reading is successful, jump to step 2.2.2), otherwise jump to step 2.2.3); 2.2.2) If the five elements of the input terminal, output terminal, source or drain, N or P type, and the number of fins in the read row content cell_line are consistent with the transistor to be found, then the number of fins Fin read in the row content cell_line is the number of fins Fin per gate nfin; jump to step 2.2.1); 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates gate_num of the transistor to be searched in the current unit, multiply the number of fins Fin per gate nfin by the number of gates gate_num of each transistor in the current unit to obtain the total number of fins Fin in each transistor all_fin_num; jump to step 2.3).

[0007] Optionally, step 2.3) includes: 2.3.1A) Get the preset number of gates add_gate_num to be added to the transistors on the pull-up or pull-down path through which the current in the current unit passes; 2.3.2A) Determine the number of fins Fin to be added need_add_num according to the number of gates add_gate_num of transistors on the pull-up or pull-down path through which the current in the current unit passes and the number of fins Fin per gate nfin; 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A); otherwise, jump to step 4); 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.5A), otherwise jump to step 4); 2.3.5A) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.6A), otherwise jump to step 2.3.4A) to continue reading the next row; 2.3.6A) Read the number of fins Fin in the row content cell_line. If the number of fins Fin in the row content cell_line plus the number of fins Fin to be added need_add_num is less than or equal to the preset maximum number of fins Fin that can be added to a gate max_fin_num, then modify the number of fins Fin in a gate in the row content cell_line representing the information of a gate nfin to the sum of the original number of fins Fin in a gate nfin plus the total number of fins Fin all_fin_num, and then set the number of fins Fin to be added need_add_num to 0; otherwise, modify the number of fins Fin in a gate in the row content cell_line to max_fin_num, and update the number of fins Fin to be added need_add_num according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

[0008] Optionally, the function expression for determining the number of fins Fin to be added need_add_num in step 2.3.2A) is: need_add_num=add_gate_num*nfin In the above formula, add_gate_num is the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the current unit, and nfin is the number of fins contained in each gate.

[0009] Optionally, step 2.3) includes: 2.3.1B) Get the preset number of gates minus_gate_num that the transistors on the pull-up or pull-down path that the current does not pass through in the current unit need to reduce; 2.3.2B) Determine whether the gate number minus_gate_num to be reduced is equal to 0 and whether it is less than the gate number gate_num of each transistor in each current unit. If the gate number minus_gate_num to be reduced is not equal to 0 and the gate number minus_gate_num to be reduced is less than the gate number gate_num of each transistor in each current unit, jump to step 2.3.3B; otherwise jump to step 4); 2.3.3B) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.4B), otherwise jump to step 4); 2.3.4B) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain terminal, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.5B), otherwise jump to step 2.3.3B) to continue reading the next row; 2.3.5B) Delete the row where the read row content cell_line is located, reduce the number of gates to be reduced minus_gate_num by 1, and jump to step 2.3.3B) to continue reading the next row.

[0010] Optionally, step 4) further includes simulating the timing path after the layout is redrawn to obtain an optimized delay.

[0011] In addition, the present invention also provides a transistor-level delay optimization system based on circuit topology structure, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure.

[0012] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure through a processor.

[0013] In addition, the present invention also provides a computer program product, including a computer program or instructions, wherein the computer program or instructions are programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure through a processor.

[0014] Compared with the prior art, the present invention mainly has the following advantages: 1. The method of the present invention can automatically find the delay-sensitive unit and determine the transistor size after the unit is optimized, and achieve greater delay optimization with minimal design changes, providing guidance for layout design and avoiding the blindness and arbitrariness of manual optimization and adjustment of the layout; 2. The method of the present invention can perform delay optimization on the path according to the circuit topology structure, and can quickly and efficiently find the delay-sensitive unit and determine the transistor size after the unit is optimized, and has the characteristics of high automation, flexibility and good adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0016] Figure 2 It is the original timing path in the method of the embodiment of the present invention.

[0017] Figure 3 In the embodiment of the present invention, based on Figure 2 The original timing path and the timing path after delay optimization.

[0018] Figure 4 Schematic diagram of the two-dimensional planar structure of finFET in an embodiment of the present invention.

[0019] Figure 5 Schematic diagram of the three-dimensional structure of finFET in an embodiment of the present invention.

[0020] Figure 6 It is a stick diagram of the original layout of the two-input NAND gate unit netlist in the embodiment of the present invention.

[0021] Figure 7 It is a stick diagram of the layout after the netlist of the two-input NAND gate unit is optimized in the embodiment of the present invention.

[0022] Figure 8 Schematic diagram of the original partial layout of the finFET unit netlist in an embodiment of the present invention.

[0023] Fig. 9 FIG. 1 is a schematic diagram of a portion of the layout after the finFET unit netlist is optimized in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] like Figure 1 As shown, the transistor-level delay optimization method based on the circuit topology structure of this embodiment includes the following steps: 1) Obtain all N units on the timing path to be optimized; 2) Perform transistor-level delay optimization on each unit to obtain the delay-optimized timing path, for example Figure 2The bold path in the original timing path shown is a pull-up or pull-down path through which the current passes, and the non-bold path is a pull-up or pull-down path through which the current does not pass; Figure 3 For Figure 2 The timing path after delay optimization. Delay optimization adds 2 gates to the transistors on the bold path and reduces 1 gate to the transistors on the non-bold path, and shows the change in the number of fins before and after optimization. BUFV3, NOR2V6, INV6, NOR3V4 and AOI21V4 are the unit names in the timing path, I, A1, A2, A3, B are inputs, Z, ZN are outputs, and the numbers represent the number of fins in the transistor. N1, N2, P1, P2 next to the transistor are transistor labels, and other transistors are labeled with inputs, distinguished by N or P type transistors and the current unit name, and are no longer labeled separately; 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N; 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization.

[0025] In this embodiment, there are a total of N units on the timing path to be optimized, so step 1) obtains all the N units on the timing path to be optimized so as to provide data for subsequent optimization of each unit one by one.

[0026] In this embodiment, step 2) includes: 2.1) Traverse N units to obtain a unit as the current unit. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the timing path after delay optimization has been obtained, and jump to step 3); 2.2) Find and calculate the number of gates gate_num of each transistor in the current unit, the number of fins Fin of each gate nfin and the total number of fins Fin all_fin_num; 2.3) Based on the number of gates gate_num in each transistor in the current unit, the number of fins Fin in each gate nfin and the total number of fins Fin all_fin_num, the number of gates in the transistor in the current unit is modified according to the unit type and circuit structure to achieve transistor-level delay optimization, and then jump to step 2.1).

[0027] In this embodiment, step 2.2) includes: 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell, if the reading is successful, jump to step 2.2.2), otherwise jump to step 2.2.3); 2.2.2) If the five elements of the input terminal, output terminal, source or drain, N or P type, and the number of fins in the read row content cell_line are consistent with the transistor to be found, then the number of fins Fin read in the row content cell_line is the number of fins Fin per gate nfin; jump to step 2.2.1); 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates of the transistor to be searched in the current unit, gate_num. Multiply the number of fins Fin per gate, nfin, by the number of gates of each transistor in the current unit, gate_num, to get the total number of fins Fin in each transistor, all_fin_num; for example Figure 4 In the two-dimensional planar structure of the finFET shown, the number of fins Fin (indicated as fin1 to fin5) contained in the gate is nfin, which is 5. The total number of fins Fin in each transistor is all_fin_num obtained by multiplying 5 by the number of gates contained in each transistor in the current unit, gate_num. Figure 5 The three-dimensional structure of the finFET shown better demonstrates the relationship between the gate and the fin Fin in the finFET, where L is the length of the gate, H is the height of the fin Fin, and W is the width of the fin Fin; jump to step 2.3).

[0028] In this embodiment, step 2.3) includes: 2.3.1A) Get the preset number of gates add_gate_num to be added to the transistors on the pull-up or pull-down path through which the current in the current unit passes; 2.3.2A) Determine the number of fins Fin to be added need_add_num according to the number of gates add_gate_num of transistors on the pull-up or pull-down path through which the current in the current unit passes and the number of fins Fin per gate nfin; 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A); otherwise, jump to step 4); 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.5A), otherwise jump to step 4); 2.3.5A) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.6A), otherwise jump to step 2.3.4A) to continue reading the next row; 2.3.6A) Read the number of fins Fin in the row content cell_line. If the number of fins Fin in the row content cell_line plus the number of fins Fin to be added need_add_num is less than or equal to the preset maximum number of fins Fin that can be added to a gate max_fin_num, then modify the number of fins Fin in a gate in the row content cell_line representing the information of a gate nfin to the sum of the original number of fins Fin in a gate nfin plus the total number of fins Fin all_fin_num, and then set the number of fins Fin to be added need_add_num to 0; otherwise, modify the number of fins Fin in a gate in the row content cell_line to max_fin_num, and update the number of fins Fin to be added need_add_num according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

[0029] In step 2.3.2A) of this embodiment, the function expression for determining the number of fins Fin to be added, need_add_num, is: need_add_num=add_gate_num*nfin In the above formula, add_gate_num is the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the current unit, and nfin is the number of fins contained in each gate.

[0030] Refer to steps 2.3.1A) to 2.3.6A). If the path is to add gates, the number of gates to be added add_gate_num is obtained, and the number of fins to be added is need_add_num=add_gate_num*nfin. Then the loop starts. If the number of fins to be added need_add_num is not equal to 0, the loop continues. The content is read from the standard cell netlist to be modified row by row as cell_line. When the five elements of the input terminal, output terminal, source or drain, whether it is n or p type, and whether it contains the number of fins in the field cell_line match the transistor to be found, the position of the row to be modified is found. If the nfin in the current cell_line row plus need_add_num is less than or equal to the maximum number of fins that can be added to a gate max_fin_num, the number of fins in this row is modified to be equal to the sum of nfin and all_fin_num originally contained in this row, and then need_add_num is set to 0, and the addition is completed. If the sum of nfin in the current cell_line row and need_add_num is greater than the maximum number of fins that can be added to a gate, max_fin_num, change the number of fins in this row to max_fin_num, and the number of fins that need to be added is: need_add_num=need_add_num-max_fin_num+nfin, Then read the next line of the cell netlist. If it does not match, read the next line of the cell netlist. If the cell_line content is empty, exit the loop.

[0031] Step 2.3) of this embodiment includes: 2.3.1B) Get the preset number of gates minus_gate_num that the transistors on the pull-up or pull-down path that the current does not pass through in the current unit need to reduce; 2.3.2B) Determine whether the gate number minus_gate_num to be reduced is equal to 0 and whether it is less than the gate number gate_num of each transistor in each current unit. If the gate number minus_gate_num to be reduced is not equal to 0 and the gate number minus_gate_num to be reduced is less than the gate number gate_num of each transistor in each current unit, jump to step 2.3.3B; otherwise jump to step 4); 2.3.3B) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.4B), otherwise jump to step 4); 2.3.4B) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain terminal, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.5B), otherwise jump to step 2.3.3B) to continue reading the next row; 2.3.5B) Delete the row where the read row content cell_line is located, reduce the number of gates to be reduced minus_gate_num by 1, and jump to step 2.3.3B) to continue reading the next row.

[0032] Refer to steps 2.3.1B) to 2.3.5B). If it is a path gate reduction, get the number of gates to be reduced minus_gate_num, start the loop, and keep looping if the number of gates to be reduced minus_gate_num is not equal to 0. If the number of gates to be reduced minus_gate_num is greater than or equal to the number of gates gate_num contained in the transistor, it will be displayed that the gate cannot be reduced and exit the loop. If the number of gates to be reduced minus_gate_num is less than the number of gates gate_num contained in the transistor, continue to read from the standard cell netlist to be modified row by row. When the five elements of the input terminal, output terminal, source or drain, whether it is n or p type, and whether it contains the number of fins in the row match the transistor to be found, find the position of the row to be modified and delete this row. Because a row in the netlist represents a gate in the transistor, it is equivalent to subtracting a gate. The number of gates to be subtracted is minus_gate_num-1. Because after deleting this row, the number of rows behind it moves forward as a whole, so the number of rows remains unchanged and the loop continues. If it does not match, read the next row of the cell netlist. If the cell_line content is empty, exit the loop.

[0033] After inputting the information to modify the number of gates, determine whether to add or subtract gates. If adding gates, the loop will continue until add_gate_num is equal to 0. If subtracting gates, the loop will continue until minus_gate_num is equal to 0. Figure 6 It is a stick diagram of the original layout of the two-input NAND gate (NAND2V3) unit netlist in this embodiment. Figure 7 This is a stick diagram of the layout after the optimization of the netlist of the two-input NAND gate (NAND2V3) unit in this embodiment, see Figure 6 and Figure 7 The stick diagrams of the layout before and after optimization show that the optimization program in this embodiment adds 2 gates to the transistors on the pull-down paths corresponding to the cell inputs A1 and A2, and subtracts 1 gate from the transistors on the pull-up paths corresponding to the inputs A1 and A2. Figure 6 and Figure 7 In the stick diagram in the middle layout, A1 and A2 are input names, 0-9 are grid names, and ZN and 4 are line names.

[0034] As an optional implementation, after step 4) of this embodiment, the timing path after the layout is redrawn is simulated to obtain the optimized delay. After obtaining n delay-sensitive units, the layout is redrawn according to the optimized number of unit fins, and post-simulation is performed to evaluate the optimization effect, and the optimization is completed. Figure 8 Schematic diagram of the original partial layout of the finFET unit netlist in an embodiment of the present invention, Fig. 9 For Figure 8 The part of the layout after adding a gate on the basis of the circuit. Adding a gate in the layout is equivalent to adding five fins Fin, where Gate is the gate, A2 is the input port, ZN is the output port, VSS is the ground, M0G is the metal connecting the gate and the through hole, M0 is the metal, and the fins Fin (represented as fin1~fin5 in the figure).

[0035] In summary, the transistor-level delay optimization method based on the circuit topology structure of this embodiment includes: (1) obtaining all cells in a path; (2) setting the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the cell as add_gate_num, and the number of gates to be reduced to the transistors on the pull-up or pull-down path through which the current does not pass as minus_gate_num; (3) finding the number of gates contained in each transistor in the cell as gate_num, the number of fins contained in each gate as nfin, and the total number of fins as all_fin_num; (4) modifying the number of gates in the transistor in the cell based on the cell type and the circuit structure, as shown in the attached figure. Figure 2 The bold path in the circuit diagram is the pull-up or pull-down path through which the current passes. Two gates are added to the transistors on the path, and one gate is subtracted from the transistors on the pull-up or pull-down path through which the current does not pass. The change in the number of fins before and after optimization is displayed; (5) Repeat the above steps (3)-(4) until each unit in the path is modified; (6) Compare the delay results of the original path with the simulation results of the modified path, and find the n units with the largest delay changes before and after the modification as delay-sensitive units; (7) Only the n delay-sensitive units in the path are modified and the entire modified path is simulated. The aforementioned transistor-level delay optimization method based on circuit topology structure in this embodiment uses a method based on circuit topology structure to automatically find delay-sensitive units for the timing path to be optimized, and can automatically determine the delay-sensitive units and their transistor sizes in the path based on the topology structure of the circuit diagram. It has the characteristics of high automation, high flexibility, and good adaptability, and can help optimize the delay of the path quickly and efficiently.

[0036] In addition, this embodiment also provides a transistor-level delay optimization system based on circuit topology structure, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure.

[0037] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on the circuit topology structure through a processor.

[0038] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure through a processor.

[0039] Those skilled in the art should understand that the technical solutions provided by the embodiments of the present application may be in the form of methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0040] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A transistor-level delay optimization method based on circuit topology, characterized in that: The steps include: 1) Obtain all N units on the timing path to be optimized; 2) Perform transistor-level delay optimization on each unit to obtain the timing path after delay optimization; 3) Simulate the optimized timing path to obtain the optimized path delay, and select n units with the largest delay change relative to the original timing path as n delay-sensitive units, where n is less than or equal to N; 4) Redraw the layout for the selected n delay-sensitive units according to the modifications corresponding to the delay optimization.

2. The transistor-level delay optimization method based on circuit topology structure according to claim 1, characterized in that: Step 2) includes: 2.1) Traverse N units to obtain a unit as the current unit. If the traversal is successful, jump to step 2.2). Otherwise, it is determined that the timing path after delay optimization has been obtained, and jump to step 3); 2.2) Find and calculate the number of gates gate_num of each transistor in the current unit, the number of fins Fin of each gate nfin and the total number of fins Fin all_fin_num; 2.3) Based on the number of gates gate_num in each transistor in the current unit, the number of fins Fin in each gate nfin and the total number of fins Fin all_fin_num, the number of gates in the transistor in the current unit is modified according to the unit type and circuit structure to achieve transistor-level delay optimization, and then jump to step 2.1).

3. The transistor-level delay optimization method based on circuit topology structure according to claim 2, characterized in that: Step 2.2) includes: 2.2.1) Read the row content cell_line from the standard cell netlist of the current cell, if the reading is successful, jump to step 2.2.2), otherwise jump to step 2.2.3); 2.2.2) If the five elements of the input terminal, output terminal, source or drain, N or P type, and the number of fins in the read row content cell_line are consistent with the transistor to be found, then the number of fins Fin read in the row content cell_line is the number of fins Fin per gate nfin; jump to step 2.2.1); 2.2.3) Record the number of rows where the five elements match the transistor to be searched as the number of gates gate_num of the transistor to be searched in the current unit, multiply the number of fins Fin per gate nfin by the number of gates gate_num of each transistor in the current unit to obtain the total number of fins Fin in each transistor all_fin_num; jump to step 2.3).

4. The transistor-level delay optimization method based on circuit topology structure according to claim 2, characterized in that: Step 2.3) includes: 2.3.1A) Get the preset number of gates add_gate_num to be added to the transistors on the pull-up or pull-down path through which the current in the current unit passes; 2.3.2A) Determine the number of fins Fin to be added need_add_num according to the number of gates add_gate_num of transistors on the pull-up or pull-down path through which the current in the current unit passes and the number of fins Fin per gate nfin; 2.3.3A) Determine whether the number of fins to be added, need_add_num, is equal to 0. If not, jump to step 2.3.4A); otherwise, jump to step 4); 2.3.4A) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.5A), otherwise jump to step 4); 2.3.5A) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.6A), otherwise jump to step 2.3.4A) to continue reading the next row; 2.3.6A) Read the number of fins Fin in the row content cell_line. If the number of fins Fin in the row content cell_line plus the number of fins Fin to be added need_add_num is less than or equal to the preset maximum number of fins Fin that can be added to a gate max_fin_num, then modify the number of fins Fin in a gate in the row content cell_line representing the information of a gate nfin to the sum of the original number of fins Fin in a gate nfin plus the total number of fins Fin all_fin_num, and then set the number of fins Fin to be added need_add_num to 0; otherwise, modify the number of fins Fin in a gate in the row content cell_line to the preset maximum number of fins Fin that can be added to a gate max_fin_num, and update the number of fins Fin to be added need_add_num according to the following formula: need_add_num=need_add_num-max_fin_num+nfin; jump to execute step 2.3.4A) to continue reading the next row.

5. The transistor-level delay optimization method based on circuit topology structure according to claim 4, characterized in that: The function expression for determining the number of fins to be added, need_add_num, in step 2.3.2A is: need_add_num=add_gate_num*nfin In the above formula, add_gate_num is the number of gates to be added to the transistors on the pull-up or pull-down path through which the current passes in the current unit, and nfin is the number of fins contained in each gate.

6. The transistor-level delay optimization method based on circuit topology structure according to claim 2, characterized in that: Step 2.3) includes: 2.3.1B) Get the preset number of gates minus_gate_num that the transistors on the pull-up or pull-down path that the current does not pass through in the current unit need to reduce; 2.3.2B) Determine whether the gate number minus_gate_num to be reduced is equal to 0 and whether it is less than the gate number gate_num of each transistor in each current unit. If the gate number minus_gate_num to be reduced is not equal to 0 and the gate number minus_gate_num to be reduced is less than the gate number gate_num of each transistor in each current unit, jump to step 2.3.3B; otherwise jump to step 4); 2.3.3B) Read the row content cell_line from the standard cell netlist of the current cell to be modified, if the reading is successful, jump to step 2.3.4B), otherwise jump to step 4); 2.3.4B) If the five elements of the read row content cell_line, namely, the input terminal, the output terminal, the source or drain terminal, the N or P type, and the number of fins, match the transistor to be found, then jump to step 2.3.5B), otherwise jump to step 2.3.3B) to continue reading the next row; 2.3.5B) Delete the row where the read row content cell_line is located, reduce the number of gates to be reduced minus_gate_num by 1, and jump to step 2.3.3B) to continue reading the next row.

7. The transistor-level delay optimization method based on circuit topology structure according to claim 1, characterized in that: Step 4) also includes simulating the timing path after redrawing the layout to obtain the optimized delay.

8. A transistor-level delay optimization system based on a circuit topology structure, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure as claimed in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure described in any one of claims 1 to 7 through a processor.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the transistor-level delay optimization method based on circuit topology structure described in any one of claims 1 to 7 through a processor.

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