Iris recognition system, iris recognition method and equipment based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of biological recognition, and discloses an iris recognition system, an iris recognition method and equipment based on an FPGA, and the iris recognition system comprises an iris collection and preprocessing module, a database, a DPU IP network reasoning module and a PS result processing module. According to the method, the iris image is quickly and accurately recognized by utilizing high-speed reasoning and low-precision loss of the DPU. And the DPU processing result is analyzed, so that the recognition result of the system is obtained, and the iris recognition function is achieved. In addition, the database part is specially processed, the scheme that feature values are obtained through reasoning of a single picture for comparison and recognition is not adopted any more, three-channel pictures are adopted for training and reasoning, and then the accuracy of the model is better improved.

Description

Technical Field

[0001] The present application relates to the field of biometrics technology, for example, to an iris recognition system, an iris recognition method and a device based on FPGA. Background Art

[0002] With the development of biometric technology, biometric technology represented by face recognition and fingerprint recognition has been widely used in the fields of consumer, electronic equipment, furniture security, etc. In the fields with high security requirements, the two types of recognition are combined to improve security. While biometric technology is convenient for people, it has also aroused people's attention to the security issues caused by biometrics. In view of the characteristics that fingerprint information is easy to copy and face information can be extracted by others at certain times, biometric technology represented by iris recognition can solve the above pain points well. From daily check-in, e-commerce, airport and station security, forensic identification and national security, there are applications for iris recognition everywhere, and it has become an indispensable part of modern society.

[0003] According to the different deployment platforms, iris recognition systems can be divided into two categories: PC iris recognition systems and embedded iris recognition systems. The PC-based iris recognition system has the characteristics of simple and convenient development, easy maintenance, mature technology, fast processing speed and large storage space, but its large size and high cost make it mainly used in national security and areas with particularly high requirements for recognition speed; while the iris recognition system based on the embedded platform has the characteristics of low price, wide application field and simple structure, but its operation processing speed limits its application in some occasions. For example, the ARM-based embedded development platform has great advantages in the processing of logical instructions, but cannot support parallel computing, resulting in a great disadvantage in computing speed. The Field Programmable Gate Array (FPGA) device was invented by Xilinx in 1985. Its appearance has largely made up for the shortcomings of insufficient computing power of traditional embedded chips. FPGA devices have the characteristics of low power consumption and strong computing power. Compared with ARM embedded devices, FPGA development platforms are not as convenient as the latter in terms of software or model deployment, and are also more expensive. However, the data processing speed and power consumption are unmatched by ARM devices.

[0004] With the rapid development of artificial intelligence (AI), AI has been widely used in all walks of life, not only in emerging fields, but also in traditional fields. In the field of iris recognition, with the help of AI, a powerful tool, high-precision iris recognition can be achieved. AI model deployment is mainly divided into two categories: PC-side model deployment and embedded-side model deployment. The PC side has the characteristics of strong computing power, wide application range, and simple development; the embedded-side model deployment has the characteristics of low power consumption, simple structure, and low price. The current mainstream hardware deployment platforms include CPU, GPU, FPGA, ASIC, etc. Due to the limitations of its own architecture, it is difficult for the CPU to support parallel computing; although the GPU has powerful computing power, it is expensive, so it is generally used in combination with a PC for model training; ASIC has the characteristics of low power consumption and strong computing power, but poor versatility and low portability; FPGA has become a rising star in the eyes of engineers due to its low power consumption, strong versatility, and high computing power. However, FPGA acceleration of artificial intelligence algorithms also faces the following challenges: the development and rapid iteration of AI models have led to higher and higher requirements for resources and computing power, but the computing power resources of FPGAs have developed slowly and cannot keep up with the development of computing power. Therefore, developers need to pay attention to resource utilization at all times to prevent deployment failures or calculation errors. The FPGA learning cycle is long, and developers have to learn FPGA theory knowledge on top of learning AI model knowledge, which invisibly increases the difficulty of model deployment.

[0005] Therefore, in the existing technical solutions, feature recognition based on FPGA has the problems of slow inference speed and poor accuracy.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The present disclosure provides an iris recognition system based on FPGA, and the iris recognition system includes:

[0009] Iris collection and preprocessing module, database, DPU IP network reasoning module and PS result processing module;

[0010] An iris acquisition and preprocessing module is used to acquire human iris data through an iris camera and perform preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations;

[0011] The database is used to store registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm;

[0012] DPU IP network inference module, used to implement network inference through the optimized DPU IP provided by Xilinx;

[0013] The PS result processing module is used to analyze the results processed by the DPU IP network reasoning module to obtain the system recognition results.

[0014] In some embodiments, the iris data of the human eye is collected by an iris camera and the corresponding function is called by a preset OpenCV function library to collect data.

[0015] In some embodiments, the positioning of the iris includes removing the reflected light spot in the pupil; binarizing the grayscale image of the iris; calling a preset opencv function library and using the Hough gradient method to detect the inner and outer boundaries of the iris;

[0016] Normalization, including conversion between polar coordinate system and rectangular coordinate system, normalizing the iris ring located between the sclera and the pupil in the rectangular coordinate system to a standard rectangle in the rectangular coordinate system;

[0017] Data augmentation, including increasing image contrast and improving dynamic range.

[0018] In some embodiments, the database includes pre-processed iris data images of left and right eyes of multiple people, and during training, the left eye is compared with the left eye, or the right eye is compared with the right eye, instead of comparing the left and right eyes at the same time.

[0019] In some embodiments, three-channel images are fed into the network during training, and the left eye or right eye image of one person is combined with the two left eye or right eye images of the remaining other people into three channels.

[0020] In some embodiments, data augmentation includes augmenting image data by image flipping, cropping, rotating, and scaling;

[0021] and / or enhancing non-image data by adding noise, changing color space;

[0022] and / or enhance the labeled data by adding labels.

[0023] In some embodiments, network inference is implemented through an optimized DPU IP provided by Xilinx, including:

[0024] The three-channel iris images input into the database are sent to the MobileNet neural network for training to achieve network inference.

[0025] In some embodiments, the results processed by the DPU IP network inference module are analyzed to obtain the recognition results of the system, including:

[0026] Analyze the results processed by the DPU IP network inference module to obtain the classification situation, determine whether the recognized iris image is in the database, print the results, and obtain the system's recognition situation.

[0027] The embodiment of the present disclosure further provides an iris recognition method based on FPGA, which is applied to the above iris recognition system. The method includes:

[0028] Collecting human iris data through an iris camera and performing preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations;

[0029] Store registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm;

[0030] Implement network inference through the optimized DPU IP provided by Xilinx;

[0031] The results of the DPU IP network inference processing are analyzed to obtain the system recognition results.

[0032] An embodiment of the present disclosure provides an electronic device, the device comprising at least one processor;

[0033] and a memory communicatively coupled to the at least one processor;

[0034] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor so that the at least one processor can execute the above-mentioned iris recognition method based on FPGA.

[0035] The iris recognition system, iris recognition method and device based on FPGA provided in the embodiments of the present disclosure can achieve the following technical effects:

[0036] The present disclosure utilizes the high-speed reasoning and low-precision loss of DPU to realize fast and accurate recognition of iris images. By analyzing the results of DPU processing, the recognition results of the system are obtained to achieve the function of iris recognition. The present disclosure also performs special processing on the database part. Instead of using a single picture to infer the feature value for comparative recognition, a three-channel picture is used for training and reasoning, which can better improve the accuracy of the model.

[0037] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0039] Figure 1 is a structural diagram of an iris recognition system based on FPGA provided in an embodiment of the present disclosure;

[0040] Figure 2 is a schematic diagram of the structure of another iris recognition system based on FPGA provided in an embodiment of the present disclosure;

[0041] Figure 3 is a schematic diagram of image normalization provided by an embodiment of the present disclosure;

[0042] Figure 4 is a schematic diagram of a combined three-channel image provided by an embodiment of the present disclosure;

[0043] Figure 5 is a structural diagram of a MobileNet network provided by an embodiment of the present disclosure;

[0044] Figure 6 It is a schematic diagram of building a VitisAI working environment provided by an embodiment of the present disclosure;

[0045] Figure 7 is a schematic diagram of quantization compilation provided by an embodiment of the present disclosure;

[0046] Figure 8 is a structural diagram of a DPU provided by an embodiment of the present disclosure;

[0047] Fig. 9 It is a flowchart of an iris recognition method based on FPGA provided in an embodiment of the present disclosure;

[0048] Fig.10 It is a structural schematic diagram of an iris recognition device based on FPGA provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0050] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0051] Unless otherwise stated, the term "plurality" means two or more.

[0052] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0053] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0054] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0055] In order to solve the above problems, the present disclosure provides an iris recognition system, an iris recognition method and a device based on FPGA.

[0056] The following describes an iris recognition system, an iris recognition method, and a device based on FPGA provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0057] Figure 1 It is a structural diagram of an iris recognition system based on FPGA provided in an embodiment of the present disclosure.

[0058] like Figure 1 As shown, the iris recognition system based on FPGA may include an iris acquisition and preprocessing module, a database, a DPU IP network reasoning module, and a PS result processing module;

[0059] An iris acquisition and preprocessing module is used to acquire human iris data through an iris camera and perform preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations;

[0060] The database is used to store registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm;

[0061] DPU IP network inference module, used to implement network inference through the optimized DPU IP provided by Xilinx;

[0062] The PS result processing module is used to analyze the results processed by the DPU IP network reasoning module to obtain the system recognition results.

[0063] In some embodiments, the iris data of the human eye is collected by an iris camera and the corresponding function is called by a preset OpenCV function library to collect data.

[0064] In some embodiments, the positioning of the iris includes removing the reflected light spot in the pupil; binarizing the grayscale image of the iris; calling a preset opencv function library and using the Hough gradient method to detect the inner and outer boundaries of the iris;

[0065] Normalization, including conversion between polar coordinate system and rectangular coordinate system, normalizing the iris ring located between the sclera and the pupil in the rectangular coordinate system to a standard rectangle in the rectangular coordinate system;

[0066] Data augmentation, including increasing image contrast and improving dynamic range.

[0067] In some embodiments, the database includes pre-processed iris data images of left and right eyes of multiple people, and during training, the left eye is compared with the left eye, or the right eye is compared with the right eye, instead of comparing the left and right eyes at the same time.

[0068] In some embodiments, three-channel images are fed into the network during training, and the left eye or right eye image of one person is combined with the two left eye or right eye images of the remaining other people into three channels.

[0069] In some embodiments, data augmentation includes augmenting image data by image flipping, cropping, rotating, and scaling;

[0070] and / or enhancing non-image data by adding noise, changing color space;

[0071] and / or enhance the labeled data by adding labels.

[0072] In some embodiments, network inference is implemented through an optimized DPU IP provided by Xilinx, including:

[0073] The three-channel iris images input into the database are sent to the MobileNet neural network for training to achieve network inference.

[0074] In some embodiments, the results processed by the DPU IP network inference module are analyzed to obtain the recognition results of the system, including:

[0075] Analyze the results processed by the DPU IP network inference module to obtain the classification situation, determine whether the recognized iris image is in the database, print the results, and obtain the system's recognition situation.

[0076] In a specific example, the FPGA-based iris recognition system may include iris image acquisition, iris image preprocessing, iris camera, database, DPU IP network inference, MobileNet neural network, VitisAI, network quantization and compilation, ZCU104 board, and PS-side result processing part;

[0077] Iris image collection refers to iris images collected by an iris camera;

[0078] The iris preprocessing part detects circles using the Hough gradient method to locate and segment the iris.

[0079] The iris camera is used to collect the iris of the human eye;

[0080] The database is the images saved during the iris image registration phase;

[0081] DPU IP network inference is used to realize the inference acceleration operation of the quantized compiled neural network;

[0082] The MobileNet neural network is used to implement the training and reasoning of iris images, specifically using deep convolution and point-by-point convolution operations;

[0083] Network quantization and compilation are used to quantize the neural network to obtain a lightweight model, and then compile the neural network to obtain code instructions that can be recognized by the DPU;

[0084] VitisAI is the official working environment provided by Xilinx, in which the network can be compiled and quantized.

[0085] The ZCU104 board is used to deploy the platform and has an FPGA chip on it;

[0086] PS result processing is used in the Linux system on the ZCU104 board to classify and output the results by calling related functions.

[0087] The iris recognition system based on FPGA can use a dedicated iris recognition camera to collect irises, which can specifically include the collection of iris images and the preprocessing of iris images;

[0088] For the acquisition of iris images, you can use OpenCV. You can call related functions by installing the OpenCV function library in the Linux system. The preprocessing process of iris images mainly includes the following parts:

[0089] (1) Image positioning: First, remove the reflected light spot in the pupil; then, binarize the grayscale image of the iris; call the OpenCV function library to implement the Hough gradient method to detect the inner and outer boundaries of the iris.

[0090] (2) Image normalization: Using the transformation between polar coordinate system and rectangular coordinate system, the iris ring located between the sclera and pupil in the rectangular coordinate system is normalized to the standard rectangle of the rectangular coordinate system;

[0091] (3) Image data enhancement: This increases the contrast of the image, improves the dynamic range, and obtains a clear iris image, preparing for the subsequent network training to better extract iris features.

[0092] Optionally, the iris recognition system based on FPGA uses the collected and registered iris images to build a database. Each person in the database can contain 8 collected iris data images for the left and right eyes, and these images are stored in the database after preprocessing. During training, only the left eye is considered for comparison. There will be no situation where the left and right eyes are compared at the same time.

[0093] Optionally, the combination of database images needs to be implemented in a certain way. In order to improve the generalization ability, three-channel images are sent to the network during training. The left eye or right eye image of one person is combined with the two left eye or right eye images of the remaining others into three channels. There will be no combination of left eye and right eye, and there will be no combination of one iris image of three people into a three-channel image. On the one hand, this processing can improve the recognition accuracy, because it can improve the accuracy when compared with two images of the same person. Another reason is that when the database is small, this operation can increase the amount of training data. When the database is too small, using data enhancement technology is an effective solution. Data enhancement refers to the technology of increasing the amount of training data by using existing data sets and some data transformation technologies.

[0094] Specifically, data enhancement can be achieved in the following ways:

[0095] First, image data can be enhanced by techniques such as image flipping, cropping, rotating, and scaling. Second, non-image data can be enhanced by techniques such as adding noise and changing color space. Finally, labeled data can be enhanced by techniques such as adding labels. By using data augmentation techniques, the size of the dataset can be effectively increased, thereby improving the accuracy and generalization ability of the model.

[0096] After selecting the above three data images, we need to proceed to the next step. First, reshape them into iris images of size 103*360.

[0097] The FPGA-based iris recognition system uses DPU IP to implement the network reasoning part. DPU is a set of parameterizable IP cores pre-implemented in hardware, without the need for layout and routing. DPU is designed to accelerate the computational workload of deep learning reasoning algorithms widely used in various computer vision applications (such as image / video classification, semantic segmentation, and object detection / tracking). DPU is released together with the Vitis AI dedicated instruction set, which facilitates the efficient implementation of deep learning networks. The efficient tensor-level instruction set is designed to support and accelerate various popular convolutional neural networks, such as VGG, ResNet, GoogLeNet, YOLO, SSD, and MobileNet. DPU is scalable to adapt to various Xilinx Zynq-7000 devices, ZynqUltraScale+MPSoC, Xilinx Kria KV260, Versal cards, and Alveo boards from edge to cloud to meet the needs of many different applications.

[0098] The iris recognition system based on FPGA inputs three-channel iris images from the database and sends them to the neural network for training. The present invention uses MobileNet for experiments, mainly considering that MobileNet is a lightweight network, which is particularly suitable for the deployment of edge device platforms and consumes less resources. The results of DPU processing are analyzed to obtain the classification situation, determine whether the recognized iris image is in the database, and then print the results to obtain the recognition situation of the system.

[0099] Combination Figures 2 to 8 ,right Figure 1 The FPGA-based iris recognition system is further described in detail.

[0100] Embodiment 1, iris recognition system based on FPGA, such as Figure 2 As shown, it can specifically include iris collection and preprocessing, database, DPU IP network reasoning, and PS result processing;

[0101] Iris collection and preprocessing are used to collect human iris data through an iris camera and then perform preprocessing, including iris positioning, normalization and data enhancement operations; the size of the iris image after preprocessing is fixed at 360*103, where 8 images are collected for each eye of each person. The database is used to store registered iris images. When performing inference, the images collected by the iris camera will be combined with the images in the database through an algorithm to form a three-channel image; the combined images have a specific pattern, and the recognized human eye is combined with two images of one person in the database, and they are all left or right eye combinations. DPU IP network inference is used to implement the network inference part through the highly optimized DPU IP provided by Xilinx; the network used during training and the FPGA deployment inference must be the same network. Before inference, the trained network is quantized. This step will quantize the weight and bias part of the network from 32-bit floating point numbers to 8-bit integers. After quantization, the VitisAI tool provided by Xilinx is called for compilation. PS result processing is used to analyze the results of DPU processing, print the results, and obtain the recognition results of the system.

[0102] Embodiment 2, the iris recognition system based on FPGA may include iris picture acquisition, iris picture preprocessing, iris camera, database, DPU IP network reasoning, MobileNet neural network, VitisAI, network quantization and compilation, ZCU104 board, and PS end result processing; iris picture acquisition refers to the iris picture collected by the iris camera; the iris preprocessing part realizes the positioning and segmentation of the iris by detecting the circle by the Hough gradient method; the iris camera is used for: iris acquisition of the human eye; the database is the picture saved in the iris image registration stage; the DPU IP network reasoning is used for: realizing the reasoning acceleration operation of the quantized compiled neural network; the MobileNet neural network is used for: the training and reasoning part of the iris picture, which adopts deep convolution and point-by-point convolution operations; the network quantization and compilation are used for: quantizing the neural network to obtain a lightweight model, and then compiling the neural network to obtain code instructions that can be recognized by the DPU; VitisAI is the working environment officially provided by Xilinx, in which the compilation and quantization of the network can be realized. The ZCU104 board is used for: the deployment platform with an FPGA chip on it; PS result processing is used for: in the Linux system on the ZCU104 board, the classification processing and output of the results are realized by calling relevant functions;

[0103] Embodiment 3, an iris recognition system based on FPGA, according to embodiment 1, is a leading step in the operation of the entire system in terms of iris acquisition and preprocessing. Iris acquisition requires the use of a dedicated iris recognition camera to acquire irises, which specifically includes: iris image acquisition, iris image preprocessing;

[0104] For the iris image acquisition part, OpenCV is used. You can call related functions by installing the OpenCV function library in the Linux system. There is a special driver interface on the ZCU104 development board. When the interface is connected to the iris camera, the Linux system will detect the presence of the camera. The preprocessing process of the iris image mainly includes the following parts:

[0105] (1) Image positioning

[0106] First, remove the reflected light spot in the pupil; then, binarize the grayscale image of the iris; call the opencv function library to implement the Hough gradient method to detect the inner and outer boundaries of the iris, so as to locate the inner and outer boundaries of the iris.

[0107] The specific definition is as follows:

[0108]

[0109] The specific implementation idea is that three non-collinear points on a plane correspond to a cluster of cones in the three-dimensional parameter space intersecting at a specific point (x c ,y c ,r), this point is the center of the circle we are looking for, (x i ,y i ) can be the coordinates of the point i to be detected in the image, and n is the number of points to be detected. Analogously to the iris, we find the three points on the boundary, and then find the coordinate position of the center of the circle through a lot of calculations. This method involves three-dimensional parameter space calculations, so the amount of calculation is also very large, but the robustness will be much stronger.

[0110] The iris images collected by the same person at different times and locations will have certain changes. The distance of collection, changes in light, etc. will cause the size of the collected irises to be different, because the adjustment function of the human eye will change the size of the pupil. Moreover, the iris cut out after positioning is in a circular shape, which is very inconvenient for later processing, especially for the recognition and matching of two irises. Therefore, we need to process the polar coordinates to convert the circular iris into a rectangular image of the same pixel size, which is convenient for the subsequent input of the neural network. As mentioned earlier, human eyelashes and eyelids are common interference sources. When analyzing, we can consider certain interception processing of the image after normalization, remove those parts that are greatly affected by the interference source, and select the part with rich texture for the next step of processing. Due to the influence of lighting and collection environment, the collected iris has the problem of uneven grayscale distribution. Usually we need to enhance the image. Generally, the histogram equalization method is used to improve the grayscale distribution of the iris, which can greatly improve the accuracy of later recognition.

[0111] (2) Image normalization: By transforming the polar coordinate system into the rectangular coordinate system, the iris ring between the sclera and the pupil in the rectangular coordinate system is normalized to a standard rectangle in the rectangular coordinate system. Figure 3 As shown in the figure, considering the influence of eyelashes and ambient light, we have cropped the normalized image to some extent. ;

[0112] (3) Image data enhancement: This increases the contrast of the image, improves the dynamic range, and obtains a clear iris image, which prepares for the subsequent network training to better extract iris features. The present invention uses the data enhancement of the histogram equalization method.

[0113] Embodiment 4, according to Embodiment 3, the preprocessed iris images can be saved in the database. When building a database using the collected and registered iris images, each person in the database contains 8 collected iris data images for the left and right eyes, and these images are saved in the database after preprocessing. During training, only the left eye is considered for comparison. There will be no situation where the left and right eyes are compared at the same time. There is no point in doing this. Although it can improve the robustness of the network, the accuracy will be affected. The combination of database images needs to be implemented in a certain way. In order to improve the generalization ability, three-channel images are sent to the network during training. The left eye or right eye image of one person is combined with the two left eye or right eye images of the remaining others into three channels. There will be no situation where the left eye is combined with the right eye, and there will be no situation where one iris image of each of the three people is combined into a three-channel image. Specifically, Figure 4 As shown. Improve recognition accuracy, because it can improve accuracy by comparing two photos of the same person. Another reason is that when the database is small, this operation can increase the amount of training data. When the database is too small, using data enhancement technology is an effective solution. Data enhancement refers to the technology of increasing the amount of training data by using existing data sets and some data transformation techniques.

[0114] Data augmentation can be achieved in the following ways:

[0115] First, image data can be enhanced by techniques such as image flipping, cropping, rotating, and scaling. Second, non-image data can be enhanced by techniques such as adding noise and changing color space. Finally, labeled data can be enhanced by techniques such as adding labels. By using data augmentation techniques, the size of the dataset can be effectively increased, thereby improving the accuracy and generalization ability of the model.

[0116] After selecting the above three data images, we need to proceed to the next step. First, reshape them into iris images of size 103*360.

[0117] Example 5, an iris recognition system, all the preparations can be completed through Example 3. The present invention uses the MobileNet network to train and classify images, such as Figure 5 The main structure of the network is shown in Table 1. It mainly consists of depthwise convolution and point-by-point convolution, and changes are made to the number of channels and resolution to greatly reduce the number of parameters.

[0118] Table 1

[0119]

[0120]

[0121]

[0122]

[0123] The network uses 3×3 deep convolution to extract features, followed by a BN layer, followed by a ReLU layer, and then point-by-point convolution, and finally BN and ReLU. This is also in line with the depth-separable convolution. Compared with the standard convolution operation network, this network splits the standard convolution into a deep convolution and a point-by-point convolution. The total number of parameters is 3209026.

[0124] The network will eventually be deployed on the DPU IP. The DPU is a set of parameterizable IP cores pre-implemented in hardware, without the need for layout and routing. There are two ways to deploy it on your own development board. Method 1: If you are using an official development board, then you can directly download the development board image from the Xilinx official website, which already includes the DPU IP. Method 2: If you are using a third-party development board, but the chip must be from Xilinx, then you can build the DPU into the system through Vitis, and then build it into your own image file through the Petalinux software. Before deploying the DPU on the network, you need to build the working environment VitisAI. The specific process is as follows: Figure 6 As shown. In the Linux environment, install Docker, and then build the environment in Docker according to the tutorial provided on the official website. After the working environment is built, the network needs to be quantized and compiled, as shown below Figure 7 As shown in the figure, after the quantization operation, the weight and bias parameters of the neural network can be quantized from 32-bit floating point data to 8-bit integer data. The size of the model can be greatly reduced, and the impact on accuracy is acceptable. The quantized model still needs to be compiled. The DPU cannot directly read the quantized network model. The quantized network needs to be compiled into specific code instructions, which are provided to the DPU for reading operations. The specific structure of the DPU is as follows Figure 8 As shown in the figure, the CPU refers to the PS part in the FPGA, the scheduler, instruction fetch unit, PE hybrid computing array, and global memory constitute the entire DPU IP core, and the RAM is used as a temporary storage for data. The action control instructions of the DPU IP and the computing engine are stored. The instructions for controlling the actions of the DPU IP are transmitted through the CPU and optimized by the scheduler. The global memory is used to store model data, buffer input, intermediate information and output information, and reuse data as much as possible to improve efficiency. In addition, the action instructions of the hybrid computing array also come from the off-chip storage unit, which is responsible for the scheduling of the internal programmable logic. The processing element PE in the convolution computing engine is the core element of the convolution operation. It can form a variety of computing units such as multipliers and adders. In addition, the pipeline design makes it further improve efficiency. The main interface connecting the DPU to the basic circuit system with PS is mainly used for data access and instruction acquisition. The high-bandwidth port is used for data access, while the low-bandwidth port is used for instruction transfer.

[0125] Example 6, an iris recognition system based on FPGA. By Example 5, the output result of DPU can be obtained, but this result is not the final recognition result. The output value needs to be processed. For iris recognition, it can be simply regarded as a 2-classification problem. For example, if the person to be recognized is in the database, then our recognition result is 1, that is, in the database; if the recognition classification result is 0, that is, the recognition image is not in the database, DPU cannot directly print out the classification result. We need to send the final DPU output value to the PS end for processing, and finally print the recognition result of the system. Figure 2 As shown, the output result of DPU is directly sent to the application on the PS side. The application is a user function written by the user, which is mainly responsible for calling database data, calling DPU and printing the final result.

[0126] In combination with the above content, in a specific example, the iris recognition system based on FPGA mainly includes iris acquisition and preprocessing, database, DPU IP network reasoning, and PS result processing;

[0127] Iris collection and preprocessing are used to: collect human iris data through an iris camera, and then perform preprocessing, including iris positioning, normalization and data enhancement operations;

[0128] The database is used to store registered iris images. When performing inference, the images collected by the iris camera are combined with the images in the database through an algorithm to form a three-channel image.

[0129] DPU IP network inference is used to: implement the network inference part through the highly optimized DPU IP provided by Xilinx;

[0130] PS result processing is used to: analyze the results of DPU processing, print the results, and obtain the recognition results of the system;

[0131] The iris recognition system uses a dedicated iris recognition camera to collect irises, which specifically includes: iris image collection, iris image preprocessing;

[0132] The iris recognition system uses OpenCV to collect iris images. You can call related functions by installing the OpenCV function library in the Linux system. The preprocessing process of iris images mainly includes the following parts:

[0133] (1) Image positioning

[0134] First, remove the reflected light spot in the pupil; then, binarize the grayscale image of the iris; call the opencv function library to implement the Hough gradient method to detect the inner and outer boundaries of the iris.

[0135] (2) Image normalization: By transforming the polar coordinate system into the rectangular coordinate system, the iris ring located between the sclera and the pupil in the rectangular coordinate system is normalized to the standard rectangle in the rectangular coordinate system.

[0136] (3) Image data enhancement: This increases the contrast of the image, improves the dynamic range, and obtains a clear iris image, preparing for the subsequent network training to better extract iris features.

[0137] The iris recognition system uses the collected and registered iris images to build a database. Each person in the database contains 8 collected iris data images for the left and right eyes. These images are stored in the database after preprocessing. During training, only the left eye is considered for comparison. There will be no situation where the left and right eyes are compared at the same time.

[0138] The iris recognition system needs a certain way to combine the database pictures. In order to improve the generalization ability, three-channel pictures are sent to the network during training. The left eye or right eye picture of one person is combined with the two pictures of the left eye or right eye of the remaining other people into three channels. There will be no combination of left eye and right eye, nor will there be a situation where one iris picture of three people is combined into a three-channel picture. On the one hand, this processing can improve the recognition accuracy, because it can improve the accuracy by comparing with two pictures of the same person. Another reason is that when the database is small, this operation can increase the amount of training data. When the database is too small, using data enhancement technology is an effective solution. Data enhancement refers to the technology of increasing the amount of training data by using existing data sets and some data transformation technologies.

[0139] Data augmentation can be achieved in the following ways:

[0140] First, image data can be enhanced by techniques such as image flipping, cropping, rotating, and scaling. Second, non-image data can be enhanced by techniques such as adding noise and changing color space. Finally, labeled data can be enhanced by techniques such as adding labels. By using data augmentation techniques, the size of the dataset can be effectively increased, thereby improving the accuracy and generalization ability of the model.

[0141] After selecting the above three data images, we need to proceed to the next step. First, reshape them into iris images of size 103*360.

[0142] The iris recognition system uses DPU IP to implement the network reasoning part. DPU is a set of parameterizable IP cores pre-implemented in hardware, without the need for layout and routing. DPU is designed to accelerate the computational workload of deep learning reasoning algorithms widely used in various computer vision applications (such as image / video classification, semantic segmentation, and object detection / tracking). DPU is released together with the Vitis AI dedicated instruction set, which facilitates the efficient implementation of deep learning networks. The efficient tensor-level instruction set is designed to support and accelerate various popular convolutional neural networks, such as VGG, ResNet, GoogLeNet, YOLO, SSD, and MobileNet. DPU is scalable to adapt to various Xilinx Zynq-7000 devices, ZynqUltraScale+MPSoC, Xilinx Kria KV260, Versal cards, and Alveo boards from edge to cloud to meet the needs of many different applications.

[0143] The iris recognition system inputs three-channel iris images from the database and sends them to the neural network for training. MobileNet is used for experiments. The main consideration is that MobileNet is a lightweight network, which is particularly suitable for deployment on edge device platforms and consumes less resources.

[0144] The iris recognition system analyzes the results of DPU processing to obtain the classification status, determines whether the recognized iris image is in the database, and then prints the results to obtain the recognition status of the system.

[0145] After actual testing, this application can achieve the successful deployment of the MobileNet network on FPGA, with an inference time of 3.3ms.

[0146] This application uses DPU IP to implement the network reasoning part. DPU is a set of parameterizable IP cores pre-implemented in hardware, without the need for layout and routing. DPU is designed to accelerate the computational workload of deep learning reasoning algorithms widely used in various computer vision applications (such as image / video classification, semantic segmentation, and object detection / tracking). DPU is released together with the Vitis AI dedicated instruction set, which facilitates the efficient implementation of deep learning networks. The efficient tensor-level instruction set is designed to support and accelerate various popular convolutional neural networks, such as VGG, ResNet, GoogLeNet, YOLO, SSD, and MobileNet. DPU is scalable to adapt to various Xilinx Zynq-7000 devices, Zynq UltraScale+MPSoC, Xilinx Kria KV260, Versal cards, and Alveo boards from edge to cloud to meet the needs of a variety of different applications.

[0147] This application inputs a three-channel iris image from the database and sends it to the neural network for training. This application uses MobileNet for experiments, mainly considering that MobileNet is a lightweight network, especially suitable for deployment on edge device platforms, and consumes less resources. The results of DPU processing are analyzed to obtain the classification situation, determine whether the recognized iris image is in the database, and then print the results to obtain the recognition situation of the system.

[0148] This application uses the high-speed reasoning and low-precision loss of DPU to achieve fast and accurate recognition of iris images. By analyzing the results of DPU processing, the recognition results of the system are obtained to achieve the function of iris recognition. The present invention also performs special processing on the database part. Instead of using a single picture to infer the feature value for comparative recognition, a three-channel picture is used for training and reasoning, which can better improve the accuracy of the model.

[0149] This application includes iris acquisition and preprocessing, database, DPU IP network reasoning and PS result processing; iris acquisition and preprocessing collects human iris data through an iris camera, and then performs preprocessing, including iris positioning, normalization and data enhancement operations; the database mainly stores registered iris images, and when reasoning, the images collected by the iris camera will be combined with the images in the database into three-channel images through an algorithm; DPU IP network reasoning mainly implements the network reasoning part through the highly optimized DPU IP provided by Xilinx; PS result processing analyzes the results of DPU processing and prints the recognition results. The present invention realizes the deployment and implementation of the iris recognition algorithm on FPGA. Compared with the IP core implementation generated by HLS, this application is simple to deploy, has better performance, is applicable to a wider range of networks, and reduces the difficulty of development.

[0150] Fig. 9 The present invention provides an iris recognition method based on FPGA, which is applied to Figure 1 In the iris recognition system based on FPGA, the method comprises:

[0151] S901, collecting human iris data through an iris camera and performing preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations;

[0152] S902, storing the registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm;

[0153] S903, network inference is achieved through the optimized DPU IP provided by Xilinx;

[0154] S904, analyzing the result of the DPU IP network inference processing to obtain a system recognition result.

[0155] In some embodiments, the iris data of the human eye is collected by an iris camera and the corresponding function is called by a preset OpenCV function library to collect data.

[0156] In some embodiments, the positioning of the iris includes removing the reflected light spot in the pupil; binarizing the grayscale image of the iris; calling a preset opencv function library and using the Hough gradient method to detect the inner and outer boundaries of the iris;

[0157] Normalization, including conversion between polar coordinate system and rectangular coordinate system, normalizing the iris ring located between the sclera and the pupil in the rectangular coordinate system to a standard rectangle in the rectangular coordinate system;

[0158] Data augmentation, including increasing image contrast and improving dynamic range.

[0159] In some embodiments, the database includes pre-processed iris data images of left and right eyes of multiple people, and during training, the left eye is compared with the left eye, or the right eye is compared with the right eye, instead of comparing the left and right eyes at the same time.

[0160] In some embodiments, three-channel images are fed into the network during training, and the left eye or right eye image of one person is combined with the two left eye or right eye images of the remaining other people into three channels.

[0161] In some embodiments, data augmentation includes augmenting image data by image flipping, cropping, rotating, and scaling;

[0162] and / or enhancing non-image data by adding noise, changing color space;

[0163] and / or enhance the labeled data by adding labels.

[0164] In some embodiments, network inference is implemented through an optimized DPU IP provided by Xilinx, including:

[0165] The three-channel iris images input into the database are sent to the MobileNet neural network for training to achieve network inference.

[0166] In some embodiments, the results processed by the DPU IP network inference module are analyzed to obtain the recognition results of the system, including:

[0167] Analyze the results processed by the DPU IP network inference module to obtain the classification situation, determine whether the recognized iris image is in the database, print the results, and obtain the system's recognition situation.

[0168] Combination Fig.10 As shown, the embodiment of the present disclosure also provides an iris recognition device 1000 based on FPGA, including a processor 1004 and a memory 1001. Optionally, the system may also include a communication interface 1002 and a bus 1003. The processor 1004, the communication interface 1002, and the memory 1001 may communicate with each other through the bus 1003. The communication interface 1002 may be used for information transmission. The processor 1004 may call the logic instructions in the memory 1001 to execute the iris recognition method based on FPGA of the above embodiment.

[0169] In addition, the logic instructions in the above-mentioned memory 1001 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0170] The memory 1001 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 1004 executes the function application and data processing by running the program instructions / modules stored in the memory 1001, that is, implementing the iris recognition method based on FPGA in the above embodiment.

[0171] The memory 1001 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 1001 may include a high-speed random access memory and may also include a non-volatile memory.

[0172] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute an iris recognition method based on FPGA.

[0173] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0174] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0175] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or including (comprising) refer to the existence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or these groups. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0176] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. Technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. Technicians can clearly understand that for the convenience and simplicity of description, the specific working process of the systems, devices and units described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0177] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0178] The flowchart and block diagram in the accompanying drawings show the possible architecture, functions and operations of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

[0179] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0180] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0181] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0182] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0183] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0184] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0185] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of this disclosure can be achieved, and this document is not limited here.

[0186] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An iris recognition system based on FPGA, characterized in that: The iris recognition system includes an iris acquisition and preprocessing module, a database, a DPU IP network reasoning module, and a PS result processing module; The iris acquisition and preprocessing module is used to acquire human iris data through an iris camera and perform preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations; The database is used to store registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm; The DPU IP network inference module is used to implement network inference through the optimized DPU IP provided by Xilinx; The PS result processing module is used to analyze the results processed by the DPU IP network reasoning module to obtain the recognition result of the system.

2. The iris recognition system according to claim 1, characterized in that: The method of collecting human iris data through an iris camera uses a preset OpenCV function library to call a corresponding function to collect data.

3. The iris recognition system according to claim 1, characterized in that: The iris positioning includes removing the reflected light spot in the pupil; performing binarization processing on the grayscale image of the iris; calling a preset opencv function library and using the Hough gradient method to detect the inner and outer boundaries of the iris; The normalization includes converting the polar coordinate system into the rectangular coordinate system to normalize the iris ring between the sclera and the pupil in the rectangular coordinate system to a standard rectangle in the rectangular coordinate system; The data enhancement includes increasing image contrast and improving dynamic range.

4. The iris recognition system according to claim 1, characterized in that: The database includes pre-processed iris data images of left and right eyes of multiple people. During training, the left eye is compared with the left eye, or the right eye is compared with the right eye, but the left and right eyes are not compared at the same time.

5. The iris recognition system according to claim 4, characterized in that: During training, three-channel images are sent to the network, and the left or right eye image of one person is combined with the two left or right eye images of the remaining others to form a three-channel image.

6. The iris recognition system according to claim 1, characterized in that: The data enhancement includes enhancing the image data by image flipping, cropping, rotating and scaling; and / or enhancing non-image data by adding noise, changing color space; and / or enhance the labeled data by adding labels.

7. The iris recognition system according to claim 1, characterized in that: The network inference is realized by the optimized DPUIP provided by Xilinx, including: The three-channel iris images input into the database are sent to the MobileNet neural network for training to achieve network inference.

8. The iris recognition system according to claim 1, characterized in that: The analyzing the result processed by the DPU IP network inference module to obtain the recognition result of the system includes: Analyze the results processed by the DPU IP network inference module to obtain the classification situation, determine whether the recognized iris image is in the database, print the results, and obtain the system's recognition situation.

9. An iris recognition method based on FPGA, applied to the system according to any one of claims 1 to 8, characterized in that: The method comprises: Collecting human iris data through an iris camera and performing preprocessing, wherein the preprocessing includes iris positioning, normalization and data enhancement operations; Store registered iris images. During the inference process, the images collected by the iris camera and the images in the database are combined into a three-channel image through a preset algorithm; Implement network inference through the optimized DPU IP provided by Xilinx; The results of the DPU IP network inference processing are analyzed to obtain the system recognition results.

10. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; It is characterized in that the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of claim 9.

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