Scan driving circuit, display panel and electronic device

Abstract

The application provides a scanning driving circuit, a display panel and an electronic device, and power consumption can be reduced. The first selection module of each stage of scanning driving units receives a shift signal output by a previous stage of scanning driving units and receives a shift signal output by a next stage of scanning driving units; when the Nth stage of scanning driving units receives shift signals output by the (N-1)th stage of scanning driving units and the (N+1)th stage of scanning driving units, and the Nth stage of scanning driving units receives a trigger signal, the first selection module controls a scanning signal output module of the Nth stage of scanning driving units to start outputting a scanning signal; the second selection module of each stage of scanning driving units receives a scanning signal output by a previous stage of scanning driving units; when the Mth stage of scanning driving units receives a scanning signal output by the (M-1)th stage of scanning driving units, and the Mth stage of scanning driving units receives a cutoff signal, the second selection module controls a scanning signal output module of the Mth stage of scanning driving units to stop outputting a scanning signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a scan driving circuit, a display panel and an electronic device. BACKGROUND

[0002] The main component of an electronic device to realize display function is a display panel. The display panel includes a display area and a non-display area, and the display area includes a plurality of pixels arranged in an array. Each pixel includes a pixel circuit and a light emitting element, and the pixel circuit is used to drive the light emitting element to emit light to display an image; the non-display area is provided with a scan driving circuit, which is used to provide a scan signal for the pixel circuit to make the light emitting element light up row by row under the driving of the pixel circuit.

[0003] Currently, when an electronic device displays an image, the refresh frequency of the picture in all regions is the same, that is, the scan signals of all rows are refreshed at the same frequency, which makes the power consumption of the display panel relatively high, and is not conducive to improving the endurance of the electronic device and reducing the user experience. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a scan driving circuit, a display panel and an electronic device. The power consumption can be reduced.

[0005] In a first aspect, an embodiment of the present application provides a scan driving circuit, which includes: n scan driving units arranged in cascade, n being a positive integer greater than or equal to 2; each scan driving unit includes a first selection module, a second selection module and a scan signal output module; the first selection module of each scan driving unit receives a shift signal output by the first selection module in the previous scan driving unit and receives a shift signal output by the first selection module in the next scan driving unit; when the first selection module of the Nth scan driving unit receives the shift signal output by the first selection module in the (N-1)th scan driving unit and receives the shift signal output by the first selection module in the (N+1)th scan driving unit, and the first selection module of the Nth scan driving unit receives a trigger signal, the first selection module is used to control the scan signal output module of the Nth scan driving unit to start outputting a scan signal; the second selection module of each scan driving unit receives a scan signal output by the scan signal output module in the previous scan driving unit; when the second selection module of the Mth scan driving unit receives the scan signal output by the scan signal output module in the (M-1)th scan driving unit, and the second selection module of the Mth scan driving unit receives a cutoff signal, the second selection module is used to control the scan signal output module of the Mth scan driving unit to stop outputting the scan signal; N

[0006] The first selection module and the second selection module can control the time when the scanning signal output module outputs the effective scanning signal and the cutoff of the effective scanning signal, so as to control the refresh frequency of the local pixels, so that the refresh frequency of some areas is higher and the refresh frequency of some areas is lower, without providing a higher refresh frequency for each area, thereby reducing the power consumption of the display panel.

[0007] For example, the scanning signal is an effective scanning signal, which can control the conduction of the corresponding transistor. When the transistor is a P-type transistor, the effective scanning signal is a low-level signal; when the transistor is an N-type transistor, the effective scanning signal is a high-level signal.

[0008] For example, the shift signal, the trigger signal, and the cutoff signal are effective shift signals, effective trigger signals, and effective cutoff signals, which can control the conduction of the corresponding transistor. When the transistor is a P-type transistor, the effective signal is a low-level signal; when the transistor is an N-type transistor, the effective signal is a high-level signal.

[0009] According to the first aspect, the first selection module is electrically connected with the first shift signal input end, the second shift signal input end, the first clock signal end, the trigger signal input end, the first level signal receiving end, the shift signal output end and the first node; the second selection module is electrically connected with the first node, the scan signal input end, the first level signal receiving end, the second level signal receiving end, the cutoff signal input end and the second node; the second node is communicated with the second level signal receiving end; the scan signal output module is electrically connected with the first node, the second node, the first clock signal end, the second clock signal end, the first level signal receiving end, the second level signal receiving end and the scan signal output end; the first selection module is used for receiving the first shift signal received by the first shift signal input end, the first clock signal of the first clock signal end, the trigger signal input by the trigger signal input end and the first level signal received by the first level signal receiving end, and outputting the shift signal through the shift signal output end in response to the first shift signal and the second shift signal received by the second shift signal input end, and controlling the signal of the first node; wherein the first shift signal input end of the current scan driving unit is electrically connected with the shift signal output end of the previous scan driving unit, the second shift signal input end is electrically connected with the shift signal output end of the next scan driving unit, the first shift signal is the shift signal output by the shift signal output end of the previous scan driving unit, and the second shift signal is the shift signal output by the shift signal output end of the next scan driving unit; the second selection module is used for receiving the first level signal received by the first level signal receiving end, the second level signal received by the second level signal receiving end and the first scan signal received by the scan signal input end, and controlling the signal of the first node in response to the cutoff signal input by the cutoff signal input end and the signal at the second node; the first scan signal is the scan signal output by the scan signal output module of the previous stage; the scan signal output module is used for receiving the first level signal received by the first level signal receiving end, the signal at the first node and the signal at the second node, the first clock signal received by the first clock signal end and the second clock signal received by the second clock signal end, and controlling the scan signal output by the scan signal output end in response to the first clock signal, the second clock signal and the second level signal received by the second level signal receiving end.

[0010] The cooperation of the first selection module and the second selection module can select and control the scan signal output by the scan signal output module, so that the refresh frequencies of different regions of the display panel are different.

[0011] According to the first aspect, or any one of the implementations of the first aspect, the first selection module comprises a shift unit and a start scanning unit; the shift unit is electrically connected with the first shift signal input end, the second shift signal input end, the first clock signal end, the first level signal receiving end and the shift signal output end; the start scanning unit is electrically connected with the trigger signal input end, the shift signal output end and the first node; the shift unit is configured to receive the first shift signal received by the first shift signal input end, the first clock signal of the first clock signal end and the first level signal received by the first level signal receiving end, and output a shift signal through the shift signal output end in response to the first shift signal and the second shift signal received by the second shift signal input end; the start scanning unit is configured to receive a trigger signal input by the trigger signal input end, and control the signal at the first node in response to the shift signal output by the shift signal output end.

[0012] The shift unit and the start scanning unit jointly complete the shifting of the shift signal and the output of the effective scanning signal. Of course, the specific structure of the first selection module is not limited thereto, and a person skilled in the art can set it according to the actual situation.

[0013] According to the first aspect, or any one of the implementations of the first aspect, the shift unit comprises an input subunit and an output subunit; the input subunit is electrically connected with the first shift signal input end and the third node; the output subunit is electrically connected with the third node, the second shift signal input end, the first level signal receiving end, the first clock signal end and the shift signal output end; the input subunit is configured to receive the first shift signal received by the first shift signal input end, and control the signal of the third node in response to the first shift signal; the output subunit is configured to receive the first clock signal of the first clock signal end, and control the shift signal output end to output a shift signal in response to the signal of the third node; or, the output subunit is configured to receive the first level signal of the first level signal receiving end, and control the shift signal output end to output a shift signal in response to the second shift signal of the second shift signal input end.

[0014] The input subunit and the output subunit jointly complete the shifting of the shift signal. Of course, the specific structure of the shift unit is not limited thereto, and a person skilled in the art can set it according to the actual situation.

[0015] According to the first aspect, or any one of the implementations of the first aspect, the input subunit comprises a first transistor, the gate of the first transistor and the first pole of the first transistor are both electrically connected with the first shift signal input end, and the second pole of the first transistor is electrically connected with the third node.

[0016] That is, the structure of the input subunit is simple, and thus the structure of the scan driving unit is simple, which is conducive to the narrow frame design of the display panel.

[0017] According to the first aspect, or any one of the implementations of the first aspect, the output subunit comprises a second transistor, a third transistor, a fourth transistor and a first capacitor; the gate of the second transistor, the first pole of the first capacitor and the first pole of the third transistor are electrically connected with the third node, the first pole of the second transistor is electrically connected with the first clock signal terminal, the second pole of the second transistor, the second pole of the first capacitor and the first pole of the fourth transistor are electrically connected with the shift signal output terminal, the gate of the third transistor and the gate of the fourth transistor are electrically connected with the second shift signal input terminal, and the second pole of the third transistor and the second pole of the fourth transistor are electrically connected with the first level signal receiving terminal.

[0018] That is, the structure of the output subunit is simple, and thus the structure of the scan driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0019] According to the first aspect, or any one of the implementations of the first aspect, the start scan unit comprises a fifth transistor, the gate of the fifth transistor is electrically connected with the shift signal output terminal, the first pole of the fifth transistor is electrically connected with the trigger signal input terminal, and the second pole of the fifth transistor is electrically connected with the first node.

[0020] That is, the structure of the start scan unit is simple, and thus the structure of the scan driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0021] According to the first aspect, or any one of the implementations of the first aspect, the second selection module comprises a cutoff scan unit, a first level signal input unit and a second level signal input unit; the cutoff scan unit is electrically connected with the first node, the scan signal input terminal and the fourth node; the first level signal input unit is electrically connected with the fourth node, the first level signal receiving terminal and the cutoff signal input terminal; the second level signal input unit is electrically connected with the fourth node, the second node and the second level signal receiving terminal; the second level signal input unit is configured to receive the second level signal received by the second level signal receiving terminal, and to control the signal at the fourth node in response to the second level signal; the first level signal input unit is configured to receive the first level signal received by the first level signal receiving terminal, and to change the signal at the fourth node in response to the cutoff signal input by the cutoff signal input terminal; and the cutoff scan unit is configured to receive the first scan signal input by the scan signal input terminal, and to control the signal at the first node in response to the signal at the fourth node.

[0022] The cutoff scan unit, the first level signal input unit and the second level signal input unit jointly cut off the output of the effective scan signal. Of course, the specific structure of the second selection module is not limited thereto, and a person skilled in the art can set it according to the actual situation.

[0023] According to the first aspect, or any one of the implementations of the first aspect, the cutoff scanning unit comprises a sixth transistor and a seventh transistor; a gate of the sixth transistor is electrically connected with the fourth node; a gate of the seventh transistor and a first electrode of the seventh transistor are electrically connected with the scanning signal input end; a second electrode of the seventh transistor is electrically connected with a first electrode of the sixth transistor; and a second electrode of the sixth transistor is electrically connected with the first node.

[0024] That is, the structure of the cutoff scanning unit is simple, and thus the structure of the scanning driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0025] According to the first aspect, or any one of the implementations of the first aspect, the first level signal input unit comprises an eighth transistor; a gate of the eighth transistor is electrically connected with the cutoff signal input end; a first electrode of the eighth transistor is electrically connected with the fourth node; and a second electrode of the eighth transistor is electrically connected with the first level signal receiving end.

[0026] That is, the structure of the first level signal input unit is simple, and thus the structure of the scanning driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0027] According to the first aspect, or any one of the implementations of the first aspect, the second level signal input unit comprises a ninth transistor; a gate of the ninth transistor is electrically connected with the second node; a first electrode of the ninth transistor is electrically connected with the second level signal receiving end; and a second electrode of the ninth transistor is electrically connected with the fourth node.

[0028] That is, the structure of the second level signal input unit is simple, and thus the structure of the scanning driving unit is simple, which is beneficial to the narrow frame design of the display panel.

[0029] According to the first aspect, or any one of the implementations of the first aspect, the scan signal output module comprises: an input unit, electrically connected with the first node, the first clock signal terminal and the fifth node; a first control unit, electrically connected with the first clock signal terminal, the second node and the sixth node; a second control unit, electrically connected with the first level signal receiving terminal, the second clock signal terminal, the fifth node and the sixth node; and an output unit, electrically connected with the first level signal receiving terminal, the second level signal receiving terminal, the second clock signal terminal, the fifth node, the sixth node and the scan signal output terminal. The input unit is configured to receive a signal at the first node and control a signal at the fifth node in response to a first clock signal received by the first clock signal terminal. The first control unit is configured to receive the first clock signal received by the first clock signal terminal and a signal at the second node, and control a signal at the sixth node in response to the signal at the fifth node and the first clock signal received by the first clock signal terminal. The second control unit is configured to receive a first level signal received by the first level signal receiving terminal, and change the signal at the fifth node in response to a signal at the sixth node and a second clock signal received by the second clock signal terminal. The output unit is configured to receive the first level signal received by the first level signal receiving terminal, and control a scan signal output by the scan signal output terminal in response to the signal at the sixth node. Alternatively, the output module is configured to receive the second clock signal received by the second clock signal terminal, and control the scan signal output by the scan signal output terminal in response to the signal at the fifth node.

[0030] The scan signal output module provided by the embodiments of the present application has fewer signal terminals, and accordingly, fewer signal lines are provided for the signal terminals, and the structure is simple, thereby making the structure of the scan driving unit simple, which is conducive to the narrow frame design of the display panel and low in cost.

[0031] According to the first aspect, or any one of the implementations of the first aspect, the input unit comprises a tenth transistor. The gate of the tenth transistor is electrically connected with the first clock signal terminal, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the fifth node.

[0032] The signal at the fifth node can be controlled by one transistor, and the structure of the input unit is simple, thereby making the structure of the scan driving unit simple.

[0033] According to the first aspect, or any one of the implementations of the first aspect, the first control unit comprises an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is electrically connected with the first clock signal terminal, the first pole of the eleventh transistor is electrically connected with the second node, and the second pole of the eleventh transistor and the second pole of the twelfth transistor are both electrically connected with the sixth node. The gate of the twelfth transistor is electrically connected with the fifth node, and the first pole of the twelfth transistor is electrically connected with the first clock signal terminal.

[0034] The sixth node signal is controlled by two transistors, the first control unit is simple in structure, and thus the scan driving unit is simple in structure.

[0035] According to the first aspect, or any one of the implementations of the first aspect, the second control unit includes a thirteenth transistor and a fourteenth transistor; a gate of the thirteenth transistor is electrically connected with the second clock signal terminal, a first pole of the thirteenth transistor is electrically connected with the fifth node, and a second pole of the thirteenth transistor is electrically connected with a first pole of the fourteenth transistor; a gate of the fourteenth transistor is electrically connected with the sixth node, and a second pole of the fourteenth transistor is electrically connected with the first level signal receiving terminal.

[0036] The second control unit is simple in structure, and thus the scan driving unit is simple in structure.

[0037] According to the first aspect, or any one of the implementations of the first aspect, the output unit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second capacitor and a third capacitor; a gate of the fifteenth transistor is electrically connected with the second level signal receiving terminal, a first pole of the fifteenth transistor is electrically connected with the fifth node, and a second pole of the fifteenth transistor is electrically connected with a first pole of the second capacitor and a gate of the sixteenth transistor respectively; a second pole of the second capacitor, a second pole of the sixteenth transistor and a first pole of the seventeenth transistor are electrically connected with the scan signal output terminal; a first pole of the sixteenth transistor is electrically connected with the second clock signal terminal; a gate of the seventeenth transistor and a first pole of the third capacitor are electrically connected with the sixth node, and a second pole of the seventeenth transistor and a second pole of the third capacitor are electrically connected with the first level signal receiving terminal.

[0038] The output unit is simple in structure, and thus the scan driving unit is simple in structure, and the capacitors are arranged, so that signals of the gates of the fifteenth transistor and the sixteenth transistor are more stable.

[0039] According to the first aspect, or any one of the implementations of the first aspect, the scan driving circuit further includes a first clock signal line and a second clock signal line; the first clock signal terminal of the odd-stage scan driving unit is electrically connected with the first clock signal line, and the second clock signal terminal of the odd-stage scan driving unit is electrically connected with the second clock signal line; the first clock signal terminal of the even-stage scan driving unit is electrically connected with the second clock signal line, and the second clock signal terminal of the even-stage scan driving unit is electrically connected with the first clock signal line.

[0040] The first clock signal line and the second clock signal line do not need to be arranged for each scan driving unit, the number of clock signal lines is reduced, and the structure is simple.

[0041] In a second aspect, an embodiment of the present application provides a display panel, comprising the scanning driving circuit of the first aspect and any one of the implementation manners of the first aspect, the plurality of pixels arranged in an array, and the plurality of scan line groups; the scan line group comprises at least one scan signal line; the scan signal lines of the plurality of scan line groups are electrically connected with the scan signal output modules of the plurality of scan driving units respectively; different pixel rows correspond to different scan line groups, and each pixel in the same row is electrically connected with the scan signal line of the same scan line group; the scan signal output by the scan signal output module is provided to the pixel through the scan signal line.

[0042] The second aspect corresponds to the first aspect and any one of the implementation manners of the first aspect. The technical effects corresponding to the second aspect can be referred to the technical effects corresponding to the first aspect and any one of the implementation manners of the first aspect, which will not be described herein.

[0043] According to the second aspect, the number of the scanning driving circuits is two, and the two scanning driving circuits comprise a first scanning driving circuit and a second scanning driving circuit; each row of pixels comprises a first pixel group and a second pixel group, and the first pixel group and the second pixel group each comprise a plurality of pixels; the scan signal line comprises a first scan signal sub-line segment and a second scan signal sub-line segment; each pixel of the first pixel group is electrically connected with the same first scan signal sub-line segment, and each pixel of the second pixel group is electrically connected with the same second scan signal sub-line segment; the scan signal output by the scan signal output module of the plurality of scan driving units in the first scanning driving circuit is provided to each pixel of the first pixel group through the first scan signal sub-line segment, and the scan signal output by the scan signal output module of the plurality of scan driving units in the second scanning driving circuit is provided to each pixel of the second pixel group through the second scan signal sub-line segment.

[0044] The first scanning driving circuit can control different regions of the left part of the display area of the display panel to realize different refresh frequencies, and the second scanning driving circuit can control different regions of the right part of the display area of the display panel to realize different refresh frequencies.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, which comprises the display panel of the second aspect and any one of the implementation manners of the second aspect. The third aspect corresponds to the second aspect and any one of the implementation manners of the second aspect. The technical effects corresponding to the third aspect can be referred to the technical effects corresponding to the second aspect and any one of the implementation manners of the second aspect, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 One of the application scenarios of the electronic device provided by the embodiment of the present application is that

[0047] Figure 2 The structural schematic diagram of the electronic device provided by the embodiment of the present application is shown in FIG. 1.

[0048] Figure 3 A structural schematic diagram of a display panel provided for an embodiment of the present application;

[0049] Figure 4 A structural schematic diagram of a pixel circuit provided for an embodiment of the present application;

[0050] Figure 5 A structural schematic diagram of a display panel provided for an embodiment of the present application;

[0051] Figure 6 A structural schematic diagram of a display panel provided for an embodiment of the present application;

[0052] Figure 7 A structural schematic diagram of a scan driving unit provided for an embodiment of the present application;

[0053] Figure 8 A timing diagram of signals of a scan driving unit provided for an embodiment of the present application, starting from the Nth row;

[0054] Figure 9 Specific signals at each position of a scan driving unit ASG in a first stage provided for an embodiment of the present application;

[0055] Figure 10 Specific signals at each position of a scan driving unit ASG in a second stage provided for an embodiment of the present application;

[0056] Figure 11 Specific signals at each position of a scan driving unit ASG in a third stage provided for an embodiment of the present application;

[0057] Figure 12 Specific signals at each position of a scan driving unit ASG in an Nth stage provided for an embodiment of the present application;

[0058] Figure 13 Specific signals at each position of a scan driving unit ASG in an (N+1)th stage provided for an embodiment of the present application;

[0059] Figure 14 A timing diagram of signals of a scan driving unit provided for an embodiment of the present application, ending from the Mth row;

[0060] Figure 15 Specific signals at each position of a (M-1)th stage scan driving unit ASG(M-1) and a Mth stage scan driving unit ASGM in a (M-1)th stage provided for an embodiment of the present application;

[0061] Figure 16The specific signals of the Mth-stage scanning driving unit ASGM at each position in the Mth stage are provided for the embodiments of the present application.

[0062] Figure 17 A timing diagram of each signal in the scanning driving circuit is provided for the embodiments of the present application.

[0063] Figure 18 A refresh process of the display screen is provided for the embodiments of the present application.

[0064] Figure 19 Another structural schematic diagram of the display panel is provided for the embodiments of the present application.

[0065] Figure 20 Another structural schematic diagram of the display panel is provided for the embodiments of the present application.

[0066] Figure 21 One of the application scenarios of the electronic device is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0068] The term “and / or” in the present document is merely used to describe an association relationship of associated objects, and indicates that three relationships may exist, for example, A and / or B may represent three cases of existence of A alone, existence of A and B simultaneously, and existence of B alone.

[0069] The terms “first” and “second” and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0070] In the embodiments of the present application, the words “exemplary” or “for example” are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Rather, the use of the words “exemplary” or “for example” is intended to present concepts in a specific manner.

[0071] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0072] Figure 1 An application scenario is shown by way of example. As shown in Figure 1 , the electronic device 100 displays various contents through the display panel. In Figure 1 , the display area of the display panel displaying the contents is divided into three areas: a status bar 101, a video playing area 102, and a static content display area 103. The status bar 101 is used to display status information, such as displaying the remaining battery power, time, and the like. The video playing area 102 is used to display dynamic contents, such as playing videos and the like. The static content display area 103 is used to display static contents, such as displaying text, pictures, and the like.

[0073] In a case similar to Figure 1 , if the same refresh rate is used to refresh the display contents of all areas, the power consumption of the display panel will be relatively high, but the display quality will not be significantly improved.

[0074] Based on this, the embodiments of the present application provide a scanning driving circuit, a display panel applying the scanning driving circuit, and an electronic device applying the display panel. The electronic device can be a smart terminal including a display panel, such as a mobile phone, a tablet computer, a notebook computer, a personal digital assistant (PDA), a vehicle-mounted computer, a smart wearable device, a smart home device, and the like. The embodiments of the present application do not limit the specific form of the electronic device.

[0075] The display contents of areas with unchanged display contents or displaying static contents such as text and pictures are refreshed at a relatively low refresh frequency, and the display contents of areas with real-time changing display contents or displaying dynamic contents such as videos are refreshed at a relatively high refresh frequency. In other words, according to the different display contents of different areas, different refresh frequencies are selected to refresh the display contents. In this way, the refresh frequency of areas such as areas with unchanged display contents or displaying static contents such as text and pictures is relatively low. Since the display contents of these areas are unchanged or displaying static contents such as text and pictures, although the refresh frequency is reduced, the display quality is not significantly affected, thereby reducing the power consumption of the display panel while maintaining the display quality, and further improving the endurance of the electronic device.

[0076] The principles that different refresh frequencies can be achieved in different areas of the display panel provided by the embodiments of the present application will be introduced below in combination with an electronic device. For reference, Figure 2Let's take a mobile phone as an example to illustrate this.

[0077] like Figure 2 As shown, the mobile phone 100 includes a display panel 10, a back cover 20, and a mid-frame 30. The display panel 10, back cover 20, and mid-frame 30 can form a receiving cavity. A printed circuit board, a battery, and functional components (not shown) are disposed within the receiving cavity. The functional components include, for example, a display driver chip and a processor. The display driver chip and processor are disposed on the printed circuit board, and are electrically connected through the printed circuit board. The processor sends corresponding signals to the display driver chip to cause the display driver chip to drive the display panel 10 to display a screen.

[0078] The material of the back cover 20 may include, for example, opaque materials such as plastic, vegan leather, and fiberglass; or it may include light-transmitting materials such as glass. This application does not limit the material of the back cover 20.

[0079] Display panel 10 includes, for example, a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display panel, and an LED display panel, wherein the LED display panel includes, for example, a micro-LED display panel and a mini-LED display panel. This application embodiment does not limit the type of display panel 10. The following description uses an OLED display panel as an example.

[0080] See Figure 3 , Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 3 As shown, the display panel 10 includes a display area AA and a non-display area NAA, wherein the non-display area NAA is located on at least one side of the display area AA. Figure 3 The explanation uses the non-display area NAA surrounding the display area AA as an example. The display area AA of the display panel 10 contains an array of pixels 11, multiple scan line groups 12, and multiple data lines 13. Each pixel 11 includes a pixel circuit 111 and a display unit (also called a light-emitting element, etc.) 112. Each data line 13 corresponds one-to-one with a pixel circuit 111 in a column of pixels 11; that is, one data line 13 corresponds to one pixel circuit 111 in one column of pixels 11. Each scan line group 12 corresponds one-to-one with a pixel circuit 111 in a row of pixels 11; that is, one scan line group 12 corresponds to one pixel circuit 111 in one row of pixels 11.

[0081] Combination Figure 4 , Figure 4The pixel circuit 111 is a structural schematic diagram of a pixel circuit, and the pixel circuit 111 may, for example, include 7T1C (7 transistors and 1 storage capacitor), that is, the pixel circuit 111 may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light-emitting control transistors M6 and M7, and a storage capacitor Cst.

[0082] It can be understood that the specific structure of the pixel circuit 111 includes but is not limited to the above example, and in other optional embodiments, the pixel circuit 111 may also be in other settings (that is, include a larger number of transistors or a smaller number of transistors, and include a larger number of storage capacitors or a smaller number of storage capacitors) as long as the display unit 112 can be driven to emit light.

[0083] The driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, the light-emitting control transistors M6 and M7 are all transistors with silicon material as an active layer. The silicon material may include polycrystalline silicon material and the like, and the polycrystalline silicon material may include low temperature polycrystalline silicon (LTPS) material. The transistors are, for example, P-type transistors.

[0084] Of course, this is not enough to limit the present application, and in other optional embodiments of the present application, the reset transistor M4 and the threshold compensation transistor M3 may be transistors with oxide semiconductor material as an active layer. The oxide semiconductor material may include indium gallium zinc oxide (IGZO) material, and the transistors are, for example, N-type transistors. The driving transistor M1, the data writing transistor M2, the reset transistor M5, the light-emitting control transistors M6 and M7 are transistors with silicon material as an active layer, and the transistors are, for example, P-type transistors. That is, the LTPS transistor and the IGZO transistor are integrated on one substrate to form a low temperature polycrystalline oxide (LTPO) display panel 10.

[0085] The embodiments of the present application are described by taking the driving transistor M1, the data writing transistor M2, the threshold compensation transistor M3, the reset transistors M4 and M5, the light-emitting control transistors M6 and M7 as transistors with LTPS material as an active layer, and the transistors are, for example, P-type transistors as an example.

[0086] Continuing to refer to Figure 4The pixel circuit 111 further includes an initialization signal terminal Vref, a first power supply terminal PVDD, a second power supply terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3, and an emission control signal terminal Emit. The first electrode of the emission control transistor M6 is electrically connected to the first power supply terminal PVDD, the first electrode of the data write transistor M2 is electrically connected to the data signal terminal Data, the gate electrode of the data write transistor M2 and the gate electrode of the threshold compensation transistor M3 are both electrically connected to the second scan signal terminal Scan2, the first electrodes of the reset transistors M4 and M5 are respectively electrically connected to the initialization signal terminal Vref (the corresponding initialization signal terminals of the two can be the same or different), the gate electrode of the reset transistor M4 can be electrically connected to the first scan signal terminal Scan1, the gate electrode of the reset transistor M5 can be electrically connected to the third scan signal terminal Scan3, the gate electrodes of the emission control transistors M6 and M7 can be respectively electrically connected to the emission control signal terminal Emit, the emission control transistor M7 is electrically connected to the anode of the display unit 112, and the cathode of the display unit 112 is electrically connected to the second power supply terminal PVEE.

[0087] Continuing to refer to Figure 3 Each scan line group 12 includes a scan signal line 121 and an emission control signal line 122.

[0088] The pixel circuit 111 in a column of pixels 11 corresponds to one data line 13, that is, the data signal terminal Data in the pixel circuit 111 of each pixel 11 in the same column is electrically connected to the same data line 13. The pixel circuit 111 in a row of pixels 11 corresponds to one scan line group 12, that is, the second scan signal terminal Scan2 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to the row, the emission control signal terminal Emit in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the emission control signal line 122 corresponding to the row, the first scan signal terminal Scan1 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to another row (such as the row above), and the third scan signal terminal Scan3 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to another row (such as the row below).

[0089] It should be noted that, in order to ensure the simplicity and clarity of the circuit, Figure 3 The first scan signal terminal Scan1 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to another row, and the third scan signal terminal Scan3 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the scan signal line 121 corresponding to another row.

[0090] That is, the scan signal transmitted by the scan signal line 121 can control the turn-on or turn-off of the data writing transistor M2 and the threshold compensation transistor M3, that is, the scan signal transmitted by the scan signal line 121 corresponding to the row where the data writing transistor M2 and the threshold compensation transistor M3 are located can control the turn-on or turn-off of the data writing transistor M2 and the threshold compensation transistor M3; the scan signal transmitted by the scan signal line 121 corresponding to the other row (such as the previous row) can control the turn-on or turn-off of the reset transistor M4, and the scan signal transmitted by the scan signal line 121 corresponding to the other row (such as the next row) can control the turn-on or turn-off of the reset transistor M5; the light emission control signal transmitted by the light emission control signal line 122 can control the turn-on or turn-off of the light emission control transistors M6 and M7 on the light emission branch.

[0091] When the scan signal line 121 provides the scan signal to the corresponding row of pixels 11, the pixels 11 that need to be refreshed can be selected. The data line 13 provides the data signal to the corresponding column of pixel circuits 111, and the data signal is refreshed to the pixels 11 selected by the scan signal. The light emission control signal line provides the light emission control signal to the corresponding row of pixels 11 to control the light emission time of the pixels 11. The pixel circuit 111 generates a driving current to drive the display unit 112 to emit light under the action of the scan signal, the light emission control signal and the data signal. The specific principle of the pixel circuit 111 generating a driving current to drive the display unit 112 to emit light based on the data signal, the light emission control signal and the scan signal is similar to that of the 7T1C pixel circuit in the prior art, and will not be described here.

[0092] The above-mentioned refreshing of different regions of the display panel is refreshing the pixels 11 in different regions of the display panel, that is, providing new data signals to the pixel circuits 111 of the pixels 11 in the region, so that the data signal in the pixel circuit 111 is updated (that is, the potential of the gate of the driving transistor M1 is refreshed), so that the driving current of the driving transistor M1 is refreshed. When the pixel 11 is not refreshed, the data signal in the pixel circuit 111 of the pixel 11 remains the data signal of the previous frame, and the driving current remains the driving current of the previous frame when emitting light. When the pixel 11 is not refreshed, the corresponding transistor remains off, and no current flows, so the power consumption is reduced.

[0093] Continuing to refer to Figure 3A driving circuit 14 is provided in the non-display area NAA of the display panel 10. The driving circuit 14 may include, for example, a scan driving circuit and a light emission control driving circuit. The scan driving circuit includes multiple scan signal output terminals, and the light emission control driving circuit includes multiple light emission control signal output terminals. The multiple scan signal output terminals of the scan driving circuit are electrically connected one-to-one with multiple scan signal lines 121 of the display area AA, and the multiple light emission control signal output terminals of the light emission control driving circuit are electrically connected one-to-one with the light emission control signal lines 122 of the display area AA. The scan driving circuit transmits the scan signals to the scan signal lines 121 through the scan signal output terminals, and the light emission control driving circuit transmits the light emission control signals to the light emission control signal lines 122 through the light emission control signal output terminals.

[0094] It should be noted that the driving circuit 14 can be located on one side of the display area AA, such as... Figure 3 As shown. The driving circuit 14 can also be located on opposite sides of the display area AA, meaning that driving circuits 14 are located on both opposite sides of the display area AA, such as... Figure 5 As shown. That is, the scanning drive circuit can be located on one side of the display area AA, or on both opposite sides of the display area AA; the light emission control drive circuit can be located on one side of the display area AA, or on both opposite sides of the display area AA. For example, when the scanning drive circuit in drive circuit 14 is located on both opposite sides of the display area AA (i.e., scanning drive circuits are located on both opposite sides of the display area AA), the scanning signal output terminals of both scanning drive circuits are electrically connected to a scanning signal line 121 to provide scanning signals to the scanning signal line 121. This arrangement reduces the voltage drop of the scanning signal. When the light emission control drive circuit in drive circuit 14 is located on both opposite sides of the display area AA (i.e., light emission control drive circuits are located on both opposite sides of the display area AA), the light emission control signal output terminals of both light emission control drive circuits are electrically connected to a light emission control signal line 122 to provide light emission control signals to the light emission control signal line 122. This arrangement reduces the voltage drop of the light emission control signal.

[0095] See Figure 6 , Figure 6 This is a schematic diagram of another display panel provided in an embodiment of this application. For example... Figure 6 As shown, the scan driving circuit 14a (the driving circuit that provides scan signals to pixel 11) includes n cascaded scan driving units ASG, for example, it may include n scan driving units ASG1 to ASGn, where n≥2. The specific value of n can be set by those skilled in the art according to the actual situation, and is not limited here.

[0096] Each stage of the scan driving unit ASG includes a first clock signal end SCK1, a second clock signal end SCK2, a trigger signal input end STV, a cutoff signal input end Close, a first level signal receiving end VGH, a second level signal receiving end VGL, a first shift signal input end Scan input, a second shift signal input end Scan reset, a shift signal output end Scanout, a scan signal input end GIN, and a scan signal output end GOUT.

[0097] The scan signal output end GOUT of each stage of the scan driving unit ASG, except the last stage of the scan driving unit ASGn, is electrically connected to the scan signal input end GIN of the next stage of the scan driving unit ASG. The scan signal input end GIN of the first stage of the scan driving unit ASG1 is electrically connected to a scan signal input line (not shown in the figure), which is used to transmit the scan signal from the display driving chip to the scan signal input end GIN of the first stage of the scan driving unit ASG1.

[0098] The shift signal output end Scanout of each stage of the scan driving unit ASG, except the first stage of the scan driving unit ASG1 and the last stage of the scan driving unit ASGn, is electrically connected to the first shift signal input end Scan input of the next stage of the scan driving unit ASG and the second shift signal input end Scan reset of the previous stage of the scan driving unit ASG. The shift signal output end Scanout of the first stage of the scan driving unit ASG1 is only electrically connected to the first shift signal input end Scan input of the second stage of the scan driving unit ASG2, and the shift signal output end Scanout of the last stage of the scan driving unit ASGn is only electrically connected to the second shift signal input end Scan reset of the (n-1)th stage of the scan driving unit ASG2. The first shift signal input end Scan input of the first stage of the scan driving unit ASG1 is electrically connected to a shift signal line (not shown in the figure), which is used to transmit the shift signal from the display driving chip to the first shift signal input end Scan input of the first stage of the scan driving unit ASG1. In order to reduce the number of signal lines, the scan driving circuit 14a further includes at least one dummy scan driving unit ASG dummy, wherein, Figure 6The scan driving circuit 14a further comprises a dummy scan driving unit ASG dummy. The dummy scan driving unit ASG dummy is cascaded with the n cascaded scan driving units ASG, and the second shift signal input end Scan reset of the last scan driving unit ASGn is electrically connected with the shift signal output end Scan out of the dummy scan driving unit ASG dummy, so as to provide the shift signal for the second shift signal input end Scan reset of the last scan driving unit ASGn through the shift signal output end Scan out of the dummy scan driving unit ASG dummy. The second shift signal input end Scan reset of the dummy scan driving unit ASG dummy is also electrically connected with the scan signal input line, which is used to transmit the scan signal from the display driving chip to the scan signal input end GIN of the first scan driving unit ASG1 and the second shift signal input end Scan reset of the dummy scan driving unit ASG dummy.

[0099] The dummy scan driving unit ASG dummy has the same circuit structure as the other scan driving units ASG, but does not provide the scan signal for the pixels 11 in the display area AA.

[0100] The scan driving unit ASG outputs the shift signal through the shift signal output end Scan out and the scan signal through the scan signal output end GOUT according to the first clock signal input from the first clock signal end SCK1, the second clock signal input from the second clock signal end SCK2, the trigger signal input from the trigger signal input end STV, the cutoff signal input from the cutoff signal input end Close, the first level signal input from the first level signal receiving end VGH, the second level signal input from the second level signal receiving end VGL, the scan signal (also referred to as the first scan signal) input from the scan signal input end GIN, the shift signal (also referred to as the first shift signal) input from the first shift signal input end Scan input, and the shift signal (also referred to as the second shift signal) input from the second shift signal input end Scan reset, so as to provide the scan signal for the scan signal line 121 through the scan signal output end GOUT, and provide the scan signal to each pixel 11 through the scan signal line 121.

[0101] The scan driving circuit 14a further comprises a first clock signal line SCKL1, a second clock signal line SCKL2, a first voltage level signal line VGHL, a second voltage level signal line VGLL, a trigger signal line STVL and a close signal line CloseL in the non-display area NAA, and the clock signal outputted by the first clock signal line SCKL1 and the clock signal outputted by the second clock signal line SCKL2 are two opposite clock signals. The first voltage level signal receiving end VGH of each scan driving unit ASG in the scan driving circuit 14a is electrically connected to the same first voltage level signal line VGHL, and the second voltage level signal receiving end VGL of each scan driving unit ASG in the scan driving circuit 14a is electrically connected to the same second voltage level signal line VGLL. The first clock signal end SCK1 of the odd-stage scan driving unit ASG is electrically connected to the first clock signal line SCKL1, and the second clock signal end SCK2 of the odd-stage scan driving unit ASG is electrically connected to the second clock signal line SCKL2; the first clock signal end SCK1 of the even-stage scan driving unit ASG is electrically connected to the second clock signal line SCKL2, and the second clock signal end SCK2 of the even-stage scan driving unit ASG is electrically connected to the first clock signal line SCKL1. The trigger signal input end STV of each scan driving unit ASG in the scan driving circuit 14a is electrically connected to the same trigger signal line STVL, and the close signal input end Close of the scan driving unit ASG is electrically connected to the close signal line CloseL. The first clock signal line SCKL1, the second clock signal line SCKL2, the first voltage level signal line VGHL, the second voltage level signal line VGLL, the trigger signal line STVL and the close signal line CloseL are used for receiving the first clock signal, the second clock signal, the first voltage level signal, the second voltage level signal, the trigger signal and the close signal provided by the display driving chip, and transmitting the first clock signal, the second clock signal, the first voltage level signal, the second voltage level signal, the trigger signal and the close signal to the signal ends connected thereto, respectively.

[0102] In combination Figure 7 , Figure 7 A structural schematic diagram of a scan driving unit provided by the embodiment of the application is shown. The scan driving unit ASG of the scan driving circuit 14a further comprises a first selection module 141, a second selection module 142 and a scan signal output module 143.

[0103] The first selection module 141 comprises a shift unit 1411 and a start scan unit 1412.

[0104] The shift unit 1411 includes an input sub-unit 14111 and an output sub-unit 14112. The input sub-unit 14111 can include a first transistor T1, a gate of the first transistor T1 and a first electrode of the first transistor T1 are electrically connected with a first shift signal input end Scan input, a second electrode of the first transistor T1 is electrically connected with a third node N3. The output sub-unit 14112 can include a second transistor T2, a third transistor T3, a fourth transistor T4 and a first capacitor C1, a gate of the second transistor T2, a first electrode of the first capacitor C1 and a first electrode of the third transistor T3 are electrically connected with the third node N3, a first electrode of the second transistor T2 is electrically connected with a first clock signal end SCK1, a second electrode of the second transistor T2, a second electrode of the first capacitor C1 and a first electrode of the fourth transistor T4 are electrically connected with a shift signal output end Scan out, a gate of the third transistor T3 and a gate of the fourth transistor T4 are electrically connected with a second shift signal input end Scan reset, a second electrode of the third transistor T3 and a second electrode of the fourth transistor T4 are electrically connected with a first level signal receiving end VGH.

[0105] The start scanning unit 1412 can include a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected with the shift signal output end Scan out, a first electrode of the fifth transistor T5 is electrically connected with a trigger signal input end STV, a second electrode of the fifth transistor T5 is electrically connected with a first node N1.

[0106] The second selection module 142 can include a cutoff scanning unit 1421, a first level signal input unit 1422 and a second level signal input unit 1423.

[0107] The cutoff scanning unit 1421 can include a sixth transistor T6 and a seventh transistor T7, a gate of the sixth transistor T6 is electrically connected with a fourth node, a gate of the seventh transistor T7 and a first electrode of the seventh transistor T7 are electrically connected with a scanning signal input end GIN, a second electrode of the seventh transistor T7 is electrically connected with a first electrode of the sixth transistor T6, a second electrode of the sixth transistor T6 is electrically connected with the first node N1.

[0108] The first level signal input unit 1422 includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected with a cutoff signal input end Close, a first electrode of the eighth transistor T8 is electrically connected with a fourth node N4, a second electrode of the eighth transistor T8 is electrically connected with the first level signal receiving end VGH.

[0109] The second level signal input unit 1423 includes a ninth transistor T9, a gate of the ninth transistor T9 is electrically connected with the second node N2, a first electrode of the ninth transistor T9 is electrically connected with the second level signal receiving end VGL, and a second electrode of the ninth transistor T9 is electrically connected with the fourth node N4. Wherein, the second node N2 is communicated with the second level signal receiving end VGL, that is, the signal at the second node N2 is the second level signal received by the second level signal receiving end VGL.

[0110] The scan signal output module 143 can include an input unit 1431, a first control unit 1432, a second control unit 1433 and an output unit 1434.

[0111] The input unit 1431 can include a tenth transistor T10, a gate of the tenth transistor T10 is electrically connected with the first clock signal end SCK1, a first electrode of the tenth transistor T10 is electrically connected with the first node N1, and a second electrode of the tenth transistor T10 is electrically connected with the fifth node N5.

[0112] The first control unit 1432 can include an eleventh transistor T11 and a twelfth transistor T12, a gate of the eleventh transistor T11 is electrically connected with the first clock signal end SCK1, a first electrode of the eleventh transistor T11 is electrically connected with the second node N2, both a second electrode of the eleventh transistor T11 and a second electrode of the twelfth transistor T12 are electrically connected with the sixth node N6, a gate of the twelfth transistor T12 is electrically connected with the fifth node N5, and a first electrode of the twelfth transistor T12 is electrically connected with the first clock signal end SCK1.

[0113] The second control unit 1433 can include a thirteenth transistor T13 and a fourteenth transistor T14, a gate of the thirteenth transistor T13 is electrically connected with the second clock signal end SCK2, a first electrode of the thirteenth transistor T13 is electrically connected with the fifth node N5, a second electrode of the thirteenth transistor T13 is electrically connected with a first electrode of the fourteenth transistor T14, a gate of the fourteenth transistor T14 is electrically connected with the sixth node N6, and a second electrode of the fourteenth transistor T14 is electrically connected with the first level signal receiving end VGH.

[0114] The output unit 1434 can include a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a second capacitor C2 and a third capacitor C3, the gate of the fifteenth transistor T15 is electrically connected with the second level signal receiving end VGL, the first electrode of the fifteenth transistor T15 is electrically connected with the fifth node N5, the second electrode of the fifteenth transistor T15 is electrically connected with the first electrode of the second capacitor C1 and the gate of the sixteenth transistor T16 respectively, the second electrode of the second capacitor C2, the second electrode of the sixteenth transistor T16 and the first electrode of the seventeenth transistor T17 are electrically connected with the scanning signal output end GOUT, the first electrode of the sixteenth transistor T16 is electrically connected with the second clock signal end SCK2, the gate of the seventeenth transistor T17 and the first electrode of the third capacitor C3 are electrically connected with the sixth node N6, and the second electrode of the seventeenth transistor T17 and the second electrode of the third capacitor C3 are electrically connected with the first level signal receiving end VGH.

[0115] The structure of the scan driving unit ASG of the scan driving circuit 14 is specifically introduced above. It should be noted that the structures of the first selection module 141, the second selection module 142 and the scan signal output module 143 are not limited to the above examples, and a person skilled in the art can set the specific structures of the first selection module 141, the second selection module 142 and the scan signal output module 143 according to the actual situation, as long as the first selection module 141 controls the scan signal output module of the Nth stage scan driving unit to start outputting the scan signal, and the second selection module controls the scan signal output module of the Mth stage scan driving unit to stop outputting the scan signal, the control of the refresh frequency of different regions of the display panel is within the protection scope of the present application.

[0116] The working process of the scan driving unit ASG of the scan driving circuit 14a to realize local scanning is introduced below. Taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 as P-type transistors, and taking the first level signal received by the first level signal receiving end VGH as a high level signal and the second level signal received by the second level signal receiving end VGL as a low level signal as examples.

[0117] First, the specific description process of the scan driving circuit 14a starting scanning from the Nth row is described.

[0118] Figure 8The timing diagram of each signal scanned by the scan drive unit starting from row N is shown. The following section, in conjunction with this timing diagram, discusses... Figure 7 The operation of the scan drive unit 14a of the scan drive circuit 14 shown will be explained.

[0119] In the first stage T1, i.e., the low-level shift signal input stage: see Figure 9 , Figure 9 This diagram illustrates the specific signals at each position of the scan drive unit ASG during the first stage. Thick solid lines represent the first level signal (high level), and thick dashed lines represent the second level signal (low level). The first shift signal input terminal (Scan input) of the first-stage scan drive unit ASG1 receives the shift signal transmitted from the shift signal line (the shift signal sent to the shift signal line from the display driver chip side). When this shift signal changes from high to low, the first transistor T1 turns on. The low-level shift signal received at the first shift signal input terminal (Scan input) is written to the third node N3, pulling N3 low and charging the first capacitor C1, turning on the second transistor T2. Since the first clock signal received by the second transistor T2 is high at this time, the shift signal output terminal (Scan out) outputs a high-level signal. At this time, the third transistor T3, fourth transistor T4, and fifth transistor T5 are all off. Because the sixth transistor T6 is normally open, a low-level signal is written to the fourth node N4, and the sixth transistor T6 is turned on. The high-level signal at the scan signal input terminal (GIN) makes the signal at node N1 high.

[0120] In the second stage T2, i.e., the low-level shift signal output stage: see Figure 10 , Figure 10 This section describes the specific signals at each position of the scanning drive unit ASG during the second stage. The thick solid lines represent the first level signal (high level), and the thick dashed lines represent the second level signal (low level). Due to the presence of the first capacitor C1, the second transistor T2 remains conducting. Therefore, when the first clock signal received by the second transistor T2 changes from a high level to a low level, the shift signal output terminal Scan out outputs a low level signal.

[0121] It can be understood that the low level signal output by the shift signal output end Scan out can be written to the first shift signal input end Scan input of the next stage scan driving unit ASG, so that the next stage scan driving unit ASG starts the step of the first stage T1, and the shift signal output end Scan out of the next stage scan driving unit ASG outputs a low level signal when the first clock signal received by the second transistor T2 of the next stage scan driving unit ASG is a low level signal. It can be understood here that the first clock signal end SCK1 of the current stage scan driving unit ASG is a low level signal, and the first clock signal end SCK1 of the scan driving unit ASG of the next row is a high level signal. In this way, the scan driving circuit 14a starts to output low level signals from the shift signal output end Scan out of the first stage scan driving unit ASG1 in turn, so as to realize the shift. When the shift reaches the Nth stage scan driving unit ASGN, the shift signal output end Scan out of the Nth stage scan driving unit ASGN outputs a low level signal.

[0122] In the third stage T3, that is, the low level shift signal cutoff stage: referring to Figure 11 , Figure 11 The specific signals at each position of the scan driving unit ASG in the third stage are shown in the figure, in which the thick solid line represents the first level signal, that is, the high level signal; the thick dashed line represents the second level signal, that is, the low level signal. When the next stage scan driving unit ASG outputs a low level signal from the shift signal output end Scan out, the low level shift signal received by the second shift signal input end Scan reset of the current stage scan driving unit ASG, the third transistor T3 and the fourth transistor T4 are turned on, the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 receive the high level signal at the first level signal receiving end VGH, the signal output by the shift signal output end Scan out changes from the low level signal to the high level signal, and remains the high level signal.

[0123] That is, the above process is sequentially shifted. However, during the shift, the scan signal output end GOUT of the shifted scan driving unit ASG outputs a high level signal. Correspondingly, the P-type transistor (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the corresponding pixel row (the row corresponding to the scan signal line 121 electrically connected with the scan driving unit ASG) cannot be turned on (that is, work), that is, the corresponding pixel row of the shifted scan driving unit ASG is not refreshed, such as the first pixel row corresponding to the first stage scan driving unit ASG1 to the (N-1)th pixel row corresponding to the (N-1)th stage scan driving unit ASG(N-1).

[0124] In order to realize the refresh of the Nth pixel row corresponding to the Nth scan driving unit ASGN, the signal transmitted by the trigger signal line STVL electrically connected to the trigger signal input end STV of each scan driving unit ASG is changed from high level to low level when the Nth scan driving unit ASGN is shifted. Based on the low level signal input by the trigger signal input end STV, the scan signal output end GOUT of the Nth scan driving unit ASGN outputs a low level signal to drive the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the Nth pixel row to be turned on (i.e., work), that is, the Nth pixel row is refreshed.

[0125] Specifically, in the Nth stage TN, i.e., the trigger signal low level input stage: referring to Figure 12 , Figure 12 The specific signals at each position of the scan driving unit ASG in the Nth stage are shown in the figure, in which the thick solid line represents the first level signal, i.e., the high level signal; the thick dashed line represents the second level signal, i.e., the low level signal. As known from the foregoing, the shift signal output end Scan out of the Nth scan driving unit ASGN outputs a low level signal when the Nth scan driving unit ASGN is shifted. The low level signal at the shift signal output end Scan out makes the fifth transistor T5 conduct. Since the signal input by the trigger signal input end STV at this time is a low level signal, the low level signal input by the trigger signal input end STV is written to the first node N1, and the signal at the first node N1 is pulled low. Since the first clock signal received by the first clock signal end SCK1 is changed from high level to low level and the second clock signal received by the second clock signal end SCK2 is changed from low level to high level at this time, the tenth transistor T10 and the eleventh transistor T11 are turned on, the low level signal input by the trigger signal input end STV is written to the fifth node N5, the signal at the fifth node N5 is pulled low, the twelfth transistor T12 is opened, and the sixth node N6 is at low level. The thirteenth transistor T13 is closed, and the high level cannot be written to the sixth node N6 through the thirteenth transistor T13. The low level signal at the fifth node N5 makes the sixteenth transistor T16 conduct, and the low level at the sixth node N6 makes the seventeenth transistor T17 open, and the scan signal output by the scan signal output end GOUT is high level at this time.

[0126] In the (N+1)th stage T(N+1), i.e., the scan signal output end output low level stage: referring to Figure 13 , Figure 13The specific signals at the positions of the scan driving unit ASG at the (N+1)th stage are shown in the figure, in which the thick solid line represents the first level signal, i.e. the high level signal; the thick dashed line represents the second level signal, i.e. the low level signal. The first clock signal received by the first clock signal terminal SCK1 changes from low level to high level, the second clock signal received by the second clock signal terminal SCK2 changes from high level to low level, the tenth transistor T10 and the eleventh transistor T11 are turned off, the fifth node N5 maintains low level, the twelfth transistor T12 continues to be turned on, and the high level of the first clock signal is written to the sixth node N6. The low level of the fifth node N5 turns on the sixteenth transistor T16, the high level of the sixth node N6 turns off the seventeenth transistor T17, and the low level of the second clock signal is transmitted to the scan signal output terminal GOUT through the sixteenth transistor T16, i.e. the scan signal output by the scan signal output terminal GOUT is low level at this time, so as to drive the P-type transistor (the data writing transistor M2 and the threshold compensation transistor M3) in the pixel circuit 111 of the corresponding pixel row (the row corresponding to the scan signal line 121 electrically connected to the scan driving unit ASG) to be turned on (i.e. to work), i.e. the Nth pixel row is refreshed.

[0127] It can be understood that the scan signal (low level signal) output by the scan signal output terminal GOUT can be written to the scan signal input terminal GIN of the next stage scan driving unit ASG, so that the next stage scan driving unit ASG starts the step of the Nth stage TN, and the scan signal output terminal GOUT of the next stage scan driving unit ASG outputs the low level signal when the first clock signal received by the first clock signal terminal SCK1 of the next stage scan driving unit ASG changes from low level to high level and the second clock signal received by the second clock signal terminal SCK2 changes from high level to low level. In this way, the scan driving circuit 14a starts from the scan signal output terminal GOUT of the Nth scan driving unit ASGN and outputs the low level signal in turn, so as to realize the shift of the scan signal in turn. That is, the Nth pixel row corresponding to the Nth scan driving unit ASGN, the (N+1)th pixel row corresponding to the (N+1)th scan driving unit ASGN, the (N+2)th pixel row corresponding to the (N+2)th scan driving unit ASGN, and so on are refreshed.

[0128] In the (N+2)th stage T(N+2), i.e. the stage in which the scan signal output end outputs a high level: the first clock signal received by the first clock signal end SCK1 changes from a high level to a low level, the second clock signal received by the second clock signal end SCK2 changes from a low level to a high level, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the high level signal input by the trigger signal input end STV is written to the fifth node N5, the twelfth transistor T12 is turned off, and the low level signal received by the second level signal receiving end VGL is written to the sixth node N6. The high level at the fifth node N5 causes the sixteenth transistor T16 to be turned off, and the low level at the sixth node N6 causes the seventeenth transistor T17 to be turned on, so that the scan signal output by the scan signal output end GOUT is a high level signal at this time. At this time, the P-type transistors (data writing transistors M2 and threshold compensation transistors M3) in the pixel circuit 111 of the corresponding pixel row are turned off.

[0129] The above describes the process of scanning from the Nth row. It should be noted that N can be any number, for example, scanning can start from the fourth row, scanning can start from the fourteenth row, scanning can start from the fortieth row, and so on.

[0130] The following describes the specific process of the scan driving circuit 14a ending scanning from the Mth row. M is greater than N.

[0131] Figure 14 The timing diagram of the signals of the scan driving unit ending scanning from the Mth row is shown. The following describes the working process of the scan driving unit ASG of the scan driving circuit 14a shown in the timing diagram. Figure 7 The working process of the scan driving unit ASG of the scan driving circuit 14a shown in the timing diagram is described.

[0132] In the (M-1)th stage T(M-1), i.e. the stage in which the scan signal output end outputs a high level: referring to Figure 15 , Figure 15 The specific signals at the positions of the (M-1)th scan driving unit ASG(M-1) and the Mth scan driving unit ASGM in the (M-1)th stage are shown, in which the thick solid line represents the first level signal, i.e. the high level signal; the thick dashed line represents the second level signal, i.e. the low level signal. The scan signal output end GOUT of the (M-1)th scan driving unit ASG(M-1) outputs a scan signal (low level signal).

[0133] Meanwhile, the scan signal (low level signal) outputted by the scan signal output terminal GOUT of the (M-1)th stage scan driving unit ASG(M-1) can be written into the scan signal input terminal GIN of the Mth stage scan driving unit ASGM, so that the Mth stage scan driving unit ASGM starts to output low level scan signal. However, in order to end the scanning of the Mth pixel row, i.e. in order to make the scan signal output terminal GOUT of the Mth stage scan driving unit ASGM not output low level scan signal. In the (M-1)th stage T(M-1), the signal transmitted from the cutoff signal line CloseL and received by the cutoff signal input terminal Close becomes low level signal from high level signal of the (M-2)th stage T(M-2), at this time, the eighth transistor T8 of the Mth stage scan driving unit ASGM is turned on, the high level signal received by the first level signal receiving terminal VGH is written into the gate of the sixth transistor T6 through the eighth transistor T8, the sixth transistor T6 is cut off, and the low level signal received by the scan signal input terminal GIN of the Mth stage scan driving unit ASGM cannot be written into the first node N1.

[0134] In addition, at this time, the first clock signal received by the first clock signal terminal SCK1 of the Mth stage scan driving unit ASGM is low level, the second clock signal received by the second clock signal terminal SCK2 is high level, the tenth transistor T10 and the eleventh transistor T11 are turned on, and the sixth node N6 is low level. The low level at the sixth node N6 makes the seventeenth transistor T17 open, and the scan signal outputted by the scan signal output terminal GOUT is high level at this time.

[0135] In the Mth stage TM, i.e. the high level maintaining stage of the scan signal output terminal GOUT: refer to Figure 16 , Figure 16The specific signal of the Mth scan driving unit ASGM at each position at the Mth stage is shown, in which the thick solid line represents the first level signal, i.e. the high level signal; the thick dashed line represents the second level signal, i.e. the low level signal. The signal received by the close signal input terminal Close changes from the low level signal to the high level signal, at this time, the eighth transistor T8 is cut off. Since the first clock signal received by the first clock signal terminal SCK1 is at the high level and the second clock signal received by the second clock signal terminal SCK2 is at the low level at this time, the tenth transistor T10 and the eleventh transistor T11 are cut off. Since the low level first clock signal received by the first clock signal terminal SCK1 of the Mth scan driving unit ASGM is written to the third capacitor C3 at the (M-1)th stage T(M-1), the signal at the sixth node N6 is kept at the low level signal, the low level signal at the sixth node N6 makes the seventeenth transistor T17 open, and the scan signal output by the scan signal output terminal GOUT is still at the high level at this time. At the same time, the voltage across the second capacitor C2 changes from the low level signal to the high level signal, and the high level signal at the fifth node N5 makes the sixteenth transistor T16 cut off.

[0136] From the working process of the scan driving unit ASG, it can be seen that the scan driving circuit 14a provided by the embodiment of the present application can realize scanning from the Nth pixel row to the Mth pixel row, i.e. completing refreshing of the Nth pixel row to the Mth pixel row, and the pixel rows before the Nth pixel row and the pixel rows after the Mth pixel row are not refreshed.

[0137] It should be understood that, Figure 14 The waveforms and timing of the signals are not limited to Figure 14 shown. For example, after the signal received by the close signal input terminal Close changes from the high level signal to the low level signal, it can be kept at the low level until the next frame, and then the signal received by the close signal input terminal Close changes from the low level signal to the high level signal.

[0138] In combination with Figure 17 , Figure 17 The timing diagram of the signals in the scan driving circuit 14a is shown, Figure 17 In order to better compare the shift signal and the scan signal, the shift signal received by the first shift signal input terminal Scan input of each stage and the scan signal output by the scan signal output terminal GOUT of each stage are adjacent, and in order to distinguish the shift signal received by the first shift signal input terminal Scan input of each stage, the shift signal is represented by a thin line, and the scan signal output by the scan signal output terminal GOUT of each stage is represented by a thick line.

[0139] From the above Figure 17It can be known that, in the shift stage: when the shift signal received by the first shift signal input end Scan input of the first-stage scan driving unit ASG1 is a low-level signal, the first-stage scan driving unit ASG1 outputs the low-level shift signal to the first shift signal input end Scan input of the next-stage (i.e. the second-stage) scan driving unit ASG2 through the shift signal output end Scan out of the current stage; when the first shift signal input end Scan input of the second-stage scan driving unit ASG2 receives the low-level shift signal, the second-stage scan driving unit ASG2 outputs the low-level shift signal to the first shift signal input end Scan input of the next-stage (i.e. the third-stage) scan driving unit ASG3 through the shift signal output end Scan out of the current stage; and so on; when the first shift signal input end Scan input of the (N-1)-stage scan driving unit ASG(N-1) receives the low-level shift signal, the (N-1)-stage scan driving unit ASG(N-1) outputs the low-level shift signal to the first shift signal input end Scan input of the next-stage (i.e. the N-stage) scan driving unit ASG through the shift signal output end Scan out of the current stage, i.e. the shift signal is sequentially shifted from the first-stage scan driving unit ASG1 to the N-stage scan driving unit ASG. At the same time (i.e. in the shift stage), the scan signal output from the scan signal output end GOUT of the first-stage scan driving unit ASG1 to the (N-1)-stage scan driving unit ASG(N-1) is a high-level signal, which cannot drive the P-type transistor (the data writing transistor M2 and the threshold compensation transistor M3) in the pixel circuit 111 of the first pixel row to the Nth pixel row to open (i.e. work). That is, the pixel rows corresponding to the first-stage scan driving unit ASG1 to the (N-1)-stage scan driving unit ASG(N-1) are not refreshed.

[0140] By Figure 17It can be known that, in the scanning stage: when the shift signal received by the first shift signal input end Scaninput of the Nth scanning driving unit ASGN is a low-level signal, the Nth scanning driving unit ASGN outputs a low-level shift signal from the first shift signal input end Scaninput of the next stage (i.e. the (N+1)th scanning driving unit ASG(N+1)) through the shift signal output end Scanout of the present stage; ……; when the first shift signal input end Scaninput of the (M-1)th scanning driving unit ASG(M-1) receives a low-level shift signal, the (M-1)th scanning driving unit ASG(M-1) outputs a low-level shift signal from the first shift signal input end Scaninput of the next stage (i.e. the Mth scanning driving unit ASGN) through the shift signal output end Scanout of the present stage; when the first shift signal input end Scaninput of the Mth scanning driving unit ASGM receives a low-level shift signal, the Mth scanning driving unit ASGM outputs a low-level shift signal from the first shift signal input end Scaninput of the next stage (i.e. the (M+1)th scanning driving unit ASG(M+1)) through the shift signal output end Scanout of the present stage. That is, the shift signal is sequentially shifted from the Nth scanning driving unit ASGN to the (M+1)th scanning driving unit ASG. At the same time, when the shift signal is shifted to the first shift signal input end Scaninput of the (N-1)th scanning driving unit ASG(N-1), the signal inputted by the trigger signal input end STV is changed from a high-level signal to a low-level signal.When the signal inputted into the trigger signal input terminal STV is a low level signal and the second clock signal terminal SCK2 receives a low level second clock signal, the Nth scan driving unit ASGN outputs a low level scan signal to the Nth pixel row corresponding to the Nth scan driving unit ASGN through the scan signal output terminal GOUT of the Nth scan driving unit ASGN, and outputs the low level scan signal to the (N+1)th scan driving unit ASG(N+1) of the next stage.

[0141] By Figure 17It can be seen that, in the scanning stop stage: when the Mth scanning driving unit ASGM outputs a low-level scanning signal to the Mth pixel row corresponding to the Mth scanning driving unit ASGM through the scanning signal output terminal GOUT of the current stage, and outputs a low-level scanning signal to the next stage (i.e., the (M+1)th scanning driving unit ASG(M+1)) at the same time, the signal received by the cutoff signal input terminal Close changes from a low-level signal to a high-level signal. When the signal received by the cutoff signal input terminal Close is a high-level signal, the scanning signal output by the scanning signal output terminal GOUT of the (M+1)th scanning driving unit ASG(M+1) changes to a high-level scanning signal. At this time, the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the (M+1)th pixel row are turned off, and the refresh cannot be implemented.

[0142] It can be seen that, in the scanning stop stage: when the Mth scanning driving unit ASGM outputs a low-level scanning signal to the Mth pixel row corresponding to the Mth scanning driving unit ASGM through the scanning signal output terminal GOUT of the current stage, and outputs a low-level scanning signal to the next stage (i.e., the (M+1)th scanning driving unit ASG(M+1)) at the same time, the signal received by the cutoff signal input terminal Close changes from a low-level signal to a high-level signal. When the signal received by the cutoff signal input terminal Close is a high-level signal, the scanning signal output by the scanning signal output terminal GOUT of the (M+1)th scanning driving unit ASG(M+1) changes to a high-level scanning signal. At this time, the P-type transistors (data writing transistor M2 and threshold compensation transistor M3) in the pixel circuit 111 of the (M+1)th pixel row are turned off, and the refresh cannot be implemented.

[0143] It should be understood that, Figure 17 It should be understood that, Figure 17 The waveforms and timing of the signals in the above-described structure and working process are not limited to those shown in FIG. 6. Figure 15 The waveforms and timing of the signals in the above-described structure and working process are not limited to those shown in FIG. 6.

[0144] Based on the above structure and working process, the refresh rate of the pixel rows corresponding to the scanning driving units ASG between the Nth scanning driving unit ASGN and the Mth scanning driving unit ASGM is different from that of the pixel rows corresponding to the scanning driving units ASG before the Nth scanning driving unit ASGN and after the Mth scanning driving unit ASGM. Figure 1The process of realizing different refresh rates of the status bar 101, the video playing area 102 and the static content display area 103 is introduced. Taking the status bar 101 with a refresh frequency of 1 hz, the video playing area 102 with a refresh frequency of 60 hz and the static content display area 103 with a refresh frequency of 30 hz as examples, the process is described.

[0145] Referring to Figure 18 , Figure 18 A refresh process of a display screen provided by the embodiment of the present application is provided, wherein the refresh process is a process of a display driving chip providing a data signal to a display panel. As shown in Figure 18As shown, at the first frame, the scan driving circuit 14a completes the scanning of all pixel rows, i.e. the trigger signal input to the trigger signal input end STV needs to output a low level signal from the first stage scan driving unit ASG1 until all pixel rows are scanned, and the signal received by the close signal input end Close changes from a low level signal to a high level signal, i.e. the first frame completes the full refresh of the status bar 101, the video playing area 102 and the static content display area 103; at the second frame, the scan driving circuit 14a needs to complete the scanning of the pixel rows where the video playing area 102 and the static content display area 103 are located, i.e. when the shift signal shifts to the upper stage scan driving unit ASG of the scan driving unit ASG corresponding to the first pixel row in the pixel rows where the video playing area 102 and the static content display area 103 are located, the trigger signal input to the trigger signal input end STV starts to output a low level signal until the scanning of the pixel rows where the video playing area 102 and the static content display area 103 are located is completed, and the signal received by the close signal input end Close changes from a low level signal to a high level signal, i.e. the second frame completes the partial refresh of the video playing area 102 and the static content display area 103; at the third frame, the scan driving circuit 14a needs to complete the scanning of the pixel rows where the video playing area 102 is located, i.e. when the shift signal shifts to the upper stage scan driving unit ASG of the scan driving unit ASG corresponding to the first pixel row in the pixel rows where the video playing area 102 is located, the trigger signal input to the trigger signal input end STV starts to output a low level signal until the scanning of the pixel rows where the video playing area 102 is located is completed, and the signal received by the close signal input end Close changes from a low level signal to a high level signal, i.e. the third frame completes the partial refresh of the video playing area 102; at the fourth frame, the scan driving circuit 14a needs to complete the scanning of the pixel rows where the video playing area 102 and the static content display area 103 are located, i.e. when the shift signal shifts to the upper stage scan driving unit ASG of the scan driving unit ASG corresponding to the first pixel row in the pixel rows where the video playing area 102 and the static content display area 103 are located, the trigger signal input to the trigger signal input end STV starts to output a low level signal until the scanning of the pixel rows where the video playing area 102 and the static content display area 103 are located is completed, and the signal received by the close signal input end Close changes from a low level signal to a high level signal, i.e. the fourth frame completes the partial refresh of the video playing area 102 and the static content display area 103; and so on, i.e. the refresh mode of the second frame and the third frame is sequentially cycled until the sixty-first frame, and the refresh mode of the first frame to the sixtieth frame is recycled again, so as to realize the display of different refresh rates in different areas, i.e. the refresh frequency of the status bar 101 is 1hz, the refresh frequency of the video playing area 102 is 60hz, and the refresh frequency of the static content display area 103 is 30hz.

[0146] It should be noted that the refresh frequency described above is only an example, and does not constitute a limitation on the present application. A person skilled in the art can set the signals of the trigger signal input by the trigger signal input end STV and the cutoff signal received by the cutoff signal input end Close according to the actual situation, and then realize different refresh frequencies corresponding to different regions.

[0147] It should be further noted that the above examples are described by taking three regions corresponding to different refresh frequencies as an example, but do not constitute a limitation on the present application. In other optional embodiments of the present application, four regions can also correspond to different refresh frequencies, five regions can also correspond to different refresh frequencies, and so on. In addition, the refresh frequencies of two non-adjacent regions can also be the same, and so on, as long as the trigger signal input by the trigger signal input end STV and the cutoff signal received by the cutoff signal input end Close are changed.

[0148] From the foregoing, it can be seen that when the scan driving circuit is arranged on the two opposite sides of the display area AA (i.e., the scan driving circuit is arranged on the two opposite sides of the display area AA), the scan signal output ends of the two scan driving circuits are electrically connected to one scan signal line 121, so as to provide the scan signal line 121 with scan signals. That is, referring to Figure 19 Figure 19 Another structure diagram of a display panel provided by an embodiment of the present application is shown. The number of scan driving circuits 14a is two, and the two scan driving circuits 14a include a first scan driving circuit 14a1 and a second scan driving circuit 14a2. The scan signal output ends of the first scan driving circuit 14a1 and the second scan driving circuit 14a2 are electrically connected to one scan signal line 121, so as to provide the scan signal line 121 with scan signals.

[0149] Optionally, referring to Figure 20 Figure 20 Another structure diagram of a display panel provided by an embodiment of the present application is shown. In order to clearly show the invention point, Figure 20 only the scan signal line 121 is shown, and the light emission control signal line 122 is not shown. As Figure 20 ​​As shown, each scan signal line 121 includes a first scan signal sub-line segment 121a and a second scan signal sub-line segment 121b; each row of pixels 11 includes a first pixel group and a second pixel group, and each of the first pixel group and the second pixel group includes a plurality of pixels 11. Each pixel 11 of the first pixel group is electrically connected to the first scan signal sub-line segment 121a in the scan signal line 121, and each pixel 11 of the second pixel group in the same pixel row as the first pixel group is electrically connected to the second scan signal sub-line segment 121b in the scan signal line 121. The scan signals output by the scan signal output modules of the plurality of scan driving units ASG in the first scan driving circuit 14a1 are provided to each pixel 11 of the first pixel group through the first scan signal sub-line segment 121a, and the scan signals output by the scan signal output modules of the plurality of scan driving units ASG in the second scan driving circuit 14a2 are provided to each pixel 11 of the second pixel group through the second scan signal sub-line segment 121b. For example, each pixel 11 of the first pixel group in the first row of pixels is electrically connected to the first scan signal sub-line segment 121a in the first scan signal line 121, and each pixel 11 of the second pixel group in the first row of pixels is electrically connected to the second scan signal sub-line segment 121b in the first scan signal line 121. The scan signals output by the scan signal output modules of the first-stage scan driving unit ASG1 in the first scan driving circuit 14a1 are provided to each pixel 11 of the first pixel group in the first row of pixels through the first scan signal sub-line segment 121a in the first scan signal line 121, and the scan signals output by the scan signal output modules of the first-stage scan driving unit ASG1 in the second scan driving circuit 14a2 are provided to each pixel 11 of the second pixel group in the first row of pixels through the second scan signal sub-line segment 121b in the first scan signal line 121; …; each pixel 11 of the first pixel group in the Nth row of pixels is electrically connected to the first scan signal sub-line segment 121a in the Nth scan signal line 121, and each pixel 11 of the second pixel group in the Nth row of pixels is electrically connected to the second scan signal sub-line segment 121b in the Nth scan signal line 121. The scan signals output by the scan signal output modules of the Nth-stage scan driving unit ASGN in the first scan driving circuit 14a1 are provided to each pixel 11 of the first pixel group in the Nth row of pixels through the first scan signal sub-line segment 121a in the Nth scan signal line 121, and the scan signals output by the scan signal output modules of the Nth-stage scan driving unit ASGN in the second scan driving circuit 14a2 are provided to each pixel 11 of the second pixel group in the Nth row of pixels through the second scan signal sub-line segment 121b in the Nth scan signal line 121.

[0150] That is, the left and right portions of the display panel 10 display area AA are controlled by the first scan driving circuit 14a1 and the second scan driving circuit 14a2, respectively.

[0151] In this case, as shown in Figure 21 , Figure 21 One of the application scenarios of the electronic device provided by the embodiments of the present application is that, according to the refresh mode described above, the first scan driving circuit 14a1 can control different regions in the left part of the display panel display area AA to achieve different refresh frequencies, such as achieving different refresh frequencies of the 101 region, the 102 region, the 103 region, the 104 region and the 105 region in the left part of the display panel display area AA, and the second scan driving circuit 14a2 can control different regions in the right part of the display panel display area AA to achieve different refresh frequencies, such as achieving different refresh frequencies of the 106 region, the 107 region and the 108 region in the right part of the display panel display area AA.

[0152] As can be seen from the above, through the scan driving circuit provided by the embodiments of the present application, the pixels 11 in different regions of the display panel 10 refresh the data signals at different refresh rates, that is, different regions of the display panel 10 refresh the display content at different refresh rates. For regions that display pictures / characters and the like that do not change, the display content can be refreshed at a lower refresh rate, for example, at a refresh rate of 1Hz or 10Hz. For regions that display videos and the like that change in real time, the display content can be refreshed at a higher refresh rate, for example, at a refresh rate of 60Hz. In this way, since the refresh rate of the display panel 10 is reduced in different regions, the power consumption of the display panel is reduced.

[0153] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A scan driving circuit characterized by comprising: The application relates to a scan driving unit and a display device. The scan driving unit comprises a first selection module, a second selection module and a scan signal output module. The first selection module of each scan driving unit receives a shift signal output by the first selection module of the previous scan driving unit and receives a shift signal output by the first selection module of the next scan driving unit. When the first selection module of the Nth scan driving unit receives a shift signal output by the first selection module of the (N-1)th scan driving unit and receives a shift signal output by the first selection module of the (N+1)th scan driving unit and the first selection module of the Nth scan driving unit receives a trigger signal, the first selection module is used to control the scan signal output module of the Nth scan driving unit to start outputting a scan signal. The second selection module of each scan driving unit receives a scan signal output by the scan signal output module of the previous scan driving unit. When the second selection module of the Mth scan driving unit receives a scan signal output by the scan signal output module of the (M-1)th scan driving unit and the second selection module of the Mth scan driving unit receives a stop signal, the second selection module is used to control the scan signal output module of the Mth scan driving unit to stop outputting the scan signal. N The first selection module is electrically connected with a first shift signal input end, a second shift signal input end, a first clock signal end, a trigger signal input end, a first level signal receiving end, a shift signal output end and a first node.

2. The scan driving circuit according to claim 1, wherein The second selection module is electrically connected with the first node, a scan signal input end, the first level signal receiving end, a second level signal receiving end, a stop signal input end and a second node. The scan signal output module is electrically connected with the first node, the second node, the first clock signal end, a second clock signal end, the first level signal receiving end, the second level signal receiving end and a scan signal output end. The first selection module is used to receive a first shift signal received by the first shift signal input end, a first clock signal of the first clock signal end, a trigger signal input by the trigger signal input end and a first level signal received by the first level signal receiving end, and output a shift signal through the shift signal output end in response to a first shift signal and a second shift signal received by the second shift signal input end, and control the signal of the first node. ​ The second selection module is configured to receive the first level signal received by the first level signal receiving end, the second level signal received by the second level signal receiving end and the first scan signal received by the scan signal input end, and control the signal of the first node in response to the cutoff signal input by the cutoff signal input end and the signal at the second node; the first scan signal is the scan signal output by the scan signal output module of the previous stage; The scan signal output module is configured to receive the first level signal received by the first level signal receiving end, the signals at the first node and the second node, the first clock signal received by the first clock signal end and the second clock signal received by the second clock signal end, and control the scan signal output by the scan signal output end in response to the first clock signal, the second clock signal and the second level signal received by the second level signal receiving end.

3. The scan driving circuit according to claim 2, wherein The first selection module comprises a shift unit and a start scanning unit. The shift unit is electrically connected with the first shift signal input end, the second shift signal input end, the first clock signal end, the first level signal receiving end and the shift signal output end. The start scanning unit is electrically connected with the trigger signal input end, the shift signal output end and the first node. The shift unit is configured to receive the first shift signal received by the first shift signal input end, the first clock signal of the first clock signal end and the first level signal received by the first level signal receiving end, and output the shift signal through the shift signal output end in response to the first shift signal and the second shift signal received by the second shift signal input end. The start scanning unit is configured to receive the trigger signal input by the trigger signal input end, and control the signal at the first node in response to the shift signal output by the shift signal output end.

4. The scan driving circuit according to claim 3, wherein The shift unit comprises an input subunit and an output subunit. The input subunit is electrically connected with the first shift signal input end and the third node. The output subunit is electrically connected with the third node, the second shift signal input end, the first level signal receiving end, the first clock signal end and the shift signal output end. The input subunit is configured to receive the first shift signal received by the first shift signal input end, and control the signal of the third node in response to the first shift signal. The output subunit is configured to receive the first clock signal of the first clock signal end, and control the shift signal output by the shift signal output end in response to the signal of the third node. Alternatively, the output subunit is configured to receive the first level signal of the first level signal receiving end, and control the shift signal output by the shift signal output end in response to the second shift signal of the second shift signal input end.

5. The scan driving circuit according to claim 4, wherein The input subunit comprises a first transistor, the gate of the first transistor and the first electrode of the first transistor are electrically connected with the first shift signal input end, and the second electrode of the first transistor is electrically connected with the third node.

6. The scan driving circuit according to claim 4, wherein The output subunit comprises a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate of the second transistor, the first pole of the first capacitor and the first pole of the third transistor are electrically connected with the third node, the first pole of the second transistor is electrically connected with the first clock signal end, the second pole of the second transistor, the second pole of the first capacitor and the first pole of the fourth transistor are electrically connected with the shift signal output end, the gate of the third transistor and the gate of the fourth transistor are electrically connected with the second shift signal input end, the second pole of the third transistor and the second pole of the fourth transistor are electrically connected with the first level signal receiving end.

7. The scan driving circuit according to any one of claims 3 to 6, wherein The starting scanning unit comprises a fifth transistor, the gate of the fifth transistor is electrically connected with the shift signal output end, the first pole of the fifth transistor is electrically connected with the trigger signal input end, and the second pole of the fifth transistor is electrically connected with the first node.

8. The scan driving circuit according to claim 2, wherein The second selection module comprises a cutoff scanning unit, a first level signal input unit and a second level signal input unit; The cutoff scanning unit is electrically connected with the first node, a scan signal input end and a fourth node; The first level signal input unit is electrically connected with the fourth node, the first level signal receiving end and a cutoff signal input end; The second level signal input unit is electrically connected with the fourth node, the second node and the second level signal receiving end; The second level signal input unit is used for receiving a second level signal received by the second level signal receiving end and controlling a signal at the fourth node in response to the second level signal; The first level signal input unit is used for receiving a first level signal received by the first level signal receiving end and changing the signal at the fourth node in response to a cutoff signal input by the cutoff signal input end; The cutoff scanning unit is used for receiving a first scan signal received by the scan signal input end and controlling a signal at the first node in response to the signal at the fourth node.

9. The scan driving circuit according to claim 8, wherein, The cutoff scanning unit comprises a sixth transistor and a seventh transistor; the gate of the sixth transistor is electrically connected with the fourth node, the gate of the seventh transistor and the first pole of the seventh transistor are electrically connected with the scan signal input end, the second pole of the seventh transistor is electrically connected with the first pole of the sixth transistor, and the second pole of the sixth transistor is electrically connected with the first node.

10. The scan driving circuit according to claim 8, wherein The first level signal input unit comprises an eighth transistor, the gate of the eighth transistor is electrically connected with the cutoff signal input end, the first pole of the eighth transistor is electrically connected with the fourth node, and the second pole of the eighth transistor is electrically connected with the first level signal receiving end.

11. The scan driving circuit according to claim 8, wherein The second level signal input unit comprises a ninth transistor, the gate of the ninth transistor is electrically connected with the second node, the first pole of the ninth transistor is electrically connected with the second level signal receiving end, and the second pole of the ninth transistor is electrically connected with the fourth node.

12. The scan driving circuit according to claim 2, wherein The scan signal output module comprises: The input unit is electrically connected with the first node, the first clock signal terminal and the fifth node; The first control unit is electrically connected with the first clock signal terminal, the second node and the sixth node; The second control unit is electrically connected with the first level signal receiving terminal, the second clock signal terminal, the fifth node and the sixth node; The output unit is electrically connected with the first level signal receiving terminal, the second level signal receiving terminal, the second clock signal terminal, the fifth node, the sixth node and the scan signal output terminal; The input unit is configured to receive a signal at the first node and control a signal of the fifth node in response to a first clock signal received by the first clock signal terminal; The first control unit is configured to receive a first clock signal received by the first clock signal terminal and a signal at the second node, and control a signal of the sixth node in response to a signal at the fifth node and the first clock signal received by the first clock signal terminal; The second control unit is configured to receive a first level signal received by the first level signal receiving terminal, and change the signal of the fifth node in response to a signal at the sixth node and a second clock signal received by the second clock signal terminal; The output unit is configured to receive a first level signal received by the first level signal receiving terminal, and control a scan signal output by the scan signal output terminal in response to the signal of the sixth node, or the output unit is configured to receive a second clock signal received by the second clock signal terminal, and control a scan signal output by the scan signal output terminal in response to the signal of the fifth node.

13. The scan driving circuit according to claim 12, wherein, The input unit comprises a tenth transistor; The gate of the tenth transistor is electrically connected with the first clock signal terminal, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the fifth node.

14. The scan driving circuit according to claim 12, wherein, The first control unit comprises an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is electrically connected with the first clock signal terminal, the first pole of the eleventh transistor is electrically connected with the second node, and the second pole of the eleventh transistor and the second pole of the twelfth transistor are both electrically connected with the sixth node; The gate of the twelfth transistor is electrically connected with the fifth node, and the first pole of the twelfth transistor is electrically connected with the first clock signal terminal.

15. The scan driving circuit according to claim 12, wherein, The second control unit comprises a thirteenth transistor and a fourteenth transistor; The gate of the thirteenth transistor is electrically connected with the second clock signal terminal, the first pole of the thirteenth transistor is electrically connected with the fifth node, and the second pole of the thirteenth transistor is electrically connected with the first pole of the fourteenth transistor; The gate of the fourteenth transistor is electrically connected with the sixth node, and the second pole of the fourteenth transistor is electrically connected with the first level signal receiving terminal.

16. The scan driving circuit according to claim 12, wherein, The output unit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a second capacitor and a third capacitor; The gate of the fifteenth transistor is electrically connected with the second level signal receiving end, the first pole of the fifteenth transistor is electrically connected with the fifth node, and the second pole of the fifteenth transistor is electrically connected with the first pole of the second capacitor and the gate of the sixteenth transistor respectively; The second pole of the second capacitor, the second pole of the sixteenth transistor and the first pole of the seventeenth transistor are electrically connected with the scan signal output end; The first pole of the sixteenth transistor is electrically connected with the second clock signal end; The gate of the seventeenth transistor and the first pole of the third capacitor are electrically connected with the sixth node, and the second pole of the seventeenth transistor and the second pole of the third capacitor are electrically connected with the first level signal receiving end.

17. The scan driving circuit according to claim 2, wherein Further comprising a first clock signal line and a second clock signal line; The first clock signal end of the odd-stage scan driving unit is electrically connected with the first clock signal line, and the second clock signal end of the odd-stage scan driving unit is electrically connected with the second clock signal line; the first clock signal end of the even-stage scan driving unit is electrically connected with the second clock signal line, and the second clock signal end of the even-stage scan driving unit is electrically connected with the first clock signal line.

18. A display panel, characterized by Comprising at least one scan driving circuit as claimed in any one of claims 1-17, a plurality of pixels arranged in an array and a plurality of scan line groups; The scan signal lines of the plurality of scan line groups are electrically connected with the scan signal output modules of the plurality of scan driving units respectively; Different pixel rows correspond to different scan line groups, and each pixel in the same row is electrically connected with the scan signal line of the same scan line group; the scan signal output by the scan signal output module is provided to the pixel through the scan signal line.

19. The display panel of claim 18, wherein, The number of the scan driving circuits is two, and the two scan driving circuits comprise a first scan driving circuit and a second scan driving circuit; Each row of pixels comprises a first pixel group and a second pixel group, and the first pixel group and the second pixel group each comprise a plurality of pixels; The scan signal lines comprise a first scan signal sub-line segment and a second scan signal sub-line segment; Each pixel of the first pixel group is electrically connected with the same first scan signal sub-line segment, and each pixel of the second pixel group is electrically connected with the same second scan signal sub-line segment; The scan signal output by the scan signal output modules of the plurality of scan driving units in the first scan driving circuit is provided to each pixel of the first pixel group through the first scan signal sub-line segment, and the scan signal output by the scan signal output modules of the plurality of scan driving units in the second scan driving circuit is provided to each pixel of the second pixel group through the second scan signal sub-line segment.

20. An electronic device, comprising: The display panel as claimed in claim 18 or 19.

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