Display device

Abstract

A display device includes a plurality of data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixels. The plurality of pixels includes a first group of pixels and a second group of pixels. The plurality of data lines includes a first group of data lines connected to the first group of pixels and a second group of data lines connected to the second group of pixels. A data signal is provided to the first group of pixels in a first subframe period of one frame period. A data signal is provided to the second group of pixels in a second subframe period of the one frame period adjacent to the first subframe period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0142317 filed in the Korean Intellectual Property Office on October 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure are directed to a display device with reduced power consumption and improved display quality. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, car navigation units, and gaming devices include display devices for displaying images. The display device may include an organic light emitting display (OLED) device. Compared to conventional light emitting diode (LED) televisions, OLED technology in televisions provides superior image quality with better contrast and viewing angle. OLED screens in mobile phones provide excellent contrast, deep blacks, and vivid colors.

[0005] An organic light emitting display device may include a light emitting element that generates light through recombination of electrons and holes, such as an organic light emitting diode. The organic light emitting display device has a fast response speed and is driven with low power consumption. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device with reduced power consumption and improved display quality.

[0007] According to an embodiment, a display device includes: a plurality of data lines; a plurality of first gate lines arranged in a second direction; a plurality of second gate lines arranged in a second direction intersecting the first direction; and a plurality of pixels, each of the plurality of pixels being connected to a corresponding data line among the plurality of data lines and a corresponding gate line among the plurality of first gate lines and the plurality of second gate lines. The plurality of pixels include a first group of pixels and a second group of pixels. The plurality of data lines include a first group of data lines connected to the first group of pixels and a second group of data lines connected to the second group of pixels. Data signals are provided to the first group of pixels in a first subframe period of a frame period. Data signals are provided to the second group of pixels in a second subframe period of a frame period adjacent to the first subframe period.

[0008] The plurality of first gate lines and the plurality of second gate lines may alternate with each other in the second direction. The plurality of first gate lines may be sequentially activated in the first subframe period. The plurality of second gate lines may be sequentially activated in the second subframe period.

[0009] The display device may further include a demultiplexer connected to the plurality of data lines. The demultiplexer may include a plurality of first control transistors connected to the first group of data lines in a one-to-one correspondence and a plurality of second control transistors connected to the second group of data lines in a one-to-one correspondence. The plurality of first control transistors may be configured to be controlled by a first control signal provided via a first control line, and the plurality of second control transistors may be configured to be controlled by a second control signal provided via a second control line.

[0010] In the first subframe period, the first control signal may have an activation level and a disable level that alternate with each other, and the second control signal may have a disable level. In the second subframe period, the first control signal may have a disable level, and the second control signal may have an activation level and a disable level that alternate with each other.

[0011] The plurality of pixels may include: a first pixel that outputs light having a first color; a second pixel that outputs light having a second color different from the first color; a third pixel that outputs light having a third color different from the first color and the second color; and a fourth pixel that outputs light having the second color. The first pixel and the third pixel may be alternately arranged one after another in the first direction and the second direction, and the second pixel and the fourth pixel may be alternately arranged one after another in the first direction and the second direction.

[0012] The first group of pixels may include a first pixel and a third pixel, and the second group of pixels may include a second pixel and a fourth pixel.

[0013] Each of the first and third pixels may be electrically connected to a corresponding first gate line among the plurality of first gate lines, and each of the second and fourth pixels may be electrically connected to a corresponding second gate line among the plurality of second gate lines.

[0014] The first group of data lines may be connected to the first pixel and the third pixel, respectively, and the second group of data lines may be connected to the second pixel and the fourth pixel, respectively. The first group of data lines and the second group of data lines may alternate with each other.

[0015] The first group of data lines may include a first-first group of data lines connected to the first pixel and a first-second group of data lines connected to the third pixel. The second group of data lines may be connected to the second pixel and the fourth pixel, respectively. The first-first group of data lines, one data line in the second group of data lines, and another data line in the first-second group of data lines and the second group of data lines may be arranged sequentially.

[0016] The first group of data lines may include a first-first group of data lines connected to the first pixel and the third pixel and a first-second group of data lines connected to the second pixel and the fourth pixel. The second group of data lines may include a second-first group of data lines connected to the second pixel and the fourth pixel and a second-second group of data lines connected to the first pixel and the third pixel. The first-first group of data lines, the second-first group of data lines, the second-second group of data lines and the first-second group of data lines may be arranged sequentially.

[0017] Each of the first pixel, the second pixel, the third pixel and the fourth pixel is provided in plurality, and the first group of data lines may include a first-first group of data lines connected to the first pixel among the plurality of first pixels, a first-second group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, a first-third group of data lines connected to the third pixel among the plurality of third pixels, and a first-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The second group of data lines may include a second-first group of data lines connected to the third pixel among the plurality of third pixels, a second-second group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, a second-third group of data lines connected to the first pixel, and a second-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The first-first group of data lines, the second-first group of data lines, the first-second group of data lines, the second-second group of data lines, the second-third group of data lines, the first-fourth group of data lines, the second-fourth group of data lines and the first-fourth group of data lines may be arranged sequentially.

[0018] Each of the first pixel, the second pixel, the third pixel and the fourth pixel is provided in plurality, and the first group of data lines may include a first-first group of data lines connected to the first pixel among the plurality of first pixels, a first-second group of data lines connected to the third pixel among the plurality of third pixels, a first-third group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, and a first-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The second group of data lines may include a second group of data lines including a second-first group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, a second-second group of data lines connected to the first pixel among the plurality of first pixels, a second-third group of data lines connected to the third pixel among the plurality of third pixels, and a second-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The first-first group of data lines, the second-first group of data lines, the first-second group of data lines, the second-fourth group of data lines, the second-second group of data lines, the first-third group of data lines, the second-third group of data lines and the first-fourth group of data lines are sequentially arranged.

[0019] Each of the first pixel, the second pixel, the third pixel, and the fourth pixel is provided in plurality, and the first group of data lines may include a first-first group of data lines connected to the first pixel among the plurality of first pixels, a first-second group of data lines connected to the third pixel among the plurality of third pixels, a first-third group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, and a first-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The second group of data lines may include a second-first group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels, a second-second group of data lines connected to the first pixel among the plurality of first pixels, a second-third group of data lines connected to the third pixel among the plurality of third pixels, and a second-fourth group of data lines connected to the second pixel among the plurality of second pixels and the fourth pixel among the plurality of fourth pixels. The first-first group of data lines, the first-second group of data lines, the second-first group of data lines, the second-fourth group of data lines, the second-second group of data lines, the second-third group of data lines, the first-third group of data lines, and the first-fourth group of data lines may be arranged sequentially.

[0020] The first pixel and the third pixel may emit light in the first sub frame period, and the second pixel and the fourth pixel may emit light in the second sub frame period.

[0021] The first pixel, the second pixel, the third pixel, and the fourth pixel may emit light in the first sub frame period and the second sub frame period.

[0022] According to an embodiment, a display device includes: a plurality of first data lines arranged in a first direction; a plurality of second data lines arranged in the first direction; a plurality of gate lines arranged in a second direction intersecting the first direction; a plurality of first pixels electrically connected to the plurality of first data lines and the plurality of gate lines; a plurality of second pixels electrically connected to the plurality of second data lines and the plurality of gate lines; and a demultiplexer. The demultiplexer includes a plurality of first control transistors connected to the plurality of first data lines in a one-to-one correspondence and a plurality of second control transistors connected to the plurality of second data lines in a one-to-one correspondence. In a first subframe period of a frame period, a first control signal for controlling the plurality of first control transistors has an activation level and a disable level alternating with each other, and a second control signal for controlling the plurality of second control transistors has a disable level. In a second subframe period of a frame period adjacent to the first subframe period, the first control signal has a disable level, and the second control signal has an activation level and a disable level alternating with each other.

[0023] The plurality of gate lines may include a plurality of first gate lines electrically connected to the plurality of first pixels and a plurality of second gate lines electrically connected to the plurality of second pixels. The plurality of first gate lines may be sequentially activated in a first subframe period, and the plurality of second gate lines may be sequentially activated in a second subframe period.

[0024] The plurality of first pixels and the plurality of second pixels may include: a first-first pixel that outputs light having a first color; a second-second pixel that outputs light having a second color different from the first color; a first-third pixel that outputs light having a third color different from the first color and the second color; and a second-fourth pixel that outputs light having the second color, and the first-first pixel, the second-second pixel, the first-third pixel, and the second-fourth pixel may emit light in one frame period.

[0025] In the first subframe period, the first-first pixel and the first-third pixel may emit light, and in the second subframe period, the second-second pixel and the second-fourth pixel may emit light. Alternatively, in the first subframe period and the second subframe period, the first-first pixel, the second-second pixel, the first-third pixel and the second-fourth pixel may emit light.

[0026] According to an embodiment, a display device includes: a plurality of data lines arranged in a first direction; a plurality of gate lines arranged in a second direction intersecting the first direction; a plurality of pixels electrically connected to the plurality of data lines and the plurality of gate lines; a plurality of first control transistors connected one-to-one to some of the plurality of data lines; and a plurality of second control transistors connected one-to-one to other data lines of the plurality of data lines. A data signal is provided to only some of the data lines connected to the plurality of first control transistors in a first subframe period of a frame period. A data signal is provided to only other data lines connected to the plurality of second control transistors in a second subframe period of a frame period adjacent to the first subframe period. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0029] Figure 3 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 4 is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0032] Figure 6 is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure.

[0033] Figure 7 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0034] Figure 8 is a timing diagram of the operation of the display device according to an embodiment of the present disclosure.

[0035] Fig.9A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0036] Fig. 9B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0037] Fig.10 is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0038] Fig.11 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0039] Fig. 12A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0040] Fig. 12B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0041] Fig.13 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0042] Fig.14A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0043] Fig. 14B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0044] Fig.15 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0045] Fig.16A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0046] Fig. 16B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0047] Fig.17 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0048] Fig.18A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0049] Fig.18B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0050] Fig.19 is a view showing a portion of a display device according to an embodiment of the present disclosure.

[0051] Fig. 20A is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0052] Fig. 20B is a view illustrating an operation of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals may represent the same components.

[0054] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may exist between the component and the other component.

[0055] The terms "component" and "unit" may refer to a software component or a hardware component that performs a specific function. A hardware component may include, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A software component may refer to executable code in an addressable storage medium and / or data used by the executable code. Thus, a software component may be, for example, an object-oriented software component, a class component, and a working component, and may include a process, a function, a property, a program, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, or a variable.

[0056] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0057] Figure 1 is a perspective view of an electronic device 1000 according to an embodiment of the present disclosure.

[0058] Reference Figure 1 , exemplifying that the electronic device 1000 is a mobile phone. The electronic device 1000 may include a display device DD. The active area 1000A and the peripheral area 1000NA may be defined in the display device DD. The active area 1000A may refer to a portion of the display where light emission occurs. The display device DD may display an image through the active area 1000A. The active area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may surround the periphery of the active area 1000A. In an embodiment of the present disclosure, the peripheral area 1000NA is omitted.

[0059] The thickness direction of the electronic device 1000 or the display device DD may be parallel to a third direction DR3 crossing the first direction DR1 and the second direction DR2. Therefore, the front surface (or upper surface) and the rear surface (or lower surface) of the components constituting the electronic device 1000 or the display device DD may be defined based on the third direction DR3.

[0060] Figure 2 is a perspective view of an electronic device 1000 - 1 according to an embodiment of the present disclosure.

[0061] Reference Figure 2, the electronic device 1000-1 may include a display device DD. The display device DD may include a folding area FA and a plurality of non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2. The folding area FA may be referred to as a foldable area, and the first non-folding area NFA1 and the second non-folding area NFA2 may be referred to as a first non-foldable area and a second non-foldable area. For example, the non-foldable area may be rigid to prevent the generation of an additional folding area.

[0062] like Figure 2 As shown in , the folding area FA can be folded around a folding axis FX parallel to the second direction DR2. In the folded state of the electronic device 1000-1, the folding area FA can have a predetermined curvature and a predetermined curvature radius. The electronic device 1000-1 can be folded in an inner folding manner so that the first non-folding area NFA1 and the second non-folding area NFA2 face each other and the display surface is not exposed to the outside. For example, when the electronic device 1000-1 is in the inner folding state, the image may not be visible.

[0063] In an embodiment of the present disclosure, the electronic device 1000-1 may be folded in an outer folding manner so that the display surface is exposed to the outside. For example, when the electronic device 1000-1 is in an outer folding state, an image may be visible. In an embodiment of the present disclosure, the electronic device 1000-1 may be folded in an inner folding or outer folding manner in an unfolded state. However, the present disclosure is not limited thereto.

[0064] although Figure 2 An example is shown in which a single folding axis FX is defined in the electronic device 1000-1, but the present disclosure is not limited thereto. For example, a plurality of folding axes may be defined in the electronic device 1000-1, and the electronic device 1000-1 may be folded inwardly or outwardly about the plurality of folding axes in an unfolded state.

[0065] Although referring to Figure 1 and Figure 2 The electronic devices 1000 and 1000 - 1 are shown as electronic devices having a bar shape, but the present disclosure is not limited thereto. For example, the following description may be applied to various electronic devices such as a bendable electronic device, a rollable electronic device, and a slidable electronic device.

[0066] Figure 3 is a perspective view of an electronic device 1000 - 2 according to an embodiment of the present disclosure.

[0067] Reference Figure 3, it is illustrated that the electronic device 1000-2 is a notebook computer. The electronic device 1000-2 may include a display device DD. The active area 1000A and the peripheral area 1000NA may be defined in the display device DD. The display device DD may display an image through the active area 1000A.

[0068] The electronic device 1000, 1000-1 or 1000-2 may be activated according to an electrical signal. For example, the electronic device 1000, 1000-1 or 1000-2 may be a mobile phone, a foldable mobile phone, a notebook computer, a television, a tablet computer, a car navigation unit, a game console or a wearable device, but is not limited thereto. The wearable device worn on a part of the user's body may include a head mounted display (HMD) that implements extended reality (XR).

[0069] Figure 4 is a block diagram of a display device DD according to an embodiment of the present disclosure. The electronic device 1000, 1000-1, or 1000-2 may include a display device DD.

[0070] Reference Figure 4 , the display device DD may include a driving controller TC (eg, a controller circuit), a data driving circuit DDC, a demultiplexer DM, a first driving circuit SDC1, a second driving circuit SDC2, and pixels PXij disposed in an active area 1000A.

[0071] In an embodiment of the present disclosure, the demultiplexer DM, the first driving circuit SDC1, the second driving circuit SDC2, and the pixel PXij disposed in the active area 1000A may be included in a display panel 100 (refer to FIG. 1 ) to be described below. Figure 6 The driving controller TC and the data driving circuit DDC may be implemented with an integrated circuit (IC) and may be directly mounted on a specific area of ​​the display panel 100, or may be mounted on a separate printed circuit board in a chip on film (COF) manner and may be electrically connected to the display panel 100.

[0072] The display device DD may include first gate lines GWL1-1 to GWL1-n, second gate lines GWL2-1 to GWL2-n, and data lines DL1 to DLm. The data lines DL1 to DLm may be arranged in a first direction DR1, the first gate lines GWL1-1 to GWL1-n may be arranged in a second direction DR2 crossing the first direction DR1, and the second gate lines GWL2-1 to GWL2-n may be arranged in the second direction DR2. The first gate lines GWL1-1 to GWL1-n may be referred to as first write scan lines, and the second gate lines GWL2-1 to GWL2-n may be referred to as second write scan lines.

[0073] The display device DD may include a plurality of pixels connected to first gate lines GWL1-1 to GWL1-n, second gate lines GWL2-1 to GWL2-n, and data lines DL1 to DLm. Figure 4 , one pixel PXij is representatively shown. One pixel PXij may be electrically connected to one gate line GWLi among the first gate lines GWL1-1 to GWL1-n and the second gate lines GWL2-1 to GWL2-n and one data line DLj among the data lines DL1 to DLm, where m and n are integers greater than or equal to 1. Wherein, i is an integer greater than or equal to 1 and less than or equal to n, and j is an integer greater than or equal to 1 and less than or equal to m.

[0074] In an embodiment of the present disclosure, the signal line connected to the pixel PXij may be arranged differently according to the circuit structure of the pixel PXij. Figure 4 In the embodiment, one gate line and one data line are shown as an example, and the pixel PXij can be electrically connected to Figure 4 Lines other than those shown in .

[0075] The driving controller TC receives the image signal RGB and the control signal CTRL. The driving controller TC generates the image data signal DATA by converting the data format of the image signal RGB according to the specification of the interface with the data driving circuit DDC. In addition, the driving controller TC generates the first control signal DCS for controlling the data driving circuit DDC and the second control signal SCS for controlling the first driving circuit SDC1 and the second driving circuit SDC2.

[0076] In an embodiment of the present disclosure, the display device DD further includes channel lines CL1 to CLx, where x is an integer greater than or equal to 1 and less than or equal to m. The channel lines CL1 to CLx may be selectively electrically connected to the data lines DL1 to DLm through the demultiplexer DM. The number of channel lines CL1 to CLx may be less than the number of data lines DL1 to DLm. Although it has been described that the demultiplexer DM is included in the display panel 100, the present disclosure is not particularly limited thereto. For example, the demultiplexer DM may be included in the data drive circuit DDC, may be implemented with a separate integrated circuit, or may be integrated into a printed circuit board on which the data drive circuit DDC is mounted.

[0077] According to an embodiment of the present disclosure, the number of channels of data outputted from the data driving circuit DDC by the demultiplexer DM is less than the number of data lines DL1 to DLm. The number of channels may correspond to the number of channel lines CL1 to CLx. In this case, Figure 3The number of IC chips of the data driving circuit DDC included in the medium-to-large electronic device 1000-2 can be reduced as the number of channels is reduced. In addition, as the number of channels of a single IC chip including the data driving circuit DDC is reduced, the cost of the IC chip can be reduced.

[0078] The data driving circuit DDC receives a first control signal DCS and an image data signal DATA from a driving controller TC. The data driving circuit DDC converts the image data signal DATA into a data signal, and outputs the data signal to the channel lines CL1 to CLx. The data signal is an analog voltage corresponding to a gray level value of the image data signal DATA. The demultiplexer DM may electrically connect some of the data lines DL1 to DLm to the channel lines CL1 to CLx, and the data signal may be output to some of the data lines DL1 to DLm. For example, the demultiplexer DM may electrically connect some of the data lines DL1 to DLm to one of the channel lines CL1 to CLx.

[0079] In an embodiment, the first drive circuit SDC1 is connected to the first gate lines GWL1-1 to GWL1-n, and the second drive circuit SDC2 is connected to the second gate lines GWL2-1 to GWL2-n. The first drive circuit SDC1 and the second drive circuit SDC2 may receive a second control signal SCS from the drive controller TC, and may provide scan signals to the first gate lines GWL1-1 to GWL1-n and the second gate lines GWL2-1 to GWL2-n based on the second control signal SCS.

[0080] The scan signal can be set to a voltage that turns on the transistor receiving the scan signal. For example, the scan signal provided to the P-type transistor can be set to a logic low level, and the scan signal provided to the N-type transistor can be set to a logic high level. In the following, when the scan signal is supplied or activated, this can mean that the scan signal is supplied at a logic level that turns on the transistor controlled by the scan signal. In addition, when the scan signal is disabled, this can mean that the scan signal is supplied at a logic level that turns off the transistor controlled by the scan signal.

[0081] In the embodiment of the present disclosure, the first driving circuit SDC1 and the second driving circuit SDC2 are included in the display panel 100. For example, the pixel PXij includes a light emitting element ED (refer to Figure 5 ) and a pixel circuit PDC (refer to Figure 5 ). The pixel circuit PDC may include one or more transistors and one or more capacitors. The first drive circuit SDC1 and the second drive circuit SDC2 may include transistors formed by the same process as the pixel circuit PDC.

[0082] In the embodiment of the present disclosure, the first drive circuit SDC1 and the second drive circuit SDC2 are spaced apart from each other, and the active area 1000A is interposed between the first drive circuit SDC1 and the second drive circuit SDC2. However, the present disclosure is not limited thereto. For example, the first drive circuit SDC1 and the second drive circuit SDC2 may be disposed on the same side of the active area 1000A, or at least a portion of the first drive circuit SDC1 and at least a portion of the second drive circuit SDC2 may be disposed in the active area 1000A.

[0083] Figure 5 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present disclosure.

[0084] Reference Figure 5 , the pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. In an embodiment of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in response to a data signal DT. The light emitting element ED may emit light having a specific brightness in response to the amount of current provided from the pixel circuit PDC.

[0085] The pixel driving circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a capacitor Cst. The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in FIG. 1 is merely illustrative, and various changes and modifications may be made to the configuration of the pixel circuit PDC.

[0086] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be transistors having an LTPS semiconductor layer.

[0087] The first transistor T1 can directly affect the brightness of the light emitting element ED. The first transistor T1 may include a semiconductor layer formed of polysilicon with high reliability. Therefore, a display device with high resolution can be realized. Oxide semiconductors have high carrier mobility and low leakage current, and therefore even if the operation time is long, the voltage drop is not large. That is, even during low-frequency operation, the color of the image does not change greatly depending on the voltage drop, and therefore low-frequency operation is possible. Since oxide semiconductors have low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be implemented by oxide semiconductors to reduce power consumption while preventing leakage current that may flow to the gate electrode of the first transistor T1.

[0088] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the other transistors may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0089] However, the configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel circuit PDC shown in is merely illustrative, and various changes and modifications may be made to the configuration of the pixel circuit PDC. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0090] The i-th initialization scan line GILi, the i-th compensation scan line GCLi, the i-th gate line GWLi (also referred to as the gate line GWLi), the i-th black scan line GBLi, and the i-th emission control line ECLi may transmit the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, the i-th write scan signal GWi, the i-th black scan signal GBi, and the i-th emission control signal EMi to the pixel PXij, respectively. The j-th data line DLj (also referred to as the data line DLj) transmits the data signal DT to the pixel PXij. The data signal DT may have a voltage level corresponding to the image signal.

[0091] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0092] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 can receive the data signal DT transmitted by the j-th data line DLj according to the switching operation of the second transistor T2, and can supply a driving current to the light emitting element ED.

[0093] The second transistor T2 is connected between the jth data line DLj and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the jth data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the ith gate line GWLi. The second transistor T2 may be turned on according to the ith write scan signal GWi transmitted through the ith gate line GWLi, and may transmit the data signal DT transmitted from the jth data line DLj to the first electrode of the first transistor T1.

[0094] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the i-th compensation scan line GCLi. The third transistor T3 may be turned on according to the i-th compensation scan signal GCi transmitted through the i-th compensation scan line GCLi, and may diode-connect the first transistor T1 by connecting the third electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0095] The fourth transistor T4 is connected between the first initialization voltage line VL3 through which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 through which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the i-th initialization scan line GILi. The fourth transistor T4 is turned on according to the i-th initialization scan signal GIi transmitted through the i-th initialization scan line GILi. The turned-on fourth transistor T4 initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage VINT to the first node N1.

[0096] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the i-th emission control line ECLi. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the i-th emission control line ECLi.

[0097] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the i-th emission control signal EMi transmitted through the i-th emission control line ECLi. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then can be transmitted to the light emitting element ED through the sixth transistor T6.

[0098] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 through which a second initialization voltage VAINT is transmitted, a second electrode connected to a second node N2, and a third electrode (e.g., a gate electrode) connected to an i-th black scan line GBLi. In an embodiment, a voltage level of the second initialization voltage VAINT is lower than or equal to a voltage level of the first initialization voltage VINT.

[0099] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the opposite end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. In an embodiment, the second driving voltage ELVSS has a voltage level lower than the first driving voltage ELVDD.

[0100] Figure 6 is a cross-sectional view showing a portion of a display device DD according to an embodiment of the present disclosure.

[0101] Reference Figure 6 The display device DD may include a display panel 100, a sensor 200, and an anti-reflection layer 300. Depending on the electronic device to which the display device DD is applied, at least one of the sensor 200 and the anti-reflection layer 300 may be omitted. Figure 6 In addition to the components shown in , the display device DD may further include other components, for example, a window.

[0102] The display panel 100 may include a base layer 110 , a barrier layer BRL, a buffer layer BFL, a circuit layer 120 , an element layer 130 , and an encapsulation layer 140 .

[0103] The base layer 110 may be a glass substrate, a metal substrate or a polymer substrate, etc. However, the base layer 110 is not limited thereto. For example, the base layer 110 may be an inorganic layer, an organic layer or a composite layer. In an embodiment of the present disclosure, the base layer 110 includes a plurality of sub-base layers. For example, each of the plurality of sub-base layers may include at least one of a polyimide resin, an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin and a perylene resin. The "~~" class resin described herein refers to a resin including a "~~" functional group.

[0104] The barrier layer BRL may be disposed on the base layer 110. The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer 110 into the first semiconductor pattern SCP1. In addition, the buffer layer BFL may adjust a speed at which heat is provided during a crystallization process for forming the first semiconductor pattern SCP1, thereby enabling the first semiconductor pattern SCP1 to be uniformly formed.

[0105] Each of the barrier layer BRL and the buffer layer BFL may include a plurality of inorganic layers, and each of the plurality of inorganic layers may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon, but is not limited thereto.

[0106] The first lower metal layer BML1 may be disposed between the barrier layer BRL and the buffer layer BFL. The first lower metal layer BML1 may be referred to as a first lower layer, a first lower light blocking layer, a first lower electrode layer, a first lower shielding layer, a first light blocking layer, a first metal layer, a first electrode layer, a first shielding layer, or a first overlapping layer. Figure 6 Unlike in the embodiment of the present disclosure, the first lower metal layer BML1 may be disposed between the barrier layer BRL and the plurality of inorganic layers. In an embodiment of the present disclosure, the first lower metal layer BML1 is omitted.

[0107] One pixel PXij may include a light emitting element ED and a pixel circuit PDC. The circuit layer 120 may be disposed on the buffer layer BFL, and the element layer 130 may be disposed on the circuit layer 120. Figure 6 , the pixel circuit PDC may be included in the circuit layer 120 , and the light emitting element ED may be included in the element layer 130 .

[0108] exist Figure 6 In the figure, as an example, a silicon thin film transistor S-TFT and an oxide thin film transistor O-TFT of a pixel circuit PDC are shown. The silicon thin film transistor S-TFT can be a reference Figure 5 One of the described first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, and seventh transistor T7, and the oxide thin film transistor O-TFT may be one of the third transistor T3 and fourth transistor T4.

[0109] The first semiconductor pattern SCP1 may be disposed on the buffer layer BFL. The first semiconductor pattern SCP1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SCP1 may include low temperature polycrystalline silicon.

[0110] Figure 6 Only a portion of the first semiconductor pattern SCP1 disposed on the buffer layer BFL is shown, and the first semiconductor pattern SCP1 may be additionally disposed in other regions. The first semiconductor pattern SCP1 may be arranged across pixels according to a specific rule. The first semiconductor pattern SCP1 may have different electrical properties depending on whether the first semiconductor pattern SCP1 is doped. The first semiconductor pattern SCP1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or may be a region doped more lightly than the first region.

[0111] In an embodiment, the conductivity of the first region is higher than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the first semiconductor pattern SCP1 may be an active region of a transistor, another portion of the first semiconductor pattern SCP1 may be a source or drain of the transistor, and another portion of the first semiconductor pattern SCP1 may be a connection electrode or a connection signal line.

[0112] The source region SE1, the active region AC1, and the drain region DE1 of the silicon thin film transistor S-TFT may be formed by the first semiconductor pattern SCP1. The source region SE1 and the drain region DE1 may extend in opposite directions from the active region AC1 on a given cross section.

[0113] exist Figure 6 , a portion of a connection signal line CSL formed by the first semiconductor pattern SCP1 is shown. The connection signal line CSL may be electrically connected to the sixth transistor T6 (refer to Figure 5 ) and the second electrode of the seventh transistor T7 (refer to Figure 5 )'s second electrode.

[0114] The circuit layer 120 may include a plurality of inorganic layers and a plurality of organic layers. In an embodiment, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 sequentially stacked on the buffer layer BFL are inorganic layers, and the sixth insulating layer 60 and the seventh insulating layer 70 are organic layers. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be referred to as inorganic insulating layers. In an embodiment of the present disclosure, except for Figure 6 In addition to the insulating layer shown in FIG. , other insulating layers may be added and may be omitted. Figure 6 At least some of the insulating layers shown in .

[0115] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SCP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single silicon oxide layer. The insulating layers of the first insulating layer 10 and the circuit layer 120 to be described below may have a single-layer structure or a multi-layer structure.

[0116] The gate electrode GT1 of the silicon thin film transistor S-TFT may be disposed on the first insulating layer 10. The gate electrode GT1 may be a part of the metal pattern. The gate electrode GT1 overlaps the active area AC1. The gate electrode GT1 may be used as a mask in the process of doping the first semiconductor pattern SCP1. The gate electrode GT1 may include titanium, silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, or indium zinc oxide, but is not limited thereto.

[0117] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode GT1. The second insulating layer 20 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer 20 may have a single-layer structure including a silicon nitride layer.

[0118] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer and may have a single layer structure or a multilayer structure. For example, the third insulating layer 30 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer. Figure 5 One electrode Csta of the capacitor Cst may be disposed between the second insulating layer 20 and the third insulating layer 30. In addition, the other electrode of the capacitor Cst may be disposed between the first insulating layer 10 and the second insulating layer 20.

[0119] The second semiconductor pattern SCP2 may be disposed on the third insulating layer 30. The second semiconductor pattern SCP2 may include an oxide semiconductor. Depending on whether the metal oxide is reduced, the oxide semiconductor may include a plurality of regions that are different from each other. The region where the metal oxide is reduced (hereinafter, referred to as a reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as a non-reduction region). The reduction region is basically used as a source / drain or a signal line of a transistor. The non-reduction region basically corresponds to an active region (or semiconductor region or channel) of a transistor. In other words, a portion of the second semiconductor pattern SCP2 may be an active region of a transistor, another portion of the second semiconductor pattern SCP2 may be a source region or a drain region of a transistor, and another portion of the second semiconductor pattern SCP2 may be a signal transmission region.

[0120] The source region SE2, the active region AC2, and the drain region DE2 of the oxide thin film transistor O-TFT may be formed by the second semiconductor pattern SCP2. The source region SE2 and the drain region DE2 may extend in opposite directions from the active region AC2 on a given cross section.

[0121] The oxide thin film transistor O-TFT may overlap with the second lower metal layer BML2. The second lower metal layer BML2 may be referred to as a second lower layer, a second lower light blocking layer, a second lower electrode layer, a second lower shielding layer, a second light blocking layer, a second metal layer, a second electrode layer, a second shielding layer, or a second overlapping layer.

[0122] Light incident from below the display panel 100 may be blocked by the second lower metal layer BML2 and thus not provided to the active area AC2 of the oxide thin film transistor O-TFT. The second lower metal layer BML2 may be disposed between the second insulating layer 20 and the third insulating layer 30. The second lower metal layer BML2 may be connected to the capacitor Cst (refer to Figure 5 ) includes the same material and can be connected to the capacitor Cst (refer to Figure 5 ) is formed by the same process. In the embodiment of the present disclosure, the second lower metal layer BML2 is omitted.

[0123] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the second semiconductor pattern SCP2. The fourth insulating layer 40 may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the fourth insulating layer 40 may have a single-layer structure including silicon oxide.

[0124] The gate electrode GT2 of the oxide thin film transistor O-TFT may be disposed on the fourth insulating layer 40. The gate electrode GT2 may be a part of the metal pattern. The gate electrode GT2 overlaps the active area AC2. The gate electrode GT2 may be used as a mask in the process of reducing the second semiconductor pattern SCP2. In an embodiment of the present disclosure, the second lower metal layer BML2 is used as a bottom gate electrode. For example, the second lower metal layer BML2 may be electrically connected to the gate electrode GT2, or may receive the same signal as the gate electrode GT2. However, the present disclosure is not limited thereto.

[0125] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the gate electrode GT2. The fifth insulating layer 50 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. For example, the fifth insulating layer 50 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0126] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0127] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60, and may cover the second connection electrode CNE20.

[0128] Each of the sixth insulating layer 60 and the seventh insulating layer 70 may include an inorganic material or an organic material. For example, each of the sixth insulating layer 60 and the seventh insulating layer 70 may include, but is not limited to, a general polymer (such as polystyrene (PS)), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0129] The element layer 130 including the light emitting element ED may be disposed on the circuit layer 120. The light emitting element ED may include a pixel electrode AE ​​(or anode), a first functional layer HFL, an emission layer EL, a second functional layer EFL, and a common electrode CE (or cathode). The first functional layer HFL, the second functional layer EFL, and the common electrode CE may be commonly provided to the pixel.

[0130] The pixel electrode AE ​​may be disposed on the seventh insulating layer 70. The pixel electrode AE ​​may be connected to the second connection electrode CNE20 through the third contact hole CH3 penetrating the seventh insulating layer 70. The pixel electrode AE ​​may be a semi-transmissive and semi-reflective electrode, a transmissive electrode, or a reflective electrode. In an embodiment, the pixel electrode AE ​​may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the pixel electrode AE ​​may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked.

[0131] The pixel defining layer PDL may be disposed on the seventh insulating layer 70. A pixel defining opening PDLop for exposing a portion of the pixel electrode AE ​​may be defined in the pixel defining layer PDL. That is, the pixel defining layer PDL may cover the periphery of the pixel electrode AE. The emission region PXA may be defined by the pixel defining opening PDLop defined in the pixel defining layer PDL. For example, one emission region PXA may be defined for the light emitting element ED.

[0132] The pixel defining layer PDL may have a property of absorbing light. For example, the pixel defining layer PDL may be black in color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide of the metal.

[0133] The first spacer HSPC may be disposed on the pixel defining layer PDL. The first protruding spacer SPC may be disposed on the first spacer HSPC. The first spacer HSPC and the first protruding spacer SPC may be formed integrally with each other and may be formed of the same material. For example, the first spacer HSPC and the first protruding spacer SPC may be formed by the same process through a halftone mask. However, the present disclosure is not limited thereto. For example, the first spacer HSPC and the first protruding spacer SPC may include different materials and may be formed by separate processes.

[0134] The first functional layer HFL may be disposed on the pixel electrode AE, the pixel defining layer PDL, the first spacer HSPC, and the first protrusion spacer SPC. The first functional layer HFL may include a hole transport layer (HTL), a hole injection layer (HIL), or both a hole transport layer and a hole injection layer.

[0135] The emission layer EL may be disposed on the first functional layer HFL and may be disposed in a region corresponding to the pixel defining opening PDLop of the pixel defining layer PDL. The emission layer EL may include an organic material, an inorganic material, or an organic-inorganic material that emits light having a specific color. The second functional layer EFL may be disposed on the first functional layer HFL and may cover the emission layer EL. The second functional layer EFL may include an electron transport layer (ETL), may include an electron injection layer (EIL), or may include an electron transport layer and an electron injection layer. The common electrode CE may be disposed on the second functional layer EFL.

[0136] The element layer 130 may further include a cap layer CPL disposed on the common electrode CE. The cap layer CPL may be used to improve luminous efficiency through the principle of constructive interference. The cap layer CPL may include, for example, a material having a refractive index of 1.6 or greater for light having a wavelength of 589 nm. The cap layer CPL may be an organic cap layer including an organic material, an inorganic cap layer including an inorganic material, or a composite cap layer including an organic material and an inorganic material. For example, the cap layer CPL may include a carbocyclic compound, a heterocyclic compound, a compound containing an amine group, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof. Substituents including O, N, S, Se, Si, F, Cl, Br, I, or a combination thereof may selectively replace the carbocyclic compound, the heterocyclic compound, and the compound containing an amine group.

[0137] The encapsulation layer 140 may be disposed on the element layer 130. The encapsulation layer 140 may include an inorganic layer 141, an organic layer 142, and an inorganic layer 143, which are sequentially stacked. However, the layers constituting the encapsulation layer 140 are not limited thereto.

[0138] The inorganic layers 141 and 143 may protect the element layer 130 from moisture and oxygen, and the organic layer 142 may protect the element layer 130 from foreign substances such as dust particles. The inorganic layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer 142 may include an acrylic organic layer, but is not limited thereto.

[0139] The sensor 200 may be disposed on the display panel 100. The sensor 200 may be referred to as a sensor layer, an input sensing layer, or an input sensing panel. The sensor 200 may include a sensor base layer 210, a first sensor conductive layer 220, a sensor insulating layer 230, a second sensor conductive layer 240, and a sensor cover layer 250.

[0140] The sensor base layer 210 may be directly disposed on the display panel 100. The sensor base layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the sensor base layer 210 may be an organic layer including an epoxy resin, an acrylic resin, or an imide resin. The sensor base layer 210 may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0141] Each of the first sensor conductive layer 220 and the second sensor conductive layer 240 may have a single layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0142] The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide or indium zinc tin oxide. In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire or graphene.

[0143] The conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0144] The sensor insulating layer 230 may be disposed between the first sensor conductive layer 220 and the second sensor conductive layer 240. The sensor insulating layer 230 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0145] Alternatively, the sensor insulating layer 230 may include an organic film, which may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0146] The sensor cover layer 250 may be disposed on the sensor insulating layer 230 and may cover the second sensor conductive layer 240. The second sensor conductive layer 240 may include a conductive pattern. The sensor cover layer 250 may cover the conductive pattern and may reduce or eliminate the possibility of damaging the conductive pattern in a subsequent process. The sensor cover layer 250 may include an inorganic material. For example, the sensor cover layer 250 may include silicon nitride, but is not limited thereto. In an embodiment of the present disclosure, the sensor cover layer 250 may be omitted.

[0147] The anti-reflection layer 300 may be disposed on the sensor 200. The anti-reflection layer 300 may include a spacer layer 310, a plurality of color filters 320, and a planarization layer 330.

[0148] The spacer layer 310 may be disposed to overlap with the conductive pattern of the second sensor conductive layer 240. The sensor cover layer 250 may be disposed between the spacer layer 310 and the second sensor conductive layer 240. The spacer layer 310 may prevent external light from being reflected by the second sensor conductive layer 240. The material constituting the spacer layer 310 is a material that absorbs light. The spacer layer 310 may be a black layer. In an embodiment, the spacer layer 310 may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide of the metal.

[0149] The partition layer 310 may have a plurality of partition openings 310op defined therein. The partition openings 310op may overlap the plurality of emission layers EL, respectively. The color filter 320 may be disposed to correspond to the partition openings 310op. The color filter 320 may transmit light provided from the emission layer EL overlapped with the color filter 320.

[0150] The planarization layer 330 may cover the partition layer 310 and the color filter 320. The planarization layer 330 may include an organic material, and may provide a flat surface on an upper surface of the planarization layer 330. In an embodiment, the planarization layer 330 is omitted.

[0151] In an embodiment of the present disclosure, the anti-reflection layer 300 includes a reflection control layer instead of the color filter 320. For example, in Figure 6 The color filter 320 may be omitted, and a reflection control layer may be added at the position where the color filter 320 is omitted. The reflection control layer may selectively absorb light of a partial wavelength band from light reflected from inside the display panel and / or the electronic device, or light of a partial wavelength band from light incident from outside the display panel and / or the electronic device.

[0152] For example, the reflection control layer may absorb light in a first wavelength range of 490 nm to 505 nm and light in a second wavelength range of 585 nm to 600 nm, and thus the transmittance in the first wavelength range and the second wavelength range may be 40% or less. The reflection control layer may absorb light outside the wavelength range of red light, green light, and blue light emitted from the emission layer EL. As described above, since the reflection control layer absorbs light outside the wavelength range of red light, green light, and blue light emitted from the emission layer EL, a reduction in the brightness of the display panel and / or the electronic device may be prevented or minimized. In addition, the degradation of the luminous efficiency of the display panel and / or the electronic device may be prevented or minimized, and visibility may be improved.

[0153] The reflection control layer can be implemented with an organic layer including dyes, pigments or combinations thereof. The reflection control layer can include tetraazaporphyrin (TAP) compounds, porphyrin compounds, metal porphyrin compounds, oxazine compounds, squarylium compounds, triarylmethane compounds, polymethine compounds, anthraquinone compounds, phthalocyanine compounds, azo compounds, perylene compounds, xanthene compounds, diimmonium compounds, dipyrromethane compounds, cyanine compounds and combinations thereof.

[0154] In an embodiment, the reflection control layer has a transmittance in a range of about 64% to about 72%.The transmittance of the reflection control layer may be adjusted according to the content of the pigment and / or dye included in the reflection control layer.

[0155] In an embodiment of the present disclosure, the anti-reflection layer 300 may include a phase retarder and / or a polarizer. The anti-reflection layer 300 may include at least a polarizing film. In this case, the anti-reflection layer 300 may be attached to the sensor 200 through an adhesive layer.

[0156] Figure 7 is a view showing a portion of a display device according to an embodiment of the present disclosure. Figure 8 is a timing diagram of the operation of the display device according to an embodiment of the present disclosure. Fig.9A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig. 9B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0157] Reference Figure 7 , four first gate lines GWL1-1, GWL1-2, GWL1-3 and GWL1-4, four second gate lines GWL2-1, GWL2-2, GWL2-3 and GWL2-4, eight data lines DL and 32 pixels PX11 to PX18, PX21 to PX28, PX31 to PX38 and PX41 to PX48 are shown as examples.

[0158] The plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38 and PX41 to PX48 may include first pixels PX11, PX12, PX13, PX14, PX15, PX16, PX17 and PX18, second pixels PX21, PX22, PX23, PX24, PX25, PX26, PX27 and PX28, third pixels PX31, PX32, PX33, PX34, PX35, PX36, PX37 and PX38 and fourth pixels PX41, PX42, PX43, PX44, PX45, PX46, PX47 and PX48.

[0159] Each of the first pixels PX11 to PX18 may include a first emission region that outputs light having a first color. Each of the second pixels PX21 to PX28 may include a second emission region that outputs light having a second color different from the first color. Each of the third pixels PX31 to PX38 may include a third emission region that outputs light having a third color different from the first color and the second color. Each of the fourth pixels PX41 to PX48 may include a fourth emission region that outputs light having a second color. The first color may be red, the second color may be green, and the third color may be blue.

[0160] exist Figure 7 In the embodiment, the shape of the second emission region of the second pixels PX21 to PX28 is symmetrical with the shape of the fourth emission region of the fourth pixels PX41 to PX48.

[0161] In an embodiment of the present disclosure, the first emission region and the third emission region alternate with each other in the first direction DR1 and the second direction DR2. The second emission region and the fourth emission region may alternate with each other in the first direction DR1 and the second direction DR2. For example, each of the second emission regions may be disposed in a region defined by two first emission regions and two third emission regions adjacent to each other.

[0162] Each of the plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 may be electrically connected to a corresponding one of the first gate lines GWL1-1, GWL1-2, GWL1-3, and GWL1-4 and a corresponding one of the second gate lines GWL2-1, GWL2-2, GWL2-3, and GWL2-4 and a corresponding one of the data lines DL.

[0163] The data lines DL may include a first group DLG1 and a second group DLG2. For example, when a data signal is provided to the first group DLG1, the data signal is not provided to the second group DLG2. Also, when a data signal is provided to the second group DLG2, the data signal is not provided to the first group DLG1.

[0164] exist Figure 7 , four first group data lines DL1-1, DL1-2, DL1-3, and DL1-4 included in the first group DLG1 and four second group data lines DL2-1, DL2-2, DL2-3, and DL2-4 included in the second group DLG2 are shown as examples. The first group data lines DL1-1, DL1-2, DL1-3, and DL1-4 and the second group data lines DL2-1, DL2-2, DL2-3, and DL2-4 may alternate with each other. For example, the first group DLG1 may include odd data lines, and the second group DLG2 may include even data lines.

[0165] The first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4 and the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4 may be connected to the demultiplexer DM. For example, the demultiplexer DM may include a plurality of first control transistors CTR1 connected to the first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4 in one-to-one correspondence, and a plurality of second control transistors CTR2 connected to the second group of data lines DL21-1, DL2-2, DL2-3 and DL2-4 in one-to-one correspondence.

[0166] Reference Figure 7 and Figure 8 , the first control transistor CTR1 may be controlled by a first control signal CLA provided through a first control line CTL1 , and the second control transistor CTR2 may be controlled by a second control signal CLB provided through a second control line CTL2 .

[0167] In an embodiment of the present disclosure, the first gate lines GWL1-1, GWL1-2, GWL1-3 and GWL1-4 and the second gate lines GWL2-1, GWL2-2, GWL2-3 and GWL2-4 may alternate with each other in the second direction DR2. Hereinafter, the pixels between a first gate line (e.g., the first gate line GWL1-1) and a second gate line (e.g., the second gate line GWL2-1) are defined as a pixel row. Therefore, it can be understood that Figure 7 . Each of the pixels arranged in each pixel row may be electrically connected to a first gate line or a second gate line spaced apart from each other, the pixel row being interposed between the first gate line and the second gate line.

[0168] The first pixel PX11, the second pixel PX21, the third pixel PX31, the fourth pixel PX41, the first pixel PX12, the second pixel PX22, the third pixel PX32, and the fourth pixel PX42 may be arranged in a first pixel row. The third pixel PX33, the fourth pixel PX43, the first pixel PX13, the second pixel PX23, the third pixel PX34, the fourth pixel PX44, the first pixel PX14, and the second pixel PX24 may be arranged in a second pixel row. The first pixel PX15, the second pixel PX25, the third pixel PX35, the fourth pixel PX45, the first pixel PX16, the second pixel PX26, the third pixel PX36, and the fourth pixel PX46 may be arranged in a third pixel row. The third pixel PX37 , the fourth pixel PX47 , the first pixel PX17 , the second pixel PX27 , the third pixel PX38 , the fourth pixel PX48 , the first pixel PX18 , and the second pixel PX28 may be arranged in a fourth pixel row.

[0169] In an embodiment of the present disclosure, a plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 are divided into a plurality of first group pixels PX11 to PX18 and PX31 to PX38 connected to a first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4, and a plurality of second group pixels PX21 to PX28 and PX41 to PX48 connected to a second group of data lines DL2-1, DL2-2, DL2-3, and DL2-4. The plurality of first group pixels PX11 to PX18 and PX31 to PX38 may be referred to as a plurality of first pixels, and the first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4 may be referred to as a plurality of first data lines. The plurality of second group pixels PX21 to PX28 and PX41 to PX48 may be referred to as a plurality of second pixels, and the second group of data lines DL2 - 1 , DL2 - 2 , DL2 - 3 , and DL2 - 4 may be referred to as a plurality of second data lines.

[0170] In an embodiment of the present disclosure, the first group of pixels PX11 to PX18 and PX31 to PX38 may include first pixels PX11 to PX18 and third pixels PX31 to PX38. The second group of pixels PX21 to PX28 and PX41 to PX48 includes second pixels PX21 to PX28 and fourth pixels PX41 to PX48. Each of the first pixels PX11 to PX18 and the third pixels PX31 to PX38 may be electrically connected to a corresponding first gate line among the first gate lines GWL1-1, GWL1-2, GWL1-3, and GWL1-4, and each of the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48 may be electrically connected to a corresponding second gate line among the second gate lines GWL2-1, GWL2-2, GWL2-3, and GWL2-4.

[0171] The first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4 may be connected to the first pixels PX11 to PX18 and the third pixels PX31 to PX38, and the second group of data lines DL2-1, DL2-2, DL2-3, and DL2-4 may be connected to the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48. For example, the first pixels PX11 and PX15 and the third pixels PX33 and PX37 may be connected to the first group of data lines DL1-1, and the second pixels PX21 and PX25 and the fourth pixels PX43 and PX47 may be connected to the second group of data lines DL2-1. The description of this paragraph and Figure 7 The contents of the remaining first group of data lines and the second group of data lines that are not described are not understood from the diagram.

[0172] Reference Figure 7 and Figure 8 In an embodiment, one frame period FR includes a first subframe period HFR1 and a second subframe period HFR2 continuous with the first subframe period HFR1. In an embodiment, when the first subframe period HFR1 ends, the second subframe period HFR2 begins. Data corresponding to a complete image can be provided to the display panel in one frame period FR. Therefore, the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 can all emit light in one frame period FR.

[0173] According to an embodiment of the present disclosure, in the first subframe period HFR1, the first control signal CLA has an activation level and a disable level that alternate with each other, and the second control signal CLB has a disable level. The activation level may be a low level, and the disable level may be a high level. In addition, in the first subframe period HFR1, a plurality of first gate lines GWL1-1, GWL1-2, GWL1-3, and GWL1-4 may be sequentially activated. For example, the first gate lines GWL1-1 to GWL1-n (refer to Figure 4 ) may sequentially have an activation level (e.g., a low level). In the first subframe period HFR1, a data signal may be provided to a first group of pixels PX11 to PX18 and PX31 to PX38 connected to the first group of data lines DL1-1, DL1-2, DL1-3, and DL1-4 among the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48.

[0174] Refer to Figure 7 , Figure 8 and Fig.9A , in the first subframe period HFR1, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4 through the first control transistor CTR1. In an embodiment, when the first gate lines GWL1-1, GWL1-2, GWL1-3 and GWL1-4 are activated, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 transmit the first color data signal RD, the third color data signal BD, the first color data signal RD and the third color data signal BD to the first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4, respectively.

[0175] For example, in the first subframe period HFR1, each of the first channel line CL1 and the third channel line CL3 may alternately output the first color data signal RD and the third color data signal BD, and each of the second channel line CL2 and the fourth channel line CL4 may alternately output the third color data signal BD and the first color data signal RD. That is, in the first subframe period HFR1, the display device DD (refer to Figure 4) can display a first sub-image composed of a first color (or red) and a third color (or blue). For example, based on a combination of the first color and the third color, the first sub-image can be magenta. In an embodiment, a color data signal of the second color (or green) is not output in the first sub-frame period HFR1.

[0176] According to the embodiments of the present disclosure, Figure 8 As shown in, in the second subframe period HFR2, the first control signal CLA has a disable level (e.g., remains constant without switching), and the second control signal CLB has an activation level and a disable level (e.g., switches) that alternate with each other. In the second subframe period HFR2, the second gate lines GWL2-1, GWL2-2, GWL2-3, and GWL2-4 may be activated sequentially. For example, the second scanning signals GW2-1, GW2-2, ..., GW2-(n-3), GW2-(n-2), GW2-(n-1), and GW2-n provided to the second gate lines GWL2-1 to GWL2-n may sequentially have an activation level (e.g., a logic low level). In the second subframe period HFR2, data signals are provided to the second group of pixels PX21 to PX28 and PX41 to PX48 connected to the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4 among the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38 and PX41 to PX48.

[0177] Refer to Figure 7 , Figure 8 and Fig. 9B , in the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4 through the second control transistor CTR2. Therefore, when the second gate lines GWL2-1, GWL2-2, GWL2-3 and GWL2-4 are activated, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 transmit the (for example, green) second color data signal GD to the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4. For example, in the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 output the second color data signal GD. That is, in the second subframe period HFR2, the display device DD (refer to Figure 4 ) displays a second sub-image composed of the second color (or green). In an embodiment, in the second sub-frame period HFR2, the color data signals of the first color and the third color are not output.

[0178] According to an embodiment of the present disclosure, in each of the first subframe period HFR1 and the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can transmit the data signal to the first group of data lines DL1-1, DL1-2, DL1-3 and DL1-4 through the first control transistor CTR1, or can transmit the data signal to the second group of data lines DL2-1, DL2-2, DL2-3 and DL2-4 through the second control transistor CTR2.

[0179] That is, in one subframe period HFR1 or HFR2, only the first control transistor CTR1 may be activated or only the second control transistor CTR2 may be activated. In this case, different types of color data signals output in one subframe period HFR1 or HFR2 may be reduced. For example, instead of outputting three different types of color data signals per subframe period, one subframe period may be used to output two different types of color data signals, and another subframe period may be used to output a single type of color data signal. The color data signal may include a data signal corresponding to red, a data signal corresponding to green, and a data signal corresponding to blue, but is not limited thereto. For example, in an optional embodiment, the color data signal may include data signals corresponding to three colors different from red, green, and blue.

[0180] Therefore, the charging operation and the discharging operation based on the change of the type of the color data signal can be reduced or eliminated, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption. For example, an example of a change in the type of the color data signal may include a change from a red data signal to a green data signal. For example, the change in type may be reduced by maintaining the blue data signal during the second subframe period.

[0181] Fig.10 is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0182] Reference Figure 7 , Fig.9A , Fig. 9B and Fig.10 , briefly showing the levels of data voltages provided to the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 according to a pattern / image. In the table, channel "odd" corresponds to the first channel line CL1 and the third channel line CL3, and channel "even" corresponds to the second channel line CL2 and the fourth channel line CL4.

[0183] When the white pattern is displayed on the display device DD (refer to Figure 4), the first to fourth pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 all emit light in the first subframe period HFR1 and the second subframe period HFR2. For example, when the first pixels PX11 to PX18 display a gray level of 255, the data voltage may be 3.9V. When the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48 display a gray level of 255, the data voltage may be 3.8V, and when the third pixels PX31 to PX38 display a gray level of 255, the data voltage may be 3.4V. In addition, in the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be maintained at 3.8V.

[0184] When the red pattern is displayed in the display device DD, the first pixels PX11 to PX18 emit light, and the second to fourth pixels PX21 to PX28, PX31 to PX38, and PX41 to PX48 do not emit light. For example, when the second and fourth pixels PX21 to PX28 and PX41 to PX48 display 0 grayscale, the data voltage may be 6.5V. When the third pixels PX31 to PX38 display 0 grayscale, the data voltage may be 6.6V. For example, when the pixel receives the data voltage displaying 0 grayscale, it does not emit light. In the first subframe period HFR1, the levels of the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be repeatedly changed to 3.9V and 6.6V, or alternate between 3.9V and 6.6V. In the second sub frame period HFR2 , the first channel line CL1 , the second channel line CL2 , the third channel line CL3 , and the fourth channel line CL4 may be maintained at 6.5V.

[0185] When the green pattern is displayed in the display device DD, the second and fourth pixels PX21 to PX28 and PX41 to PX48 emit light, and the first and third pixels PX11 to PX18 and PX31 to PX38 do not emit light. For example, when the first pixels PX11 to PX18 display 0 grayscale, the data voltage may be 6.7V. In the first subframe period HFR1, the levels of the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be repeatedly changed to 6.7V and 6.6V, or alternate between 6.7V and 6.6V. In the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be maintained at 3.8V.

[0186] When the blue pattern is displayed in the display device DD, the third pixels PX31 to PX38 emit light, and the first pixels PX11 to PX18, the second pixels PX21 to PX28, and the fourth pixels PX41 to PX48 do not emit light. In the first subframe period HFR1, the levels of the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be repeatedly changed to 3.4 V and 6.7 V, or alternate between 3.4 V and 6.7 V. In the second subframe period HFR2, the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4 may be maintained at 6.5 V.

[0187] According to an embodiment of the present disclosure, switching in which a voltage change occurs is reduced or eliminated in the second subframe period HFR2. In addition, when displaying a white pattern and a green pattern, the switching in the first subframe period HFR1 may only generate a specific voltage difference (e.g., 0.5V or 0.1V) due to the color difference. Therefore, the charging operation and the discharging operation may be reduced, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0188] Fig.11 is a view showing a portion of a display device according to an embodiment of the present disclosure. Fig. 12A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig. 12B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0189] Reference Fig.11 , a plurality of pixels PX11 to PX18, PX21 to PX28, PX31 to PX38, and PX41 to PX48 are divided into a plurality of first groups of pixels PX11 to PX18 and PX31 to PX38 and a plurality of second groups of pixels PX21 to PX28 and PX41 to PX48. The first group of pixels PX11 to PX18 and PX31 to PX38 may include first pixels PX11 to PX18 and third pixels PX31 to PX38. The second group of pixels PX21 to PX28 and PX41 to PX48 includes second pixels PX21 to PX28 and fourth pixels PX41 to PX48. Each of the first pixels PX11 to PX18 and the third pixels PX31 to PX38 can be electrically connected to a corresponding first gate line among the first gate lines GWL1-1, GWL1-2, GWL1-3 and GWL1-4, and each of the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48 can be electrically connected to a corresponding second gate line among the second gate lines GWL2-1, GWL2-2, GWL2-3 and GWL2-4.

[0190] The first group of data lines DL1-1a, DL1-2a, DL1-3a, and DL1-4a may include first-first group of data lines DL1-1a and DL1-3a connected to first pixels PX11 to PX18 and first-second group of data lines DL1-2a and DL1-4a connected to third pixels PX31 to PX38.

[0191] For example, the first pixels PX11 and PX15 are connected to the first-first group data line DL1-1a, and the third pixels PX31, PX33, PX35, and PX37 are connected to the first-second group data line DL1-2a. The first pixels PX12, PX13, PX16, and PX17 are connected to the first-first group data line DL1-3a, and the third pixels PX32, PX34, PX36, and PX38 are connected to the first-second group data line DL1-4a.

[0192] The second pixels PX21 and PX25 and the fourth pixels PX43 and PX47 are connected to the second group of data lines DL2-1a. The second group of data lines DL2-1a, DL2-2a, DL2-3a and DL2-4a are connected to the second pixels PX21 to PX28 and the fourth pixels PX41 to PX48. Fig.11 The diagram is used to understand the contents of the remaining second group of data lines that are not described.

[0193] In an embodiment, the first-first group of data lines DL1-1a, the second group of data lines DL2-1a, the first-second group of data lines DL1-2a, the second group of data lines DL2-2a, the first-first group of data lines DL1-3a, the second group of data lines DL2-3a, the first-second group of data lines DL1-4a and the second group of data lines DL2-4a are sequentially arranged in the first direction DR1.

[0194] Reference Fig.11 and Fig. 12A , in the first subframe period HFR1a, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the first group of data lines DL1-1a, DL1-2a, DL1-3a and DL1-4a through the first control transistor CTR1. The first channel line CL1 and the third channel line CL3 may sequentially output the first color data signal RD, and the second channel line CL2 and the fourth channel line CL4 may sequentially output the third color data signal BD.

[0195] According to an embodiment of the present disclosure, in one subframe period, data signals provided to pixels having the same color may be provided to the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4. For example, according to an embodiment of the present disclosure, when the display device DD (refer to Figure 4 ) displays a white or black pattern, in each of the first channel line CL1, the second channel line CL2, the third channel line CL3, and the fourth channel line CL4, a gray voltage difference representing a gray level of 255 for each color and a gray voltage difference representing a gray level of 0 for each color can be eliminated. Therefore, the charging operation and the discharging operation can be reduced, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0196] Reference Fig.11 and Fig. 12B , in the second subframe period HFR2a, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the second group of data lines DL2-1a, DL2-2a, DL2-3a and DL2-4a through the second control transistor CTR2. In the second subframe period HFR2a, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 output the second color data signal GD. That is, in the second subframe period HFR2a, the display device DD displays the second sub-image composed of the second color (or green). For example, the display device DD does not need to display the image composed of the first color and the third color during the second subframe period HFR2a.

[0197] Fig.13 is a view showing a portion of a display device according to an embodiment of the present disclosure. Fig.14A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig. 14B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0198] Reference Fig.13 The first group of data lines DL1-1b, DL1-2b, DL1-3b and DL1-4b include a first-first group of data lines DL1-1b and DL1-3b connected to the first pixels PX11, PX12, PX15 and PX16 and the third pixels PX33, PX34, PX37 and PX38, and a first-second group of data lines DL1-2b and DL1-4b connected to the second pixels PX23, PX24, PX27 and PX28 and the fourth pixels PX41, PX42, PX45 and PX46.

[0199] In an embodiment of the present disclosure, the second group of data lines DL2-1b, DL2-2b, DL2-3b and DL2-4b include a second-first group of data lines DL2-1b and DL2-3b connected to the second pixels PX21, PX22, PX25 and PX26 and the fourth pixels PX43, PX44, PX47 and PX48, and a second-second group of data lines DL2-2b and DL2-4b connected to the first pixels PX13, PX14, PX17 and PX18 and the third pixels PX31, PX32, PX35 and PX36.

[0200] In an embodiment of the present disclosure, the first-first group of data lines DL1-1b, the second-first group of data lines DL2-1b, the second-second group of data lines DL2-2b, the first-second group of data lines DL1-2b, the first-first group of data lines DL1-3b, the second-first group of data lines DL2-3b, the second-second group of data lines DL2-4b and the first-second group of data lines DL1-4b are arranged sequentially in the first direction DR1.

[0201] Reference Fig.13 and Fig.14A In the first subframe period HFR1b, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the first group of data lines DL1-1b, DL1-2b, DL1-3b and DL1-4b through the first control transistor CTR1. The first color data signal RD and the third color data signal BD may be alternately output to the first channel line CL1 and the third channel line CL3, and the second color data signal GD may be sequentially output to the second channel line CL2 and the fourth channel line CL4. That is, in the first subframe period HFR1b, the display device DD (refer to Figure 4 ) can display a first sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0202] Reference Fig.13 and Fig. 14B In the second subframe period HFR2b, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the second group of data lines DL2-1b, DL2-2b, DL2-3b and DL2-4b through the second control transistor CTR2. The second color data signal GD may be sequentially output to the first channel line CL1 and the third channel line CL3, and the third color data signal BD and the first color data signal RD may be alternately output to the second channel line CL2 and the fourth channel line CL4. That is, in the second subframe period HFR2b, the display device DD (refer to Figure 4) can display a second sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0203] According to an embodiment, in each of the first subframe period HFR1b and the second subframe period HFR2b, the switching of the channel line to which the second color data signal GD is provided can be minimized. In addition, even in the case of the channel line to which the first color data signal RD and the third color data signal BD are provided, the switching in each of the first subframe period HFR1b and the second subframe period HFR2b can only generate a specific voltage difference (for example, 0.5V or 0.1V) due to the color difference when displaying the white pattern and the green pattern. Therefore, the charging operation and the discharging operation can be reduced, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0204] In addition, according to an embodiment of the present disclosure, a sub-image consisting of a first color (or red), a second color (or green), and a third color (or blue) can be displayed in each of the first sub-frame period HFR1b and the second sub-frame period HFR2b. Therefore, the possibility of a color break-up phenomenon in which a color difference between the first sub-frame period HFR1b and the second sub-frame period HFR2b is visible can be reduced or eliminated.

[0205] Fig.15 is a view showing a portion of a display device according to an embodiment of the present disclosure. Fig.16A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig. 16B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0206] Reference Fig.15 The first group of data lines DL1-1c, DL1-2c, DL1-3c and DL1-4c include a first-first group of data lines DL1-1c connected to the first pixels PX11 and PX15, a first-second group of data lines DL1-2c and DL1-4c connected to the second pixels PX21, PX24, PX25 and PX28 and the fourth pixels PX42, PX43, PX46 and PX47, and a first-third group of data lines DL1-3c connected to the third pixels PX32, PX34, PX36 and PX38.

[0207] In an embodiment of the present disclosure, the second group of data lines DL2-1c, DL2-2c, DL2-3c and DL2-4c include a second-first group of data lines DL2-1c connected to the third pixels PX31, PX33, PX35 and PX37, a second-second group of data lines DL2-2c and DL2-4c connected to the second pixels PX22, PX23, PX26 and PX27 and the fourth pixels PX41, PX44, PX45 and PX48, and a second-third group of data lines DL2-3c connected to the first pixels PX12, PX13, PX16 and PX17.

[0208] In an embodiment of the present disclosure, the first-first group of data lines DL1-1c, the second-first group of data lines DL2-1c, the first-second group of data lines DL1-2c, the second-second group of data lines DL2-2c, the second-third group of data lines DL2-3c, the first-third group of data lines DL1-3c, the second-second group of data lines DL2-4c and the first-second group of data lines DL1-4c are arranged sequentially in the first direction DR1.

[0209] Reference Fig.15 and Fig.16A , in the first subframe period HFR1c, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the first group of data lines DL1-1c, DL1-2c, DL1-3c and DL1-4c through the first control transistor CTR1. In an embodiment, the first color data signal RD is sequentially output to the first channel line CL1, the second color data signal GD is sequentially output to the second channel line CL2 and the fourth channel line CL4, and the third color data signal BD is sequentially output to the third channel line CL3. That is, in the first subframe period HFR1c, the display device DD (refer to Figure 4 ) can display a first sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0210] Reference Fig.15 and Fig. 16B , in the second subframe period HFR2c, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 may be electrically connected to the second group of data lines DL2-1c, DL2-2c, DL2-3c and DL2-4c through the second control transistor CTR2. In an embodiment, the third color data signal BD is sequentially output to the first channel line CL1, the second color data signal GD is sequentially output to the second channel line CL2 and the fourth channel line CL4, and the first color data signal RD is sequentially output to the third channel line CL3. That is, in the second subframe period HFR2c, the display device DD (refer to Figure 4 ) can display a second sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0211] According to an embodiment of the present disclosure, in each of the first subframe period HFR1c and the second subframe period HFR2c, data signals provided to pixels having the same color are provided to a single channel line. Therefore, the charging operation and the discharging operation depending on the change in the type of the color data signal can be eliminated, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0212] In addition, according to an embodiment of the present disclosure, a sub-image consisting of a first color (or red), a second color (or green), and a third color (or blue) can be displayed in each of the first sub-frame period HFR1c and the second sub-frame period HFR2c. Therefore, the possibility of a color separation phenomenon in which a color difference between the first sub-frame period HFR1c and the second sub-frame period HFR2c is visible can be reduced or eliminated.

[0213] Fig.17 is a view showing a portion of a display device according to an embodiment of the present disclosure. Fig.18A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig.18B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0214] Reference Fig.17 The first group of data lines DL1-1d, DL1-2d, DL1-3d and DL1-4d include a first-first group of data lines DL1-1d connected to the first pixels PX11 and PX15, a first-second group of data lines DL1-2d connected to the third pixels PX31, PX33, PX35 and PX37, and a first-third group of data lines DL1-3d and DL1-4d connected to the second pixels PX22, PX24, PX26 and PX28 and the fourth pixels PX42, PX44, PX46 and PX48.

[0215] In an embodiment of the present disclosure, the second group of data lines DL2-1d, DL2-2d, DL2-3d and DL2-4d include the second-first group of data lines DL2-1d and DL2-2d connected to the second pixels PX21, PX23, PX25 and PX27 and the fourth pixels PX41, PX42, PX45 and PX47, the second-second group of data lines DL2-3d connected to the first pixels PX12, PX13, PX16 and PX17, and the second-third group of data lines DL2-4d connected to the third pixels PX32, PX34, PX36 and PX38.

[0216] In an embodiment of the present disclosure, the first-first group of data lines DL1-1d, the second-first group of data lines DL2-1d, the first-second group of data lines DL1-2d, the second-first group of data lines DL2-2d, the second-second group of data lines DL2-3d, the first-third group of data lines DL1-3d, the second-third group of data lines DL2-4d and the first-third group of data lines DL1-4d are arranged sequentially in the first direction DR1.

[0217] Reference Fig.17 and Fig.18A , in the first subframe period HFR1d, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the first group of data lines DL1-1d, DL1-2d, DL1-3d and DL1-4d through the first control transistor CTR1. The first color data signal RD is sequentially output to the first channel line CL1, the third color data signal BD is sequentially output to the second channel line CL2, and the second color data signal GD is sequentially output to the third channel line CL3 and the fourth channel line CL4. That is, in the first subframe period HFR1d, the display device DD (refer to Figure 4 ) can display a first sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0218] Reference Fig.17 and Fig.18B , in the second subframe period HFR2d, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the second group of data lines DL2-1d, DL2-2d, DL2-3d and DL2-4d through the second control transistor CTR2. The second color data signal GD is sequentially output to the first channel line CL1 and the second channel line CL2, the first color data signal RD is sequentially output to the third channel line CL3, and the third color data signal BD is sequentially output to the fourth channel line CL4. That is, in the second subframe period HFR2d, the display device DD (refer to Figure 4 ) can display a second sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0219] According to an embodiment of the present disclosure, in each of the first subframe period HFR1d and the second subframe period HFR2d, the data signal provided to the pixel having the same color is provided to the single channel line. Therefore, the charging operation and the discharging operation according to the change of the type of the color data signal can be eliminated, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0220] In addition, according to an embodiment of the present disclosure, a sub-image consisting of a first color (or red), a second color (or green), and a third color (or blue) can be displayed in each of the first sub-frame period HFR1d and the second sub-frame period HFR2d. Therefore, the possibility of a color separation phenomenon in which a color difference between the first sub-frame period HFR1d and the second sub-frame period HFR2d is visible can be reduced or eliminated.

[0221] Fig.19 is a view showing a portion of a display device according to an embodiment of the present disclosure. Fig. 20A is a view illustrating an operation of a display device according to an embodiment of the present disclosure. Fig. 20B is a view illustrating an operation of a display device according to an embodiment of the present disclosure.

[0222] Reference Fig.19 The first group of data lines DL1-1e, DL1-2e, DL1-3e and DL1-4e include a first-first group of data lines DL1-1e connected to the first pixels PX11 and PX15, a first-second group of data lines DL1-2e connected to the third pixels PX31, PX33, PX35 and PX37, and a first-third group of data lines DL1-3e and DL1-4e connected to the second pixels PX22, PX24, PX26 and PX28 and the fourth pixels PX42, PX44, PX46 and PX48.

[0223] In an embodiment of the present disclosure, the second group of data lines DL2-1e, DL2-2e, DL2-3e and DL2-4e include the second-first group of data lines DL2-1e and DL2-2e connected to the second pixels PX21, PX23, PX25 and PX27 and the fourth pixels PX41, PX43, PX45 and PX47, the second-second group of data lines DL2-3e connected to the first pixels PX12, PX13, PX16 and PX17, and the second-third group of data lines DL2-4e connected to the third pixels PX32, PX34, PX36 and PX38.

[0224] In an embodiment of the present disclosure, the first-first group of data lines DL1-1e, the first-second group of data lines DL1-2e, the second-first group of data lines DL2-1e, the second-first group of data lines DL2-2e, the second-second group of data lines DL2-3e, the second-third group of data lines DL2-4e, the first-third group of data lines DL1-3e and the first-third group of data lines DL1-4e are arranged sequentially in the first direction DR1.

[0225] Reference Fig.19 and Fig. 20A, in the first subframe period HFR1e, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the first group of data lines DL1-1e, DL1-2e, DL1-3e and DL1-4e through the first control transistor CTR1. The first color data signal RD is sequentially output to the first channel line CL1, the third color data signal BD is sequentially output to the second channel line CL2, and the second color data signal GD is sequentially output to the third channel line CL3 and the fourth channel line CL4. That is, in the first subframe period HFR1e, the display device DD (refer to Figure 4 ) can display a first sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0226] Reference Fig.19 and Fig. 20B , in the second subframe period HFR2e, the first channel line CL1, the second channel line CL2, the third channel line CL3 and the fourth channel line CL4 can be electrically connected to the second group of data lines DL2-1e, DL2-2e, DL2-3e and DL2-4e through the second control transistor CTR2. The second color data signal GD is sequentially output to the first channel line CL1 and the second channel line CL2, the first color data signal RD is sequentially output to the third channel line CL3, and the third color data signal BD is sequentially output to the fourth channel line CL4. That is, in the second subframe period HFR2e, the display device DD (refer to Figure 4 ) can display a second sub-image consisting of a first color (or red), a second color (or green) and a third color (or blue).

[0227] According to an embodiment of the present disclosure, in each of the first subframe period HFR1e and the second subframe period HFR2e, data signals provided to pixels having the same color are provided to a single channel line. Therefore, the charging operation and the discharging operation according to the change of the type of the color data signal can be eliminated, and thus the data driving circuit DDC (refer to Figure 4 ) power consumption.

[0228] In addition, according to an embodiment of the present disclosure, a sub-image consisting of a first color (or red), a second color (or green), and a third color (or blue) can be displayed in each of the first sub-frame period HFR1e and the second sub-frame period HFR2e. Therefore, the possibility of a color separation phenomenon in which a color difference between the first sub-frame period HFR1e and the second sub-frame period HFR2e is visible can be reduced or eliminated.

[0229] As described above, in each of the subframe periods, the channel line may transmit the data signal to the data line through the first control transistor, or may transmit the data signal to the data line through the second control transistor. That is, in one subframe period, only the first control transistor may be activated or only the second control transistor may be activated. In this case, different types of color data signals output in one subframe period may be reduced. Therefore, the charging operation and the discharging operation according to the change of the type of the color data signal may be reduced or eliminated, and thus the power consumption of the data driving circuit may be reduced.

[0230] In addition, in each of the subframe periods, a sub-image consisting of a first color (or red), a second color (or green), and a third color (or blue) can be displayed. Therefore, the possibility of a color separation phenomenon in which a color difference between subframe periods is visible can be reduced or eliminated.

[0231] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: A plurality of data lines are arranged in a first direction; A plurality of first gate lines are arranged in a second direction intersecting the first direction; a plurality of second gate lines arranged in the second direction; and a plurality of pixels, each of the plurality of pixels being connected to a corresponding one of the plurality of data lines and a corresponding one of the plurality of first gate lines and the plurality of second gate lines, the plurality of pixels comprising a first group of pixels and a second group of pixels, The plurality of data lines include a first group of data lines connected to the first group of pixels and a second group of data lines connected to the second group of pixels, wherein the data signal is provided to the first group of pixels in a first subframe period of a frame period, and The data signal is provided to the second group of pixels in a second sub-frame period adjacent to the first sub-frame period of the one frame period.

2. The display device according to claim 1, wherein: The plurality of first gate lines and the plurality of second gate lines alternate with each other in the second direction, wherein the plurality of first gate lines are sequentially activated in the first subframe period, and The plurality of second gate lines are sequentially activated in the second subframe period.

3. The display device according to claim 1, wherein: The display device further includes: a demultiplexer connected to the plurality of data lines, The demultiplexer includes a plurality of first control transistors connected to the first group of data lines in a one-to-one correspondence and a plurality of second control transistors connected to the second group of data lines in a one-to-one correspondence. wherein the plurality of first control transistors are configured to be controlled by a first control signal provided through a first control line, and The plurality of second control transistors are configured to be controlled by a second control signal provided via a second control line.

4. The display device according to claim 3, wherein: In the first subframe period, the first control signal has an activation level and a deactivation level that alternate with each other, and the second control signal has a deactivation level, and In the second subframe period, the first control signal has a disable level, and the second control signal has an activation level and a disable level that alternate with each other.

5. The display device according to claim 1, wherein: The plurality of pixels include: a first pixel configured to output light having a first color; a second pixel configured to output light having a second color different from the first color; a third pixel configured to output light having a third color different from the first color and the second color; and a fourth pixel configured to output light having the second color, wherein the first pixels and the third pixels are arranged alternately one after another in the first direction and the second direction, and The second pixels and the fourth pixels are arranged alternately one after another in the first direction and the second direction.

6. The display device according to claim 5, wherein: The first group of pixels includes the first pixel and the third pixel, and The second group of pixels includes the second pixel and the fourth pixel.

7. The display device according to claim 6, wherein: Each of the first pixel and the third pixel is electrically connected to a corresponding first gate line among the plurality of first gate lines, and Each of the second pixel and the fourth pixel is electrically connected to a corresponding second gate line among the plurality of second gate lines.

8. The display device according to claim 6, wherein: The first group of data lines are connected to the first pixel and the third pixel respectively, and the second group of data lines are connected to the second pixel and the fourth pixel respectively, and The first group of data lines and the second group of data lines alternate with each other.

9. The display device according to claim 6, wherein: The first group of data lines includes a first-first group of data lines connected to the first pixel and a first-second group of data lines connected to the third pixel, The second group of data lines are connected to the second pixel and the fourth pixel respectively, and The first-first group of data lines, one of the second group of data lines, the first-second group of data lines and the other of the second group of data lines are sequentially arranged.

10. The display device according to claim 5, wherein: The first group of data lines includes a first-first group of data lines connected to the first pixel and the third pixel and a first-second group of data lines connected to the second pixel and the fourth pixel, wherein the second group of data lines includes a second-first group of data lines connected to the second pixel and the fourth pixel and a second-second group of data lines connected to the first pixel and the third pixel, and The first-first group of data lines, the second-first group of data lines, the second-second group of data lines and the first-second group of data lines are arranged sequentially.

11. The display device according to claim 5, wherein: Each of the first pixel, the second pixel, the third pixel, and the fourth pixel is provided in plurality, The first group of data lines includes a first-first group of data lines connected to a first pixel among the plurality of first pixels, a first-second group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, a first-third group of data lines connected to a third pixel among the plurality of third pixels, and a first-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels. wherein the second group of data lines includes a second-first group of data lines connected to a third pixel among the plurality of third pixels, a second-second group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, a second-third group of data lines connected to the first pixel, and a second-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, and Among them, the first-first group of data lines, the second-first group of data lines, the first-second group of data lines, the second-second group of data lines, the second-third group of data lines, the first-fourth group of data lines, the second-fourth group of data lines and the first-fourth group of data lines are arranged sequentially.

12. The display device according to claim 5, wherein: Each of the first pixel, the second pixel, the third pixel, and the fourth pixel is provided in plurality, The first group of data lines includes a first-first group of data lines connected to a first pixel among the plurality of first pixels, a first-second group of data lines connected to a third pixel among the plurality of third pixels, a first-third group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, and a first-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels. wherein the second group of data lines includes a second-first group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, a second-second group of data lines connected to a first pixel among the plurality of first pixels, a second-third group of data lines connected to a third pixel among the plurality of third pixels, and a second-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, and Among them, the first-first group of data lines, the second-first group of data lines, the first-second group of data lines, the second-fourth group of data lines, the second-second group of data lines, the first-third group of data lines, the second-third group of data lines and the first-fourth group of data lines are arranged sequentially.

13. The display device according to claim 5, wherein: Each of the first pixel, the second pixel, the third pixel, and the fourth pixel is provided in plurality, The first group of data lines includes a first-first group of data lines connected to a first pixel among the plurality of first pixels, a first-second group of data lines connected to a third pixel among the plurality of third pixels, a first-third group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, and a first-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels. wherein the second group of data lines includes a second-first group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, a second-second group of data lines connected to a first pixel among the plurality of first pixels, a second-third group of data lines connected to a third pixel among the plurality of third pixels, and a second-fourth group of data lines connected to a second pixel among the plurality of second pixels and a fourth pixel among the plurality of fourth pixels, and Among them, the first-first group of data lines, the first-second group of data lines, the second-first group of data lines, the second-fourth group of data lines, the second-second group of data lines, the second-third group of data lines, the first-third group of data lines and the first-fourth group of data lines are arranged sequentially.

14. The display device according to claim 5, wherein: The first pixel and the third pixel are configured to emit light in the first sub frame period, and the second pixel and the fourth pixel are configured to emit light in the second sub frame period.

15. The display device according to claim 5, wherein: The first pixel, the second pixel, the third pixel, and the fourth pixel are configured to emit light in the first sub frame period and the second sub frame period.

16. A display device, wherein: The display device comprises: A plurality of first data lines arranged in a first direction; A plurality of second data lines arranged in the first direction; A plurality of gate lines are arranged in a second direction intersecting the first direction; a plurality of first pixels electrically connected to the plurality of first data lines and the plurality of gate lines; a plurality of second pixels electrically connected to the plurality of second data lines and the plurality of gate lines; and a demultiplexer including a plurality of first control transistors connected to the plurality of first data lines in a one-to-one correspondence and a plurality of second control transistors connected to the plurality of second data lines in a one-to-one correspondence, wherein, in a first subframe period of one frame period, a first control signal controlling the plurality of first control transistors has an activation level and a disable level that alternate with each other, and a second control signal controlling the plurality of second control transistors has a disable level, and In which, in a second sub-frame period adjacent to the first sub-frame period of the one frame period, the first control signal has a disable level, and the second control signal has an activation level and a disable level alternating with each other.

17. The display device according to claim 16, wherein: The plurality of gate lines include a plurality of first gate lines electrically connected to the plurality of first pixels and a plurality of second gate lines electrically connected to the plurality of second pixels, and wherein the plurality of first gate lines are sequentially activated in the first subframe period, and The plurality of second gate lines are sequentially activated in the second subframe period.

18. The display device according to claim 17, wherein: The plurality of first pixels and the plurality of second pixels include: first-first pixels configured to output light having a first color; second-second pixels configured to output light having a second color different from the first color; first-third pixels configured to output light having a third color different from the first color and the second color; and second-fourth pixels configured to output light having the second color, and The first-first pixel, the second-second pixel, the first-third pixel and the second-fourth pixel are configured to emit light in the one frame period.

19. The display device according to claim 18, wherein: The first-first pixel and the first-third pixel are configured to emit light in the first subframe period, and the second-second pixel and the second-fourth pixel are configured to emit light in the second subframe period, or The first-first pixel, the second-second pixel, the first-third pixel and the second-fourth pixel are configured to emit light in the first sub-frame period and the second sub-frame period.

20. A display device, wherein: The display device comprises: A plurality of data lines are arranged in a first direction; A plurality of gate lines are arranged in a second direction intersecting the first direction; a plurality of pixels electrically connected to the plurality of data lines and the plurality of gate lines; a plurality of first control transistors connected to some of the plurality of data lines in a one-to-one correspondence; and A plurality of second control transistors are connected to other data lines among the plurality of data lines in a one-to-one correspondence, wherein the data signal is provided to only some of the data lines connected to the plurality of first control transistors in a first subframe period of a frame period, and The data signal is provided only to the other data lines connected to the plurality of second control transistors in a second sub-frame period adjacent to the first sub-frame period of the one frame period.

Images