A memory information storage method, device, memory and storage medium

Abstract

The present invention discloses a memory information storage method, device, memory, and storage medium. The memory information storage method includes: writing target parameter data into a target word line; maintaining two groups of adjacent word lines adjacent to the target word line in an erased state; and writing the target parameter data into the remaining word lines, where the remaining word lines are word lines other than the target word line and the two groups of adjacent word lines. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line into the remaining word lines. By maintaining the two groups of adjacent word lines adjacent to the target word line in an erased state, interference from changes in the voltage of the adjacent word lines is reduced, effectively avoiding data interference and misreading, thereby improving the reliability and accuracy of stored data.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory information storage method, device, memory, and storage medium. Background Art

[0002] When NAND FLash is used in the client, it has an ECC error correction function. With the help of the ECC error correction function, the correctness of the data stored by the user can be judged just after it is written and after it has been stored for a certain period of time.

[0003] NAND flash itself contains a lot of important data written to fixed locations. After the chip is powered on, during a power-on read, this important data is read into the chip's latches. When the chip is used, the latch parameters (including the aforementioned important data) are used. However, during a power-on read, these parameters haven't yet been read into the latches, so the default parameters are used. For example, the voltage applied to the select word line (WL) during a read is specified. The chip's design allows this voltage to range from 0-2V, in 0.1V steps, and the default voltage is 0.1V. However, experimental results show that setting this voltage to 0.5V provides the best performance. Therefore, the 0.5V data is written to a dedicated block area on the chip. Similar voltage information is common and critical. If it's incorrect, the power-on read will fail, and the chip will not function properly.

[0004] During a power-on read, NAND Flash stores its parameters in a corresponding cache. However, these parameters are fixed by design and lack an ECC (Error Correction Code) algorithm, making them suboptimal for the NAND Flash. Furthermore, after the chip is deployed, this information is only read during power-on and is not erased or reprogrammed. This requires the NAND Flash to remain stable for its entire lifespan. If errors occur, the chip will no longer be able to read or write properly, resulting in poor reliability. Summary of the Invention

[0005] The present invention provides a memory information storage method that aims to improve the storage quality of important data information in NAND FLash itself, thereby ensuring the accuracy of this important data information. The present invention strengthens the target parameter data on the target word line by writing the same target parameter data as the target word line on other word lines. By keeping two groups of adjacent word lines adjacent to the target word line in an erased state, interference from changes in the voltage of adjacent word lines is reduced, effectively avoiding data interference and misreading, thereby improving the reliability and accuracy of stored data.

[0006] To achieve the above-mentioned purpose, the present invention proposes an information storage method for a memory.

[0007] The memory is a Nand flash memory, which includes a plurality of memory cells connected in series, each memory cell corresponding to a word line, and the method includes:

[0008] Writing target parameter data into the target word line;

[0009] maintaining two groups of adjacent word lines adjacent to the target word line in an erased state;

[0010] The target parameter data is written into the remaining word lines, which are the target word line and word lines other than the two groups of adjacent word lines.

[0011] Optionally, after writing the target parameter data into the remaining word lines, the method further includes:

[0012] When powering on and reading data, applying a conduction voltage to the two groups of adjacent word lines and the remaining word lines;

[0013] And, applying a read voltage to the target word line to obtain read data on the target word line.

[0014] Optionally, after applying a read voltage to the target word line to obtain read data on the target word line, the method further includes:

[0015] Verifying the read data on the target word line by using a positive and negative code verification method;

[0016] If the verification passes, the target parameter data is read into the latch.

[0017] Optionally, after verifying the read data, the method further includes:

[0018] If the verification fails, applying a read voltage to the remaining word lines to obtain read data on the remaining word lines;

[0019] The read data on the remaining word lines are verified by a positive and negative code verification method until the verification succeeds or all the verifications fail.

[0020] Optionally, after reading the target parameter data into the latch, the method further includes:

[0021] reading the target parameter data in the latch into a cache memory;

[0022] The Nand flash memory is configured using the target parameter data in the cache memory.

[0023] Optionally, the read voltage is configured to be between a first voltage threshold and a second voltage threshold, wherein the first voltage threshold is a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold is a threshold voltage when there are no electrons on the floating gate of the memory cell.

[0024] Optionally, the target parameter data includes non-default operating parameter data required by the Nand flash memory when reading data.

[0025] The present invention also proposes a memory information storage device, which includes a memory, a processor, and a computer program stored on the memory and runnable on the processor. When the computer program is executed by the processor, the steps of the above-mentioned memory information storage method are implemented.

[0026] The present invention also provides a memory comprising a Nand flash memory and a memory information storage device, and a plurality of serially connected memory cells, each memory cell corresponding to a word line, wherein the memory information storage device is the above-mentioned memory information storage device.

[0027] The present invention further provides a storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements the steps of the above-mentioned memory information storage method.

[0028] The technical solution of the information storage method of the memory of the present invention includes writing target parameter data into a target word line; maintaining two groups of adjacent word lines adjacent to the target word line in an erased state; and writing target parameter data into the remaining word lines, where the remaining word lines are word lines other than the target word line and the two groups of adjacent word lines. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line into the remaining word lines. By maintaining the two groups of adjacent word lines adjacent to the target word line in an erased state, interference from changes in the voltage of the adjacent word lines is reduced, effectively avoiding data interference and misreading, thereby improving the reliability and accuracy of stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a flow chart of a method for storing information in a memory according to an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a NAND FLash word line arrangement provided by an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the internal structure of a NAND FLash provided by an embodiment of the present invention;

[0032] Figure 4 Schematic diagram of a positive and negative code verification method provided by an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the influence between storage units provided by an embodiment of the present invention;

[0034] Figure 6 A schematic structural diagram of an information storage device of a memory provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0037] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element.

[0038] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0039] See Figure 1 , Figure 1 1 is a flow chart of a method for storing information in a memory provided by an embodiment of the present invention. The method for storing information in a memory includes the following steps:

[0040] S10 , writing target parameter data into the target word line.

[0041] In this embodiment, the memory is a Nand flash memory, which includes multiple storage cells connected in series. Nand flash memory can also be called NAND flash memory or Nand flash memory. Nand flash memory is a type of flash memory that uses a nonlinear macrocell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. In Nand flash memory, the storage cell is a double-layer floating gate MOS tube similar to NMOS, also known as a floating gate transistor. The storage cell consists of a source, a drain, a control electrode (usually a word line), and a floating gate. The floating gate is surrounded by insulating layers above and below and is used to store charge.

[0042] Writing (programming) a memory cell: By applying a high voltage to the control electrode, a quantum tunneling effect is triggered, causing electrons to be injected from the source through the insulating layer into the floating gate. This changes the charge state on the floating gate, which in turn affects the conduction state of the transistor, indicating the stored information (usually "0" or "1").

[0043] Memory cell erase operation: Erasing is usually performed in blocks. By applying a high voltage to the substrate, a quantum tunneling effect is triggered, which removes electrons from the floating gate and restores the transistor to its original state.

[0044] Memory cell read operation: The cell state is read by applying a low read voltage to the gate and detecting the conduction state between the source and drain. If there are electrons in the floating gate, the read voltage is offset, turning the transistor off, indicating that the stored information is "0". If there are no electrons in the floating gate, the transistor is on, indicating that the stored information is "1".

[0045] The word line distribution of NAND FLash is as follows Figure 2 As shown, Figure 2 This is a schematic diagram of a word line arrangement of a NAND FLash provided by an embodiment of the present invention. The internal structure of the NAND FLash is as follows Figure 3 As shown, Figure 3 This is a schematic diagram of the internal structure of a NANDFLash provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the internal structure of a NAND FLash provided by an embodiment of the present invention.

[0046] exist Figure 2 In the embodiment of the present invention, a method of writing many WLs is adopted to strengthen the storage of target parameter data. n The writing method remains unchanged. n-2 , WL n-3 , WL n-4 , WL n+2 , WL n+3 , WL n+4 Write the target word line WL n Same data as WL n Two adjacent word lines WL n+1 and WL n-1 Still keep the Erase status.

[0047] Power on read (power on read) still reads and verifies the target word line WL n , the remaining word lines WL n-2 , WL n-3 , WL n-4 , WL n+2 , WL n+3 , WL n+4 The data above can reinforce the data of WLn.

[0048] The target word line may be a middle word line. A group of word lines may include at least one word line, that is, the target word line may be one word line or multiple word lines. In the embodiment of the present invention, considering that there is less target parameter data in the NAND Flash, the target word line may be a middle word line.

[0049] exist Figure 2In, WL n For the target word line, the above target parameter data can be non-default parameter data of NAND Flash. The default parameter data of NAND Flash is fixed parameter data stored in the cache. If the non-default parameter data of NAND Flash is not read, the NAND Flash will be configured according to the default parameter data in the cache.

[0050] After the target parameter data is written into the target word line, there are electrons in the Floating Gate in the cell corresponding to the target word line, and the corresponding flag data is "0". If the target parameter data is not written into the target word line, there are no electrons in the Floating Gate in the cell corresponding to the target word line, and the corresponding flag data is "1".

[0051] exist Figure 3 In the example, cells are connected in series to form a cell string (…, WL n-4 , WL n-3 , WL n-2 , WL n-1 , WL n , WL n+1 , WL n+2 , WL n+3 , WL n+4 , …), the source end of the current cell is connected to the drain end of the next cell, and the drain end of the first cell is connected to the bit line.

[0052] S20 , maintaining two groups of adjacent word lines adjacent to the target word line in an erased state.

[0053] In an embodiment of the present invention, the adjacent word lines are adjacent to the target word line and may be a group of word lines preceding the target word line and a group of word lines following the target word line, with the two groups of adjacent word lines preceding and following the target word line, respectively. The erased state indicates that no data is written, i.e., in the cell corresponding to the adjacent word line, the floating gate has no electrons and the corresponding flag data is "1."

[0054] Each group of adjacent word lines includes at least one word line. Specifically, the number of word lines can be determined based on the degree of interference between adjacent word lines. The greater the degree of interference between two adjacent word lines, the more word lines there are in each group of adjacent word lines. This can reduce interference when adjacent word lines change.

[0055] exist Figure 2 In the example, the adjacent word line may be a WL adjacent to the target word line. n , namely WL n+1 and WL n-1.WL n+1 and WL n-1 Remains in erased state and no data is written.

[0056] S30 , writing target parameter data into the remaining word lines.

[0057] In an embodiment of the present invention, the above-mentioned remaining word lines are word lines other than the target word line and the adjacent word lines. The target parameter data identical to that of the target word line is written into the above-mentioned remaining word lines, thereby reinforcing the target parameter data of the target word line. When the target parameter data is written into the target word line and the target parameter data is written into the remaining word lines, when the power is turned on and the data is read, the probability of the target word line reading the flag data 0 is increased.

[0058] The information storage method of the memory of this embodiment is implemented by writing target parameter data into a target word line; maintaining two groups of adjacent word lines adjacent to the target word line in an erased state; and writing target parameter data into the remaining word lines, where the remaining word lines are word lines other than the target word line and the two groups of adjacent word lines. The present invention reinforces the target parameter data on the target word line by writing the same target parameter data as the target word line onto the remaining word lines. By maintaining the two groups of adjacent word lines adjacent to the target word line in an erased state, interference from changes in the voltage of the adjacent word lines is reduced, effectively avoiding data interference and misreading, thereby improving the reliability and accuracy of stored data.

[0059] It is understandable that in the specific implementation of this application, when memory data, control data, parameter data and other related data are involved, when the embodiments in this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data, as well as the training and use of various models need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0060] Optionally, after the step of writing target parameter data in the remaining word lines, a conduction voltage can be applied to two groups of adjacent word lines and the remaining word lines when the power is turned on to read data; and a read voltage can be applied to the target word line to obtain the read data on the target word line.

[0061] In an embodiment of the present invention, during the initial stage of powering on and reading data, a conduction voltage is first applied to two groups of adjacent word lines and the remaining word lines. This places the adjacent word lines and the remaining word lines in a conducting state, thereby creating the necessary conditions for subsequent data reading operations. Application of the conduction voltage is typically achieved through a voltage control circuit within the memory.

[0062] The on-state voltage is a relatively high voltage, which can be determined based on the default parameters of the NAND Flash. If the voltage is too low, the word line may not be fully turned on, resulting in data read failure. Therefore, in actual applications, it is necessary to select an appropriate on-state voltage value based on the specific characteristics and usage requirements of the memory.

[0063] After applying the turn-on voltage to the two sets of adjacent word lines and the remaining word lines, a read voltage must next be applied to the target word line. The read voltage is a voltage specifically used to read data from a memory cell, and its magnitude is typically configured between a first voltage threshold and a second voltage threshold. The first voltage threshold corresponds to the threshold voltage when there are no electrons on the floating gate of the memory cell, while the second voltage threshold corresponds to the threshold voltage when there are electrons on the floating gate. By applying the read voltage, the data state of the memory cell can be determined, thereby reading the stored information.

[0064] When a read voltage is applied to the target word line, the current or voltage signal in the memory cell will change accordingly. Figure 3 , Bit Line is charged during Read, except the target word line WL n The other word lines WL are connected with a higher voltage to turn on the cell. n The read voltage is added. If there are electrons on the floating gate of the cell, the voltage threshold VT is higher (VT1, the first voltage threshold). If there are no electrons on the floating gate, VT is very low (VT2, the second voltage threshold). The read voltage is between VT1 and VT2.

[0065] Furthermore, a cell can be considered a resistor. When voltage is applied to WL, the cell conducts, and it can be considered a small resistor. When the voltage on WL is insufficient to conduct the cell, it can be considered a large resistor. If there are electrons in the floating gate, the cell does not conduct, the BL (Block) charge cannot be discharged, and the read flag data is 0. If there are no electrons in the floating gate, the cell can conduct, the BL charge can be discharged, and the read flag data is 1.

[0066] By applying a turn-on voltage to two groups of adjacent word lines and the remaining word lines, and applying a read voltage to a target word line, data in a memory cell can be effectively read, and the accuracy and reliability of the data can be ensured.

[0067] Optionally, after applying a read voltage to the target word line to obtain the read data on the target word line, the read data on the target word line can also be verified by a positive and negative code verification method; if the verification passes, the target parameter data is read into the latch.

[0068] In the embodiment of the present invention, in order to ensure the correctness of the target parameter data, the positive and negative codes may be written to the target parameter data, and multiple copies of the positive and negative codes may be written.

[0069] Verification checks detect errors during data transmission or storage by comparing the original data value with its inverted value. In Nand flash memory, verification checks are used to ensure that the data read from the target word line is correct.

[0070] Specifically, when a read voltage is applied to the target wordline, the memory outputs the data read from that wordline. To verify the correctness of this data, a complement of this data is generated. This complement is typically generated by inverting each bit of the data, turning 0 into 1 and 1 into 0. The system then compares the original data with the generated complement. If the two are identical, the data read was error-free and the verification passes. If there is a discrepancy, the data may have been interfered with or damaged, and the verification fails.

[0071] Specifically, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a positive and negative code verification method provided by an embodiment of the present invention. Figure 4 In the example, multiple copies are included, namely copy1, copy2, copy3, copy4, ..., each copy includes byte1 positive code, byte1 inverse code, byte2 positive code, byte2 inverse code, ...

[0072] After the chip is powered on, when performing a Power on read, if the verification passes, the information will be read into the latch of the chip. When the user uses the chip, the parameters in the latch will be used.

[0073] like Figure 4 When doing power on read, the positive and negative codes are checked based on the byte. If the positive and negative code check fails, the next copy is read from the failed byte until all information is correctly read into the latch. Otherwise, the status inside the chip will be set to 1. In the embodiment of the present invention, the target word line and the remaining word lines are checked according to Figure 3 In the method of writing information, the adjacent blurred lines adjacent to the target word line in the block are all in the FF state (erased state).

[0074] Optionally, after the step of verifying the read data, if the verification fails, a read voltage can be applied to the remaining word lines to obtain the read data on the remaining word lines; the read data on the word lines can be verified by a positive and negative code verification method until the verification succeeds or all verifications fail.

[0075] In an embodiment of the present invention, considering that the target parameter data is also written into the remaining word lines, after the read data verification of the target word line fails, a read voltage can be applied to the remaining word lines to obtain the read data on the remaining word lines, and the read data on the remaining word lines is verified. The verification method is the same as the verification method for the target word line and is not further elaborated here.

[0076] Optionally, after the step of reading the target parameter data into the latch, the target parameter data in the latch may be read into a cache memory; and the Nand flash memory is configured using the target parameter data in the cache memory.

[0077] In the embodiments of the present invention, the latch described above acts as a temporary storage element, offering fast data access. However, due to its limited storage capacity and access speed, it is generally unsuitable as a storage medium for long-term or large amounts of data. Therefore, the target parameter data in the latch can be read into a cache memory.

[0078] Cache memory is a component in a computer system that temporarily stores data for quick access. It sits between the main memory and the processor, improving overall system performance by reducing the number of times the processor accesses main memory. In the context of Nand flash memory, cache memory can be used to store frequently accessed or critical data, such as configuration parameters and index information, so that it can be quickly accessed when needed.

[0079] The process of reading data from latches into cache memory typically involves data movement and cache management strategies. Specifically, during a power-on read, if the target wordline read data passes verification, the NAND Flash reads its target parameter data into the read latch, which is then read from the latch into the corresponding cache. When the NAND Flash is used, the target parameter data is read from the cache to configure the NAND Flash.

[0080] Once the target parameter data has been successfully read into the cache memory, it can be used to configure the Nand flash memory. During the configuration process, the cache memory's advantage lies in its fast access speed. Since configuration parameters often need to be read and applied before memory initialization or specific operations, storing them in the cache memory can significantly reduce configuration time and improve memory response speed.

[0081] Optionally, the read voltage is configured to be between a first voltage threshold and a second voltage threshold, the first voltage threshold being a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold being a threshold voltage when there are no electrons on the floating gate of the memory cell.

[0082] In embodiments of the present invention, the read voltage is specifically used to read data from a memory cell, and its magnitude is typically configured between a first voltage threshold and a second voltage threshold. The first voltage threshold corresponds to the threshold voltage when there are no electrons on the floating gate of the memory cell, while the second voltage threshold corresponds to the threshold voltage when there are electrons on the floating gate. By applying the read voltage, the data state of the memory cell can be determined, thereby reading the stored information.

[0083] When a read voltage is applied to the target word line, the current or voltage signal in the memory cell will change accordingly. Figure 3 , Bit Line is charged during Read, except the target word line WL n The other word lines WL are connected with a higher voltage to turn on the cell. n The read voltage is added. If there are electrons on the floating gate of the cell, the voltage threshold VT is higher (VT1, the first voltage threshold). If there are no electrons on the floating gate, VT is very low (VT2, the second voltage threshold). The read voltage is between VT1 and VT2.

[0084] Optionally, the target parameter data includes non-default operating parameter data required by the Nand flash memory when reading data.

[0085] In an embodiment of the present invention, the above-mentioned target parameter data may be non-default operating parameter data of the NAND Flash. The default operating parameter data of the NAND Flash is fixed parameter data stored in the cache. If the non-default operating parameter data of the NAND Flash is not read, the NAND Flash will be configured using the default operating parameter data in the cache.

[0086] For example, the target parameter data mentioned above is the read voltage applied to the select WL (select word line) during a read operation. During chip design, this voltage range is allowed to be 0-2V, with a step of 0.1V. By default, the read voltage is 0.1V. However, experimental results show that setting the read voltage to 0.5V provides the best performance for the chip. Therefore, the information indicating a read voltage of 0.5V is written to the corresponding block area of ​​the chip. There are many other voltage information like this, such as the erase voltage and the programming voltage. Generally, this voltage does not exceed one-eighth of a chip page (storage page).

[0087] In the embodiment of the present invention, please refer to Figure 3 , the same value is written in the bit line direction, either all floating gates have electrons or none. For a 0, except for the floating gates of WLn+1 and WLn-1 cells, all floating gates have electrons. This increases the resistance of the entire cell string, increasing the probability of reading a 0. For a 1, the floating gates of the entire cell string have no electrons, which does not affect the reading of a 1.

[0088] Because the spacing between NAND FLash cells is relatively small, when the floating gate of a cell changes from no electrons to electrons, it will affect the VT of the adjacent cells, so WLn-1 and WLn+1 are not programmed.

[0089] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the influence between storage units provided by an embodiment of the present invention. Figure 5 In the example, programming the floating gates of cells ②, ④, ⑥, and ⑧ from 1 to 0 has a significant impact on the VT of cell ⑤. Programming the floating gates of cells ①, ③, ⑦, and ⑨ from 1 to 0 has a slight impact on cell ⑤. This shows that the voltage impact between cells is strongly correlated with the distance between them.

[0090] The present invention also provides an information storage device for a memory, see Figure 6 , Figure 6 It is a structural diagram of an information storage device of a memory in a hardware operating environment involved in an embodiment of the present invention.

[0091] The information storage device of the memory of the embodiment of the present invention can be a computing device such as a desktop computer, a notebook, a palmtop computer, and a server. Figure 6As shown, the information storage device of the memory may include: a processor 1001 (such as a CPU), a network interface 1004, a user interface 1003, a memory 1005 and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or it may be a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may optionally be a storage device independent of the aforementioned processor 1001.

[0092] Those skilled in the art will understand that Figure 6 The information storage device structure of the memory shown in the figure does not constitute a limitation on the information storage device of the memory, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0093] The present invention also proposes a memory, which includes a Nand flash memory and a memory information storage device, and a plurality of memory cells connected in series, each memory cell corresponding to a word line, and the memory information storage device is Figure 6 The memory shown is an information storage device.

[0094] like Figure 6 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0095] exist Figure 6 In the information storage device of the memory shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the above-mentioned memory information storage method are implemented.

[0096] Based on the computer program proposed in the aforementioned embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the information storage method of the memory described in the aforementioned embodiment is implemented.

[0097] The information storage device, memory and storage medium of the memory of the present invention can implement the steps of the above-mentioned information storage method of the memory, and therefore have at least all the beneficial effects brought about by the technical solutions of the above-mentioned information storage method embodiments of the memory, and will not be described in detail here.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection of devices or modules through some interfaces, which can be electrical, mechanical or other forms.

[0099] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of the present embodiment according to actual needs.

[0100] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0101] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0102] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. Any equivalent structural transformation made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields, is included in the scope of protection of the present invention.

Claims

1. A method for storing information in a memory, characterized in that: The memory is a Nand flash memory, which includes a plurality of memory cells connected in series, each memory cell corresponding to a word line, and the method includes: Writing target parameter data into the target word line; maintaining two groups of adjacent word lines adjacent to the target word line in an erased state; each group of adjacent word lines includes at least one word line, and the number of word lines is determined according to the degree of interference between adjacent word lines. The greater the degree of interference between two adjacent word lines, the more word lines there are in each group of adjacent word lines; Writing the target parameter data into the remaining word lines, wherein the remaining word lines are the target word line and word lines other than the two groups of adjacent word lines; When powering on and reading data, applying a conduction voltage to the two groups of adjacent word lines and the remaining word lines; And, applying a read voltage to the target word line to obtain read data on the target word line.

2. The information storage method of the memory according to claim 1, characterized in that: After applying a read voltage to the target word line to obtain read data on the target word line, the method further includes: Verifying the read data on the target word line by using a positive and negative code verification method; If the verification passes, the target parameter data is read into the latch.

3. The information storage method of the memory according to claim 2, characterized in that: After verifying the read data, the method further includes: If the verification fails, applying a read voltage to the remaining word lines to obtain read data on the remaining word lines; The read data on the remaining word lines are verified by a positive and negative code verification method until the verification succeeds or all the verifications fail.

4. The information storage method of the memory according to claim 2, characterized in that: After reading the target parameter data into the latch, the method further includes: reading the target parameter data in the latch into a cache memory; The Nand flash memory is configured using the target parameter data in the cache memory.

5. The information storage method of the memory according to claim 1, characterized in that: The read voltage is configured to be between a first voltage threshold and a second voltage threshold, wherein the first voltage threshold is a threshold voltage when there are electrons on the floating gate of the memory cell, and the second voltage threshold is a threshold voltage when there are no electrons on the floating gate of the memory cell.

6. The information storage method of the memory according to any one of claims 1 to 5, characterized in that: The target parameter data includes non-default operating parameter data required by the Nand flash memory when reading data.

7. An information storage device of a memory, characterized in that: The information storage device of the memory includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the memory information storage method according to any one of claims 1 to 6 are implemented.

8. A memory, characterized in that: The memory includes a Nand flash memory and an information storage device of the memory, and a plurality of memory cells connected in series, each memory cell corresponding to a word line. The information storage device of the memory is the information storage device of the memory according to claim 7.

9. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the information storage method of the memory according to any one of claims 1 to 7.

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