A shift register, a gate driving circuit and a display device

Abstract

The present disclosure provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register of the present disclosure comprises an input sub-circuit configured to control the potential of a first node and a second node in response to a first clock signal provided by a first clock signal line and a second clock signal provided by a second clock signal line; a first control sub-circuit configured to control the potential of the first node in response to the signal of the second node and a third clock signal provided by a third clock signal line; a second control sub-circuit configured to control the potential of a third node in response to the signal of the first node, the signal of the second node and a fourth clock signal provided by a fourth clock signal line; and an output sub-circuit configured to output a first output signal in response to the signal of the first node or output a second output signal in response to the signal of the third node.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] In the field of display technology, pixel arrays in display panels, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, typically consist of multiple rows of gate lines and multiple columns of data lines interspersed with the gate lines. Driving the gate lines can be achieved through bundled integrated driver circuitry.

[0003] Gate Drive on Array (GOA) technology is a commonly used technique in display panels that integrates row scanning drive signal circuitry onto the array substrate to drive the gate rows sequentially. Currently, as the resolution requirements of existing display products continue to increase, higher-resolution displays increasingly have more shift register stages in their integrated gate drive circuits. This increases the capacitive and resistive load on the clock and power signal lines, ultimately affecting the display image. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a shift register, a gate drive circuit, and a display device.

[0005] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a shift register, including a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit;

[0006] The input sub-circuit is configured to control the potential of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line;

[0007] The first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line;

[0008] The second control sub-circuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node, and the fourth clock signal provided by the fourth clock signal line;

[0009] The output sub-circuit is configured to output a first output signal in response to a signal from the first node, or to output a second output signal in response to a signal from the third node.

[0010] In some embodiments, within one clock cycle, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the third clock signal, and the pulse of the third clock signal precedes the pulse of the fourth clock signal.

[0011] In some embodiments, within one clock cycle, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the fourth clock signal, and the pulse of the fourth clock signal precedes the pulse of the third clock signal.

[0012] In some embodiments, the first clock signal and the second clock signal have the same timing sequence; the third clock signal has the opposite timing sequence to the first clock signal; and the fourth clock signal has the same timing sequence as the third clock signal.

[0013] In some embodiments, the first clock signal and the second clock signal include a first level; the potential of the first level of the first clock signal is different from the potential of the first level of the second clock signal; and / or,

[0014] The third clock signal and the fourth clock signal include a third level; the potential of the third level of the third clock signal is different from the potential of the third level of the fourth clock signal.

[0015] In some embodiments, the potential of the first level of the first clock signal is less than the potential of the first level of the second clock signal; and / or,

[0016] The potential of the third level of the third clock signal is less than the potential of the third level of the fourth clock signal.

[0017] In some embodiments, the first clock signal and the second clock signal further include a second level, which is different from the first level; the potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; and / or,

[0018] The third clock signal and the fourth clock signal also include a fourth level, which is different from the third level; the potential of the fourth level of the third clock signal is different from the potential of the fourth level of the fourth clock signal.

[0019] In some embodiments, the potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or,

[0020] The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

[0021] In some embodiments, the shift register further includes a first power signal line, a second power signal line, a third power signal line, and a fourth power signal line;

[0022] The input sub-circuit is electrically connected to the first power signal line, the first control sub-circuit is electrically connected to the third power signal line, the second control sub-circuit is electrically connected to the fourth power signal line, and the output sub-circuit is electrically connected to the second power signal line and the third power signal line.

[0023] In some embodiments, the potential of the first power signal transmitted by the first power signal line is less than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is less than the potential of the fourth power signal transmitted by the fourth power signal line; and the potential of the second power signal is less than the potential of the third power signal.

[0024] In some embodiments, the potential of the first level of the first clock signal is equal to the potential of the first power supply signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power supply signal;

[0025] The potential of the first level of the second clock signal is equal to the potential of the second power supply signal, and the potential of the second level of the second clock signal is equal to the potential of the third power supply signal;

[0026] The potential of the third level of the third clock signal is equal to the potential of the first power supply signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power supply signal.

[0027] The potential of the third level of the fourth clock signal is equal to the potential of the second power supply signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power supply signal.

[0028] In some embodiments, the pulse width of the first level of the first clock signal is less than the pulse width of the second level; and / or, the pulse width of the third level of the third clock signal is less than the pulse width of the fourth level.

[0029] In some embodiments, the input sub-circuit includes a first transistor, a second transistor, and a third transistor;

[0030] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line.

[0031] The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node;

[0032] The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0033] In some embodiments, the input sub-circuit includes a first transistor, a second transistor, and a third transistor;

[0034] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line.

[0035] The first electrode of the second transistor is electrically connected to the first clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node;

[0036] The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0037] In some embodiments, the input sub-circuit includes a first transistor, a second transistor, and a third transistor;

[0038] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line.

[0039] The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node;

[0040] The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

[0041] In some embodiments, the shift register further includes an isolation sub-circuit;

[0042] The isolation sub-circuit is configured to isolate the first node and the first control sub-circuit electrically connected to the first node; isolate the first node and the output sub-circuit electrically connected to the first node; and isolate the second node and the second control sub-circuit electrically connected to the second node.

[0043] The first control sub-circuit is electrically connected to the fifth node; the output sub-circuit is electrically connected to the fifth node; and the second control sub-circuit is electrically connected to the fourth node.

[0044] In some embodiments, the isolation sub-circuit includes an eleventh transistor and a twelfth transistor;

[0045] The first electrode of the eleventh transistor is electrically connected to the second node, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first power signal line.

[0046] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

[0047] In some embodiments, the isolation sub-circuit includes an eleventh transistor and a twelfth transistor;

[0048] The first electrode of the eleventh transistor is electrically connected to the second node, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first power signal line.

[0049] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

[0050] In some embodiments, the first control sub-circuit includes a fourth transistor, a fifth transistor, and a third capacitor;

[0051] The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the fifth node;

[0052] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node.

[0053] The second plate of the third capacitor is electrically connected to the fifth node.

[0054] In some embodiments, the second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor;

[0055] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the first capacitor.

[0056] The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line.

[0057] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

[0058] In some embodiments, the second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor, and a first capacitor;

[0059] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the capacitor.

[0060] The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line.

[0061] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

[0062] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the preset control terminal.

[0063] In some embodiments, the input sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0064] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line.

[0065] The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node;

[0066] The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0067] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

[0068] In some embodiments, the shift register further includes an isolation sub-circuit;

[0069] The isolation sub-circuit is configured to isolate the first node and the first control sub-circuit electrically connected to the first node; isolate the first node and the output sub-circuit electrically connected to the first node; isolate the first node and the second control sub-circuit electrically connected to the first node; and isolate the second node and the second control sub-circuit electrically connected to the second node.

[0070] The first control sub-circuit is electrically connected to the fifth node; the output sub-circuit is electrically connected to the fifth node; the second control sub-circuit is electrically connected to the fourth node and the fifth node.

[0071] In some embodiments, the input sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0072] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line.

[0073] The first electrode of the second transistor is electrically connected to the first clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node;

[0074] The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0075] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

[0076] In some embodiments, the first control sub-circuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor, and a third capacitor;

[0077] The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the second plate of the third capacitor.

[0078] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node.

[0079] The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line;

[0080] The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

[0081] In some embodiments, the second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor, and a first capacitor;

[0082] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the first capacitor.

[0083] The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line.

[0084] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node.

[0085] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the preset control terminal.

[0086] In some embodiments, the output sub-circuit includes a ninth transistor, a tenth transistor, and a second capacitor;

[0087] The first electrode of the ninth transistor is electrically connected to the third power signal line and the first plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

[0088] The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node.

[0089] The second plate of the second capacitor is electrically connected to the third node.

[0090] Secondly, embodiments of this disclosure also provide a gate driving circuit, including N cascaded shift registers; except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0091] In some embodiments, the first clock signal line in the i-th stage shift register is multiplexed as the fourth clock signal line in the (i+1)-th stage shift register, the second clock signal line in the i-th stage shift register is multiplexed as the first clock signal line in the (i+1)-th stage shift register, the third clock signal line in the i-th stage shift register is multiplexed as the second clock signal line in the (i+1)-th stage shift register, and the fourth clock signal line in the i-th stage shift register is multiplexed as the third clock signal line in the (i+1)-th stage shift register.

[0092] In some embodiments, the first clock signal line in the i-th stage shift register is multiplexed as the third clock signal line in the (i+1)-th stage shift register, the second clock signal line in the i-th stage shift register is multiplexed as the fourth clock signal line in the (i+1)-th stage shift register, the third clock signal line in the i-th stage shift register is multiplexed as the first clock signal line in the (i+1)-th stage shift register, and the fourth clock signal line in the i-th stage shift register is multiplexed as the second clock signal line in the (i+1)-th stage shift register.

[0093] Thirdly, embodiments of this disclosure also provide a display device, including a pixel driving circuit and a gate driving circuit as described in any one of the second aspects, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit. Attached Figure Description

[0094] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure;

[0095] Figure 2 Example 1 provided for embodiments of this disclosure: a timing diagram of each clock signal line within one clock cycle;

[0096] Figure 3 Example 2 provided for embodiments of this disclosure: a timing diagram of each clock signal line within one clock cycle;

[0097] Figure 4 Example 3 provided for embodiments of this disclosure: a timing diagram of each clock signal line within one clock cycle;

[0098] Figure 5a This is a schematic diagram of another shift register structure provided in an embodiment of the present disclosure;

[0099] Figure 5b This is a schematic diagram of another shift register structure provided in an embodiment of the present disclosure;

[0100] Figure 6 A circuit diagram of a 12T3C circuit structure provided in this embodiment of the present disclosure;

[0101] Figure 7 A circuit diagram of another 12T3C circuit structure provided in this embodiment of the present disclosure;

[0102] Figure 8 A circuit diagram of a 13T3C circuit structure provided in an embodiment of this disclosure;

[0103] Figure 9 A circuit diagram of another 13T3C circuit structure provided in this embodiment of the present disclosure;

[0104] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present disclosure;

[0105] Figure 11 A circuit diagram of a 16T3C circuit structure provided in an embodiment of this disclosure;

[0106] Figure 12 A circuit diagram of another 16T3C circuit structure provided in this embodiment of the present disclosure;

[0107] Figure 13 A timing diagram of an exemplary shift register provided for embodiments of this disclosure;

[0108] Figure 14 Timing diagram of another exemplary shift register provided for embodiments of this disclosure;

[0109] Figure 15 Timing diagram of another exemplary shift register provided for embodiments of this disclosure;

[0110] Figure 16 A schematic diagram of a gate driving circuit provided in an embodiment of this disclosure;

[0111] Figure 17 A schematic diagram of another gate driving circuit provided in an embodiment of this disclosure;

[0112] Figure 18 Provided for the embodiments of this disclosure Figure 6 The circuit diagram of the cascaded shift registers in the 12T3C circuit structure is shown.

[0113] Figure 19 Provided for the embodiments of this disclosure Figure 8 The circuit diagram of the cascaded shift registers in the 13T3C circuit structure is shown.

[0114] Figure 20 Provided for the embodiments of this disclosure Figure 11 The circuit diagram of the cascaded shift registers in the 16T3C circuit structure is shown.

[0115] Figure 21 Provided for the embodiments of this disclosure Figure 7 The circuit diagram of the cascaded shift registers in the 12T3C circuit structure is shown.

[0116] Figure 22 Provided for the embodiments of this disclosure Figure 9 The circuit diagram of the cascaded shift registers in the 13T3C circuit structure is shown.

[0117] Figure 23 Provided for the embodiments of this disclosure Figure 12The circuit diagram shown is a cascaded shift register of the 16T3C circuit structure. Detailed Implementation

[0118] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0119] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0120] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0121] In related technologies, shift registers are connected to a set of clock signals with opposite timing sequences, while clock signals with the same timing sequence are transmitted using the same clock signal line. However, in high-resolution display products, the more stages of shift registers integrated into the gate driver circuit, the more capacitive and resistive loads are generated on the same clock signal line. This increased load prolongs the output signal time of the shift register, affecting the effective working time of pixels and consequently impacting the display image. Simultaneously, the more stages of shift registers in the gate driver circuit, the more transistors are connected to the same clock signal line, resulting in larger parasitic capacitances, further affecting the display image. Furthermore, the more stages of shift registers in the gate driver circuit, the more transistors are connected to the same power signal line, increasing the load and potentially causing fluctuations in the power signal transmitted through the power signal line. This can ultimately lead to defects such as fine horizontal lines on the display image, affecting the display quality.

[0122] In view of this, embodiments of the present disclosure provide a shift register, which includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; the input sub-circuit is configured to control the potentials of a first node and a second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line; the first control sub-circuit is configured to control the potential of the first node in response to a signal from the second node and a third clock signal provided by the third clock signal line; the second control sub-circuit is configured to control the potential of a third node in response to a signal from the first node, a signal from the second node, and a fourth clock signal provided by the fourth clock signal line; the output sub-circuit is configured to output a first output signal in response to the potential of the first node, or to output a second output signal in response to the potential of the third node.

[0123] The shift register provided in this embodiment includes multiple clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. By using multiple clock signal lines to provide clock signals, the load on a single clock signal line in the aforementioned related technologies is distributed, thereby reducing product power consumption and improving display effects.

[0124] The specific circuit structure of the shift register provided in the embodiments of this disclosure will be described in detail below.

[0125] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure, as shown below. Figure 1As shown, the shift register includes a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, a fourth clock signal line CKL4, an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3, and an output sub-circuit 4.

[0126] The input sub-circuit 1 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first node N1, and the second node N2. Based on this, the input sub-circuit 1 is configured to control the potential of the first node N1 and the second node N2 in response to the first clock signal CK1 provided by the first clock signal line CKL1 and the second clock signal CK2 provided by the second clock signal line CKL2.

[0127] For example, such as Figure 1 As shown, the shift register also includes a signal input terminal (Input) and a signal output terminal (OUT), which are electrically connected to the signal input line and the pixel driving circuit, respectively. The signal input line is used to provide the input signal. The shift register is configured to provide the gate row scan signal to the pixel driving circuit.

[0128] For example, such as Figure 1 As shown, the shift register also includes a first power signal line VGL1, which provides a first power signal. The input sub-circuit 1 in the shift register is electrically connected to the signal input terminal Input and the first power signal line VGL1. The input sub-circuit 1 is configured to control the potentials of the first node N1 and the second node N2 based on the input signal and the first power signal, in response to a first clock signal CK1 and a second clock signal CK2.

[0129] Continue as Figure 1 As shown, the first control sub-circuit 2 is electrically connected to the third clock signal line CKL3, the first node N1 and the second node N2; based on this, the first control sub-circuit 2 is configured to control the potential of the first node N1 in response to the signal of the second node N2 and the third clock signal CK3 provided by the third clock signal line CKL3.

[0130] For example, such as Figure 1 As shown, the shift register also includes a third power supply signal line VGH1, which provides a third power supply signal. The first control sub-circuit 2 in the shift register is electrically connected to the third power supply signal line VGH1. The first control sub-circuit 2 is configured to control the potential of the first node N1 in response to the signal from the second node N2, based on the third clock signal CK3 and the third power supply signal.

[0131] Continue as Figure 1As shown, the second control sub-circuit 3 is electrically connected to the first node N1, the second node N2, the third node N3, and the fourth clock signal line CKL4. Based on this, the second control sub-circuit 3 is configured to control the potential of the third node N3 in response to the signals from the first node N1, the second node N2, and the fourth clock signal CK4 provided by the fourth clock signal line CKL4.

[0132] For example, such as Figure 1 As shown, the shift register also includes a fourth power signal line VGH2, which provides a fourth power signal. The second control sub-circuit 3 in the shift register is electrically connected to the fourth power signal line VGH2. The second control sub-circuit 3 is configured to control the potential of the third node N3 in response to the signals of the first node N1, the second node N2, and the fourth clock signal CK4, based on the fourth clock signal CK4 and the fourth power signal.

[0133] Continue as Figure 1 As shown, output sub-circuit 4 is electrically connected to the first node N1 and the third node N3. Based on this, output sub-circuit 4 is configured to output a first output signal in response to a signal from the first node N1, or to output a second output signal in response to a signal from the third node N3.

[0134] For example, such as Figure 1 As shown, the shift register also includes a second power signal line VGL2, which provides a second power signal. The output sub-circuit 4 in the shift register is electrically connected to the second power signal line VGL2 and the third power signal line VGH1. The output sub-circuit 4 is configured to output a first output signal in response to a signal from the first node N1, based on the second power signal. Alternatively, the output sub-circuit 4 is configured to output a second output signal in response to a signal from the third node N3, based on the third power signal.

[0135] The first output signal and the second output signal can both be used as gate row scanning signals of the pixel driving circuit, or as input signals of the next level shift register cascaded to the current shift register.

[0136] For example, the input signal is a pulse signal; the first output signal is a low-level signal, and the second output signal is a high-level signal.

[0137] For example, the first power signal line VGL1 and the second power signal line VGL2 are the same, but different from the third power signal line VGH1 and the fourth power signal line VGH2. That is, the first power signal and the second power signal are the same, and can be transmitted using the same power signal line.

[0138] For example, the third power signal line VGH1 and the fourth power signal line VGH2 are the same, but different from the first power signal line VGL1 and the second power signal line VGL2. That is, the third power signal and the fourth power signal are the same and can be transmitted using the same power signal line.

[0139] For example, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different. In this case, the first power signal and the second power signal can be the same, and the third power signal and the fourth power signal can be the same, but they are transmitted using different power signal lines.

[0140] For example, when the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, the first power signal and the second power signal can be the same or different. The third power signal and the fourth power signal can also be the same or different. However, the potentials of the first power signal and the second power signal are both lower than the potentials of the third power signal and the fourth power signal.

[0141] The shift register provided in this embodiment includes multiple clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. By using multiple clock signal lines to provide the clock signal, the load on a single clock signal line is distributed, thus reducing the number of transistors connected to a single clock signal line. This shortens the signal output time, reduces product power consumption, and improves the uniformity of image quality on large-screen displays. Furthermore, for the same power signals, such as the first and second power signals, the same power signal line (i.e., the first power signal line VGL1 and the second power signal line VGL2 are the same) can be used for transmission; similarly, the third and fourth power signals can be transmitted using the same power signal line (the third power signal line VGH1 and the fourth power signal line VGH2 are the same). This reduces the signal line layout space, which is beneficial for achieving narrow bezels. Alternatively, different power signal lines can be used to transmit the same power signals. For example, the first and second power signals can both be transmitted using different first power signal lines VGL1 and VGL2; similarly, the third and fourth power signals can both be transmitted using different third power signal lines VGH1 and VGH2. This avoids signal fluctuations caused by excessive load on a single power signal line, thus improving the stability of the signal output.

[0142] In some embodiments, Figure 2Example 1 provided for embodiments of this disclosure, a timing diagram of each clock signal line within one clock cycle, as shown below. Figure 2 As shown, within one clock cycle T, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the third clock signal, and the pulse of the third clock signal precedes the pulse of the fourth clock signal.

[0143] It should be noted that the "pulse" of the clock signal here refers to the trigger period of the effective level of a clock signal. In this disclosure, taking the effective level as low level as an example, a low level signal corresponding to a rising edge turning into a falling edge is denoted as a pulse of the clock signal.

[0144] For example, the pulse widths of the effective levels of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are the same.

[0145] For example, within one clock cycle T, the effective level cutoff time of the first clock signal can be used as the trigger time of the effective level of the second clock signal; the effective level cutoff time of the second clock signal can be used as the trigger time of the effective level of the third clock signal; and the effective level cutoff time of the third clock signal can be used as the trigger time of the effective level of the fourth clock signal.

[0146] For example, within one clock cycle T, there is a preset time interval between the effective level cutoff time of the first clock signal and the effective level trigger time of the second clock signal; there is a preset time interval between the effective level cutoff time of the second clock signal and the effective level trigger time of the third clock signal; there is a preset time interval between the effective level cutoff time of the third clock signal and the effective level trigger time of the fourth clock signal; wherein, the preset time interval is less than the effective level duration.

[0147] This embodiment uses clock signals with different timing sequences. The timing sequences of the first, second, third, and fourth clock signals are changed sequentially. Compared with the situation where the timing sequences are the same, this can avoid signal abrupt changes caused by simultaneous timing sequence changes, which would affect the display effect.

[0148] In some embodiments, Figure 3 Example 2 provided for embodiments of this disclosure, a timing diagram of each clock signal line within one clock cycle, as shown below. Figure 3 As shown, within one clock cycle T, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the fourth clock signal, and the pulse of the fourth clock signal precedes the pulse of the third clock signal.

[0149] For example, within one clock cycle T, the effective level cutoff time of the first clock signal can be used as the trigger time of the effective level of the second clock signal; the effective level cutoff time of the second clock signal can be used as the trigger time of the effective level of the fourth clock signal; and the effective level cutoff time of the fourth clock signal can be used as the trigger time of the effective level of the third clock signal.

[0150] For example, within one clock cycle T, there is a preset time interval between the effective level cutoff time of the first clock signal and the effective level trigger time of the second clock signal; there is a preset time interval between the effective level cutoff time of the second clock signal and the effective level trigger time of the fourth clock signal; there is a preset time interval between the effective level cutoff time of the fourth clock signal and the effective level trigger time of the third clock signal; wherein, the preset time interval is less than the effective level duration.

[0151] This embodiment uses clock signals with different timing sequences. The timing sequences of the first clock signal, the second clock signal, the fourth clock signal, and the third clock signal are changed sequentially. Compared with the situation where the timing sequences are the same, this can avoid signal abrupt changes caused by simultaneous timing sequence changes, which would affect the display effect.

[0152] In some embodiments, such as Figure 2 or Figure 3 As shown, the active levels of the first, second, third, and fourth clock signals are the same, and the inactive levels are the same.

[0153] In some embodiments, Figure 4 Example 3, a timing diagram of each clock signal line within one clock cycle, provided as an embodiment of this disclosure, is shown below. Figure 4 As shown, the timing of the first clock signal CK1 and the second clock signal CK2 is the same. The timing of the fourth clock signal CK4 and the third clock signal CK3 is the same.

[0154] It should be noted that timing in a circuit refers to the sequential switching of signals between high and low potentials. Same timing means that the potential transitions of the compared signals occur at the same time points, but it does not mean that their potentials are the same at the same time points.

[0155] like Figure 4 As shown, the timing of the third clock signal CK3 is opposite to that of the first clock signal CK1. Opposite timing means that within the same clock period T, the potential transition times of the compared signals are inconsistent. Alternatively, it can be understood that the signal waveforms of the first clock signal CK1 and the third clock signal CK3 are the same throughout the entire working scan phase, but the effective level transition time of the third clock signal CK3 is later than the effective level transition time of the first clock signal CK1 by a preset duration t'.

[0156] Here, the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4 are all different.

[0157] In this embodiment, the shift register uses different clock signal lines for the first clock signal CK1 and the second clock signal CK2, which have the same timing sequence. That is, the first clock signal line CKL1 and the second clock signal line CKL2 are used for transmission. For the third clock signal CK3 and the fourth clock signal CK4, which have the same timing sequence, the third clock signal line CKL3 and the fourth clock signal line CKL4 are used for transmission. This reduces the number of transistors connected to a single clock signal line, thereby reducing the load on each clock signal line, shortening the signal output time, and improving the uniformity of the image quality of the large screen display.

[0158] In some embodiments, such as Figure 4 As shown, the first clock signal CK1 and the second clock signal CK2 include a first level; the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2.

[0159] For example, the clock period T of the first clock signal CK1 and the second clock signal CK2 is the same.

[0160] For example, the first level is the low level (i.e., the effective level) in clock period T, and the potential of the low level of the first clock signal CK1 is different from the potential of the low level of the second clock signal CK2. For example, the potential of the low level of the first clock signal CK1 can be greater than the potential of the low level of the second clock signal CK2, or it can be less than the potential of the low level of the second clock signal CK2.

[0161] For example, the absolute value of the amplitude of the first clock signal CK1 is greater than the absolute value of the amplitude of the second clock signal CK2.

[0162] Continue as Figure 4 As shown, the third clock signal CK3 and the fourth clock signal CK4 include a third level; the potential of the third level of the third clock signal CK3 is different from the potential of the third level of the fourth clock signal CK4.

[0163] For example, the clock period T of the third clock signal CK3 and the fourth clock signal CK4 is the same.

[0164] For example, such as Figure 4 As shown, the clock periods T of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all the same.

[0165] For example, the third level is the low level (i.e., the effective level) in clock period T, and the potential of the low level of the third clock signal CK3 is different from the potential of the low level of the fourth clock signal CK4. For example, the potential of the low level of the third clock signal CK3 can be greater than the potential of the low level of the fourth clock signal CK4, or it can be less than the potential of the low level of the fourth clock signal CK4.

[0166] For example, the absolute value of the amplitude of the third clock signal CK3 is greater than the absolute value of the amplitude of the fourth clock signal CK4.

[0167] In some embodiments, such as Figure 4 As shown, the potential of the first level of the first clock signal CK1 is lower than the potential of the first level of the second clock signal CK2, so as to avoid at least some transistors in the input sub-circuit 1 from having hysteresis problems and affecting transistor characteristics.

[0168] Continue as Figure 4 As shown, the potential of the third level of the third clock signal CK3 is lower than the potential of the third level of the fourth clock signal CK4, which reduces the impact of threshold loss of at least some transistors in the first control sub-circuit 2 and the second control sub-circuit 3.

[0169] In some embodiments, such as Figure 4 As shown, the first clock signal CK1 and the second clock signal CK2 also include a second level, which is different from the first level; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0170] For example, the second level is a high level (i.e., an invalid level) in clock period T, and the potential of the high level of the first clock signal CK1 is different from the potential of the high level of the second clock signal CK2. For example, the potential of the high level of the first clock signal CK1 can be greater than the potential of the high level of the second clock signal CK2, or it can be less than the potential of the high level of the second clock signal CK2.

[0171] Continue as Figure 4 As shown, the third clock signal CK3 and the fourth clock signal CK4 also include a fourth level, which is different from the third level; the potential of the fourth level of the third clock signal CK3 is different from the potential of the fourth level of the fourth clock signal CK4.

[0172] For example, the fourth level is a high level (i.e., an invalid level) in clock cycle T, and the potential of the high level of the third clock signal CK3 is different from the potential of the high level of the fourth clock signal CK4. For example, the potential of the high level of the third clock signal CK3 can be greater than the potential of the high level of the fourth clock signal CK4, or it can be less than the potential of the high level of the fourth clock signal CK4.

[0173] In some embodiments, such as Figure 4 As shown, the potential of the second level of the first clock signal CK1 is greater than the potential of the second level of the second clock signal CK2; and / or, the potential of the fourth level of the third clock signal CK3 is greater than the potential of the fourth level of the fourth clock signal CK4, thereby reducing the impact of threshold loss of some transistors in the shift register.

[0174] In some embodiments, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different. The first and second power signals are both low-level signals, but their potentials differ. The third and fourth power signals are both high-level signals, but their potentials differ. The potential of the low-level signal is lower than the potential of the high-level signal.

[0175] For example, considering the impact of threshold losses of some transistors in the shift register, the potential of the first power supply signal is set to be less than the potential of the second power supply signal.

[0176] For example, the potential of the third power supply signal is lower than that of the fourth power supply signal, thereby improving the turn-off characteristics of at least some transistors in the output sub-circuit 4.

[0177] In some embodiments, such as Figure 4 As shown, the potential of the first level of the first clock signal CK1 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the second level of the first clock signal CK1 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the first level of the second clock signal CK2 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the second level of the second clock signal CK2 is equal to the potential of the third power signal transmitted by the third power signal line VGH1; the potential of the third level of the third clock signal CK3 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the fourth level of the third clock signal CK3 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the third level of the fourth clock signal CK4 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the fourth level of the fourth clock signal CK4 is equal to the potential of the third power signal transmitted by the third power signal line VGH1.

[0178] In some embodiments, such as Figure 4 As shown, the pulse width of the first level of the first clock signal CK1 is less than the pulse width of the second level; and / or, the pulse width of the third level of the third clock signal CK3 is less than the pulse width of the fourth level.

[0179] For example, the first level is a low level in clock period T, and the second level is a high level in clock period T; the pulse width of the low level of the first clock signal CK1 is less than the pulse width of the high level. The clock period T of the first clock signal CK1 and the second clock signal CK2 is the same. Therefore, the pulse width of the low level of the second clock signal CK2 is less than the pulse width of the high level.

[0180] For example, the third level is a low level in clock period T, and the fourth level is a high level in clock period T; the pulse width of the low level of the third clock signal CK3 is less than the pulse width of the high level. The clock periods T of the third clock signal CK3 and the fourth clock signal CK4 are the same. Therefore, the pulse width of the low level of the fourth clock signal CK4 is less than the pulse width of the high level.

[0181] In this embodiment, after the pulse width is widened, the first node N1 (or the fifth node N5) can be quickly lowered, thereby ensuring the output signal is output quickly and ensuring the display quality.

[0182] Figure 5a This is a schematic diagram of another shift register structure provided in an embodiment of the present disclosure; Figure 5b A schematic diagram of another shift register provided in an embodiment of this disclosure. In some embodiments, such as Figure 5a As shown, the shift register also includes an isolation sub-circuit 5; the isolation sub-circuit 5 is configured to isolate the first node N1 and the first control sub-circuit 2 electrically connected to the first node N1; isolate the first node N1 and the output sub-circuit 4 electrically connected to the first node N1; and isolate the second node N2 and the second control sub-circuit 3 electrically connected to the second node N2.

[0183] like Figure 5a As shown, the first control sub-circuit 2 is electrically connected to the fifth node N5; the output sub-circuit 4 is electrically connected to the fifth node N5; and the second control sub-circuit 3 is electrically connected to the fourth node N4 and the first node N1.

[0184] like Figure 5a As shown, the isolation sub-circuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1, and the second power signal line VGL2. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal; and simultaneously, to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0185] Or, as Figure 5bAs shown, the isolation sub-circuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, and the first power signal line VGL1. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5, and to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0186] In this embodiment, the stability of the output signal is improved by adding an isolation sub-circuit 5.

[0187] The shift register described above can adopt a 12T3C (i.e., 12 transistors and 3 capacitors) circuit structure; or, the shift register can adopt a 13T3C (i.e., 13 transistors and 3 capacitors) circuit structure; or, the shift register can also adopt a 16T3C (i.e., 16 transistors and 3 capacitors) circuit structure.

[0188] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0189] It should be noted that thin-film transistors (TFTs) can be either N-type or P-type. An N-type TFT refers to a TFT with N-type ion doping in the active layer, while a P-type TFT refers to a TFT with P-type ion doping in the active layer. The operating voltage level for an N-type TFT is high, while the operating voltage level for a P-type TFT is low.

[0190] For ease of understanding, this disclosure uses a P-type thin-film transistor as an example in the following embodiments, but this disclosure is not limited to P-type thin-film transistors.

[0191] It should be noted that, in the embodiments of this disclosure, the internal circuit structure of the shift register may be any other number of transistors besides the 12T3C, 13T3C and 16T3C listed above, and this disclosure does not limit this.

[0192] The shift registers of the circuit structures of 12T3C, 13T3C and 16T3C are described in detail below using different embodiments.

[0193] In some embodiments, a 12T3C circuit structure is used as an example for illustration. This 12T3C circuit structure adopts... Figure 2 or Figure 3 The timing control of the clock signal lines is shown. Figure 6 A circuit diagram of a 12T3C circuit structure provided in this embodiment of the present disclosure is shown below. Figure 6 As shown, input sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. First control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. Second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. Output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. Isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0194] Continue as Figure 6 As shown, for input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2. Specifically, the first clock signal CK1 can control the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and conducts, it can transmit the input signal to the first node N1. The signal of the first node N1 can control the on / off state of the second transistor T2. When the second transistor T2 responds to the signal of the first node N1 and conducts, it can transmit the second clock signal CK2 to the second node N2. The second clock signal CK2 controls the on / off state of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and conducts, it can transmit the first power supply signal to the second node N2.

[0195] Optionally, for input sub-circuit 1, the first terminal of the second transistor T2 can be electrically connected to the first clock signal line CKL1.

[0196] Continue as Figure 6As shown, for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5. Specifically, the signal at the fifth node N5 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the signal at the fifth node N5 and conducts, it can transmit the third clock signal CK3 to the sixth node N6. The signal at the second node N2 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and conducts, it can transmit the third power signal to the sixth node N6.

[0197] The second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0198] Continue as Figure 6 As shown, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1. Specifically, the signal at the fourth node N4 can control the on / off state of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and conducts, it can transmit the fourth clock signal CK4 to the seventh node N7. The fourth clock signal CK4 can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and conducts, it can transmit the signal at the seventh node N7 to the third node N3. The signal from the first node N1 can control the eighth transistor T8 to turn on. When the eighth transistor T8 responds to the signal from the first node N1 and turns on, it can transmit the fourth power supply signal to the third node N3.

[0199] The second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7, and the second plate of the first capacitor C1 are all electrically connected to the seventh node N7.

[0200] Continue as Figure 6As shown, for output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power supply signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power supply signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3. Specifically, the signal at the third node N3 controls the on / off state of the ninth transistor T9. When the ninth transistor T9 responds to the signal at the third node N3 and conducts, it transmits the third power supply signal to the signal output terminal OUT, thereby outputting the second output signal. The signal at the fifth node N5 controls the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the signal at the fifth node N5 and conducts, it outputs the second power supply signal to the signal output terminal OUT, thereby outputting the first output signal.

[0201] For example, having a third power supply signal with a lower potential than the fourth power supply signal can improve the turn-off characteristics of the ninth transistor T9. For instance, the third power supply signal might have a potential of 7.5V, and the fourth power supply signal might have a potential of 8V.

[0202] For example, if the potential of the first power supply signal is lower than that of the second power supply signal, the threshold loss of the tenth transistor T10 can be reduced, ensuring output. For instance, the potential of the first power supply signal is -8V, and the potential of the fourth power supply signal is -7.5V.

[0203] Continue as Figure 6 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the first power signal line VGL1 (or the second power signal line VGL2). Specifically, the first power signal controls the on / off state of the eleventh transistor T11 and the twelfth transistor T12. When the eleventh transistor T11 responds to the first power signal and conducts, it can transmit the signal from the second node N2 to the fourth node N4. When the twelfth transistor T12 responds to the first power signal and conducts, it can transmit the signal from the first node N1 to the fifth node N5.

[0204] In this embodiment, four clock signal lines with different timing sequences and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of the large-screen display image quality. Simultaneously, the different timing sequences of each clock signal line avoid the impact of simultaneous timing changes on the display effect. Furthermore, using different power signal lines prevents excessive load on a single power signal line, thus avoiding signal fluctuations and improving the stability of the signal output.

[0205] In some embodiments, another 12T3C circuit structure is used as an example for illustration. This 12T3C circuit structure adopts... Figure 4 The timing control of the clock signal lines is shown. Figure 7 A circuit diagram of another 12T3C circuit structure provided in this embodiment of the present disclosure is shown below. Figure 7 As shown, input sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. First control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. Second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. Output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. Isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0206] Continue as Figure 7 As shown, for input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0207] For input sub-circuit 1, specifically, the first clock signal CK1 controls the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and is turned on, the input signal can be transmitted to the first node N1. The signal of the first node N1 controls the on / off state of the second transistor T2. When the second transistor T2 responds to the signal of the first node N1 and is turned on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off state of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and is turned on, the first power supply signal can be transmitted to the second node N2.

[0208] For example, such as Figure 4 As shown, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0209] Continue as Figure 7 As shown, for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0210] Specifically, for the first control sub-circuit 2, the signal of the fifth node N5 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the signal of the fifth node N5 and is turned on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the signal of the second node N2 and is turned on, the third power supply signal can be transmitted to the sixth node N6.

[0211] The second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0212] Continue as Figure 7 As shown, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1.

[0213] Specifically, for the second control sub-circuit 3, the signal at the fourth node N4 can control the on / off state of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and is turned on, it can transmit the fourth clock signal CK4 to the seventh node N7. The fourth clock signal CK4 can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the signal at the fourth clock signal CK4 and is turned on, it can transmit the signal at the seventh node N7 to the third node N3. The signal at the first node N1 can control the eighth transistor T8 to be turned on. When the eighth transistor T8 responds to the signal at the first node N1 and is turned on, it can transmit the fourth power supply signal to the third node N3.

[0214] The second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7, and the second plate of the first capacitor C1 are all electrically connected to the seventh node N7.

[0215] Continue as Figure 7 As shown, for output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power supply signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power supply signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0216] For output sub-circuit 4, the signal from the third node N3 controls the on / off state of the ninth transistor T9. When the ninth transistor T9 responds to the signal from the third node N3 and is turned on, it transmits the third power supply signal to the signal output terminal OUT, thereby outputting the second output signal. The signal from the fifth node N5 controls the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the signal from the fifth node N5 and is turned on, it outputs the second power supply signal to the signal output terminal OUT, thereby outputting the first output signal.

[0217] For example, if the potential of the third power supply signal is lower than that of the fourth power supply signal, the turn-off characteristics of the ninth transistor T9 can be improved.

[0218] For example, if the potential of the first power supply signal is lower than that of the second power supply signal, the threshold loss of the tenth transistor T10 can be reduced, thus ensuring output.

[0219] Continue as Figure 7 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0220] For example, in the isolation sub-circuit 5, the first power supply signal controls the on / off state of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power supply signal and is turned on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power supply signal controls the on / off state of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power supply signal and is turned on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0221] In this embodiment, four clock signal lines and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of the large-screen display image quality. Simultaneously, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 are all different, which avoids signal fluctuations caused by excessive load on a single power signal line, thus improving the stability of the signal output.

[0222] In some embodiments, a 13T3C circuit structure is used as an example for illustration. This 13T3C circuit structure adopts... Figure 2 or Figure 3 The timing control of the clock signal lines is shown. Figure 8 A circuit diagram of a 13T3C circuit structure provided in this disclosure embodiment is shown below. Figure 8 As shown, with Figure 6 Compared to the 12T3C circuit shown, this embodiment adds a thirteenth transistor T13 in the second control sub-circuit 3 to improve the stability of the output signal and prevent poor display flickering.

[0223] like Figure 8 As shown, input sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. First control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. Second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1. Output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. Isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0224] The circuit structure, connection relationship, and working principle of the input sub-circuit 1, the first control sub-circuit 2, the output sub-circuit 4, and the isolation sub-circuit 5 are the same as those described above. Figure 6The input sub-circuit 1, the first control sub-circuit 2, the output sub-circuit 4, and the isolation sub-circuit 5 in the 12T3C circuit shown have the same circuit structure, connection relationship, and working principle. For details, please refer to the above description, which will not be repeated here.

[0225] Continue as Figure 8 As shown, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the preset control terminal VEL. Specifically, the signal of the fourth node N4 can control the on / off state of the sixth transistor T6. When the sixth transistor T6 responds to the signal of the fourth node N4 and conducts, it can transmit the fourth clock signal CK4 to the seventh node N7. The fourth clock signal CK4 controls the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and conducts, it can transmit the signal from the seventh node N7 to the third node N3. The signal from the first node N1 controls the conduction of the eighth transistor T8. When the eighth transistor T8 responds to the signal from the first node N1 and conducts, it can transmit the fourth power supply signal to the third node N3. The preset control terminal VEL is connected to a preset control signal, which controls the on / off state of the thirteenth transistor T13. When the thirteenth transistor T13 responds to the preset control signal and conducts, it can transmit the fourth power supply signal to the first node N1.

[0226] It should be noted that during the initialization phase before the shift register starts working, the preset control signal is a low-level signal, and the thirteenth transistor T13 is turned on; during the actual working phase, the preset control signal is always a high-level signal, and the thirteenth transistor T13 is turned off.

[0227] In some embodiments, another 13T3C circuit structure is used as an example for illustration. This 13T3C circuit structure adopts... Figure 4 The timing control of the clock signal lines is shown. Figure 9 A circuit diagram of another 13T3C circuit structure provided in this embodiment of the present disclosure is shown below. Figure 9 As shown, with Figure 7Compared to the 12T3C circuit shown, this embodiment adds a thirteenth transistor T13 in the second control sub-circuit 3 to improve the stability of the output signal and prevent poor display flickering.

[0228] like Figure 9 As shown, input sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3. First control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. Second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1. Output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. Isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0229] Continue as Figure 9 As shown, for input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0230] For input sub-circuit 1, specifically, the first clock signal CK1 controls the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and is turned on, the input signal can be transmitted to the first node N1. The signal of the first node N1 controls the on / off state of the second transistor T2. When the second transistor T2 responds to the signal of the first node N1 and is turned on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off state of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and is turned on, the first power supply signal can be transmitted to the second node N2.

[0231] For example, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0232] Continue as Figure 9As shown, for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0233] Specifically, for the first control sub-circuit 2, the signal of the fifth node N5 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the signal of the fifth node N5 and is turned on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the signal of the second node N2 and is turned on, the third power supply signal can be transmitted to the sixth node N6.

[0234] The second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the first plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0235] Continue as Figure 9 As shown, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the preset control terminal VEL.

[0236] Specifically, for the second control sub-circuit 3, the signal at the fourth node N4 can control the on / off state of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and is turned on, it can transmit the fourth clock signal CK4 to the seventh node N7. The fourth clock signal CK4 can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the signal at the fourth clock signal CK4 and is turned on, it can transmit the signal at the seventh node N7 to the third node N3. The signal at the first node N1 can control the eighth transistor T8 to be turned on. When the eighth transistor T8 responds to the signal at the first node N1 and is turned on, it can transmit the fourth power supply signal to the third node N3.

[0237] The thirteenth transistor T13 is turned on and off by a preset control signal. When the thirteenth transistor T13 responds to the preset control signal and turns on, the fourth power supply signal can be transmitted to the first node N1.

[0238] It should be noted that during the initialization phase before the shift register starts working, the preset control signal is a low-level signal, and the thirteenth transistor T13 is turned on; during the actual working phase, the preset control signal is always a high-level signal, and the thirteenth transistor T13 is turned off.

[0239] Continue as Figure 9 As shown, for output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power supply signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power supply signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0240] For output sub-circuit 4, the signal from the third node N3 controls the on / off state of the ninth transistor T9. When the ninth transistor T9 responds to the signal from the third node N3 and is turned on, it transmits the third power supply signal to the signal output terminal OUT, thereby outputting the second output signal. The signal from the fifth node N5 controls the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the signal from the fifth node N5 and is turned on, it outputs the second power supply signal to the signal output terminal OUT, thereby outputting the first output signal.

[0241] For example, if the potential of the third power supply signal is lower than that of the fourth power supply signal, the turn-off characteristics of the ninth transistor T9 can be improved.

[0242] For example, if the potential of the first power supply signal is lower than that of the second power supply signal, the threshold loss of the tenth transistor T10 can be reduced, thus ensuring output.

[0243] Continue as Figure 9 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0244] For example, in the isolation sub-circuit 5, the first power supply signal controls the on / off state of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power supply signal and is turned on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power supply signal controls the on / off state of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power supply signal and is turned on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0245] In this embodiment, four clock signal lines and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of the large-screen display image quality. Simultaneously, the different potentials of the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 prevent excessive load on a single power signal line, which can cause signal fluctuations and improve the stability of the signal output. Furthermore, the balanced load on each power signal line—for example, the first power signal line VGL1 is connected to the third transistor T3 and the eleventh transistor T11; the second power signal line VGL2 is connected to the tenth transistor T10 and the twelfth transistor T12; the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5; and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13—further improves the display effect.

[0246] In some embodiments, Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of this disclosure, as shown below. Figure 10 As shown, the shift register also includes an isolation sub-circuit 5; the isolation sub-circuit 5 is configured to isolate the first node N1 and the first control sub-circuit 2 electrically connected to the first node N1; isolate the first node N1 and the output sub-circuit 4 electrically connected to the first node N1; isolate the first node N1 and the second control sub-circuit 3 electrically connected to the first node N1; and isolate the second node N2 and the second control sub-circuit 3 electrically connected to the second node N2.

[0247] like Figure 10 As shown, the first control sub-circuit 2 is electrically connected to the fifth node N5; the output sub-circuit 4 is electrically connected to the fifth node N5; and the second control sub-circuit 3 is electrically connected to the fourth node N4 and the fifth node N5.

[0248] like Figure 10As shown, the isolation sub-circuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1, and the second power signal line VGL2. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal; and simultaneously, to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0249] Alternatively, the isolation sub-circuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, and the first power signal line VGL1. The isolation sub-circuit 5 is configured to connect the first node N1 and the fifth node N5, and to connect the second node N2 and the fourth node N4 in response to the first power signal.

[0250] In this embodiment, the stability of the output signal is improved by adding an isolation sub-circuit 5.

[0251] Taking a 16T3C circuit structure as an example, this 16T3C circuit structure adopts... Figure 2 or Figure 3 The timing control of the clock signal lines is shown. Figure 11 A circuit diagram of a 16T3C circuit structure provided in this disclosure embodiment is shown below. Figure 11 As shown, with Figure 8 Compared to the 13T3C circuit shown, this embodiment adds a fourteenth transistor T14 to the input sub-circuit 1, and adds a fifteenth transistor T15 and a sixteenth transistor T16 to the first control sub-circuit 2.

[0252] like Figure 11 As shown, the input sub-circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourteenth transistor T14; the first control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3; the second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1; the output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2; and the isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0253] The circuit structure, connection relationship, and working principle of the second control sub-circuit 3, output sub-circuit 4, and isolation sub-circuit 5 are the same as those described above. Figure 8 The circuit structure, connection relationship and working principle of the second control sub-circuit 3, output sub-circuit 4 and isolation sub-circuit 5 in the 13T3C circuit shown are the same. For details, please refer to the above description, which will not be repeated here.

[0254] Continue asFigure 11 As shown, for input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the eighth node N8, and the control electrode is electrically connected to the first clock signal line CKL1. Specifically, the first clock signal CK1 can control the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and is turned on, it can transmit the input signal to the first node N1. The signal of the first node N1 can control the on / off state of the second transistor T2. When the second transistor T2 responds to the signal of the first node N1 and is turned on, it can transmit the second clock signal CK2 to the second node N2. The second clock signal CK2 controls the on / off state of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and is turned on, the first power supply signal can be transmitted to the second node N2. The first clock signal CK1 can also control the on / off state of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the first clock signal CK1 and is turned on, the input signal can be transmitted to the eighth node N8.

[0255] Continue as Figure 11As shown, for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the second plate of the third capacitor C3; the first electrode of the fifth transistor T5 is electrically connected to the third power supply signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, the second electrode is electrically connected to the first electrode and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power supply signal line VGL1; the second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and the control electrode is electrically connected to the control electrode of the fourth transistor T4. Specifically, the signal of the fifth node N5 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the signal of the fifth node N5 and is turned on, it can transmit the third clock signal CK3 to the sixth node N6. The signal at the second node N2 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the signal at the second node N2 and is turned on, the third power supply signal can be transmitted to the sixth node N6. The first power supply signal can control the on / off state of the fifteenth transistor T15. When the fifteenth transistor T15 responds to the first power supply signal and is turned on, the signal at the eighth node N8 can be transmitted to the ninth node N9. The signal at the ninth node N9 can control the on / off state of the sixteenth transistor T16. When the sixteenth transistor T16 responds to the signal at the ninth node N9 and is turned on, the signal at the ninth node N9 can be transmitted to the fifth node N5.

[0256] In this embodiment, four clock signal lines with different timing sequences and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of the large-screen display quality. Simultaneously, the different timing sequences of each clock signal line avoid the impact of simultaneous timing changes on the display effect. Furthermore, using different power signal lines prevents excessive load on a single power signal line, thus avoiding signal fluctuations and improving signal output stability. Additionally, the balanced load on each power signal line—for example, the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13—further improves the display effect.

[0257] Optionally, for the first control sub-circuit 2, the first terminal of the fifth transistor T5 can be electrically connected to the fourth power supply signal line VGH2.

[0258] In some embodiments, another 16T3C circuit structure is used as an example for illustration. This 16T3C circuit structure adopts... Figure 4The timing control of the clock signal lines is shown. Figure 12 A circuit diagram of another 16T3C circuit structure provided in this embodiment of the present disclosure is shown below. Figure 12 As shown, with Figure 9 Compared to the 13T3C circuit shown, this embodiment adds a fourteenth transistor T14 to the input sub-circuit 1, and adds a fifteenth transistor T15 and a sixteenth transistor T16 to the first control sub-circuit 2.

[0259] like Figure 12 As shown, the input sub-circuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourteenth transistor T14; the first control sub-circuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3; the second control sub-circuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13, and a first capacitor C1; the output sub-circuit 4 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2; and the isolation sub-circuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0260] Continue as Figure 12 As shown, for input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the eighth node N8, and the control electrode is electrically connected to the second clock signal line CKL2.

[0261] For input sub-circuit 1, specifically, the first clock signal CK1 can control the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and is turned on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on / off state of the second transistor T2. When the second transistor T2 responds to the signal of the first node N1 and is turned on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on / off state of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and is turned on, the first power supply signal can be transmitted to the second node N2. The second clock signal CK2 can also control the on / off state of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the second clock signal CK2 and is turned on, the input signal can be transmitted to the eighth node N8.

[0262] For example, such as Figure 4 As shown, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2. This can avoid problems such as transistor hysteresis caused by the gate and source of the third transistor T3 and the first transistor T1 being at the same voltage difference for a long time, and the gate and source of the fourteenth transistor T14 and the first transistor T1 being at the same voltage difference for a long time, which would affect the transistor characteristics.

[0263] Continue as Figure 12 As shown, for the first control sub-circuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the second plate of the third capacitor C3; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, the second electrode is electrically connected to the first electrode and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power signal line VGL1; the second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and the control electrode is electrically connected to the control electrode of the fourth transistor T4.

[0264] Specifically, for the first control sub-circuit 2, the signal of the fifth node N5 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the signal of the fifth node N5 and is turned on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the signal of the second node N2 and is turned on, the third power supply signal can be transmitted to the sixth node N6. The first power supply signal can control the on / off state of the fifteenth transistor T15. When the fifteenth transistor T15 responds to the first power supply signal and is turned on, the signal of the eighth node N8 can be transmitted to the ninth node N9. The signal of the ninth node N9 can control the on / off state of the sixteenth transistor T16. When the sixteenth transistor T16 responds to the signal of the ninth node N9 and is turned on, the signal of the ninth node N9 can be transmitted to the fifth node N5.

[0265] The control electrode of the fourth transistor T4, the second plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, the second electrode of the sixteenth transistor T16, and the control electrode of the sixteenth transistor T16 are all electrically connected to the ninth node N9.

[0266] Continue as Figure 12As shown, for the second control sub-circuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fifth node N5; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the preset control terminal VEL.

[0267] Specifically, for the second control sub-circuit 3, the signal at the fourth node N4 can control the on / off state of the sixth transistor T6. When the sixth transistor T6 responds to the signal at the fourth node N4 and is turned on, it can transmit the fourth clock signal CK4 to the seventh node N7. The fourth clock signal CK4 can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the signal at the fourth clock signal CK4 and is turned on, it can transmit the signal at the seventh node N7 to the third node N3. The signal at the fifth node N5 can control the turn on of the eighth transistor T8. When the eighth transistor T8 responds to the signal at the fifth node N5 and is turned on, it can transmit the fourth power supply signal to the third node N3.

[0268] The preset control signal controls the on / off state of the thirteenth transistor T13. When the thirteenth transistor T13 responds to the preset control signal and turns on, the fourth power supply signal can be transmitted to the fifth node N5.

[0269] Continue as Figure 12 As shown, for output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power supply signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power supply signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0270] For output sub-circuit 4, the signal from the third node N3 controls the on / off state of the ninth transistor T9. When the ninth transistor T9 responds to the signal from the third node N3 and is turned on, it transmits the third power supply signal to the signal output terminal OUT, thereby outputting the second output signal. The signal from the fifth node N5 controls the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the signal from the fifth node N5 and is turned on, it outputs the second power supply signal to the signal output terminal OUT, thereby outputting the first output signal.

[0271] For example, if the potential of the third power supply signal is lower than that of the fourth power supply signal, the turn-off characteristics of the ninth transistor T9 can be improved.

[0272] For example, if the potential of the first power supply signal is lower than that of the second power supply signal, the threshold loss of the tenth transistor T10 can be reduced, thus ensuring output.

[0273] Continue as Figure 12 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0274] For example, in the isolation sub-circuit 5, the first power supply signal controls the on / off state of the eleventh transistor T11. When the eleventh transistor T11 responds to the first power supply signal and is turned on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power supply signal controls the on / off state of the twelfth transistor T12. When the twelfth transistor T12 responds to the second power supply signal and is turned on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0275] In this embodiment, four clock signal lines and four power signal lines with different potentials are used, reducing the number of transistors connected to a single clock signal line and a single power signal line. This reduces the load on each clock signal line and each power signal line, shortening the signal output time and improving the uniformity of the large-screen display image quality. Simultaneously, the different potentials of the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1, and the fourth power signal line VGH2 prevent excessive load on a single power signal line, thus avoiding signal fluctuations and improving signal output stability. Furthermore, the balanced load on each power signal line—for example, connecting the third power signal line VGH1 to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 to the eighth transistor T8 and the thirteenth transistor T13—further enhances the display effect.

[0276] In some embodiments, the above-mentioned Figure 7 The 12T3C shown, such as Figure 9 The 13T3C shown and as Figure 12 In the circuit structure of the 16T3C shown, the first transistor T1 and the third transistor T3 in the input sub-circuit 1 can be connected to the same first clock signal line CKL1, and the second transistor T2 is connected to the second clock signal line CKL2.

[0277] For example, the input sub-circuit 1 includes a first transistor T1, a second transistor T2, and a third transistor T3; the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power supply signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first clock signal line CKL1.

[0278] In some embodiments, the above-mentioned Figure 7 The 12T3C shown, such as Figure 9 The 13T3C shown and as Figure 12 In the circuit structure of the 16T3C shown, the eleventh transistor T11 and the twelfth transistor T12 in the isolation sub-circuit 5 can also be connected to the same first power supply signal line VGL1 to ensure the stability of the output signal during the isolation process.

[0279] The working principle of the shift register provided in the embodiments of this disclosure will be described in further detail below.

[0280] In some embodiments, Figure 13 A timing diagram of an exemplary shift register provided for embodiments of this disclosure, such as... Figure 13 As shown, to adopt Figure 2 The 12T3C circuit structure for timing control of the clock signal lines shown (i.e., as shown) Figure 6 Taking the 12T3C circuit structure shown as an example, its working stages specifically include stage t1, stage t2, stage t3, stage t4, stage t5, stage t6, stage t7, stage t8, stage t9, stage t10, stage t11, and stage t12, where:

[0281] In the first stage t1, the input signal transmitted at the Input terminal is a high-level signal, the first clock signal CK1 is active (can be understood as low-level), and the second, third, and fourth clock signals CK2, CK3, and CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, and the first node N1 and the fifth node N5 are written with high-level signals. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The third node N3 remains at the high potential of the previous stage, and the ninth transistor T9 is turned off. The output signal remains the same as in the previous stage, and the signal output terminal OUT outputs a low-level first output signal.

[0282] In the second stage t2, the input signal transmitted at the Input terminal is a high-level signal, the second clock signal CK2 is active (can be understood as low-level), and the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the third transistor T3 is turned on, the second node N2 is written with a low-level signal, the fifth transistor T5 is turned on, the sixth node N6 is written with a high-level signal, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. The first node N1 and the fifth node N5 maintain the high potential of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also turned off. The third node N3 maintains the high potential of the previous stage, and the ninth transistor T9 is turned off. The output signal at this time maintains the previous stage, and the signal output terminal OUT outputs a low-level first output signal.

[0283] In the third stage t3, the input signal transmitted at the Input terminal is a high-level signal, the third clock signal CK3 is active (can be understood as low-level), and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, while the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The second node N2 and the fourth node N4 maintain the low potential of the previous stage, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. However, the seventh transistor T7 remains off, therefore the third node N3 maintains the high potential of the previous stage, and the ninth transistor T9 is turned off. The output signal at this time maintains the previous stage, and the signal output terminal OUT outputs the first low-level output signal.

[0284] In the fourth stage t4, the input signal transmitted at the Input terminal is a high-level signal, the fourth clock signal CK4 is active (can be understood as low-level), and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are all off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and the sixth node N6 is written with a high-level signal. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, the seventh node N7 is written with a low-level signal, and simultaneously, the seventh transistor T7 is turned on, the third node N3 is written with a low-level signal, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-level second output signal.

[0285] In the fifth stage t5, the input signal transmitted at the Input terminal is a high-level signal. The first clock signal CK1 is active (can be understood as low-level), while the second, third, and fourth clock signals CK2, CK3, and CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, and the first node N1 and the fifth node N5 are written with high-level signals. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The third node N3 remains at the low potential of the previous stage, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-level second output signal.

[0286] In stage t6, the input signal transmitted at the Input terminal is a high-level signal, the second clock signal CK2 is active (can be understood as low-level), and the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the third transistor T3 is turned on, the second node N2 is written with a low-level signal, the fifth transistor T5 is turned on, the sixth node N6 is written with a high-level signal, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. The first node N1 and the fifth node N5 maintain the high potential of the previous stage. The second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also turned off. The third node N3 maintains the low potential of the previous stage, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-level second output signal.

[0287] In stage t7, the input signal transmitted at the Input terminal is a high-level signal, the third clock signal CK3 is active (can be understood as low-level), and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, while the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all off. The second node N2 and the fourth node N4 maintain the low potential of the previous stage, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. However, the seventh transistor T7 remains off, therefore the third node N3 maintains the high potential of the previous stage. The ninth transistor T9 is turned on, and at this time, the signal output terminal OUT outputs a high-level second output signal.

[0288] The operating state of stage 8 (t8) is the same as that of stage 4 (t4). Specifically, in stage 8 (t8), the input signal transmitted at the input terminal is a high-level signal, the fourth clock signal CK4 is an active level (which can be understood as a low level), and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are inactive levels (which can be understood as high levels). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and the sixth node N6 is written with a high-level signal. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, the seventh node N7 is written with a low-level signal, and the seventh transistor T7 is turned on. The third node N3 is written with a low-level signal, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-level second output signal.

[0289] In stage t9, the input signal transmitted at the Input terminal is a low-level signal. The first clock signal CK1 is active (low level), while the second, third, and fourth clock signals CK2, CK3, and CK4 are inactive (high level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, and a low-level signal is written to the first node N1. The second transistor T2 is turned on, and a high-level signal is written to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and a high-level signal is written to the sixth node N6. Also simultaneously, the eighth transistor T8 is turned on, and a high-level signal is written to the third node N3. The ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, and is at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-level first output signal.

[0290] In stage t10, the input signal transmitted at the Input terminal is a low-level signal. The second clock signal CK2 is active (can be understood as low level), while the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are inactive (can be understood as high level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the low potential V1 of the previous stage, the eighth transistor T8 remains on, the third node N3 is continuously written with a high-level signal, the ninth transistor T9 remains off, the tenth transistor T10 remains on, and the signal output terminal OUT continuously outputs the first output signal at a low potential.

[0291] In stage eleven (t11), the input signal transmitted at the Input terminal is a low-level signal. The third clock signal CK3 is active (can be understood as low level), while the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are inactive (can be understood as high level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, and the second node N2 is written with a high-level signal. The fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. At the same time, the fourth transistor T4 is turned on, the sixth node N6 is written with a low-level signal, and the third capacitor C3 further pulls the low potential V1 of the fifth node N5 down to a low potential V2. The tenth transistor T10 remains on, and the signal output terminal OUT outputs a low-level first output signal.

[0292] In stage t12, the input signal transmitted at the Input terminal is a high-level signal, the fourth clock signal CK4 is active (can be understood as low-level), and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are inactive (can be understood as high-level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, and a high-level signal is written to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and a high-level signal is written to the sixth node N6. At the same time, the eighth transistor T8 is turned on, a high-level signal is written to the third node N3, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, and is at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-level first output signal (i.e.,...). Figure 13 OUT1 in the middle. Figure 13 OUT2 in the diagram represents the signal output from the OUT terminal of the next-level shift register.

[0293] In some embodiments, Figure 14 A timing diagram of another exemplary shift register provided for embodiments of this disclosure, such as... Figure 14 As shown, to adopt Figure 3 The 12T3C circuit structure for timing control of the clock signal lines shown (i.e., as shown) Figure 6 Taking the 12T3C circuit structure shown as an example, its working stages specifically include the first stage t_1, the second stage t_2, the third stage t_3, the fourth stage t_4, the fifth stage t_5, the sixth stage t_6, the seventh stage t_7, the eighth stage t_8, the ninth stage t_9, the tenth stage t_10, the eleventh stage t_11, and the twelfth stage t_12.

[0294] This is related to the above. Figure 13 The difference in the timing sequence shown is as follows: in the third stage t_3, the seventh stage t_7, and the eleventh stage t_11, the fourth clock signal CK4 is active, while the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are inactive; in the fourth stage t_4, the eighth stage t_8, and the twelfth stage t_12, the third clock signal CK3 is active, while the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are inactive.

[0295] The working principles of the first stage t_1 and the first stage t1, the second stage t_2 and the second stage t2, the fifth stage t_5 and the fifth stage t5, the sixth stage t_6 and the sixth stage t6, the ninth stage t_9 and the ninth stage t9, and the tenth stage t_10 and the tenth stage t10 are the same, and the repeated parts will not be repeated.

[0296] like Figure 14 As shown, in the eleventh stage t11, the input signal transmitted at the Input terminal is a high-level signal, the fourth clock signal CK4 is an effective level (which can be understood as a low level), and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are ineffective levels (which can be understood as high levels). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, and the second node N2 is written with a high-level signal. The fifth transistor T5 and the sixth transistor T6 are turned off. Simultaneously, the fourth transistor T4 is turned on, and the sixth node N6 is written with a high-level signal. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, and is at a low potential V1. The tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-level first output signal.

[0297] like Figure 14 As shown, in the twelfth stage t_12, the input signal transmitted at the Input terminal is a low-level signal, the third clock signal CK3 is an active level (which can be understood as low level), and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 are inactive levels (which can be understood as high level). The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. Simultaneously, the fourth transistor T4 is turned on, the sixth node N6 is written with a low-level signal, and the third capacitor C3 further pulls the low potential V1 of the fifth node N5 down to a low potential V2. The tenth transistor T10 remains on, and the signal output terminal OUT outputs a low-level first output signal.

[0298] In some embodiments, Figure 15 A timing diagram of another exemplary shift register provided for embodiments of this disclosure, such as... Figure 15 As shown, to adopt Figure 4 The 12T3C circuit structure for timing control of the clock signal lines shown (i.e., as shown) Figure 7 Taking the 12T3C circuit structure shown as an example, its working stages specifically include the first stage t_21, the second stage t_22, the third stage t_23, the fourth stage t_24, the fifth stage t_25, and the sixth stage t_26, where:

[0299] In the first stage t_21, the input signal transmitted at the Input terminal is a high-level signal. The first clock signal CK1 and the second clock signal CK2 are both at the first level, which can be understood as low-level. The third clock signal CK3 and the fourth clock signal CK4 are both at the fourth level, which can be understood as high-level. At this time, the seventh transistor T7 is turned off, and the first transistor T1 and the third transistor T3 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally open twelfth transistor T12, thereby controlling the potential of the first node N1 and the fifth node N5 to be high. At the same time, the first power supply signal is a low-level signal, and the first power supply signal is transmitted to the fourth node N4 through the third transistor T3 and the normally open eleventh transistor T11, thereby controlling the potential of the second node N2 and the fourth node N4 to be low. Correspondingly, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned off. The output signal at this time remains the same as in the previous stage, such as... Figure 8 As shown, maintain the low-potential output of the previous stage.

[0300] In the second stage t_22, the first clock signal CK1 and the second clock signal CK2 are at the second level, which can be understood as a high level; the third clock signal CK3 and the fourth clock signal CK4 are at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, and the fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is low at this time, and the ninth transistor T9 is turned on, thus outputting the second output signal, which is the high-potential third power supply signal.

[0301] In the third stage t_23, the input signal is a high-level signal. The first clock signal CK1 and the second clock signal CK2 are both at the first level, which can be understood as low-level. The third clock signal CK3 and the fourth clock signal CK4 are both at the fourth level, which can be understood as high-level. At this time, the seventh transistor T7 is turned off, and the potential of the third node N3 remains stably at the low potential of the previous stage. At this time, the ninth transistor T9 can remain on, thereby outputting the second output signal, which is the high-level third power supply signal.

[0302] In the fourth stage t_24, the input signal is a low-level signal. The first clock signal CK1 and the second clock signal CK2 are at the second level, which can be understood as a high level. The third clock signal CK3 and the fourth clock signal CK4 are at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, while the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are all turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on. The fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is low at this time, and the ninth transistor T9 is turned on, thus outputting the second output signal, which is the high-potential third power supply signal.

[0303] In the fifth stage t_25, the input signal is a low-level signal. The first clock signal CK1 and the second clock signal CK2 are both at the first level, which can be understood as low-level. The third clock signal CK3 and the fourth clock signal CK4 are both at the fourth level, which can be understood as high-level. At this time, the seventh transistor T7 is turned off, and the first transistor T1 and the second transistor T2 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally open twelfth transistor T12, thereby controlling the potentials of the first node N1 and the fifth node N5 to be low. At the same time, the first power supply signal is a low-level signal, and it is transmitted to the fourth node N4 through the third transistor T3 and the normally open eleventh transistor T11, thereby controlling the potentials of the second node N2 and the fourth node N4 to be low. Correspondingly, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 are turned on. Since the eighth transistor T8 is turned on, the third node N3 is at a high level, so the ninth transistor T9 is turned off. At the same time, due to the threshold loss, the potential of the fifth node N5 is slightly higher than the potential of the second power supply signal. At this time, the tenth transistor T10 is not fully turned on, so the potential of the first output signal will be slightly higher than the potential of the second power supply signal.

[0304] In stage t_26, the input signal is low, the first clock signal CK1 is at the second level, the second clock signal CK2 is at the second level (which can be understood as high level), the third clock signal CK3 is at the third level, and the fourth clock signal CK4 is at the third level (which can be understood as low level). At this time, the first transistor T1 and the third transistor T3 are off, the seventh transistor T7 is on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the low potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the eighth transistor T8 and the tenth transistor T10 are on, and the fourth power supply signal is transmitted to the third node N3 through the on-circuit eighth transistor T8, pulling the potential of the third node N3 high. At this time, the ninth transistor T9 is off. At the same time, the potential of the fifth node N5 can be lowered to a potential lower than the second power supply signal through the coupling of the second capacitor C2. At this time, the tenth transistor T10 is fully turned on, and the potential of the signal output terminal OUT is lowered to the potential of the second power supply signal, that is, the first output signal.

[0305] The above is a complete description of the shift register provided in the embodiments of this disclosure.

[0306] In addition, this disclosure also provides a gate driving circuit, including N cascaded shift registers; except for the first-stage shift register, the signal input terminal Input of the (i+1)th-stage shift register is electrically connected to the signal output terminal OUT of the i-th-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0307] In some embodiments, Figure 16 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 16 As shown, the first clock signal line CKL1 in the i-th stage shift register is multiplexed as the fourth clock signal line CKL4 in the (i+1)-th stage shift register, the second clock signal line CKL2 in the i-th stage shift register is multiplexed as the first clock signal line CKL1 in the (i+1)-th stage shift register, the third clock signal line CKL3 in the i-th stage shift register is multiplexed as the second clock signal line CKL2 in the (i+1)-th stage shift register, and the fourth clock signal line CKL4 in the i-th stage shift register is multiplexed as the third clock signal line CKL3 in the (i+1)-th stage shift register.

[0308] like Figure 16 The gate drive circuit shown is suitable for, for example, Figure 2 or Figure 3 The driving timing is shown.

[0309] In some embodiments, Figure 17 A schematic diagram of another gate driving circuit provided in an embodiment of this disclosure is shown below.Figure 17 As shown, the first clock signal line CKL1 in the i-th stage shift register is multiplexed as the third clock signal line CKL3 in the (i+1)-th stage shift register, the second clock signal line CKL2 in the i-th stage shift register is multiplexed as the fourth clock signal line CKL4 in the (i+1)-th stage shift register, the third clock signal line CKL3 in the i-th stage shift register is multiplexed as the first clock signal line CKL1 in the (i+1)-th stage shift register, and the fourth clock signal line CKL4 in the i-th stage shift register is multiplexed as the second clock signal line CKL2 in the (i+1)-th stage shift register.

[0310] like Figure 17 The gate drive circuit shown is suitable for, for example, Figure 4 The driving timing is shown.

[0311] Figure 18 Provided for the embodiments of this disclosure Figure 6 The circuit diagram shown is a cascaded shift register of the 12T3C circuit structure. Figure 19 Provided for the embodiments of this disclosure Figure 8 The circuit diagram shown is a cascaded shift register of the 13T3C circuit structure. Figure 20 Provided for the embodiments of this disclosure Figure 11 The circuit diagram shown is a cascaded shift register of the 16T3C circuit structure.

[0312] In some embodiments, such as Figure 18 or Figure 19 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)-th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0313] The timing of the output signal OUT of the i-th stage shift register is shown in the figure. Figure 13 The timing of the OUT signal shown, and the output signal OUT2 of the (i+1)th stage shift register, is shown in the figure.Figure 13 The OUT2 signal is shown. Alternatively, the timing of the OUT output signal of the i-th stage shift register can be found in the example below. Figure 14 The timing of the OUT signal shown, and the output signal OUT2 of the (i+1)th stage shift register, is shown in the figure. Figure 14 The OUT2 signal is shown.

[0314] In some embodiments, such as Figure 20 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0315] Figure 21 Provided for the embodiments of this disclosure Figure 7 The circuit diagram shown is a cascaded shift register of the 12T3C circuit structure. Figure 22 Provided for the embodiments of this disclosure Figure 9 The circuit diagram shown is a cascaded shift register of the 13T3C circuit structure. Figure 23 Provided for the embodiments of this disclosure Figure 12 The circuit diagram shown is a cascaded shift register of the 16T3C circuit structure.

[0316] In some embodiments, such as Figure 21 or Figure 22As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)-th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0317] In some embodiments, such as Figure 23 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the (i+1)th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0318] Since the i-th and i+1-th cascaded shift registers in the gate drive circuit are electrically connected to a set of clock signals with different timings, namely the first clock signal CK1 and the second clock signal CK2, which have different timings from the third clock signal CK3 and the fourth clock signal CK4, their timings are not affected.

[0319] In addition, this disclosure also provides a display device, which includes a pixel driving circuit and a gate driving circuit as described above. The gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

[0320] For example, the display device can be any product with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0321] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized in that, It includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; The input sub-circuit is configured to control the potential of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line; The first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line; The second control sub-circuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node, and the fourth clock signal provided by the fourth clock signal line; The output sub-circuit is configured to output a first output signal in response to a signal from the first node, or to output a second output signal in response to a signal from the third node.

2. The shift register according to claim 1, characterized in that, Within one clock cycle, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the third clock signal, and the pulse of the third clock signal precedes the pulse of the fourth clock signal.

3. The shift register according to claim 1, characterized in that, Within one clock cycle, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the fourth clock signal, and the pulse of the fourth clock signal precedes the pulse of the third clock signal.

4. The shift register according to claim 1, characterized in that, The first clock signal and the second clock signal have the same timing sequence; the third clock signal has the opposite timing sequence to the first clock signal; the fourth clock signal has the same timing sequence as the third clock signal.

5. The shift register according to claim 4, characterized in that, The first clock signal and the second clock signal include a first level; the potential of the first level of the first clock signal is different from the potential of the first level of the second clock signal; And / or, The third clock signal and the fourth clock signal include a third level; the potential of the third level of the third clock signal is different from the potential of the third level of the fourth clock signal.

6. The shift register according to claim 5, characterized in that, The potential of the first level of the first clock signal is less than the potential of the first level of the second clock signal; and / or, The potential of the third level of the third clock signal is less than the potential of the third level of the fourth clock signal.

7. The shift register according to claim 5, characterized in that, The first clock signal and the second clock signal also include a second level, which is different from the first level; The potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; And / or, The third clock signal and the fourth clock signal also include a fourth level, which is different from the third level; The potential of the fourth level of the third clock signal is different from the potential of the fourth level of the fourth clock signal.

8. The shift register according to claim 7, characterized in that, The potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or, The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

9. The shift register according to any one of claims 1 to 8, characterized in that, The shift register also includes a first power signal line, a second power signal line, a third power signal line, and a fourth power signal line; The input sub-circuit is electrically connected to the first power signal line, the first control sub-circuit is electrically connected to the third power signal line or the fourth power signal line, the second control sub-circuit is electrically connected to the fourth power signal line, and the output sub-circuit is electrically connected to the second power signal line and the third power signal line.

10. The shift register according to claim 9, characterized in that, The potential of the first power signal transmitted by the first power signal line is less than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is less than the potential of the fourth power signal transmitted by the fourth power signal line. The potential of the second power signal is less than the potential of the third power signal.

11. The shift register according to claim 10, characterized in that, The potential of the first level of the first clock signal is equal to the potential of the first power supply signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power supply signal. The potential of the first level of the second clock signal is equal to the potential of the second power supply signal, and the potential of the second level of the second clock signal is equal to the potential of the third power supply signal; The potential of the third level of the third clock signal is equal to the potential of the first power supply signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power supply signal. The potential of the third level of the fourth clock signal is equal to the potential of the second power supply signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power supply signal.

12. The shift register according to any one of claims 4 to 8, characterized in that, The pulse width of the first level of the first clock signal is less than the pulse width of the second level; and / or, the pulse width of the third level of the third clock signal is less than the pulse width of the fourth level.

13. The shift register according to any one of claims 1 to 3, characterized in that, The input sub-circuit includes a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line. The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

14. The shift register according to any one of claims 1 to 8, characterized in that, The input sub-circuit includes a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line. The first electrode of the second transistor is electrically connected to the first clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

15. The shift register according to any one of claims 1 to 8, characterized in that, The input sub-circuit includes a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line. The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

16. The shift register according to any one of claims 1 to 8, characterized in that, The shift register also includes an isolation sub-circuit; The isolation sub-circuit is configured to isolate the first node and the first control sub-circuit electrically connected to the first node. Isolate the first node and the output sub-circuit electrically connected to the first node; In addition, the second node and the second control sub-circuit electrically connected to the second node are isolated; The first control sub-circuit is electrically connected to the fifth node; the output sub-circuit is electrically connected to the fifth node; The second control sub-circuit is electrically connected to the fourth node.

17. The shift register according to claim 16, characterized in that, The isolation sub-circuit includes an eleventh transistor and a twelfth transistor; The first electrode of the eleventh transistor is electrically connected to the second node, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first power signal line. The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

18. The shift register according to claim 16, characterized in that, The isolation sub-circuit includes an eleventh transistor and a twelfth transistor; The first electrode of the eleventh transistor is electrically connected to the second node, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first power signal line. The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

19. The shift register according to claim 16, characterized in that, The first control sub-circuit includes a fourth transistor, a fifth transistor, and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the fifth node; The first electrode of the fifth transistor is electrically connected to the third power signal line or the fourth power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node. The second plate of the third capacitor is electrically connected to the fifth node.

20. The shift register according to claim 16, characterized in that, The second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the first capacitor. The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line. The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

21. The shift register according to claim 16, characterized in that, The second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor, and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the first capacitor. The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line. The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node. The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the preset control terminal.

22. The shift register according to claim 16, characterized in that, The input sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line. The first electrode of the second transistor is electrically connected to the second clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line. The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

23. The shift register according to any one of claims 1 to 8, characterized in that, The shift register also includes an isolation sub-circuit; The isolation sub-circuit is configured to isolate the first node and the first control sub-circuit electrically connected to the first node. Isolate the first node and the output sub-circuit electrically connected to the first node; Isolate the first node and the second control sub-circuit electrically connected to the first node; and isolate the second node and the second control sub-circuit electrically connected to the second node; The first control sub-circuit is electrically connected to the fifth node; the output sub-circuit is electrically connected to the fifth node; The second control sub-circuit is electrically connected to the fourth node and the fifth node.

24. The shift register according to claim 23, characterized in that, The input sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line. The first electrode of the second transistor is electrically connected to the first clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power supply signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line. The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

25. The shift register according to claim 24, characterized in that, The first control sub-circuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor, and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the second plate of the third capacitor. The first electrode of the fifth transistor is electrically connected to the third power signal line or the fourth power signal line, the second electrode is electrically connected to the first plate of the third capacitor, and the control electrode is electrically connected to the second node. The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line; The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

26. The shift register according to claim 25, characterized in that, The second control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor, and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first plate of the first capacitor. The first electrode of the seventh transistor is electrically connected to the second plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line. The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node. The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the preset control terminal.

27. The shift register according to claim 23, characterized in that, The output sub-circuit includes a ninth transistor, a tenth transistor, and a second capacitor; The first electrode of the ninth transistor is electrically connected to the third power signal line and the first plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node. The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node. The second plate of the second capacitor is electrically connected to the third node.

28. A gate driving circuit, characterized in that, The system comprises N cascaded shift registers as described in any one of claims 1 to 27; except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the signal output terminal of the ith-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

29. The gate driving circuit according to claim 28, characterized in that, The first clock signal line in the shift register of stage i is multiplexed as the fourth clock signal line in the shift register of stage i+1, the second clock signal line in the shift register of stage i is multiplexed as the first clock signal line in the shift register of stage i+1, the third clock signal line in the shift register of stage i is multiplexed as the second clock signal line in the shift register of stage i+1, and the fourth clock signal line in the shift register of stage i is multiplexed as the third clock signal line in the shift register of stage i+1.

30. The gate driving circuit according to claim 28, characterized in that, The first clock signal line in the shift register of stage i is multiplexed as the third clock signal line in the shift register of stage i+1, the second clock signal line in the shift register of stage i is multiplexed as the fourth clock signal line in the shift register of stage i+1, the third clock signal line in the shift register of stage i is multiplexed as the first clock signal line in the shift register of stage i+1, and the fourth clock signal line in the shift register of stage i is multiplexed as the second clock signal line in the shift register of stage i+1.

31. A display device, characterized in that, It includes a pixel driving circuit and a gate driving circuit as described in any one of claims 28 to 30, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

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