Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a preparation method of a semiconductor device and the semiconductor device. The method comprises the following steps: providing a wafer, the wafer is provided with an aluminum-containing metal layer and a passivation layer, the passivation layer is a multilayer structure stacked on the metal layer in sequence, and the passivation layer comprises an oxide dielectric layer; etching the passivation layer by using a plurality of groups of etching gases corresponding to the multilayer structure to form an opening region exposing part of the metal layer; and performing a cleaning process to clean byproducts of at least the opening region; wherein the plurality of groups of etching gases comprise a first etching gas for etching the oxide dielectric layer, the first etching gas comprises a first fluorine-containing gas with a low carbon-fluorine ratio and a first auxiliary gas for removing carbon-containing polymers generated in the etching process. The application solves the polymer defects formed in the etching process of the passivation layer, and improves the yield of the semiconductor device product.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] In semiconductor manufacturing processes, pads are needed to prepare for subsequent packaging processes. Common techniques involve dry etching and cleaning a capping layer on a metal layer (e.g., aluminum) to form the pads. However, during subsequent defect detection, densely distributed polymer defects remain in the open areas of the pads on the wafer. These polymers have high adhesion to the pad areas and are difficult to remove using traditional cleaning processes, reducing pad performance and reliability, and consequently affecting the yield of semiconductor device products. Summary of the Invention

[0003] In view of at least one technical problem in the related art, the purpose of this application is to provide a method for fabricating a semiconductor device.

[0004] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor device, comprising:

[0005] A wafer is provided, on which an aluminum-containing metal layer and a passivation layer are formed, the passivation layer being a multilayer structure sequentially stacked on the metal layer, the passivation layer including an oxide dielectric layer;

[0006] Multiple sets of etching gases corresponding to the multilayer structure are used to etch the passivation layer, forming an opening region that exposes a portion of the metal layer.

[0007] Perform a cleaning process to at least clean the byproducts in the opening area;

[0008] The multiple etching gases include a first etching gas for etching the oxide dielectric layer. The first etching gas includes a first fluorine-containing gas with a low carbon-to-fluorine ratio and a first auxiliary gas. The first auxiliary gas is used to remove carbon-containing polymers generated during the etching process.

[0009] In some embodiments, the first fluorinated gas includes trifluoromethane and carbon tetrafluoride; in the first etching gas, the gas flow rate ratio of trifluoromethane to carbon tetrafluoride is 5:(24-26);

[0010] And / or, the ratio of the flow rate of the first fluorinated gas to the flow rate of the first auxiliary gas is less than 4.

[0011] In some embodiments, the first auxiliary gas includes oxygen;

[0012] In the first etching gas, the gas flow rate ratio of trifluoromethane to oxygen is 10:(19-21).

[0013] In some embodiments, the gas flow rate of carbon tetrafluoride contained in the first fluorinated gas ranges from 480 sccm to 520 sccm, and the gas flow rate of the first auxiliary gas ranges from 190 sccm to 210 sccm.

[0014] In some embodiments, a photoresist layer is formed on the passivation layer, and the first etching gas further includes a second auxiliary gas for hardening the photoresist layer; the etching of the passivation layer using multiple sets of etching gases corresponding to the multilayer structure includes:

[0015] Using the photoresist layer as a mask, the multiple sets of etching gases are used to etch the corresponding layers in the passivation layer in stages; after etching the passivation layer, the remaining thickness of the photoresist layer is greater than a preset thickness value.

[0016] In some embodiments, the second auxiliary gas includes hydrogen, and the gas flow rate ratio of the second auxiliary gas to the first auxiliary gas is (1-2):(19-21).

[0017] In some embodiments, the preset thickness value is greater than or equal to 1000 angstroms.

[0018] In some embodiments, the passivation layer further includes an etch stop layer located between the metal layer and the oxide dielectric layer; the method further includes:

[0019] After etching the passivation layer to the etching stop layer, the opening region is etched with a second etching gas to remove byproducts generated during the etching process.

[0020] In some embodiments, the second etching gas includes a second fluorinated gas having a low carbon-to-fluorine ratio and a third auxiliary gas, wherein the gas flow rate ratio of the second fluorinated gas to the third auxiliary gas is 1:(18-20).

[0021] In some embodiments, the second etching gas satisfies at least one of the following:

[0022] The second fluorinated gas includes carbon tetrafluoride;

[0023] The third auxiliary gas includes oxygen;

[0024] The flow rate of the third auxiliary gas is in the range of 1800 sccm to 2000 sccm.

[0025] On the other hand, this application also provides a semiconductor device, which is manufactured using any of the semiconductor device fabrication methods described above.

[0026] On the other hand, this application also provides a chip including any of the semiconductor devices described above.

[0027] On the other hand, this application also provides an electronic device including any of the semiconductor devices described above.

[0028] The method for fabricating a semiconductor device and the semiconductor device disclosed in this application have at least the following beneficial effects:

[0029] By employing multiple sets of etching gases to etch the multilayer structure in the passivation layer on the wafer, openings are formed in the exposed aluminum-containing metal layer, which are then cleaned. The multiple sets of etching gases include a first etching gas for etching the oxide dielectric layer in the passivation layer. This first etching gas comprises a first fluorinated gas with a low carbon-to-fluorine ratio and a first auxiliary gas. By adjusting the etching gas to a first fluorinated gas with a low carbon-to-fluorine ratio and removing the fluorinated gas with a high carbon-to-fluorine ratio, aluminum-containing polymer defects formed during the passivation layer etching process can be fundamentally reduced. Furthermore, by adding a first auxiliary gas to the first etching gas to remove carbon-containing polymers generated during etching, and combining this with the first fluorinated gas with a low carbon-to-fluorine ratio for etching, polymer defects formed during the passivation layer etching process are fundamentally resolved. This not only reduces the subsequent cleaning burden but also improves the performance and reliability of the formed pads without increasing process costs, thereby improving the yield of semiconductor device products. Attached Figure Description

[0030] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the defect detection results of the wafer corresponding to the pads formed by the etching gas used in the related technology.

[0032] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments.

[0033] Figure 3 This is a schematic diagram of the structure of a passivation layer before and after etching, according to some embodiments;

[0034] Figure 4This is a schematic diagram illustrating the process of changing etching process parameters according to some embodiments;

[0035] Figure 5 This is a schematic diagram of the defect detection results of the wafer corresponding to the pad formed in Embodiment 1 of this application.

[0036] Figure 6 This is a schematic diagram of the defect detection results of the wafer corresponding to the pad formed in Example 1.

[0037] Figure 7 This is a schematic diagram of the defect detection results of the wafer corresponding to the pad formed in Comparative Example 2.

[0038] In the figure, the reference numerals are as follows: 301, photoresist layer; 302, nitride dielectric layer; 303, silicon-rich oxide layer; 304, silicon oxide layer; 305, nitride dielectric layer; 306, etch stop layer; 307, metal layer; 301', etched photoresist layer; 320, opening region. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0040] The terms "an embodiment" or "embodiment" as used herein refer to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. In the description of the present invention, unless otherwise expressly specified and limited, the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein.

[0041] When a numerical range is disclosed in this application, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Further, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range such as “1 to 10” or “1~10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Specifically, exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0042] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, the layer or region will be located "below" or "under" the other layer or region.

[0043] In related technologies, dry etching and cleaning are typically used to form pads by covering a metal layer (such as aluminum) with a capping layer. However, during subsequent defect detection, densely distributed polymer defects still exist in the open area of ​​the pads on the wafer. These polymers have high adhesion to the pad area and are difficult to remove by traditional cleaning processes, reducing the performance and reliability of the pads and thus affecting the yield of semiconductor device products.

[0044] Specifically, in related technologies, dry etching is performed on capping layers, such as those on aluminum-copper alloys. The original, older process used four etching gases: C4F8 (octafluorocyclobutane), CHF3 (trifluoromethane), CF4 (carbon tetrafluoride), and O2 (oxygen). For example, during the etching stage of the oxide layer in the capping layer, the gas flow rates of C4F8, CHF3, CF4, and O2 could be 28 sccm, 100 sccm, 420 sccm, and 120 sccm, respectively. Afterward, resist removal and cleaning are performed to form pads. Finally, defect detection is performed on the wafer corresponding to the formed pads, and the wafer inspection results are as follows: Figure 1 As shown. Figure 1 This is a schematic diagram illustrating the defect detection results of the wafer corresponding to the pads formed by the etching gas used in related technologies. Figure 1 The image in the middle left is a schematic diagram of an electron scan of a wafer. Figure 1 The image on the right is an optical micrograph of a chip cell within the wafer shown in the left image. Figure 1As can be seen, there are densely distributed polymer defects in the open area of ​​the wafer pads (as circled in the right figure). The inventors discovered that these polymers are formed by the reaction of fluorine in the etching gas with aluminum in the etched area, and these aluminum-containing polymers have a high degree of adhesion to the aluminum in the pad area. This makes it difficult for conventional cleaning processes to remove these polymer areas, thus affecting the yield of semiconductor device products.

[0045] To address the aforementioned polymer defects, related technologies primarily focus on increasing polymer removal capacity. For example, increasing the removal capacity during the desizing stage by adding a gas to remove the polymer can improve this process. However, the added gas can easily corrode the electrostatic chuck (ESC), significantly shortening its lifespan and increasing production costs. Furthermore, since polymer removal capacity is determined by both the desizing and cleaning stages, fluctuations in any machine parameter can affect the final polymer removal effect, leading to low product stability.

[0046] In view of this, this application provides a method for fabricating a semiconductor device and a semiconductor device to solve the technical problems caused by polymer defects generated during dry etching in related technologies.

[0047] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments. It should be understood that the order of some of the operations described below may be interchanged. See also... Figure 2 As shown, the method for fabricating a semiconductor device includes the following steps:

[0048] In operation 202, a wafer is provided, on which an aluminum-containing metal layer and a passivation layer are formed. The passivation layer is a multilayer structure stacked sequentially on the metal layer and includes an oxide dielectric layer.

[0049] In this embodiment, the wafer can be a single-layer structure or a multi-layer structure. The material of the wafer includes one or a combination of semiconductor materials, insulating materials, and conductive materials. No specific limitations are made here regarding the structure and / or materials of the wafer.

[0050] An aluminum-containing metal layer and a passivation layer can be sequentially deposited on a wafer using a deposition process. Specifically, the metal layer can be located on the surface of the wafer to form bonding pads for metal interconnection between chips. The passivation layer is wrapped around the metal layer away from the wafer surface to provide isolation. Here, the passivation layer is a multi-layer structure stacked sequentially.

[0051] In this embodiment, the passivation layer includes at least an oxide dielectric layer. By way of example only, the material of the oxide dielectric layer may be one or more of, but not limited to, silicon oxide, silicon-rich oxide (SRO), etc. Figure 3 As shown, the oxide dielectric layer includes a silicon-rich oxide layer 303 and a silicon oxide layer 304.

[0052] Optionally, the passivation layer further includes at least one or more of nitride dielectric layers, oxide oxynitride dielectric layers, etc. For example, continuing as... Figure 3 As shown, the nitride dielectric layer 302 can be located on the surface of the oxide dielectric layer away from the metal layer 307, and the oxynitride dielectric layer 305 can be located on the surface of the oxide dielectric layer close to the metal layer 307. By way of example only, the material of the nitride dielectric layer may include, but is not limited to, silicon nitride, and the material of the oxynitride dielectric layer may include, but is not limited to, silicon oxynitride.

[0053] In operation 204, multiple sets of etching gases corresponding to the multilayer structure are used to etch the passivation layer, forming an opening area that exposes part of the metal layer.

[0054] The multiple etching gases include a first etching gas for etching the oxide dielectric layer. The first etching gas includes a first fluorine-containing gas with a low carbon-to-fluorine ratio and a first auxiliary gas. The first auxiliary gas is used to remove carbon-containing polymers generated during the etching process.

[0055] In this embodiment, during the dry etching process of the passivation layer, multiple sets of etching gases are used to etch part of the passivation layer material and part of the metal layer on the metal layer, forming a structure as shown in the example. Figure 3 The exposed portion of the metal layer 307 has an opening region 320. This opening region serves as the opening for the bonding pads, enabling metal interconnection between chips. Optionally, multiple sets of etching gases refer to etching gases comprising various different gas compositions and / or different gas flow rates. Different sets of etching gases can correspond to etching different layers of a multilayer structure. For example, for Figure 3 The passivation layer structure shown can be etched using different sets of etching gases for the nitride dielectric layer, oxide dielectric layer, and oxynitride dielectric layer. Each set of etching gases includes at least a main etching gas, which is a suitable gas that can react with the materials of the different layers being etched in the passivation layer to generate volatile gaseous products, such as a fluorine-containing etching gas.

[0056] In this embodiment, the multiple etching gases include a first etching gas for etching the oxide dielectric layer. The first etching gas includes a first fluorine-containing gas with a low carbon-to-fluorine ratio and a first auxiliary gas. Here, a low carbon-to-fluorine ratio refers to a low carbon and fluorine content. Specifically, the fluorine-containing etching gas generally includes gases such as CF4 and CHF. 3、The first etching gas may contain gases with low carbon-to-fluorine ratios, such as CH2F2 and CH3F, or gases with high carbon-to-fluorine ratios, such as C4F8, C4F6, and C5F8. Optionally, the first fluorine-containing gas in the first etching gas may be at least one gas with a low carbon-to-fluorine ratio, such as CF4 or CHF3, rather than a gas with a high carbon-to-fluorine ratio, such as C4F8.

[0057] In this embodiment, a first auxiliary gas is used to remove carbon-containing polymers generated during the etching process. Exemplarily, the first auxiliary gas is a gas capable of reducing the generation of carbon-containing polymers, such as oxygen.

[0058] In operation 206, a cleaning process is performed to clean at least the byproducts in the opening area.

[0059] In this embodiment, after the etching process is completed, a cleaning process, such as a wet process, can be performed to clean the formed opening area and the wafer, thereby removing byproducts such as residual reactants from the surface of the opening area and the wafer. For example, the cleaning agents used in the wet process may include, but are not limited to, hydrofluoric acid and sulfuric acid.

[0060] The inventors, through elemental analysis of polymer defects in related technologies, determined that the polymer was aluminum trifluoride (AlF3) formed by the reaction of fluorine in the etching gas and aluminum in the etching region. To reduce this polymer defect, the inventors focused on reducing the source of polymer formation, first considering lowering the proportion of fluorine in the etching gas. Continuing with the example of etching using four gases—C4F8, CHF3, CF4, and O2—in the original process, C4F8 contains the most fluorine atoms. Therefore, by removing the high carbon-to-fluorine ratio gas C4F8 and replacing it with a first fluorine-containing gas that has a low carbon-to-fluorine ratio, the problem of the polymer defect was solved.

[0061] In the above embodiments, by adjusting the etching gas to a first fluorinated gas with a low carbon-to-fluorine ratio and removing the fluorinated gas with a high carbon-to-fluorine ratio, aluminum-containing polymer defects formed during the passivation layer etching process can be fundamentally reduced. Furthermore, by adding a first auxiliary gas to the first etching gas to remove carbon-containing polymers generated during etching, and combining this with the first fluorinated gas with a low carbon-to-fluorine ratio for etching, the polymer defects formed during the passivation layer etching process are fundamentally solved. This not only reduces the subsequent cleaning burden but also improves the performance and reliability of the formed pads without increasing process costs, thereby improving the yield of semiconductor device products.

[0062] In some embodiments, the gas flow rate ratio of the first fluorinated gas to the first auxiliary gas is less than 4. Optionally, the gas flow rate ratio of the first fluorinated gas to the first auxiliary gas ranges from 2 to 4. More preferably, the gas flow rate ratio of the first fluorinated gas to the first auxiliary gas ranges from 2.5 to 3.5.

[0063] In the original, older process, the etching gas contained fluorine-containing gases including C4F8 (a gas with a high carbon-to-fluorine ratio), CHF3, and CF4, with oxygen as an auxiliary gas. The ratio of the total flow rate of the fluorine-containing gases (C4F8, CHF3, and CF4) to the flow rate of the auxiliary gas (oxygen) was typically greater than 4. In this embodiment, besides using a low carbon-to-fluorine ratio gas instead of a high-carbon-to-fluorine ratio gas in the first etching gas used to etch the oxide dielectric layer, the flow rate ratio between the first fluorine-containing gas and the first auxiliary gas is reduced to less than 4. This increases the proportion of the first auxiliary gas in the first etching gas, thereby reducing the residue of carbon-containing polymers after etching. According to wafer defect detection results, this embodiment, by adjusting the overall etching gas process parameters, can solve the polymer defect problem in related technologies. This further reduces the subsequent cleaning burden and improves the yield of semiconductor device products.

[0064] In some embodiments, the first fluorinated gas comprises trifluoromethane and carbon tetrafluoride. In the first etching gas, the gas flow rate ratio of trifluoromethane to carbon tetrafluoride is 5:(24-26). Exemplarily, the gas flow rate ratio can be a boundary value within 5:(24-26) or any integer or decimal value within that range. More preferably, in the first etching gas, the gas flow rate ratio of trifluoromethane to carbon tetrafluoride is 5:25.

[0065] Continuing with the example of the original process using four etching gases—C4F8, CHF3, CF4, and O2—the flow rates of CHF3 and CF4 in the corresponding etching stages are 100 sccm and 420 sccm, respectively, resulting in a flow rate ratio of 5:21. In this embodiment, the flow rate ratio of trifluoromethane to carbon tetrafluoride is 5:(24-26). Comparison shows that this embodiment increases the flow rate of carbon tetrafluoride in the first etching gas. Wafer testing results demonstrate that by removing fluorine-containing gases with high carbon-to-fluorine ratios and increasing the flow rate of carbon tetrafluoride in the first etching gas, not only can defects in the aluminum fluoride polymer be improved, but the etching rate can also be increased to meet the etching rate requirements during the etching process.

[0066] In some embodiments, the gas flow rate of carbon tetrafluoride contained in the first fluorinated gas ranges from 480 sccm to 520 sccm. As an example only, the gas flow rate of carbon tetrafluoride can be 480 sccm, 490 sccm, 495 sccm, 500 sccm, 506 sccm, 513 sccm, 518 sccm, or 520 sccm. More preferably, the gas flow rate of carbon tetrafluoride can be 500 sccm. Correspondingly, the gas flow rate of trifluoromethane contained in the first fluorinated gas ranges from 100 sccm.

[0067] In some embodiments, the first auxiliary gas includes oxygen. In the first etching gas, the gas flow rate ratio of trifluoromethane to oxygen is 10:(19-21). The gas flow rate ratio can be a boundary value within the range of 10:(19-21) or any integer or decimal value within that range. More preferably, in the first etching gas, the gas flow rate ratio of trifluoromethane to oxygen is 10:20.

[0068] Continuing with the example of the original process using four etching gases—C4F8, CHF3, CF4, and O2—the flow rates of CHF3 and O2 in the corresponding etching stages are 50 sccm and 50 sccm respectively, resulting in a flow rate ratio of 1:1. In this embodiment, the flow rate ratio of trifluoromethane to oxygen is 10:(19-21). Comparison shows that this embodiment increases the flow rate of oxygen in the first etching gas. By increasing the flow rate of oxygen in the first etching gas, the problem of introducing excessive carbon tetrafluoride and generating new carbon-containing polymers can be solved, fundamentally reducing polymer defects during the etching process.

[0069] In some embodiments, the flow rate of the first auxiliary gas ranges from 190 sccm to 210 sccm. As an example only, the flow rate of the first auxiliary gas can be 190 sccm, 192 sccm, 195 sccm, 200 sccm, 204 sccm, 208 sccm, 210 sccm, etc. More preferably, the flow rate of the first auxiliary gas can be 200 sccm.

[0070] In some embodiments, a photoresist layer is formed on the passivation layer, and the first etching gas further includes a second auxiliary gas for hardening the photoresist layer; the etching of the passivation layer using multiple sets of etching gases corresponding to the multilayer structure includes:

[0071] Using the photoresist layer as a mask, the multiple sets of etching gases are used to etch the corresponding layers in the passivation layer in stages; after etching the passivation layer, the remaining thickness of the photoresist layer is greater than a preset thickness value.

[0072] In the embodiments, continue as follows Figure 3 As shown, a photoresist layer 301 covers the passivation layer. Before etching the passivation layer, the photoresist layer can be etched to form an etching pattern. Then, using the etched photoresist layer as a mask, multiple sets of etching gases are used to etch the corresponding layer structures in the passivation layer in stages. At different stages, a single set of etching gases is used to etch the corresponding layer structures in the passivation layer. During the etching of the passivation layer, each set of etching gases also etches the remaining non-opening areas of the photoresist layer, resulting in a loss of photoresist layer thickness. A second auxiliary gas for hardening the photoresist layer is added to the first etching gas. During the etching of the passivation layer, this second auxiliary gas can harden the photoresist layer, reducing the amount of etching by the first etching gas, so that the remaining thickness of the etched photoresist layer 301' is greater than a preset thickness value. Thus, by adding a second auxiliary gas to the first etching gas, the photoresist layer is hardened in advance, ensuring the remaining thickness of the photoresist layer and better protecting the passivation layer in the non-opening areas.

[0073] When a photoresist layer is formed on the passivation layer, after etching the passivation layer, a photoresist removal process can be performed first, for example, using oxygen-containing plasma, to remove the remaining photoresist layer on the unetched passivation layer. Then, the above-mentioned cleaning process is performed to clean the by-products in the wafer and the opening area.

[0074] In some embodiments, the second auxiliary gas includes hydrogen, and the gas flow rate ratio of the second auxiliary gas to the first auxiliary gas is (1-2):(19-21). Taking oxygen as the first auxiliary gas and hydrogen as the second auxiliary gas as an example, the ratio of hydrogen to oxygen in the first etching gas can be any integer or decimal value within the boundary value or range of (1-2):(19-21). Taking a gas flow rate range of 190 sccm to 210 sccm as an example, based on this ratio range, the gas flow rate range of the second auxiliary gas can be determined to be 10 sccm to 20 sccm. For example, the gas flow rate of the second auxiliary gas can be 10 sccm, 12 sccm, 14 sccm, 15 sccm, 18 sccm, 20 sccm, etc. More preferably, the gas flow rate of the second auxiliary gas can be 18 sccm. Thus, by setting the second auxiliary gas to include hydrogen, while ensuring the hardening of the photoresist layer, the adjusted gas composition can be guaranteed to meet the performance requirements of the etched opening morphology.

[0075] In some embodiments, the preset thickness value is greater than or equal to 1000 angstroms. In this embodiment, the preset thickness value is 1000 angstroms, meaning that after etching the passivation layer, the remaining thickness of the photoresist layer is greater than 1000 angstroms.

[0076] In practical applications, taking trifluoromethane and carbon tetrafluoride as the first fluorinated gases, oxygen as the first auxiliary gas, and hydrogen as the second auxiliary gas as an example, with the trifluoromethane flow rate remaining constant, within the corresponding gas flow rate range mentioned above, increasing the carbon tetrafluoride flow rate will decrease the oxygen flow rate and increase the hydrogen flow rate. For instance, if the carbon tetrafluoride flow rate is 480 sccm, the oxygen flow rate will be 210 sccm, and the hydrogen flow rate will be 10 sccm. Conversely, if the carbon tetrafluoride flow rate is 480 sccm, the oxygen flow rate will be 190 sccm, and the hydrogen flow rate will be 20 sccm.

[0077] In some embodiments, the passivation layer further includes an etch stop layer located between the metal layer and the oxide dielectric layer; the method further includes:

[0078] After etching the passivation layer to the etching stop layer, the opening region is etched with a second etching gas to remove byproducts generated during the etching process.

[0079] In the embodiments, continue as follows Figure 3 As shown, the passivation layer also includes an oxide nitride dielectric layer 305 and an etch stop layer 306. The oxide dielectric layer 304 surrounds the surfaces of the oxide nitride dielectric layer 305, the etch stop layer 306, and the metal layer 307. The etch stop layer 306 is located between the oxide nitride dielectric layer 305 and the metal layer 307, covering the metal layer 307. This etch stop layer protects the metal layer during the etching process of the passivation layer. For example, the material of the etch stop layer may include, but is not limited to, TiN (titanium nitride). After etching the passivation layer to the etch stop layer, a second etching gas is used to etch the opening region for plasma post-etching treatment (PET). Since byproducts are formed during the etching process to form the opening region, some of these byproducts adhere to the opening region under gravity. Plasma post-etching treatment is used to remove these byproducts generated during the etching process.

[0080] In some embodiments, the second etching gas comprises a second fluorinated gas with a low carbon-to-fluorine ratio and a third auxiliary gas, wherein the gas flow rate ratio of the second fluorinated gas to the third auxiliary gas is 1:(18-20). Here, a low carbon-to-fluorine ratio refers to a low carbon and fluorine content. Specifically, fluorinated etching gases generally include CF4, CHF, etc. 3、The second etching gas can be a gas with a low carbon-to-fluorine ratio, such as CH2F2 or CH3F, or a gas with a high carbon-to-fluorine ratio, such as C4F8, C4F6, or C5F8. Optionally, the second fluorine-containing gas in the second etching gas can be at least one gas with a low carbon-to-fluorine ratio, such as CF4, CHF3, or CH2F2, rather than a gas with a high carbon-to-fluorine ratio, such as C4F8.

[0081] For example, the gas flow rate ratio of the second fluorinated gas to the third auxiliary gas is a boundary value of 1:(18-20) or any integer or decimal value within that range. More preferably, in the first etching gas, the gas flow rate ratio of trifluoromethane to carbon tetrafluoride is 1:19.

[0082] In some embodiments, the second fluorinated gas includes carbon tetrafluoride.

[0083] In some embodiments, the third auxiliary gas includes oxygen.

[0084] In some embodiments, the flow rate of the third auxiliary gas ranges from 1800 sccm to 2000 sccm. The flow rate of the third auxiliary gas can be 1800 sccm, 1800 sccm, 1800 sccm, 1800 sccm, 1800 sccm, 1800 sccm, etc. More preferably, the flow rate of the first auxiliary gas can be 1900 sccm. Correspondingly, the flow rate of carbon tetrafluoride contained in the second fluorinated gas ranges from 100 sccm.

[0085] It should be noted that in the dry etching process, the etching gases in some etching stages may include, but are not limited to, inert gases such as nitrogen and argon. Furthermore, compared to the original old process, the dry etching process in this embodiment only requires adjusting the gas composition and flow rate of the first and second etching gases, without needing to adjust other related etching process parameters in the old process. As an example only, other related etching process parameters may include: pressure of 50–400 mT, RF frequency of 200–1000 W, and ESC temperature of 15–30 °C, etc.

[0086] This embodiment reduces the number of reactive CF2+ groups by removing the fluorine-containing gas with a high carbon-to-fluorine ratio and using a fluorine-containing gas with a low carbon-to-fluorine ratio. This is because, under the same volume, temperature, and pressure conditions, the molar number of the two gases is the same (ideal gas law PV = nRT). CF4 and C4F8 molecules contain 4 and 8 F atoms, respectively. Therefore, despite having the same molar number, the number of F atoms in C4F8 gas is twice that of CF4 gas. A radio frequency electric field will ionize these molecules; the degree of ionization will depend on factors such as molecular structure, electric field strength, and temperature. However, since the number of F atoms in C4F8 molecules is twice that of CF4, if the degrees of ionization are the same, C4F8 will produce more F ions than CF4.

[0087] Experimental results show that the reduction of active CF2+ groups during the etching process and the suppression of CF4 formation of aluminum fluoride polymers are effective. Furthermore, increasing the proportions of the first and third auxiliary gases during etching removes newly formed carbon-containing polymers, addressing polymer defects at their source. Thus, by improving the composition and ratio of etching gases, the polymer defect problem can be directly solved in one step, demonstrating good technical stability.

[0088] To demonstrate the technical effect of the technical solution in this application, a comparative explanation is provided below using comparative examples.

[0089] Comparative Example 1

[0090] Comparative Example 1 illustrates dry etching of the passivation layer on a wafer using the original, outdated etching gases. Specifically, the etching gases in stage a include C4F8, CHF3, CF4, and O2, excluding H2; the etching gases in stage c include C4F8 and O2. Some etching process parameters for dry etching in Comparative Example 1 are shown in Table 1 below:

[0091] Table 1

[0092]

[0093] Among them, stage a refers to the etching stage of the oxide dielectric layer in the passivation layer, stage b refers to the etching stage of the oxynitride dielectric layer in the passivation layer, and stage c refers to the plasma etching post-processing PET stage.

[0094] Example 1

[0095] In Example 1, the first etching gas used for etching the oxide dielectric layer is a low carbon-to-fluorine ratio first fluorine-containing gas consisting of CHF3 and CF4, the first auxiliary gas is O2, and the second auxiliary gas is H2, excluding C4F8. The second etching gas is a low carbon-to-fluorine ratio second fluorine-containing gas consisting of CF4, and the third auxiliary gas is O2. Some etching process parameters for dry etching in this example are shown in Table 2 below.

[0096] Table 2

[0097]

[0098] Among them, stage a refers to the etching stage of the oxide dielectric layer in the passivation layer, stage b refers to the etching stage of the oxynitride dielectric layer in the passivation layer, and stage c refers to the plasma etching post-processing PET stage.

[0099] Example 2

[0100] The difference from Example 1 is that the flow rates of the first and second etching gases are different. The etching process parameters for dry etching in Example 2 are shown in Table 3 below:

[0101] Table 3

[0102]

[0103] Example 3

[0104] The difference from Example 1 is that the flow rates of the first and second etching gases are different. The etching process parameters for dry etching in Example 3 are shown in Table 4 below:

[0105] Table 4

[0106]

[0107] Combining Table 1-4 above and Figure 4 As can be seen, compared with the original old process of Comparative Example 1, the new process in Examples 1-3 removes the high carbon-to-fluorine ratio fluorine-containing gas C4F8 from the first etching gas in stage a, and increases the proportion of CF4 and O2, while also adding H2 to the first etching gas. In addition, in stage b, Examples 1-3 also increase the proportion of O2 in the second etching gas.

[0108] After dry etching and cleaning processes, defects were detected in Comparative Example 1 and each embodiment. Figure 1 This is the defect detection result of the wafer formed in Example 1, from... Figure 1 Both the electron scanning diagram on the left and the optical micrograph of the chip unit on the right show that the wafer prepared in Comparative Example 1 contains a large number of polymer defects. Figure 5 These are the defect detection results of the wafer formed in Example 1, from... Figure 5 Both the electron scanning schematic diagram on the left and the optical micrograph of the chip unit on the right show that the wafer prepared in Example 1 does not contain polymer defects. Furthermore, the wafer defect detection results of Examples 2 and 3 also indicate that the wafers do not contain polymer defects.

[0109] Furthermore, in order to demonstrate the technical effect of the multiple sets of etching gas flow ranges used in the embodiments of this application, the following description is based on Comparative Example 1 and Comparative Example 2.

[0110] The difference between Comparative Example 1 and Examples 1-3 is that in stage a, the etching gas flow rate of CF4 is less than 480 sccm to 520 sccm, the etching gas flow rate of O2 is less than 190 sccm to 210 sccm, and the etching gas flow rate of H2 is less than 10 sccm to 20 sccm; in stage c, the etching gas flow rate of O2 is less than 1800 sccm to 2000 sccm. Figure 6 This is a schematic diagram of the defect detection results of the wafer prepared in Comparative Example 1. As can be seen from the figure, when the flow rate range of the etching gas is reduced, some polymer defects still remain on the prepared wafer.

[0111] The difference between Comparative Example 2 and Examples 1-3 is that: in stage a, the etching gas flow rate of CF4 is higher than the range of 480 sccm to 520 sccm, the etching gas flow rate of O2 is higher than the range of 190 sccm to 210 sccm, and the etching gas flow rate of H2 is higher than the range of 10 sccm to 20 sccm; in stage c, the etching gas flow rate of O2 is higher than the range of 1800 sccm to 2000 sccm. Figure 7 The figure shows the defect detection results of the wafer prepared in Comparative Example 2. As can be seen from the figure, when the flow rate range of the etching gas is increased, some polymer defects still remain on the prepared wafer.

[0112] Experimental results show that in stage a, if the flow rate of the first auxiliary gas O2 is less than 190 sccm, new polymer defects may remain; if the flow rate of the first auxiliary gas O2 is greater than 210 sccm, the etching rate of the photoresist layer will increase, resulting in insufficient remaining thickness of the photoresist layer for protection. If the flow rate of the second auxiliary gas H2 is less than 10 sccm, the remaining thickness of the photoresist layer will be insufficient for protection; if the flow rate of the second auxiliary gas H2 is greater than 20 sccm, the hardened layer of the photoresist layer will be excessive, which is not conducive to the removal of carbon-containing polymers.

[0113] In some embodiments of this application, a semiconductor device is also provided, which is fabricated using any of the semiconductor device fabrication methods described above.

[0114] In some embodiments of this application, a chip is also provided, which includes the semiconductor device described in any of the above embodiments.

[0115] Some embodiments of this application also provide an electronic device, which includes the semiconductor device and printed circuit board (PCB) described in any of the above embodiments. The semiconductor device and the printed circuit board are electrically connected to enable signal communication.

[0116] In some embodiments, the electronic device is, for example, a consumer electronics product, a home electronics product, or an in-vehicle electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include car navigation systems and car DVDs. Of course, the electronic device can also be any intermediate product including semiconductor devices. This application does not impose any special limitations on the specific form of the above-described electronic device.

[0117] After being packaged, semiconductor devices can be used in electronic devices in the form of chips. Of course, they can also be used directly in electronic devices without packaging.

[0118] The technical effects achievable by the electronic device provided in this application are the same as those achievable by the semiconductor device described in any of the above embodiments, and will not be repeated here.

[0119] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0120] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for device, apparatus, or equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple; relevant parts can be referred to the description of the method embodiments.

[0121] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A wafer is provided, on which an aluminum-containing metal layer and a passivation layer are formed, the passivation layer being a multilayer structure sequentially stacked on the metal layer, the passivation layer including an oxide dielectric layer; Multiple sets of etching gases corresponding to the multilayer structure are used to sequentially etch the passivation layer, forming an opening region that exposes a portion of the metal layer. Perform a cleaning process to at least clean the byproducts in the opening area; The multiple etching gases include a first etching gas for etching the oxide dielectric layer. The first etching gas includes a first fluorinated gas with a low carbon-to-fluorine ratio and a first auxiliary gas. The first auxiliary gas is used to remove carbon-containing polymers generated during the etching process. Each gas in the first fluorinated gas with a low carbon-to-fluorine ratio satisfies the condition that the number of carbon atoms is 1 and the carbon-to-fluorine ratio is less than or equal to 1. The gas flow rate ratio of the first fluorinated gas to the first auxiliary gas is less than 4. The first etching gas also includes a second auxiliary gas for hardening the photoresist layer formed on the passivation layer. The gas flow rate ratio of the second auxiliary gas to the first auxiliary gas is (1-2):(19-21).

2. The method according to claim 1, characterized in that, The first fluorinated gas includes trifluoromethane and carbon tetrafluoride; in the first etching gas, the gas flow ratio of trifluoromethane to carbon tetrafluoride is 5:(24-26).

3. The method according to claim 2, characterized in that, The first auxiliary gas includes oxygen; In the first etching gas, the gas flow rate ratio of trifluoromethane to oxygen is 10:(19-21).

4. The method according to claim 3, characterized in that, The flow rate of carbon tetrafluoride contained in the first fluorine-containing gas ranges from 480 sccm to 520 sccm, and the flow rate of the first auxiliary gas ranges from 190 sccm to 210 sccm.

5. The method according to any one of claims 1-4, characterized in that, A photoresist layer is formed on the passivation layer, and the first etching gas also includes a second auxiliary gas for hardening the photoresist layer. The etching of the passivation layer using multiple sets of etching gases corresponding to the multilayer structure includes: Using the photoresist layer as a mask, the multiple sets of etching gases are used to etch the corresponding layer structures in the passivation layer in stages. After etching the passivation layer, the remaining thickness of the photoresist layer is greater than a preset thickness value.

6. The method according to claim 5, characterized in that, The second auxiliary gas includes hydrogen.

7. The method according to claim 5, characterized in that, The preset thickness value is greater than or equal to 1000 angstroms.

8. The method according to any one of claims 1-4, characterized in that, The passivation layer further includes an etch stop layer, the etch stop layer being located between the metal layer and the oxide dielectric layer; the method further includes: After etching the passivation layer to the etching stop layer, the opening region is etched with a second etching gas to remove byproducts generated during the etching process.

9. The method according to claim 8, characterized in that, The second etching gas includes a second fluorinated gas with a low carbon-to-fluorine ratio and a third auxiliary gas, wherein the gas flow rate ratio of the second fluorinated gas to the third auxiliary gas is 1:(18-20).

10. The method according to claim 9, characterized in that, The second etching gas satisfies at least one of the following: The second fluorinated gas includes carbon tetrafluoride; The third auxiliary gas includes oxygen; The flow rate of the third auxiliary gas is in the range of 1800 sccm to 2000 sccm.

11. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-10.

Images