SVPWM-based NPC common-mode voltage suppression method and system, and medium

Abstract

The invention provides an NPC common-mode voltage suppression method and system based on SVPWM and a medium, and relates to the technical field of common-mode voltage suppression, and the method comprises the steps: dividing a space vector diagram of a three-level converter into six sectors, taking a zero vector and two large vectors as basic output voltage vectors of each sector, calculating the action time through a volt-second balance principle, and calculating the action time of each sector; establishing an action sequence of an output voltage vector; performing primary optimization on the action sequence of the output voltage vector based on a phase duty ratio method; performing secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to eliminate a vector of which the generated common-mode voltage amplitude exceeds Udc / 6 by constraining a switch state combination; and generating a three-phase bridge arm driving signal. The technical problems that high switching loss is generated under certain operation conditions and the overall efficiency and stability of a system are reduced due to the fact that a modulation strategy in the prior art is often lack of sufficient optimization when common-mode voltage is processed are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of common mode voltage suppression, and in particular to a SVPWM-based NPC common mode voltage suppression method, system and medium. Background Art

[0002] Common-mode voltage refers to the voltage relative to the ground, which will generate unnecessary current in electrical equipment, causing system imbalance, reduced efficiency, equipment damage, and electromagnetic interference. In three-level converters, the generation of common-mode voltage is particularly prominent with the rapid switching of current and high-frequency switching operations. Specifically, in three-level converters, some voltage vectors will cause large common-mode voltages, especially when the output voltage is high, the amplitude of the common-mode voltage may exceed the allowable range, causing equipment damage, system instability and other problems. Existing modulation strategies often lack sufficient optimization when dealing with common-mode voltages, resulting in higher switching losses and current fluctuations under certain operating conditions, reducing the overall efficiency and stability of the system. Summary of the invention

[0003] The present application provides an NPC common-mode voltage suppression method, system and medium based on SVPWM, aiming to solve the technical problem that the modulation strategy of the prior art often lacks sufficient optimization when processing common-mode voltage, resulting in higher switching losses under certain operating conditions, thereby reducing the overall efficiency and stability of the system.

[0004] In a first aspect disclosed in the present application, a NPC common-mode voltage suppression method based on SVPWM is provided, the method comprising: dividing a three-level converter space vector diagram into six sectors, and using a zero vector and two large vectors as basic output voltage vectors for each sector, calculating the action time of each vector by the volt-second balance principle, and synchronously establishing an action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector whose three-phase output states are all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is a DC bus voltage; optimizing the action sequence of the output voltage vector once based on a phase duty cycle method; optimizing the action sequence after the primary optimization twice, wherein the secondary optimization is to exclude vectors that generate a common-mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; and generating a three-phase bridge arm drive signal according to the action sequence and action time after the secondary optimization.

[0005] The second aspect disclosed in the present application provides an NPC common-mode voltage suppression system based on SVPWM, which is used for the above-mentioned NPC common-mode voltage suppression method based on SVPWM, and the system includes: an action sequence establishment module, which is used to divide the three-level converter space vector diagram into 6 sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector through the volt-second balance principle, and synchronously establish the action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector whose three-phase output state is all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is the DC bus voltage; a primary optimization module, which is used to perform a primary optimization on the action sequence of the output voltage vector based on the phase duty cycle method; a secondary optimization module, which is used to perform a secondary optimization on the action sequence after the primary optimization, and the secondary optimization is to exclude the vector whose common-mode voltage amplitude exceeds Udc / 6 by constraining the switch state combination; a drive signal generation module, which is used to generate a three-phase bridge arm drive signal according to the action sequence and action time after the secondary optimization.

[0006] According to a third aspect disclosed in the present application, a storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the NPC common-mode voltage suppression method based on SVPWM in the first aspect are implemented.

[0007] One or more technical solutions provided in this application have at least the following beneficial effects: The spatial vector diagram of the three-level converter is divided into 6 sectors, and the action time of each output voltage vector is calculated by the volt-second balance principle, which makes the time allocation of the output voltage vector of each sector more reasonable and optimizes the timing of the three-phase output, making the output voltage waveform more stable and reducing harmonics and other undesirable voltage fluctuations; the action sequence of the output voltage vector is optimized based on the phase duty cycle method, which helps the system to avoid unnecessary switching while achieving the required output voltage, reduces the loss inside the converter, and improves the stability of the overall system; the action sequence after the primary optimization is optimized twice, and the vectors that generate the common-mode voltage amplitude exceeding Udc / 6 are excluded by constraining the switch state combination, which can effectively limit the amplitude of the common-mode voltage, thereby reducing electrical noise, equipment damage or electromagnetic interference caused by excessive common-mode voltage, and improving the reliability of the converter and the stability of the system; based on the optimized action sequence and action time, accurate three-phase bridge arm drive signals are generated to ensure that each bridge arm performs switching operations according to the optimized timing. Accurate timing control not only optimizes the voltage output, but also helps to avoid timing overlap between bridge arms, reduces current fluctuations and imbalance, and ensures the smooth operation of the electrical system.

[0008] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic flow chart of a NPC common mode voltage suppression method based on SVPWM provided in an embodiment of the present application; Figure 2 It is the spatial voltage vector diagram of the three-phase NPC three-level converter in the NPC common mode voltage suppression method based on SVPWM; Figure 3 In the NPC common mode voltage suppression method based on SVPWM, the sector Output voltage vector diagram; Figure 4 An exemplary application of an NPC three-level converter in a photovoltaic power generation system in an NPC common-mode voltage suppression method based on SVPWM; Figure 5 The sector when the phase duty ratio method is not used in the NPC common mode voltage suppression method based on SVPWM The action sequence of the internal switch states; Figure 6 In the NPC common mode voltage suppression method based on SVPWM, the phase duty cycle method is used to optimize the rear sector for the first time The action sequence of the internal switch states; Figure 7 The voltage waveform of the upper and lower capacitors on the DC side after the first optimized switching sequence is obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Figure 8 The common-mode voltage waveform of the converter after the first optimized switching sequence is obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig. 9 This is the waveform of the converter common-mode voltage amplification region after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.10 The line voltage waveform between the A-phase and B-phase bridge arms after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.11 The output current waveform of the three-level converter after the first optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.12The second optimized sector in the NPC common mode voltage suppression method based on SVPWM The action sequence of the internal switch states; Fig.13 The voltage waveform of the upper and lower capacitors on the DC side after the second optimized switching sequence is obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.14 The common-mode voltage waveform of the converter after the second optimized switching sequence is simulated in the NPC common-mode voltage suppression method based on SVPWM; Fig.15 The line voltage waveform between the A-phase and B-phase bridge arms after the second optimized switching sequence obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.16 The output current waveform of the three-level converter after the second optimized switching sequence is obtained by simulation in the NPC common-mode voltage suppression method based on SVPWM; Fig.17 A schematic diagram of the structure of an NPC common-mode voltage suppression system based on SVPWM provided in an embodiment of the present application.

[0010] Description of the reference numerals: action sequence establishing module 10 , primary optimization module 20 , secondary optimization module 30 , driving signal generating module 40 . DETAILED DESCRIPTION

[0011] The embodiments of the present application provide an NPC common-mode voltage suppression method, system and medium based on SVPWM, thereby solving the technical problem that the modulation strategies in the prior art often lack sufficient optimization when processing common-mode voltage, resulting in higher switching losses under certain operating conditions, thereby reducing the overall efficiency and stability of the system.

[0012] After introducing the basic principles of the present application, various non-limiting implementation methods of the present application will be specifically introduced below in conjunction with the accompanying drawings of the specification. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0013] Embodiment 1, as Figure 1 As shown, the embodiment of the present application provides an NPC common mode voltage suppression method based on SVPWM, the method comprising: The three-level converter space vector diagram is divided into 6 sectors, and each sector is taken as the basic output voltage vector by the zero vector and two large vectors. The action time of each vector is calculated by the volt-second balance principle, and the action sequence of the output voltage vector of each sector is synchronously established, wherein the zero vector is a voltage vector whose three-phase output state is all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is the DC bus voltage.

[0014] For the three-level converter space vector diagram, Figure 2 As shown, the entire voltage space is divided into 6 sectors, each sector represents a specific voltage output interval, these sectors are divided based on phase angle, usually divided at intervals of 60 degrees, each sector contains two large vectors and a zero vector, the large vector is a voltage vector with a modulus equal to 2Udc / 3, Udc is the DC bus voltage, in a three-level converter or other types of inverters, Udc is the input DC voltage, often provided by an external power source (such as a battery or rectifier), it affects the amplitude of the output voltage and the working performance of the system. The zero vector is a voltage vector with all three-phase output states of 0, the sector numbers are distributed in a clockwise direction, and each sector has its own specific output voltage vector, for example, Figure 3 As shown, the sector Output voltage vector diagram.

[0015] The volt-second balance principle means that in a control system, the impact of each output voltage vector on the system is balanced based on its action time. Through this principle, it can be ensured that within each sampling period, the impact of each voltage vector is proportional to the voltage amplitude. The action time of each vector is calculated based on this principle to ensure that the overall output voltage waveform of the system meets the requirements while maintaining voltage stability.

[0016] The action sequence of the output voltage vector of each sector is established synchronously, that is, the action time of each vector calculated is organized into a sequence to achieve the corresponding output voltage. The output voltage vector sequence of each sector is formed based on the aforementioned action time. The synchronization of the action sequence means that all voltage vectors will change within the same time period, thereby achieving stable output voltage control.

[0017] The action sequence of the output voltage vector is optimized based on the phase duty cycle method.

[0018] The duty cycle refers to the ratio of the time when the switch state is on to the total time in a cycle. In power electronic systems, the duty cycle directly affects the output voltage waveform. According to the principle of the phase duty cycle method, the sequence of the three switch states N, O and P can be optimized without changing the duty cycle (or action time) of the three switch states of each phase bridge arm, and the output voltage of each phase bridge arm will not be changed. After optimizing the action sequence of the three-phase bridge arm switch state, the basic output voltage vector will contain a small vector and a middle vector. Since the phase duty cycle method does not change the action time of the three switch states N, O and P of each phase, the sum of the midpoint currents generated by the optimized basic output voltage vector is consistent with that before optimization. Therefore, although the basic output voltage vector after optimization contains a small vector and a middle vector, the sum of the midpoint currents generated by them is always zero.

[0019] The action sequence after the primary optimization is subjected to secondary optimization, wherein the secondary optimization is to exclude vectors that generate common mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination.

[0020] The purpose of secondary optimization is to further reduce the amplitude of the common-mode voltage, especially to avoid the common-mode voltage amplitude exceeding Udc / 6. Udc represents the DC voltage, and Udc / 6 is one sixth of the DC voltage. The common-mode voltage refers to the average voltage of the three-phase voltage that does not belong to any phase, which usually has an adverse effect on the system's electrical equipment and control systems, especially the motor drive system.

[0021] By constraining the switch state combinations, the secondary optimization excludes voltage vector combinations that may cause the common-mode voltage amplitude to exceed Udc / 6. Specifically, this means that in the selection of voltage vectors and the arrangement of the action sequence, certain inappropriate combinations must be avoided. These combinations may cause voltage imbalance in the three-phase system and thus generate a large common-mode voltage. By setting constraints, it is ensured that in the voltage vector sequence, the combination of switch states does not cause the common-mode voltage to exceed the predetermined limit. For example, by checking the common-mode voltage amplitude of each vector combination, if the amplitude exceeds Udc / 6, the combination is excluded from the sequence, thereby ensuring that the optimized voltage vector sequence meets the system stability requirements and further suppresses the common-mode voltage to control the common-mode voltage within a safe range.

[0022] The three-phase bridge arm driving signal is generated according to the action sequence and action time after secondary optimization.

[0023] According to the action sequence and action time after secondary optimization, the output voltage vector at each moment is first determined. The output voltage vector consists of a zero vector and a large vector, where the large vector corresponds to the voltage vector of the three-phase output state of P or N. The output voltage vector at each moment determines the state that the three-phase bridge arm needs to reach. Each output voltage vector corresponds to a specific bridge arm switch combination. Through the time-duty cycle mapping table, the specific switch state of each bridge arm at each moment can be determined. According to the output voltage vector at each moment and its corresponding action time, a three-phase bridge arm drive signal within a period is generated. The drive signal controls the opening and closing of the switch according to the state of each phase bridge arm (P, O, N), ensuring that each bridge arm outputs the correct voltage vector at the correct time.

[0024] Taking the application of diode neutral point clamped (NPC) three-level converter in photovoltaic power generation system as an example, the main circuit structure of the system is as follows: Figure 4 As shown, two capacitors of equal capacitance are connected in series between the positive and negative DC busbars. and , their midpoint As the midpoint of the three-level inverter, each phase bridge arm of the inverter has four switch tubes. Taking phase A as an example, the four switch tubes are - , each switch tube is connected in anti-parallel with a freewheeling diode. - , and There are two box-position diodes connected in series in reverse parallel, which are - , and the series connection point of the two series clamping diodes is connected to the midpoint of the three-level inverter. This topology structure enables each phase to produce three levels, that is, each phase has three state outputs of P, O, and N.

[0025] When the given space voltage vector is located in sector I, such as Figure 5 As shown in the figure, the action sequence of the output voltage vector within a sampling period is given, which is composed of Figure 5 It can be seen that within one sampling period, the switch state of the A-phase bridge arm switched twice; the switch state of the B-phase bridge arm switched four times, and jumped directly from the N state to the P state; the switch state of the C-phase bridge arm switched twice. When the three-phase switch state switches between OOO and PNN, the three-phase bridge arm needs to switch the switch state at the same time, which increases the number of switch switching. In addition, when the three-phase switch state switches between PNN and PPN, the switch state of the B-phase bridge arm jumps, causing the four switch tubes on its bridge arm to switch states at the same time, increasing switch damage and failing to achieve smooth switching. In order to solve the above problems, the phase duty cycle method is used to optimize the action sequence of the output voltage vector.

[0026] After one optimization, the action sequence is as follows Figure 6 As shown by Figure 6 It can be seen that after the phase duty cycle method is adopted, within one sampling period, the switch state of phase A is adjusted to O→P→O, switching twice; the switch state of phase B is adjusted to N→O→P→O→N, switching four times; the switch state of phase C is adjusted to N→O→N, switching twice. Obviously, after optimization, the phenomenon of direct jump between the three-phase switch state from N to P state is avoided.

[0027] In order to verify the effectiveness of the proposed method, a Figure 4 The corresponding simulation model optimizes the action sequence of the output voltage vector based on the phase duty cycle method, and gives the waveforms of the upper and lower capacitor voltages, common mode voltage, bridge arm line voltage and output current, among which, Figure 7 As shown in the figure, the voltage waveform of the upper and lower capacitors on the DC side after the first optimization of the switching sequence is shown. It can be seen from the figure that the fluctuation of the upper and lower capacitor voltages is small, and the midpoint voltage remains balanced; Figure 8 As shown in Figure 1, the common-mode voltage waveform of the converter after the first optimized switching sequence is shown in Figure 2. Fig. 9 As shown in the figure, it is the waveform of the converter common-mode voltage amplification area after the first optimization of the switching sequence. It can be seen from the figure that the waveform of the common-mode voltage includes 0, ±Udc / 6 and ±Udc / 3 levels. This simulation result is consistent with the theoretical analysis; Fig.10 As shown in the figure, it is the line voltage waveform between the A-phase and B-phase bridge arms after the first optimization of the switching sequence. It can be seen from the figure that the line voltage waveform contains ±Udc, ±Udc / 2 and 0, which is consistent with the theory; Fig.11 As shown, it is the output current waveform of the three-level converter after the first optimization of the switching sequence. It can be seen from the figure that the amplitude of the output current is equal to the reference given value and the waveform quality is high.

[0028] according to Figure 6 The given action sequence of the three-phase switch states will cause the basic output voltage vector to include small vectors ONN and PPO, which should be avoided. Therefore, it is necessary to optimize the action sequence of the A, B, and C phase bridge arm switch states of sector I again. After the second optimization, the action sequence of the three-phase switch states is as follows: Fig.12 The second optimization simulation is performed on the action sequence after the first optimization, and the waveforms of the upper and lower capacitor voltages, common mode voltage, bridge arm line voltage and output current are also given. Fig.13 As shown in the figure, the voltage waveform of the upper and lower capacitors on the DC side after the second optimization of the switching sequence is shown. The fluctuation of the voltage of the upper and lower capacitors is small, and the midpoint voltage is also balanced. Fig.14 As shown in the figure, it is the common mode voltage waveform of the converter after the second optimized switching sequence. Figure 8 , Fig. 9In comparison, the waveform of the common-mode voltage only contains 0 and ±Udc / 6 levels, and the common-mode voltage value is significantly reduced. Therefore, the secondary optimization can further suppress the common-mode voltage; Fig.15 As shown in FIG. 1 , the line voltage waveform between the A-phase and B-phase bridge arms after the second optimization of the switching sequence is shown. The line voltage waveform in the figure also includes ±Udc, ±Udc / 2 and 0, which is consistent with the theory. Fig.16 The output current waveform of the three-level converter after the second optimized switching sequence is shown in Figure 2. Fig.11 The simulation results are the same, and the waveform quality is high.

[0029] Furthermore, the optimization of the action sequence of the output voltage vector based on the phase duty cycle method includes: A time-duty cycle mapping table of the PON state is established for each phase bridge arm; a level step constraint is established, and the state sequence of each phase bridge arm is symmetrically rearranged through the level step constraint, wherein the level step constraint is a constraint for confirming that the switching amplitude of adjacent states does not exceed one level step; and optimization of the symmetrical rearrangement result is performed based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered from the preset sampling period.

[0030] In order to achieve precise voltage control, it is necessary to establish a time-duty cycle mapping table for the PON state of each phase bridge arm. The function of this mapping table is to record the duty cycle of each state, that is, the proportion of time the state lasts. The duty cycle directly affects the output voltage waveform and the efficiency of the system. In the mapping table, each bridge arm state (P, O, N) will have a corresponding duty cycle value, which will show the proportion of time occupied by each state in each cycle of the system.

[0031] Specifically, first, according to the voltage output requirements of each bridge arm, the time that each state (P, O, N) should last within a sampling period is analyzed, and then a matrix or table is established to represent the PON state of each bridge arm at different time points and its corresponding duty cycle. Through these mappings, the switching time of each phase bridge arm can be accurately controlled to achieve optimized voltage output.

[0032] The level step constraint is a restriction condition used to control the switching amplitude of the voltage state. This constraint requires that when each state is switched, the voltage change amplitude between adjacent states cannot exceed one level step, that is, the voltage change amplitude does not exceed the size of a step. The level step usually refers to the change from one voltage value to another. This change limits the transition speed of each state in the system to avoid excessive current shock or voltage fluctuation due to too fast switching.

[0033] Symmetrical rearrangement refers to the reordering of the state sequence of each phase to ensure that the switching of each state meets the requirements of the level step constraint. This can ensure that the voltage change between adjacent states will not be too large, thereby preventing the system from becoming unstable due to improper switching. The rearranged sequence can ensure that the switch state changes of each phase bridge arm are smooth. Even if the state required by the system changes significantly, the switching process can remain smooth and will not cause impact on the entire power system.

[0034] Specifically, the various states and switching points of each phase during the voltage change process are first identified, and then it is checked whether each state switch will cause the voltage change between adjacent states to exceed the limit of the level step. If this happens, the order of state switching is readjusted through symmetrical rearrangement to avoid excessive voltage amplitude. The symmetrical rearrangement can use some standard rearrangement algorithms, such as the rearrangement method based on the principle of central symmetry. In this way, it is ensured that the state change of each phase is centrally symmetrical and will not produce an amplitude exceeding the level step.

[0035] The sequence symmetry constraint means that the switching moments of the three phases need to be avoided to occur simultaneously as much as possible, so as to reduce the generation of common-mode voltage and harmonic interference. By rearranging the symmetry, the switching state sequence of the three phases is adjusted so that the switching times between them are staggered as much as possible.

[0036] In order to ensure that the switching time of each phase does not overlap, according to the sequence symmetry requirements, the optimization of the symmetrical rearrangement results is performed so that the switching time point of each phase is staggered by the preset sampling period. The preset sampling period is set to at least 1 / 4 of the sampling period, which means that the switching moment of each phase must be within a sampling period and staggered as much as possible by a time interval of 1 / 4 of the period. Specifically, in the rearranged state sequence, for the state change of each phase, if the difference between its switching time and that of other phases is less than the preset 1 / 4 of the sampling period, then optimization is performed to ensure that the switching time of the three phases is staggered.

[0037] Furthermore, the time-duty cycle mapping table of the PON state is established for each phase bridge arm, including: A three-phase bridge arm state duty cycle matrix is ​​established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is ​​as follows: ; in, Characterization sector The three-phase state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

[0038] Specifically, the three-phase bridge arm state duty cycle matrix is ​​as follows: ; in, Indicates that in a specific sector The voltage state duty cycle of the inner three-phase bridge arm, Indicates the current sector number. , represents one of six sectors, each of which corresponds to a specific voltage vector region.

[0039] is the duty cycle value, which indicates the state duty cycle of each phase in the three phases. , , specifically, , , Indicates the duty cycle of phase A, phase B, and phase C in the P state during the sampling period; , , Indicates the duty cycle of phase A, phase B, and phase C in the O state during the sampling period; , , Indicates the duty ratio of phase A, phase B, and phase C in the N state during the sampling period.

[0040] , which means that the sum of the duty cycles of phases A, B, and C in a complete sampling period is 1, that is, the sum of the duty cycles of all states should be equal to 1. This constraint applies to the duty cycle of each phase.

[0041] The method for calculating the action time of each state in the sampling period is that the action time of each state (P, O, N) can be calculated by multiplying the duty cycle by the sampling period, where: yes Phase is in state during the sampling period The action time, Characterizes the duty cycle of phase X in state S during the sampling period is the sampling period.

[0042] In general, the three-phase bridge arm state duty cycle matrix By representing the duty cycle (P, O, N) of each phase in different states during the sampling period, the voltage state of the three-phase bridge arm in each sector is described. This matrix helps the control system determine the action time of each state, so that in each sampling period, the action time of each state is proportional to its duty cycle, thereby ensuring the balance and stability of the voltage output.

[0043] Furthermore, the symmetrically rearranging the state sequence of each phase bridge arm by the level step constraint includes: Generate a state sequence for each phase bridge arm, satisfying the following conditions: , ; in, Representation time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time The status value of .

[0044] Using the symmetric rearrangement algorithm to reconstruct the state sequence into a three-segment structure ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period action time.

[0045] Specifically, a state sequence is generated for each phase bridge arm, satisfying the following conditions: , ; This condition means that at any time and the moments thereafter Between, status and The difference between the two (i.e., the amplitude of state change) should be less than or equal to 1. This constraint ensures the stability of the state sequence and avoids excessive changes or jumps. It limits the amplitude of the phase state change, so that the system maintains a smooth transition within the sampling period and does not jump to the state. This condition applies to the state sequence generated by each phase bridge arm, and the purpose is to ensure a smooth transition of the state sequence within the entire time interval, that is, the change of the state should not exceed one unit step, ensuring a smooth transition of the system and avoiding excessive jumps.

[0046] The state sequence is reconstructed into a three-segment structure using the symmetric rearrangement algorithm, expressed as ,in, ,express yes This means that in the entire state sequence, is through The state order in the above example is reversed, so that the state can be mirrored at the beginning and end. The reverse operation is usually used to optimize the stability of the system, ensure smoother and more symmetrical state switching, and avoid unnecessary fluctuations. It is a constant state segment, which means that the state of the phase remains unchanged in this segment, which helps the system to remain stable in this stage and prevent current and voltage fluctuations caused by excessive state switching.

[0047] The duration is determined by and time increment The sum of the calculated express Phase is in state during the sampling period The action time, Represents half of the remaining time of the sampling period, where This increment is the sampling period, which ensures that the time allocation of each state segment is reasonable to avoid excessive state switching and instability.

[0048] Furthermore, the optimization of the symmetric rearrangement result based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered from the preset sampling period includes: Apply phase shift to the three-phase bridge arms respectively: ; in, Characterization Phase timing offset.

[0049] Optimize at the state transition point, and the optimization duration meets the following requirements: ; in, Characterization optimization time, Characterizes power device dead time.

[0050] Specifically, phase shifts are applied to the three-phase bridge arms respectively: ; For each phase, including A, B, and C, there is a time offset , the offset represents the phase The timing offset of phase A is , that is, there is no time offset; for phase B, the time offset , that is, the time of phase B is delayed compared to phase A ; For phase C, the time offset , that is, the time of phase C is delayed compared to phase A This time offset operation is used to adjust the timing relationship between phases to ensure the stable operation of the three-phase system. For example, by applying different time offsets to different phases, the switching operation of each phase can be controlled to avoid imbalance or current fluctuations caused by simultaneous switching.

[0051] Optimize at the state transition point, and the optimization duration meets the following requirements: ; Specifically, in order to prevent excessive switching or uneven symmetry of power devices during state transition, a dead time is inserted in some cases to optimize the duration. The calculation is done by taking the dead time and The larger value of is used to ensure the minimum time interval, which means that no matter how short the dead time is, the insertion time will be at least 5% of the sampling period. It refers to the time interval after turning off one device and waiting for another device to turn on to avoid short circuit or current surge. The formula ensures that the inserted dead time is at least the required time to ensure that the switching transition between devices is safe.

[0052] Furthermore, the symmetric rearrangement adopts a central symmetric mode.

[0053] Symmetrical rearrangement adopts the central symmetric mode. The central symmetric mode refers to rearrangement or adjustment on the symmetry axis of a reference point. It is usually to adjust the position of each state symmetrically on the time axis. Specifically, in the central symmetric mode, the change of a state is symmetrically distributed relative to a center point. In this mode, the center point is usually the middle point of the sampling period or the center of the voltage vector diagram. The state is adjusted symmetrically based on the center. Assuming the sampling period is , then the center point is , the state switching time of each phase is symmetrical with respect to this center point, that is, the switching time of the two phases should be relative to Symmetrical to avoid multiple phases switching at the same time, thereby reducing the voltage or current fluctuations of the system. By symmetrically distributing the switching time between the phases, it is possible to avoid too many state switching at the same time, reduce current shock, and maintain system balance.

[0054] Furthermore, the second optimization of the action sequence after the first optimization includes: Small vector combinations that disable specific states, including ; Constrain the state transfer path through the finite state machine and prohibit direct jumps between non-adjacent small vectors.

[0055] Small vector combinations refer to the fact that in a three-level converter, a specific combination of states results in small voltage vectors that may not be able to effectively control the motor or load, or may cause system instability, e.g. Equal combinations represent combinations of the same voltage direction, but they may result in reduced system efficiency or unbalanced voltage waveforms. Disable small vector combinations of specific states, including ,These small vector combinations may produce undesirable voltage waveforms, or may cause system overheating or damage in some cases. ,These specific small vector combinations are disabled through control ,strategies in order to reduce the nonlinear behavior of the system, ,avoid the generation of harmonics, and improve the reliability and efficiency of the ,system.

[0056] Finite state machine is a control mechanism based on state transition diagram, which is widely used in digital control systems. It defines each state and the corresponding state transition rules, and constrains the state transition path through the finite state machine to ensure that the transition between states is reasonable and does not violate the stability constraints of the system.

[0057] Adjacent small vectors refer to two voltage vectors that can be converted through a small change in the space vector diagram, and the transfer between them will not cause large voltage or current fluctuations; non-adjacent small vectors refer to voltage vectors with a large gap, and direct jumps may cause system instability or excessive voltage shocks. In order to ensure system stability, the state transfer path is constrained by the finite state machine, and direct jumps between non-adjacent small vectors are prohibited. Specifically, when the system needs to switch from one voltage vector to another, it must follow the adjacent state switching path, and cannot skip the intermediate state and directly transition to the distant state. Through the control algorithm, the finite state machine monitors each state transition to ensure that each state switch satisfies the constraint of adjacent small vectors. For example, if a state is a combination of P and O, the system can only transfer within the allowed state range, such as the transition between P, O, and N, but cannot jump from P to N to avoid large voltage mutations. This restriction helps to smooth the switching process and avoid current fluctuations, equipment damage, or additional electromagnetic interference caused by large voltage jumps.

[0058] Furthermore, the three-level converter space vector diagram is divided into six sectors, including: The space vector map is divided into 6 sectors at 60° intervals, and each sector consists of two adjacent large vector boundaries and a zero vector vertex. The sector numbers are distributed clockwise as follows: .

[0059] The space vector diagram is a plane graph that represents the position of the converter output voltage vector in space. For a three-level converter, the output voltage vector is distributed on a two-dimensional coordinate plane, where each voltage vector represents a specific voltage state, and the direction and size of each voltage vector determine the characteristics of the voltage output.

[0060] The space vector diagram is divided into 6 sectors at 60° intervals, which means that each sector occupies an angle range of 60°. Because the voltage vector of the three-level converter is generally evenly distributed on the space vector diagram, it is balanced to divide it into 6 sectors at 60° intervals. The sectors are divided in a clockwise direction. The boundary of each sector is composed of two adjacent large vectors and a zero vector vertex. There is a certain overlapping area between each sector, but the definition of each sector is independent.

[0061] A large vector refers to a voltage vector with a three-phase output state of P or N, which usually corresponds to a high voltage level and is the main output state of the control; a zero vector represents a three-phase voltage in a neutral state, usually when the output voltage is zero at a specific moment, and is mainly used to adjust the output waveform and balance the current and voltage in the system. The boundary of each sector is determined by the adjacent large vectors, and the zero vector connects these large vectors as a vertex, making the definition of each sector clearer and more independent.

[0062] The sectors are numbered in a clockwise direction and are distributed as follows: , each sector corresponds to a specific voltage vector combination, which is used to generate control commands, sectors From 0° to 60°, sector From 60° to 120°, and so on, the last sector (sector )From 300° to 360°, the space vector diagram is divided. Through this division, the representation of the space vector diagram is more systematic, which is helpful for the subsequent voltage vector control and optimization.

[0063] In summary, the NPC common mode voltage suppression method based on SVPWM provided in the embodiment of the present application has the following technical effects: The spatial vector diagram of the three-level converter is divided into 6 sectors, and the action time of each output voltage vector is calculated by the volt-second balance principle, which makes the time allocation of the output voltage vector of each sector more reasonable and optimizes the timing of the three-phase output, making the output voltage waveform more stable and reducing harmonics and other undesirable voltage fluctuations; the action sequence of the output voltage vector is optimized based on the phase duty cycle method, which helps the system to avoid unnecessary switching while achieving the required output voltage, reduces the loss inside the converter, and improves the stability of the overall system; the action sequence after the primary optimization is optimized twice, and the vectors that generate the common-mode voltage amplitude exceeding Udc / 6 are excluded by constraining the switch state combination, which can effectively limit the amplitude of the common-mode voltage, thereby reducing electrical noise, equipment damage or electromagnetic interference caused by excessive common-mode voltage, and improving the reliability of the converter and the stability of the system; based on the optimized action sequence and action time, accurate three-phase bridge arm drive signals are generated to ensure that each bridge arm performs switching operations according to the optimized timing. Accurate timing control not only optimizes the voltage output, but also helps to avoid timing overlap between bridge arms, reduces current fluctuations and imbalance, and ensures the smooth operation of the electrical system.

[0064] Embodiment 2 is based on the same inventive concept as the NPC common mode voltage suppression method based on SVPWM in the above embodiment. Fig.17 As shown, the embodiment of the present application provides an NPC common mode voltage suppression system based on SVPWM, and the system includes: An action sequence establishment module 10 is used to divide the three-level converter space vector diagram into 6 sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector by the volt-second balance principle, and synchronously establish the action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector whose three-phase output state is all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is the DC bus voltage; a primary optimization module 20 is used to perform a primary optimization on the action sequence of the output voltage vector based on the phase duty cycle method; a secondary optimization module 30 is used to perform a secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common-mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; a drive signal generation module 40 is used to generate a three-phase bridge arm drive signal according to the action sequence and action time after the secondary optimization.

[0065] Furthermore, the system further includes a first optimization module to perform the following operation steps: A time-duty cycle mapping table of the PON state is established for each phase bridge arm; a level step constraint is established, and the state sequence of each phase bridge arm is symmetrically rearranged through the level step constraint, wherein the level step constraint is a constraint for confirming that the switching amplitude of adjacent states does not exceed one level step; and optimization of the symmetrical rearrangement result is performed based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered from the preset sampling period.

[0066] Furthermore, the system further includes a duty cycle matrix establishment module to perform the following operation steps: A three-phase bridge arm state duty cycle matrix is ​​established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is ​​as follows: ; in, Characterization sector The three-phase state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

[0067] Furthermore, the system further includes a state sequence reconstruction module to perform the following operation steps: Generate a state sequence for each phase bridge arm, satisfying the following conditions: , ; in, Representation time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time The status value of .

[0068] Using the symmetric rearrangement algorithm to reconstruct the state sequence into a three-segment structure ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period action time.

[0069] Furthermore, the system further includes a second optimization module to perform the following operation steps: Apply phase shift to the three-phase bridge arms respectively: ; in, Characterization Phase timing offset.

[0070] Optimize at the state transition point, and the optimization duration meets the following requirements: ; in, Characterization optimization time, Characterizes power device dead time.

[0071] Furthermore, the symmetric rearrangement adopts a central symmetric mode.

[0072] Furthermore, the system further comprises a constraint module to perform the following operation steps: Small vector combinations that disable specific states, including ; Constrain the state transfer path through the finite state machine and prohibit direct jumps between non-adjacent small vectors.

[0073] Furthermore, the system further includes a sector division module to perform the following operation steps: The space vector map is divided into 6 sectors at 60° intervals, and each sector consists of two adjacent large vector boundaries and a zero vector vertex. The sector numbers are distributed clockwise as follows: .

[0074] Through the above detailed description of the NPC common-mode voltage suppression method based on SVPWM in this specification, those skilled in the art can clearly understand the NPC common-mode voltage suppression system based on SVPWM in this embodiment. Since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0075] Embodiment 3 provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, any step of embodiment 1 is implemented.

[0076] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The NPC common mode voltage suppression method based on SVPWM is characterized in that: The method comprises: The three-level converter space vector diagram is divided into 6 sectors, and each sector is used as a basic output voltage vector with a zero vector and two large vectors, the action time of each vector is calculated by the volt-second balance principle, and the action sequence of the output voltage vector of each sector is synchronously established, wherein the zero vector is a voltage vector whose three-phase output state is all 0, the large vector is a voltage vector whose modulus is equal to 2Udc / 3, and Udc is the DC bus voltage; An optimization is performed on the action sequence of the output voltage vector based on the phase duty ratio method; The action sequence after the primary optimization is subjected to secondary optimization, wherein the secondary optimization is to exclude vectors that generate a common mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; The three-phase bridge arm driving signal is generated according to the action sequence and action time after secondary optimization.

2. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The method of optimizing the action sequence of the output voltage vector based on the phase duty cycle method includes: Establish a time-duty cycle mapping table of the PON state for each phase bridge arm; Establishing a level step constraint, and symmetrically rearranging the state sequence of each phase bridge arm through the level step constraint, wherein the level step constraint is a constraint for confirming that the switching amplitude of adjacent states does not exceed one level step; The optimization of the symmetric rearrangement results is performed based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered from the preset sampling period.

3. The NPC common mode voltage suppression method based on SVPWM as claimed in claim 2, characterized in that: The time-duty ratio mapping table of establishing the PON state for each phase bridge arm includes: A three-phase bridge arm state duty cycle matrix is ​​established, and a time-duty cycle mapping table of the PON state is established according to the three-phase bridge arm state duty cycle matrix. The three-phase bridge arm state duty cycle matrix is ​​as follows: ； in, Characterization sector The three-phase state duty cycle matrix, , represents the current sector number, Characterization Phase is in state during the sampling period The duty cycle, , , and satisfies , the action time of each state is calculated as: , Characterization Phase is in state during the sampling period The action time, is the sampling period.

4. The NPC common mode voltage suppression method based on SVPWM as claimed in claim 3, characterized in that: The symmetrically rearranging the state sequence of each phase bridge arm by the level step constraint comprises: Generate a state sequence for each phase bridge arm, satisfying the following conditions: ， ； in, Representation time, Represents the total time t, Characterization Phase in time The status value of Characterizes the time interval between adjacent state switching, Characterization Phase in time The status value of Using the symmetric rearrangement algorithm to reconstruct the state sequence into a three-segment structure ,in, , is the constant state segment, ,in, , for Phase is in state during the sampling period action time.

5. The NPC common mode voltage suppression method based on SVPWM as claimed in claim 4, characterized in that: The optimization of the symmetric rearrangement result based on the sequence symmetry constraint to ensure that the three-phase switching time points are staggered from the preset sampling period includes: Apply phase shift to the three-phase bridge arms respectively: ； in, Characterization Phase timing offset; Optimize at the state transition point, and the optimization duration meets the following requirements: ； in, Characterization optimization time, Characterizes power device dead time.

6. The NPC common mode voltage suppression method based on SVPWM as claimed in claim 2, characterized in that: The symmetric rearrangement adopts a centrosymmetric mode.

7. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The second optimization of the action sequence after the first optimization includes: Small vector combinations that disable specific states, including ; The state transfer path is constrained by a finite state machine, prohibiting direct jumps between non-adjacent small vectors.

8. The NPC common mode voltage suppression method based on SVPWM according to claim 1, characterized in that: The three-level converter space vector diagram is divided into 6 sectors, including: The space vector map is divided into 6 sectors at 60° intervals, and each sector consists of two adjacent large vector boundaries and a zero vector vertex. The sector numbers are distributed clockwise as follows: .

9. The NPC common mode voltage suppression system based on SVPWM is characterized in that: For implementing the NPC common mode voltage suppression method based on SVPWM according to any one of claims 1 to 8, the system comprises: An action sequence establishment module is used to divide the three-level converter space vector diagram into 6 sectors, and use a zero vector and two large vectors as basic output voltage vectors for each sector, calculate the action time of each vector through the volt-second balance principle, and synchronously establish an action sequence of the output voltage vector of each sector, wherein the zero vector is a voltage vector whose three-phase output states are all 0, the large vector is a voltage vector whose module length is equal to 2Udc / 3, and Udc is the DC bus voltage; A primary optimization module, used for optimizing the action sequence of the output voltage vector based on the phase duty ratio method; A secondary optimization module, used for performing secondary optimization on the action sequence after the primary optimization, wherein the secondary optimization is to exclude vectors that generate a common mode voltage amplitude exceeding Udc / 6 by constraining the switch state combination; The driving signal generating module is used to generate the three-phase bridge arm driving signal according to the action sequence and action time after secondary optimization.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the NPC common mode voltage suppression method based on SVPWM according to any one of claims 1 to 8 are implemented.

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