Circuit for operating capacitive sensor and sensor device

Abstract

A circuit for operating a capacitive sensor may operate in first to third modes. The GM stage receives a sensor voltage applied on a sensor output of the capacitive sensor and outputs a current. The integrator integrates the current over a time variation and outputs the resulting output voltage. The circuit provides the output voltage to an analog-to-digital converter. In the first and second modes, the output voltage is provided to the capacitive sensor as a feedback voltage. In the first mode, offset correction is further performed in the GM stage and the integrator. In a second mode, the output of the capacitive sensor is switched on with high impedance. In a third mode, a reference voltage is provided to the capacitive sensor.

Description

Technical Field

[0001] The invention relates to a circuit and a sensor device for operating a capacitive sensor. Background Art

[0002] Capacitive sensors can be read by corresponding reading circuits. Petkov et al. "A fully differential charge-balanced accelerometer for electronic stability control", IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp. 262-270, 2014. The concept of charge balance is involved here, wherein the voltage applied to the capacitive bridge of the sensor on both sides is provided by a negative feedback loop. The front end includes an integrator for high gain, a summing amplifier for providing voltage feedback for the sensor, and a Sigma-Delta modulator for digitizing the signal into a bit stream processed by the back-end circuit. Electromagnetic interference (EMI) is reduced by chopping in such a way that the interference is distributed over the entire sampling frequency bandwidth. However, interference at the chopping frequency may be sampled back to DC and thus act in the baseband.

[0003] DE 10 2020 203 036 A1 discloses a circuit for operating a capacitive sensor, in which the boxcar sampling principle is used in order to reduce noise and electromagnetic interference exposure. Summary of the invention

[0004] The invention provides a circuit for operating a capacitive sensor and a sensor device having the features of the invention.

[0005] Preferred embodiments are listed below.

[0006] Therefore, according to a first aspect, the present invention relates to a circuit for operating a capacitive sensor, which is arranged to operate alternately in a first mode within a first time interval, in a second mode within a second time interval, and in a third mode within a third time interval. The circuit has a GM stage, which receives a sensor voltage applied to a sensor output of the capacitive sensor and outputs a current. An integrator integrates the current over a time course and outputs an output voltage resulting therefrom. The circuit provides the output voltage to an analog-to-digital converter. In the first and second modes, the output voltage is provided to the capacitive sensor. In the first mode, an offset correction is further performed in the GM stage and the integrator. In the second mode, the sensor output of the capacitive sensor is connected with high impedance. In the third mode, a reference voltage is provided to the capacitive sensor.

[0007] According to a second aspect, the present invention therefore relates to a sensor device having a capacitive sensor and a circuit according to the first aspect for operating the capacitive sensor.

[0008] Advantages of the present invention

[0009] The invention relates to a circuit for operating a capacitive sensor, which has better electromagnetic compatibility (EMC) and noise power. Here, not only the AC effect of electromagnetic interference is reduced, but also the DC effect is reduced. The circuit uses a double integration method to significantly reduce not only the DC effect of electromagnetic interference (EMI) but also the noise level of the circuit.

[0010] The circuit provides the capacitive sensor with an output voltage as a feedback voltage not only in the first time interval but also in the second time interval. The capacitive sensor is provided with a reference voltage only in the third time interval. As a result, the DC error induced by the electromagnetic interference is coupled in the second time interval and also remains in the third time interval. Therefore, the error is positively integrated in the second time interval and negatively integrated in the third time interval and is thus compensated.

[0011] The electromagnetic compatibility (EMC) performance can thereby be significantly improved and the noise level of the circuit can be reduced. The use of double integration for reducing electromagnetic interference effects and noise level of the circuit can be used in the case of different types of read circuits.

[0012] The first time interval is used for compensation of the offset and further for precharging the sensor.

[0013] According to one embodiment of the circuit, the second time interval and the third time interval have the same length. The DC error induced by the electromagnetic interference is positively integrated in the second time interval and negatively integrated in the third time interval. In the case of equal time interval lengths, the errors are compensated.

[0014] According to one embodiment, the circuit comprises a holding circuit which is designed to tap off the output voltage of the integrator and hold it as a holding voltage at an output of the holding circuit. For example, the holding circuit can have a ping-pong architecture, wherein other architectures are also possible.

[0015] According to one embodiment of the circuit, the GM stage, the integrator and the holding stage are differential circuits.

[0016] According to one embodiment of the circuit, the integrator is designed to integrate the electromagnetic interference-induced DC error with opposite signs during the second time interval and during the third time interval. This allows the error to be compensated.

[0017] In the integrator, the integration can be performed time-continuously or time-discretely. The invention is not limited to a specific integration. In particular, the integration can be performed in different architectures.

[0018] According to one embodiment of the circuit, the integrator is designed to integrate the time course of the charge state of at least one capacitor of the integrator, which is charged by the sensor current of the GM stage. In particular, DC errors can be compensated for in this case.

[0019] According to one embodiment of the circuit, the holding circuit is coupled to the capacitive sensor via a plurality of feedback switches. The feedback signal can be provided via the feedback switches.

[0020] According to one embodiment of the circuit, the sensor output of the capacitive sensor is coupled to the GM stage via a common-mode capacitor.

[0021] According to one embodiment of the circuit, the capacitive sensor is a MEMS sensor. The MEMS sensor can be, in particular, an acceleration sensor or a gyroscope.

[0022] According to one embodiment of the circuit, the integrator is designed to integrate the output current time continuously during one of the time intervals and to integrate discretely between two periods of the time interval.

[0023] According to one embodiment of the sensor device, the sensor output of the capacitive sensor is a common-mode electrode of the capacitive sensor.

[0024] According to one embodiment, the sensor device is a charge-balanced sensor device. However, other architectures are also possible, ie the sensor device does not necessarily have to be a charge-balanced sensor device.

[0025] Further advantages, features and details of the invention emerge from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 : a schematic block diagram of a sensor device according to an embodiment of the present invention; and

[0027] FIG. 2 : Circuit diagram of a sensor device according to another embodiment of the present invention.

[0028] In all the figures, identical elements and devices or those having the same function are provided with the same reference symbols. DETAILED DESCRIPTION

[0029] Figure 1 The schematic diagram of a sensor device 100 is shown, which has a circuit 1 for operating a capacitive sensor 10. Capacitive sensor 10 is a MEMS sensor, in particular an acceleration sensor or a MEMS gyroscope.

[0030] The sensor 10 has an input side and an output side, wherein the output side is coupled to the GM stage 2. The output signal of the capacitive sensor 10, here the sensor voltage, is converted into a sensor current by the GM stage 2. The output side of the GM stage 2 is coupled to the integrator 3. The output side of the integrator 3 is coupled to the input side of the holding circuit 4. The integrator 3 integrates the time variation of the charge state of the capacitor, which is charged by the sensor current of the GM stage 2. The output voltage of the integrator 3 obtained thereby is sampled, held, and provided to the output side of the holding circuit 4 as a holding voltage.

[0031] The holding voltage is provided as a feedback voltage to the capacitive sensor 10. An analog-to-digital converter 5 (such as a Sigma-Delta converter) is coupled to the output side of the holding circuit 4. The holding voltage is provided to the analog-to-digital converter 5 as an input voltage to be converted. According to another embodiment, the analog-to-digital converter 5 can be directly coupled to the integrator 3.

[0032] The holding circuit 4 holds the output signal, thereby resetting the capacitance and simultaneously maintaining the charge state of the capacitance of the capacitive sensor 10. Therefore, the sensor device 100 is a charge-balanced sensor, which ensures the charge balance of the capacitive sensor 10. According to further embodiments, architectures without charge balance are also possible.

[0033] The circuit provides the holding voltage as feedback voltage to capacitive sensor 10 in a first time interval Φ1 (ie, first mode) and in a subsequent second time interval Φ2 (ie, second mode). Furthermore, an offset correction is performed in GM stage 2 and integrator 3 in the first time interval Φ1.

[0034] In this case, in the second time interval Φ2, the output connection of the capacitive sensor 10 is high impedance, so that electromagnetic interference-induced DC errors couple in. This can be achieved by electrically coupling the output connection of the capacitive sensor exclusively via capacitance.

[0035] In a third time interval Φ3 (third mode) following the second time interval, the voltage on the output connection of the capacitive sensor 10 is processed by the GM stage 2, the integrator 3 and the holding circuit and is provided as an input voltage to be converted to the analog-to-digital converter 5. In the third time interval Φ3, the capacitive sensor 10 is provided with a reference voltage.

[0036] FIG. 2 shows a circuit diagram of a sensor device 200. The capacitive sensor 10 has a first capacitor C1 and a second capacitor C2. The first and second capacitors C1, C2 can each be a capacitor formed by a balance mass and a respective other electrode of the capacitive sensor 10. The first capacitor C1 and the second capacitor C2 are connected to form a bridge in that a contact of the first capacitor C1 is coupled to a contact of the second capacitor C2, whereby the common contact has a common potential, wherein the common contact is at the same time a sensor output 12 of the capacitive sensor 10, at which the sensor voltage of the capacitive sensor 10 is provided.

[0037] The contacts of the first capacitor C1 and the second capacitor C2 are not connected to each other, forming two input connections 11, 13 of the capacitive sensor 10. The first sensor input 11 is coupled to the sensor output 12 via the first capacitor C1, and the second sensor input 13 is coupled to the sensor output 12 via the second capacitor C2. An optional grounding capacitor Cpm connects a common potential, i.e. the sensor output 12, to the circuit ground of the sensor device 200. The grounding capacitor Cpm can be a parasitic capacitor.

[0038] The sensor inputs 11, 13 of the capacitive sensor 10 are coupled to the outputs 46a, 46b of the holding circuit 4 so as to be applied with holding voltages Von_zm1, Vop_zm1 which are held at the outputs 46a, 46b by the holding circuit 4. This is done via a plurality of feedback switches 61 to 68 which allow different voltages to be applied to the first sensor input 11 and the second sensor input 13.

[0039] The first sensor input 11 is coupled to first sides of the first feedback switch 61, the third feedback switch 63, the fifth feedback switch 65, and the seventh feedback switch 67, respectively. The second sensor input 13 is coupled to second sides of the second feedback switch 62, the fourth feedback switch 64, the sixth feedback switch 66, and the eighth feedback switch 68. The second sides of the feedback switches 61 to 68 are coupled to the outputs 46a, 46b of the holding circuit 4 and / or a voltage source generating a reference voltage, respectively, via feedback paths (not shown).

[0040] The sensor output 12 is connected to the input contact 20 of the GM stage 2 via a common mode capacitor 73 having a capacitance value Ccm and to the circuit ground AVSS via a switching element 74. Furthermore, the sensor output 12 is connected to a first input potential switch 71 and a second input potential switch 72, via which the sensor output 12 can be coupled to the output of the holding circuit 4. To this end, the sensor output 12 is coupled to the output of the holding circuit 4 via a feedback path (not shown).

[0041] The input contact 20 is coupled to a first input of the first amplifier 21 via a first capacitor to ground 75 having a capacitance value Coff_gm.

[0042] The second input of the first amplifier 21 is coupled to the circuit ground AVSS via a second grounding capacitor 76 having a capacitance value Coff_gm.

[0043] The GM stage 2, the integrator 3 and the holding circuit 4 are differential circuits having differential, i.e., two partial signal paths, which are hereinafter referred to as the first differential signal path and the second differential signal path. The first differential signal path and the second differential signal path are symmetrical to each other in the GM stage 2, the integrator 3 and the holding circuit 4, i.e., they have the same elements in the same circuit.

[0044] The first amplifier 21 is a differential transconductance amplifier. A first input of the first amplifier 21 is connected to the input contact 20 or forms the input contact 20 .

[0045] If capacitive sensor 10 provides a sensor voltage via its sensor output 12 , this sensor voltage is applied to input contacts 20 of GM stage 2 and converted into a sensor current by a first amplifier 21 .

[0046] The circuit 1 for operating the capacitive sensor 10 is configured to operate alternately in a first mode within a first time interval Φ1, in a second mode within a second time interval Φ2, and in a third mode within a third time interval Φ3. Here, the circuit 1 operates only in the first mode, the second mode, or the third mode. This means that at any point in time there is either a first time interval Φ1, a second time interval Φ2, or a third time interval Φ3. The first mode, the second mode, and the third mode are distinguished by causing a plurality of switching elements in the sensor device 100 to enter corresponding switching states. This is shown in FIG. 2 in such a way that the switching element marked as Φ1 enters a closed state in the first time interval Φ1. In a corresponding manner, the switching element indicated as Φ2 or Φ3 is caused to enter a closed state in the second time interval Φ2 or in the third time interval Φ3, respectively.

[0047] In addition, the circuit 1 is operated alternately in a first chopping time interval chop and in a second chopping time interval chopb. Both the first chopping time interval chop and the second chopping time interval chopb are divided into a first time interval Φ1, a second time interval Φ2 and a third time interval Φ3, respectively. Therefore, the first chopping time interval chop is composed of the first time interval Φ1, the second time interval Φ2 and the third time interval Φ3. In a corresponding manner, the second chopping time interval chopb is composed of the first time interval Φ1, the second time interval Φ2 and the third time interval Φ3.

[0048] This means that in the representation shown in FIG. 2 , the switching element identified with the index “chop” is switched into the closed state only during the first chopping time interval chop in the first, second or third time interval Φ1, Φ2, Φ3 shown respectively. This also means in a corresponding manner that the switching element identified with the index “chopb” is switched into the closed state only during the second chopping time interval chopb in the first, second or third time interval Φ1, Φ2, Φ3 shown respectively. If neither the index chop nor the index chopb is shown, the corresponding switching element is switched into the closed state regardless of the current chopping time interval.

[0049] Further use the following representation:

[0050] Φ_ij=(Φ_i|Φ_j)

[0051] Φ_ijchop=(Φ_i|Φ_j)&Φ_chop,

[0052] Φ_ijchopb=(Φ_i|Φ_j)&Φ_chopb,

[0053] Φ_straight=(Φ_2&Φ_chopb)|(Φ_3&Φ_chop)

[0054] Φ_cross=(Φ_2&Φ_chop)|(Φ_3&Φ_chopb)

[0055] Among them, i and j represent 1, 2 or 3 respectively, and the symbols “|” and “&” represent “or” and “and” respectively.

[0056] The first input of the first amplifier 21 is coupled to the first output of the first amplifier 21 via the first GM switch element 22a and to the first output 25a or the second output 25b of the GM stage 2 via the second GM switch element 23a or the third GM switch element 24a.

[0057] The second input of the first amplifier 21 is coupled to the second output of the first amplifier 21 via the fourth GM switch element 22b, and to the first output 25a or the second output 25b of the GM stage 2 via the fifth GM switch element 23b or the sixth GM switch element 24b.

[0058] During the switching time Φ_straight defined above, the second GM switching element 23 a and the sixth GM switching element 24 b are closed, whereas during the switching time Φ_cross defined above, the third GM switching element 24 a and the fifth GM switching element 23 b are closed.

[0059] The switching elements 23a, 23b, 24a, 24b are closed in such a way that the output signal of the GM stage 2 is integrated with opposite signs in Φ2 and Φ3.

[0060] The first output 25a of the GM stage 2 is connected to the first integrator input 30a of the integrator 3. The second output 25b of the GM stage 2 is connected to the second integrator input 30b of the integrator 3. The corresponding voltage is integrated over the time course via the integrator inputs 30a, 30b. This is done in the third time interval Φ3. The output voltage Vo obtained thereby is supplied to the outputs 35a, 35b of the integrator 3, which comprise a first output contact 35a and a second output contact 35b.

[0061] The integrator 3 comprises a second amplifier 36 which is also a transconductance amplifier. Like the first amplifier 21, the second amplifier 36 is also a differential amplifier.

[0062] A first input of the second amplifier 36 is connected to the first integrator input 30a via the first offset capacitor Coff1 of the integrator 3. A first output of the second amplifier 36 is connected to the first output contact 35a of the integrator 3. A second input of the second amplifier 36 is connected to the second integrator input 30b via the second offset capacitor Coff2 of the integrator 3. A second output of the second amplifier 36 is connected to the second output contact 35b of the integrator 3.

[0063] The first integrator input 30a of the integrator 3 is connected to the first output contact 35a via a current path, in which the first switching element 32a of the integrator and the integrator capacitor Cint1a are arranged. During the second time interval Φ2 and the third time interval Φ3, the charge (Ladung) in the first integrator capacitor Cint1a is integrated, which is obtained from the charge applied to the first integrator input 30a. In addition, the first input of the second amplifier 36 is connected to the first output contact 35a of the integrator 3 via a second current path, in which the second switching element 33a of the integrator and the first capacitor Cxx1 are arranged. In the first time interval Φ1, the second current path is activated by closing the second switching element 33a of the integrator 3.

[0064] The second integrator input 30b and the second output contact 35b of the integrator 3 are connected via a current path, in which another first switching element 32b of the integrator 3 and another integrator capacitor Cint1b are arranged. During the second time interval Φ2 and the third time interval Φ3, a charge is integrated in the other first integrator capacitor Cint1b, which is derived from the charge applied to the second integrator input 30b. In addition, the second input of the second amplifier 36 is connected to the second output contact 35b of the integrator 3 via a second current path, in which another second switching element 33b of the integrator 3 and another second capacitor Cxx2 are arranged. In the first time interval Φ1, the second current path is activated by closing the second switching element 33b of the integrator 3.

[0065] Through a current path between the input and output of the second amplifier 36 having integrator capacitors Cint1a, Cint1b and further capacitors Cxx1, Cxx2, it is possible to obtain an integrated value during the first time interval Φ1 of the integrator 3 and to carry out the integration process during a plurality of consecutive second time intervals Φ2 and third time intervals Φ3.

[0066] Furthermore, the integrator 3 comprises a first grounding switch 31a and a second grounding switch 34a in the first differential current path. The first grounding switch 31a is arranged to couple the first integrator input 30a to the circuit ground in the first time interval Φ1. The second grounding switch 34a is arranged to couple the potential on the input side of the first further capacitor Cxx1 to the circuit ground. Furthermore, the integrator 3 comprises a third grounding switch 31b and a fourth grounding switch 34b in the second differential current path. The third grounding switch 31b is arranged to couple the second integrator input 30b to the circuit ground in the first time interval Φ1. The fourth grounding switch 34b is arranged to couple the potential on the input side of the second further capacitor Cxx2 to the circuit ground.

[0067] The integrator 3 is therefore designed to integrate the voltage over its time course in the second time interval Φ2 and the third time interval Φ3 and to output the resulting output voltage Vo at the outputs 35 a and 35 b of the integrator 3 .

[0068] The first input contact 40a of the holding circuit 4 is connected to the first output contact 35a of the integrator 3. The second input contact 40b of the holding circuit 4 is connected to the second output contact 35b of the integrator 3.

[0069] The holding circuit 4 comprises a third amplifier 45 which is a differential transconductance amplifier. A first output of the third amplifier 45 is coupled to a first output contact 46a of the holding circuit 4. A second output of the third amplifier 45 is coupled to a second output contact 46b of the holding circuit 4.

[0070] The first output contact 35a of the integrator 3 is coupled to the first input or ground potential of the third amplifier 45 via the first holding switch element 44a, the first capacitor 41a and the second holding switch element 43c or the third holding switch element 42a. The first output contact 35a of the integrator 3 is further coupled to the first output contact 46a of the holding circuit 4 via the first holding switch element 44a and the fourth holding switch element 43b.

[0071] The first output contact 35a of the integrator 3 is coupled to the first input or ground potential of the third amplifier 45 via the fifth holding switch element 44b, the second capacitor 41b and the sixth holding switch element 43d or the seventh holding switch element 42b. The first output contact 35a of the integrator 3 is further coupled to the first output contact 46a of the holding circuit 4 via the fifth holding switch element 44b and the eighth holding switch element 43a.

[0072] The second output contact 35b of the integrator 3 is coupled to the second input or ground potential of the third amplifier 45 via the ninth holding switch element 44c, the third capacitor 41c and the tenth holding switch element 43e or the eleventh holding switch element 42c. The second output contact 35b of the integrator 3 is further coupled to the second output contact 46b of the holding circuit 4 via the ninth holding switch element 44c and the twelfth holding switch element 43h.

[0073] The second output contact 35b of the integrator 3 is coupled to the second input or ground potential of the third amplifier 45 via the thirteenth holding switch element 44d, the fourth capacitor 41d, and the fourteenth holding switch element 43f or the fifteenth holding switch element 42d. The second output contact 35b of the integrator 3 is further coupled to the second output contact 46b of the coupling holding circuit 4 via the thirteenth holding switch element 44d and the sixteenth holding switch element 43g.

[0074] The circuit 1 functions as follows. The input of the circuit 1 shown is formed by a capacitive sensor 10, for example, by a single core of a capacitive MEMS sensor. In the signal processing chain, the capacitive sensor 10 is first followed by a GM stage 2, then an integrator 3 and finally an optional holding circuit 4. The capacitive sensor is equivalent to a capacitive bridge. The Delta C / C concept is implemented, in which two identical and oppositely polarized voltages are applied to both sides of the capacitive bridge. The output signal of the capacitive sensor 10 is proportionally derived from the variable capacitances C1, C2 of the capacitive sensor 10.

[0075] The output signal provided at the sensor output 12 is proportional to the acceleration of the common-mode electrode and thus to the acceleration at the sensor output 12. The signal output from the capacitive sensor 10 is sampled by the GM stage 2 with a sampling time T. The output signal is integrated by the integrator 3, wherein an amplification occurs which results from the transconductance of the GM stage, the integration time and the integration capacitance.

[0076] The output voltage of the integrator 3 is transmitted to the holding circuit 4, which then provides the output voltage as a holding voltage to the capacitive sensor 10 and the analog-to-digital converter 5. The holding voltage is provided by the holding circuit 4 to the capacitive sensor 10 as a feedback voltage in the first time interval Φ1 and the second time interval Φ2.

[0077] In the following first to third time intervals Φ1 to Φ3, the updated output value of the integrator 3 is tapped. At the end of the third time interval Φ3, the holding voltage is fed back to the capacitive sensor 10 during the first and second time intervals Φ1 and Φ2 and is also provided to the input of the GM stage 2. Thus, a voltage difference of the capacitive sensor 10 can be set, wherein, depending on the existing chopping time interval, either half of the holding voltage Von_zm1, Von_zm1 is applied to the capacitive sensor 10 or half of the holding voltage Von_zm1, Von_zm1 is subtracted from the existing voltage.

[0078] 2 , the holding switch elements 42 a to 44 d are switched on or off in phases Φ_a and Φ_b. After every three phases Φ_1 to Φ_3 , Φ_a and Φ_b exchange their values ​​and are inverted.

[0079] The feedback voltage V_op, V_on provided by the holding circuit 4 during the first time interval Φ1 is also applied to the sensor 10 during the second time interval Φ2. The pre-voltage V_refp, V_refn of the reference voltage is applied only during the third time interval Φ3.

[0080] The electromagnetic interference-induced DC error is coupled in during the second time interval Φ2 and remains unchanged during the third time interval Φ3. Therefore, the error is positively integrated during the second time interval Φ2 and negatively integrated during the second time interval Φ3. In order to completely eliminate it, the second and third time intervals Φ2, Φ3 preferably have the same length. The error that occurs due to the remaining time difference between the second time interval Φ2 and the third time interval Φ3 can be reduced by random chopping, because Φ_straight and Φ_cross are also related to the phase of Φ_chop, and the error can therefore be distributed over the entire frequency spectrum.

[0081] Therefore, the DC error induced by the electromagnetic interference is positively integrated during the second time interval Φ2 and negatively integrated during the third time interval Φ3, thereby efficiently eliminating the error.

[0082] The holding voltages Von_zm, Vop_zm and the resulting output voltage Vo of the integrator 3 are also transmitted to the analog-to-digital converter 5, which digitizes the holding voltages and converts them into a bit stream. At the output of the holding circuit 4, the output voltage is equivalent to the value (ΔC / ΣC) multiplied by the positive reference voltage Vs. The integrators of the integrator 3 and the analog-to-digital converter 5, in particular when they are implemented as Σ-Δ (Sigma-Delta) modulators, perform offset correction.

Claims

1. A circuit (1) for operating a capacitive sensor (10), the circuit being arranged to operate alternately in a first mode within a first time interval (Φ1), in a second mode within a second time interval (Φ2), and in a third mode within a third time interval (Φ3), the circuit comprising: a GM stage (2) configured to receive a sensor voltage applied to a sensor output (12) of the capacitive sensor (10) and output a current; and an integrator (3) configured to integrate the output current over a time course and output an output voltage resulting therefrom; in, The circuit (1) is configured to provide the output voltage to an analog-to-digital converter (5); wherein the circuit (1) is configured to provide the output voltage to the capacitive sensor (10) as a feedback voltage in a first mode and in a second mode; wherein the circuit (1) is further configured to perform, in a first mode, an offset correction in the GM stage (2) and the integrator (3); The circuit (1) is further designed to connect the sensor output (12) of the capacitive sensor (10) with high impedance in a second mode, and The circuit (1) is further configured to provide a reference voltage to the capacitive sensor (10) in a third mode.

2. The circuit (1) according to claim 1, wherein: The second time interval (Φ2) and the third time interval (Φ3) have the same length.

3. The circuit (1) according to claim 1 or 2, wherein: The integrator (3) is configured to integrate the electromagnetic interference induced DC error with opposite signs during the second time interval (Φ2) and during the third time interval (Φ3).

4. The circuit (1) according to any one of the preceding claims, wherein: The integrator (3) is designed to integrate over the course of time a charge state of at least one capacitor of the integrator (3), which capacitor is charged by the sensor current of the GM stage (2).

5. The circuit (1) according to any one of the preceding claims further comprises a holding circuit (4), which is configured to tap the output voltage of the integrator (3), hold it at an output part (46a, 46b) of the holding circuit (4) as a holding voltage (Von_zm1, Vop_zm1), and provide it to an analog-to-digital converter (5) and a capacitive sensor (10).

6. The circuit (1) according to claim 5, wherein: The holding circuit (4) is coupled to the capacitive sensor (10) via a plurality of feedback switches (61 to 68).

7. The circuit (1) according to claim 5 or 6, wherein: The GM stage (2), the integrator (3) and the holding circuit (4) are differential circuits.

8. The circuit (1) according to any one of the preceding claims, wherein: The sensor output part (12) of the capacitive sensor (10) is coupled to the GM stage (2) via a common mode capacitor (73).

9. The circuit (1) according to any one of the preceding claims, wherein: The integrator (3) is designed to integrate the output current continuously during one of the time intervals (Φ1, Φ2, Φ3) and to integrate the output current discretely between two periods of the time interval (Φ1, Φ2, Φ3).

10. A sensor device (100; 200) having a capacitive sensor (10); and A circuit (1) for operating the capacitive sensor (10) according to any of the preceding claims.

11. The sensor device (100; 200) according to claim 10, wherein: The sensor output part (12) of the capacitive sensor (10) is a common mode electrode of the capacitive sensor (10).

12. The sensor device (100; 200) according to claim 10 or 11, wherein: The capacitive sensor (10) is a MEMS sensor, in particular an acceleration sensor or a gyroscope.

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