Network time synchronization method and device based on key path delay elimination

Abstract

The invention provides a network time synchronization method and device based on key path delay elimination, and relates to the technical field of wireless communication network time synchronization. According to the method, timestamp data pairs are obtained through bidirectional communication between nodes, logic clock drift, logic clock skew and estimated delay are calculated, the logic clock skew and the estimated delay are compared, and if the estimated delay is smaller than the logic clock skew, the logic clock drift and the logic clock skew are corrected at the same time; otherwise, only the logic clock skew is corrected, the synchronization accumulative error is effectively reduced, and the expansibility of the time synchronization algorithm is enhanced; the method solves the problems that a traditional system node time-frequency synchronization method is low in expansibility and poor in robustness, and the problems of time-frequency synchronization accumulated errors, time information data packet loss and the like cannot be overcome in a complex wireless channel, so that the time-frequency synchronization precision is low, the positioning service accuracy and reliability are difficult to guarantee, and the actual scene service requirements cannot be met. According to the method, the robustness of a time synchronization algorithm is improved.

Description

Technical Field

[0001] This document relates to the technical field of wireless communication network time synchronization, and in particular to a network time synchronization method and device based on critical path delay elimination. Background Art

[0002] In view of the characteristics of urban environments such as complex noise interference, large system scale, and poor wireless channel stability when satellites are denied, the traditional system node time and frequency synchronization method has low scalability and poor robustness. It is unable to overcome problems such as cumulative time and frequency synchronization errors and time information data packet loss in complex wireless channels, resulting in low time and frequency synchronization accuracy, difficulty in ensuring the accuracy and reliability of positioning services, and inability to meet actual business needs.

[0003] Therefore, it is urgent to propose a time synchronization method to solve the problems of low scalability and poor robustness of traditional system node time and frequency synchronization methods, and the inability to overcome the problems of cumulative time and frequency synchronization errors and time information data packet loss in complex wireless channels, resulting in low time and frequency synchronization accuracy, difficulty in ensuring the accuracy and reliability of positioning services, and inability to meet the business needs of actual scenarios. Summary of the invention

[0004] This specification provides a network time synchronization method based on critical path delay elimination, which is used to solve the problems of low scalability and poor robustness of traditional system node time and frequency synchronization methods, and the inability to overcome the problems of cumulative time and frequency synchronization errors and time information data packet loss in complex wireless channels, resulting in low time and frequency synchronization accuracy, difficulty in ensuring the accuracy and reliability of positioning services, and inability to meet the business needs of actual scenarios.

[0005] In a first aspect, this specification provides a network time synchronization method based on critical path delay elimination, comprising:

[0006] Based on the critical path, nodes obtain timestamps by bidirectionally exchanging time information packets;

[0007] Calculate the propagation delay based on the acquired timestamp, and use the propagation delay and timestamp to construct a timestamp data pair at the same time point;

[0008] According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two;

[0009] Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated using the least square method;

[0010] Determining an estimated delay of the node to be synchronized based on the timestamp data pair;

[0011] The logical clock offset and the estimated delay are compared. If the estimated delay is smaller than the logical clock offset, both the logical clock drift and the logical clock offset are corrected. Otherwise, only the logical clock offset is corrected.

[0012] In a second aspect, the present specification provides a network time synchronization device based on critical path delay elimination, a timestamp acquisition module, a timestamp data pair construction module, a model building module, a logical clock offset estimation module, an estimated delay determination module, and a delay elimination module; wherein:

[0013] The timestamp acquisition module is used for nodes to acquire timestamps by bidirectionally exchanging time information data packets based on the critical path;

[0014] The timestamp data pair construction module is used to calculate the propagation delay according to the acquired timestamp, and construct the timestamp data pair at the same time point using the propagation delay and the timestamp;

[0015] The model building module is used to build a linear relationship model between the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized according to the two;

[0016] The logic clock offset estimation module is used to estimate the logic clock drift and the logic clock offset based on the linear relationship model by using the least square method;

[0017] The estimated delay determination module is used to determine the estimated delay of the node to be synchronized according to the timestamp data pair;

[0018] The delay elimination module is used to compare the size of the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, the logical clock drift and the logical clock offset are corrected at the same time; otherwise, only the logical clock offset is corrected.

[0019] In a third aspect, this specification also provides a network device, including: a communication interface, a processor, and a memory;

[0020] The processor calls the program instructions in the memory to perform the following actions:

[0021] Based on the critical path, nodes obtain timestamps by bidirectionally exchanging time information packets;

[0022] Calculate the propagation delay based on the acquired timestamp, and use the propagation delay and timestamp to construct a timestamp data pair at the same time point;

[0023] According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two;

[0024] Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated using the least square method;

[0025] Determining an estimated delay of the node to be synchronized based on the timestamp data pair;

[0026] The logical clock offset and the estimated delay are compared. If the estimated delay is smaller than the logical clock offset, both the logical clock drift and the logical clock offset are corrected. Otherwise, only the logical clock offset is corrected.

[0027] The beneficial effects of the present invention are as follows:

[0028] The present specification provides a network time synchronization method and device based on critical path delay elimination. The method obtains timestamp data pairs through two-way communication between nodes, and calculates logical clock drift, logical clock offset and estimated delay; compares the size of logical clock offset and estimated delay, if the estimated delay is less than the logical clock offset, corrects the logical clock drift and logical clock offset at the same time; otherwise, only corrects the logical clock offset, effectively reduces the synchronization cumulative error, and enhances the scalability of the time synchronization algorithm; the method meets the large-scale deployment requirements of wireless positioning systems, improves the robustness of the time synchronization algorithm, and achieves a time synchronization accuracy of less than 3ns for the four indicators of maximum network error, maximum neighbor node error, average network error and hop-by-hop average network error while ensuring that the system calculation complexity meets the hardware requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0030] Figure 1 It is a schematic diagram of a network time synchronization method based on critical path delay elimination provided in an embodiment of this specification;

[0031] Figure 2 It is a schematic diagram of a network time synchronization method process based on critical path delay elimination provided in an embodiment of this specification;

[0032] Figure 3 It is a schematic diagram of a wireless synchronization system solution framework provided in an embodiment of this specification;

[0033] Figure 4 It is a schematic diagram of a PMF-FFT acquisition algorithm process provided in an embodiment of this specification;

[0034] Figure 5 It is a schematic diagram of a frequency precise search algorithm process provided in an embodiment of this specification;

[0035] Figure 6 It is a schematic diagram of a TC-OFDM tracking loop block diagram provided in an embodiment of this specification;

[0036] Figure 7 It is a schematic diagram of a synchronization mechanism of an RCPDE time synchronization algorithm provided in an embodiment of this specification;

[0037] Figure 8 It is a schematic diagram of a wireless synchronization simulation verification condition framework provided in an embodiment of this specification;

[0038] Fig. 9 It is a schematic diagram of a spread spectrum code tracking TOA result provided in an embodiment of this specification.

[0039] Fig.10 It is a schematic diagram of a network time synchronization method and device based on critical path delay elimination provided in an embodiment of this specification;

[0040] Fig.11 It is a schematic diagram of a network device structure provided in an embodiment of this specification. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and their corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this document.

[0042] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings. Specific embodiment one:

[0044] This embodiment provides a network time synchronization method based on critical path delay elimination. Figure 1-Figure 9 ;

[0045] It should be noted that in the time-frequency synchronization method, nodes calculate clock offsets by exchanging time information packets with timestamps and adjust local clocks to achieve time synchronization. However, when sending and receiving data packets, nodes will send and receive data packets layer by layer according to the computer network structure, resulting in the sending timestamp being less than the actual sending time and the receiving timestamp being greater than the actual receiving time, which affects the accuracy of time synchronization.

[0046] In order to improve the time synchronization accuracy, this method defines the data packet transmission path between two nodes as the critical path, and introduces six delays including sending delay, access delay, transmission delay, propagation delay, receiving delay and acceptance delay;

[0047] The delay in the process of sending and receiving data packets can be divided into uncertain delay and deterministic delay.

[0048] The signal system adopted in this embodiment records the timestamp at the physical layer to eliminate the influence of uncertain delays such as sending delay, access delay and receiving delay during signal transmission; the deterministic delay is eliminated by calculating the time-frequency synchronization algorithm. This embodiment proposes a large-scale highly robust network time-frequency synchronization algorithm based on critical path delay elimination for time-frequency synchronization;

[0049] The working principle of the algorithm proposed in this embodiment is:

[0050] First, the logical clock drift and logical clock offset are calculated using the least squares method through the timestamp information. Secondly, the error caused by antenna delay, first path delay, etc. is compensated by the logical clock drift correction control mechanism. and the estimated delay σ max,i If the estimated delay σ max,i Smaller than the logical clock offset Then both the logical clock drift and the logical clock offset are corrected; otherwise, only the logical clock offset is corrected.

[0051] Specifically, the algorithm proposed in this embodiment includes the following specific steps:

[0052] Step 102: Based on the critical path, the node obtains a timestamp by bidirectionally exchanging time information data packets;

[0053] like Figure 7 As shown in the figure, the i-1 layer node is the reference node, and the i layer node is the node to be synchronized. The node to be synchronized obtains the timestamp by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at the moment;

[0054] Based on this, a bidirectional exchange of data packets is used to obtain timestamps to ensure that the propagation delay in the critical path can be eliminated to the greatest extent.

[0055] Step 104: Calculate the propagation delay according to the acquired timestamp, and construct a timestamp data pair at the same time point using the propagation delay and the timestamp;

[0056] In this embodiment, the timestamp data is specifically: (k is a positive integer, i is a positive integer greater than 1);

[0057] The test point is Send the slave time information packet to the node to be synchronized at this moment. Assume that the clock value of the node to be synchronized at this moment is but:

[0058]

[0059] Where Δt is the propagation delay, which is expressed as:

[0060] Formula (1) can be rewritten as:

[0061] Step 106: construct a linear relationship model between the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized;

[0062] It should be noted that the reference node is The slave time information packet is sent to the node to be synchronized at this moment. The clock value of the node to be synchronized at this moment is

[0063] in,

[0064] Wherein, the linear relationship model includes:

[0065] Among them, α i is the logical clock drift of the node to be synchronized, β i It is the logical clock offset of the node to be synchronized.

[0066] Step 108: Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated by using the least square method;

[0067] Specifically, a specific implementation of step 108 is:

[0068] S81. Define the following matrix AX=B;

[0069] in:

[0070] S82. Solve the estimated value using the least squares method Estimate logical clock drift Logical clock offset

[0071] The node to be synchronized is calculated based on and According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two to correct its own hardware clock;

[0072] Step 110: Determine the estimated delay of the node to be synchronized according to the timestamp data pair;

[0073] Among them, the estimated delay σ of the node to be synchronized max,i , expressed as:

[0074] Among them, O k,i , O k-1,i They represent the clock offsets of the nodes to be synchronized at the kth and k-1th data packet exchanges respectively;

[0075] Specifically,

[0076] It should be noted that the linear relationship model between the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized is usually For the time-frequency synchronization error caused by antenna delay, first path delay, etc., α i =1, the offset error of the node to be synchronized:

[0077]

[0078] Among them, O k,i It represents the clock offset of the node to be synchronized at the kth data packet exchange. If the data packet exchange is performed periodically and the clock drift of the two adjacent nodes remains unchanged in multiple cycles, and The difference should be a constant. Then the difference in the offset error of the reference node in two consecutive timestamp data pairs is O k,i -O k-1,i It should also be a constant. Due to the inevitable existence of delay, O k,i -O k-1,i The value of is changing, and formula (2) becomes:

[0079]

[0080] Among them, σ k,i represents the uncertain delay of the i-level node during the k-th data packet exchange. Although σ k,i The value of will change every time, but σ k,i The maximum value of can be calculated by the following formula:

[0081] Step 112: compare the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, correct both the logical clock drift and the logical clock offset. Otherwise, only correct the logical clock offset.

[0082] After each time the timestamp is collected, the logical clock offset is determined, the delay is estimated, and a comparison is performed, and corrections are made based on the comparison results.

[0083] 1.2 Wireless time and frequency synchronization simulation verification

[0084] Wireless environment verification equipment block diagram, such as Figure 8 As shown;

[0085] The simulation results of wireless time-frequency synchronization are shown in Table 1 below:

[0086] Table 1 Wireless time-frequency synchronization simulation results

[0087]

[0088] From the simulation results in Table 1, it can be seen that the wireless synchronization accuracy of the simulation data is about 0.2ns, and the maximum difference is 0.26ns; adding noise (10dB) has little effect on the results; the code chip (1chip) offset and frequency deviation (10HZ) have little effect on the wireless synchronization time measurement results.

[0089] In the simulation verification scenario, X310-1 was used to transmit code 4, and the TOA value after X310-2 tracked code 4 was recorded (multiple acquisition records), with an average of 712ns and a standard deviation of 0.19ns; then X310-1 was restarted to transmit, and the TOA value tracked by X310-2 was re-recorded (multiple acquisition records), with an average of 711ns and a standard deviation of 0.16ns; exchange radiation verification, X310-2 transmitted code 1, and the TOA value after X310-1 tracked code 1 was recorded (multiple acquisition records), with an average of 709ns and a standard deviation of 0.36ns; X310-2 was restarted to transmit, and the TOA value of X310-1 tracking code 1 was re-recorded (multiple acquisition records), with an average of 710ns and a standard deviation of 0.24ns. The test details are recorded in the following table:

[0090] Through simulation verification scenario testing, it is analyzed that TOA delay mainly comes from the delay of the transmitting end hardware link, the delay of the 1pps feeder and the antenna feeder, the delay of the wireless signal air interface, and the delay of the receiving end hardware link. The device is restarted and the exchange transmission test is verified. Fig. 9 ,Table 2,The results show that the maximum standard deviation of tracking TOA is 0.36ns, which is much smaller than 3ns. After restarting and switching transmission, TOA has a certain change, and the difference between the maximum and minimum values ​​is 3ns. This error mainly comes from the consistency of hardware equipment, so the consistency requirements of hardware equipment should be higher in the subsequent development of wireless synchronization equipment products.

[0091] Table 2 Spread spectrum code tracking TOA result data table

[0092]

[0093]

[0094] To summarize, this embodiment obtains timestamp data pairs through bidirectional communication between nodes, calculates logical clock drift, logical clock offset and estimated delay, compares the size of logical clock offset and estimated delay, and if the estimated delay is smaller than the logical clock offset, corrects both the logical clock drift and the logical clock offset; otherwise, only corrects the logical clock offset, effectively reducing the cumulative synchronization error and enhancing the scalability of the time synchronization algorithm; this method meets the needs of large-scale deployment of wireless positioning systems, improves the robustness of the time synchronization algorithm, and achieves a time synchronization accuracy of less than 3ns for the four indicators of maximum network error, maximum neighbor node error, average network error and hop-by-hop average network error while ensuring that the system computational complexity meets the hardware requirements. Specific embodiment 2:

[0096] This embodiment proposes a large-scale highly robust network time synchronization method based on critical path delay elimination, see Figure 2 ; Specifically include the following:

[0097] 1.1 Analysis of factors affecting time-frequency synchronization accuracy

[0098] First, the factors affecting time-frequency synchronization are classified. In the time-frequency synchronization method, nodes calculate the clock offset by exchanging time information packets with timestamps and adjust the local clock to achieve time synchronization. However, when sending and receiving data packets, nodes will send and receive data packets layer by layer according to the computer network structure, resulting in the sending timestamp being less than the actual sending time and the receiving timestamp being greater than the actual receiving time, which affects the accuracy of time synchronization.

[0099] To improve the time synchronization accuracy, this embodiment defines the data packet transmission path between two nodes as a critical path, and introduces six types of delays, including sending delay, access delay, transmission delay, propagation delay, receiving delay, and acceptance delay:

[0100] (1) Sending delay is the time it takes for the application layer to construct a data packet and send it to the MAC. It is usually affected by system calls and is an uncertain delay.

[0101] (2) Access delay is the time that a data packet spends waiting at the MAC layer for the wireless channel to be idle. It is related to the load of the wireless network and the MAC layer protocol used by the wireless network and is an uncertain delay.

[0102] (3) Transmission delay is the time it takes for the MAC layer to encode the data packet according to the frame structure, add the physical layer data header and checksum, and send the data packet bit by bit to the wireless channel. It is a deterministic delay and can be calculated based on the data packet size and data transmission rate.

[0103] (4) Propagation delay is the time it takes for an information packet to be transmitted from the sender to the receiver through the wireless channel. It depends on the node spacing and is calculated based on the node spacing and radio propagation speed. It is a deterministic delay.

[0104] (5) Receive delay is the time it takes for the receiver to receive a data packet bit by bit, pass the data packet to the MAC layer, and decode and verify the data packet. It is a deterministic delay.

[0105] (6) Receiving delay: This part of the delay is the time it takes to pass the data packet from the MAC layer to the application layer. Similar to the sending delay, it is affected by system calls and operating system load and is an uncertain delay.

[0106] The delay in the process of sending and receiving data packets can be divided into uncertain delay and deterministic delay.

[0107] The signal system adopted in this embodiment records the timestamp at the physical layer to eliminate the influence of uncertain delays such as sending delay, access delay and receiving delay during signal transmission; the deterministic delay is eliminated through the calculation of the time-frequency synchronization algorithm. The project intends to propose a large-scale and highly robust network time-frequency synchronization algorithm based on critical path delay elimination to perform time-frequency synchronization, correct logical clock drift and logical clock offset, improve the accuracy of time-frequency synchronization, and compress the time synchronization accuracy to 3ns.

[0108] Furthermore, this embodiment provides a high-precision time-frequency synchronization algorithm based on critical path delay elimination;

[0109] The algorithm of this embodiment is described in detail below:

[0110] (1) Transmission delay measurement method

[0111] The measurement method of critical path transmission delay adopts the capture, frequency search, tracking and telegram technology under the TC-OFDM signal system. Figure 3 ;

[0112] The signal is captured using PMF-FFT. The capture strategy can be configured according to the actual scenario: 1ms integration, 5ms coherent integration, and 5ms+n times incoherent integration. For the PMF-FFT capture algorithm flow, see Figure 4 ;

[0113] Specifically, taking 1ms integral capture-fine synchronization as an example, after completing the coarse capture of PMF-FFT, enter the 1ms frequency fine synchronization, perform frequency search according to the configured frequency search step and interval, and record the coherent peak of the local code and data code. The peak position corresponds to the frequency deviation value of the frequency fine search. For the frequency fine search algorithm flow, see Figure 5 ;

[0114] The tracking module completes the carrier and pseudo code phase tracking of the pseudo code. The I / Q data after RF sampling is compensated for the frequency offset in the complex domain, and the integral is cleared by the leading, lagging and instant codes. Among them, the integral results of the leading and lagging paths are sent to the phase detector of the DLL (DelayLock Loop), and the phase detection results are converted into code NCO control words after loop filtering. The code NCO phase is adjusted in real time to complete the pseudo code tracking; and the instant path signal is sent to the phase-locked loop (PLL) to complete the frequency pulling and carrier phase tracking. The phase tracking result is converted into a frequency control word, and the carrier NCO phase is adjusted in real time to complete the carrier tracking; TC-OFDM tracking loop frame, see Figure 6 .

[0115] The positioning signal can be divided into three levels in structure: carrier, spread spectrum code and data code. The carrier is the bottom layer, and the spread spectrum code and data code are attached to the sine and cosine carrier through modulation. The telegram corresponds to the data code. The rate of the telegram symbol is 100sps. The telegram information mainly includes the frame synchronization header, spread spectrum code number, telegram type, health status, signal measurement time information, coding information, CRC check, etc.

[0116] (2) Calculate logical clock drift and logical clock offset

[0117] First, the node performs two-way communication to obtain and These four timestamps are then used to calculate the propagation delay, and then the propagation delay and timestamp are used to construct the timestamp data pair at the same time point. Next, use the timestamp data to Calculate the logical clock drift Logical clock skew and the estimated delay σ max,i , and finally compare the logical clock offset and the estimated delay σ max,i If the estimated delay σ max,i Smaller than the logical clock offset Then both the logical clock drift and the logical clock offset are corrected; otherwise, only the logical clock offset is corrected.

[0118] exist Figure 7 In the example, the i-1 layer node is the reference node, and the i layer node is the node to be synchronized. The node to be synchronized obtains the timestamp by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at time t, so far, the node to be synchronized has collected four timestamps.

[0119] The purpose of using a bidirectional exchange of data packets to obtain timestamps is to eliminate the propagation delay in the critical path to the greatest extent possible. Figure 7 As shown, the reference node is Send the slave time information packet to the node to be synchronized at this moment. Assume that the clock value of the node to be synchronized at this moment is but:

[0120]

[0121] Where Δt is the propagation delay, which is expressed as:

[0122] Formula (1) can be rewritten as:

[0123] According to the clock model and the relationship between the two node clocks, the reference node maintains the synchronized clock value A linear relationship can be established with the clock value of the node to be synchronized:

[0124] Among them, α i is the logical clock offset of the node to be synchronized, β i It is the logical clock drift of the node to be synchronized.

[0125] Observing formula (2), we can see that the node to be synchronized can be solved by i and β i The value of is used to correct the hardware clock to complete time synchronization. Define the following matrix:

[0126]

[0127] According to formula (2), the relationship between the three matrices is: AX = B;

[0128] Use the least squares method to estimate the unknown parameters is to make The sum of squares of the residuals of A and B is the smallest, that is:

[0129]

[0130] In such a situation The best fit with B is the highest time synchronization accuracy. Simplifying formula (3) we get:

[0131] (||AX-B||2) 2 =X T A TAX-B T AX-X T A T B+B T B (5)

[0132] The derivative of formula (4) with respect to X is:

[0133]

[0134] When the left side of (5) is zero (the derivative is zero), X has a minimum value, and the estimated value of X is obtained by solving for:

[0135]

[0136] The node to be synchronized is calculated based on and Correct its own hardware clock according to formula (2) to complete time synchronization.

[0137] (3) Logical clock drift correction control mechanism

[0138] Use timestamp data pairs Calculate the estimated delay, the offset error of the node to be synchronized is:

[0139] Among them, O k,i It represents the clock offset of the node to be synchronized at the kth data packet exchange. If the data packet exchange is performed periodically and the clock drift of the two adjacent nodes remains unchanged in multiple cycles, and The difference should be a constant. Then the difference in the offset error of the reference node in two consecutive timestamp data pairs is O k,i -O k-1,i It should also be a constant. Due to the inevitable delay, O k,i -O k-1,i The value of is changing, and formula (2) becomes formula (3);

[0140] Although k,i The value of will change every time, but σ k,i The maximum value of can be calculated by the following formula:

[0141]

[0142] The logical clock offset and the estimated delay are compared. If the estimated delay is smaller than the logical clock offset, both the logical clock drift and the logical clock offset are corrected. Otherwise, only the logical clock offset is corrected.

[0143] To summarize, this embodiment obtains timestamp data pairs through two-way communication between nodes, calculates logical clock drift, logical clock offset and estimated delay, performs time and frequency calibration according to the calculation results, effectively reduces the cumulative synchronization error, and enhances the scalability of the time synchronization algorithm; this method meets the needs of large-scale deployment of wireless positioning systems, improves the robustness of the time synchronization algorithm, and achieves time synchronization accuracy of less than 3ns for the four indicators of maximum network error, maximum neighbor node error, average network error and hop-by-hop average network error while ensuring that the system calculation complexity meets the hardware requirements. Specific embodiment three:

[0145] This embodiment provides a network time synchronization device based on critical path delay elimination. Fig.10 , including: a timestamp acquisition module 1001, a timestamp data pair construction module 1002, a model building module 1003, a logical clock offset estimation module 1004, an estimated delay determination module 1005, and a delay elimination module 1006; wherein:

[0146] The timestamp acquisition module 1001 is used for obtaining timestamps by bidirectionally exchanging time information data packets based on the critical path.

[0147] The timestamp data pair construction module 1002 is used to calculate the propagation delay according to the acquired timestamp, and construct the timestamp data pair at the same time point using the propagation delay and the timestamp;

[0148] The model building module 1003 is used to build a linear relationship model between the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized according to the two.

[0149] The logic clock offset estimation module 1004 is used to estimate the logic clock drift and logic clock offset based on the linear relationship model by using the least square method;

[0150] The estimated delay determination module 1005 is used to determine the estimated delay of the node to be synchronized according to the timestamp data pair;

[0151] The delay elimination module is used to compare the size of the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, the logical clock drift and the logical clock offset are corrected at the same time; otherwise, only the logical clock offset is corrected.

[0152] Optionally, the critical path refers to a path for transmitting data packets between two nodes;

[0153] The delay in the process of sending and receiving data packets can be divided into uncertain delay and deterministic delay;

[0154] The uncertain delay includes: sending delay, access delay and receiving delay;

[0155] Determine delays, including transmission delay, propagation delay, and reception delay;

[0156] Record timestamps at the physical layer to eliminate the impact of uncertain delays during signal transmission.

[0157] Optionally, the timestamp acquisition module 1001 is specifically used to:

[0158] The i-1 layer node is recorded as the reference node, and the i layer node is recorded as the node to be synchronized;

[0159] The nodes to be synchronized obtain timestamps by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at the moment, and the synchronization node collects four timestamps.

[0160] Optionally, the reference node is The slave time information packet is sent to the node to be synchronized at this moment. The clock value of the node to be synchronized at this moment is in

[0161]

[0162] Optionally, the linear relationship model includes:

[0163]

[0164] Among them, α i is the logical clock drift of the node to be synchronized, β i It is the logical clock offset of the node to be synchronized.

[0165] Optionally, based on the linear relationship model, the logical clock drift is estimated using the least squares method. Logical clock offset include:

[0166] Define the following matrix AX = B;

[0167] in:

[0168] Solving for estimates using the least squares method Estimate logical clock drift Logical clock offset

[0169] Optionally, the estimated delay σ of the node to be synchronized max,i , expressed as:

[0170]

[0171] Among them, O k,i , O k-1,i They represent the clock offsets of the nodes to be synchronized at the kth and k-1th data packet exchanges respectively;

[0172] Specifically,

[0173] To summarize, this embodiment obtains timestamp data pairs through two-way communication between nodes, calculates logical clock drift, logical clock offset and estimated delay, performs time and frequency calibration according to the calculation results, effectively reduces the cumulative synchronization error, and enhances the scalability of the time synchronization algorithm; this method meets the needs of large-scale deployment of wireless positioning systems, improves the robustness of the time synchronization algorithm, and achieves time synchronization accuracy of less than 3ns for the four indicators of maximum network error, maximum neighbor node error, average network error and hop-by-hop average network error while ensuring that the system calculation complexity meets the hardware requirements. Specific embodiment four:

[0175] This manual also provides an electronic device, see Fig.11 , the electronic device can implement the details of the method described in the above embodiment and achieve the same effect. Fig.11 As shown, the electronic device 1100 includes: a processor 1101, a transceiver 1102, a memory 1103, a user interface 1104 and a bus interface, wherein:

[0176] In the embodiment of this specification, the electronic device 1100 further includes: a computer program stored in the memory 1103 and executable by the processor 1101, and the computer program is executed by the processor 1101 to implement the following steps:

[0177] Based on the critical path, nodes obtain timestamps by bidirectionally exchanging time information packets;

[0178] According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two;

[0179] Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated using the least square method;

[0180] Calculate the propagation delay based on the acquired timestamp, and use the propagation delay and timestamp to construct a timestamp data pair at the same time point;

[0181] Determining an estimated delay of the node to be synchronized based on the timestamp data pair;

[0182] The logical clock offset and the estimated delay are compared. If the estimated delay is smaller than the logical clock offset, both the logical clock drift and the logical clock offset are corrected. Otherwise, only the logical clock offset is corrected.

[0183] exist Fig.11 In the embodiment, the bus framework may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1101 and various circuits of memory represented by memory 1103 are linked together. The bus framework may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described in this document. The bus interface provides an interface. The transceiver 1102 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium. For different user devices, the user interface 1104 may also be an interface capable of externally and internally connecting required devices, and the connected devices include but are not limited to a keypad, a display, a speaker, a microphone, a joystick, and the like.

[0184] The processor 1101 manages the bus architecture and the usual processing, and the memory 1103 can store data used by the processor 1101 when performing operations. Optionally, when the computer program is executed by the processor 1101, the following steps can also be implemented:

[0185] Optionally, the critical path refers to a path for transmitting data packets between two nodes;

[0186] The delay in the process of sending and receiving data packets can be divided into uncertain delay and deterministic delay;

[0187] The uncertain delay includes: sending delay, access delay and receiving delay;

[0188] Determine delays, including transmission delay, propagation delay, and reception delay;

[0189] Record timestamps at the physical layer to eliminate the impact of uncertain delays during signal transmission.

[0190] Optionally, the node obtains the timestamp by bidirectionally exchanging a time information data packet, including:

[0191] The i-1 layer node is recorded as the reference node, and the i layer node is recorded as the node to be synchronized;

[0192] The nodes to be synchronized obtain timestamps by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at the moment, and the synchronization node collects four timestamps.

[0193] Optionally, the reference node is The slave time information packet is sent to the node to be synchronized at this moment. The clock value of the node to be synchronized at this moment is in

[0194]

[0195] Optionally, the linear relationship model includes:

[0196]

[0197] Among them, α i is the logical clock drift of the node to be synchronized, β i It is the logical clock offset of the node to be synchronized.

[0198] Optionally, based on the linear relationship model, the logical clock drift is estimated using the least squares method. Logical clock offset include:

[0199] Define the following matrix AX = B;

[0200] in:

[0201] Solving for estimates using the least squares method Estimate logical clock drift Logical clock offset

[0202] Optionally, the estimated delay σ of the node to be synchronized max,i , expressed as:

[0203]

[0204] Among them, O k,i , O k-1,i They represent the clock offsets of the nodes to be synchronized at the kth and k-1th data packet exchanges respectively;

[0205] Specifically,

[0206] To summarize, this embodiment obtains timestamp data pairs through two-way communication between nodes, calculates logical clock drift, logical clock offset and estimated delay, performs time and frequency calibration according to the calculation results, effectively reduces the cumulative synchronization error, and enhances the scalability of the time synchronization algorithm; this method meets the needs of large-scale deployment of wireless positioning systems, improves the robustness of the time synchronization algorithm, and achieves time synchronization accuracy of less than 3ns for the four indicators of maximum network error, maximum neighbor node error, average network error and hop-by-hop average network error while ensuring that the system calculation complexity meets the hardware requirements.

[0207] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. For those skilled in the art, this specification may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.

Claims

1. A network time synchronization method based on critical path delay elimination, characterized in that: include: Based on the critical path, nodes obtain timestamps by bidirectionally exchanging time information packets; Calculate the propagation delay based on the acquired timestamp, and use the propagation delay and timestamp to construct a timestamp data pair at the same time point; According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two; Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated using the least square method; Determining an estimated delay of the node to be synchronized based on the timestamp data pair; Compare the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, correct both the logical clock drift and the logical clock offset. Otherwise, only the logical clock offset is corrected.

2. The method according to claim 1, characterized in that The critical path refers to the path for transmitting data packets between two nodes; The delay in the process of sending and receiving data packets can be divided into uncertain delay and deterministic delay; The uncertain delay includes: sending delay, access delay and receiving delay; Determine delays, including transmission delay, propagation delay, and reception delay; Record timestamps at the physical layer to eliminate the impact of uncertain delays during signal transmission.

3. The method according to claim 2, characterized in that Based on the critical path, the nodes obtain the timestamp by bidirectionally exchanging time information data packets, including: The i-1 layer node is recorded as the reference node, and the i layer node is recorded as the node to be synchronized; The nodes to be synchronized obtain timestamps by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at the moment, and the synchronization node collects four timestamps.

4. The method according to claim 3, characterized in that The reference node is The slave time information packet is sent to the node to be synchronized at this moment. The clock value of the node to be synchronized at this moment is in, k is a positive integer, and i is a positive integer greater than 1.

5. The method according to claim 4, characterized in that The linear relationship model comprises: Among them, α i is the logical clock drift of the node to be synchronized, β i It is the logical clock offset of the node to be synchronized.

6. The method according to claim 4, characterized in that Based on the linear relationship model, the logical clock drift is estimated using the least squares method. Logical clock skew include: Define the following matrix AX = B; in: Solving for estimates using the least squares method Estimate logical clock drift Logical clock skew 7. The method according to claim 6, characterized in that The estimated delay σ of the node to be synchronized max,i , expressed as: Among them, O k,i , O k-1,i They represent the clock offsets of the nodes to be synchronized at the kth and k-1th data packet exchanges respectively; Specific location, 8. A network time synchronization device based on critical path delay elimination, applied to the method according to any one of claims 1 to 7, characterized in that: include: Timestamp acquisition module, timestamp data pair construction module, model building module, logical clock offset estimation module, estimated delay determination module, delay elimination module; wherein: The timestamp acquisition module is used for nodes to acquire timestamps by bidirectionally exchanging time information data packets based on the critical path; The timestamp data pair construction module is used to calculate the propagation delay according to the acquired timestamp, and construct the timestamp data pair at the same time point using the propagation delay and the timestamp; The model building module is used to build a linear relationship model between the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized according to the two; The logic clock offset estimation module is used to estimate the logic clock drift and the logic clock offset based on the linear relationship model by using the least square method; The estimated delay determination module is used to determine the estimated delay of the node to be synchronized according to the timestamp data pair; The delay elimination module is used to compare the size of the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, the logical clock drift and the logical clock offset are corrected at the same time; otherwise, only the logical clock offset is corrected.

9. The device according to claim 8, characterized in that The timestamp acquisition module is specifically used for: The i-1 layer node is recorded as the reference node, and the i layer node is recorded as the node to be synchronized; The nodes to be synchronized obtain timestamps by exchanging time information packets in both directions. The master time information packet is sent to the reference node at all times. The reference node receives the data packet at The slave time information packet is sent to the node to be synchronized at all times. The data packet is received at the moment, and the synchronization node collects four timestamps.

10. A network device, characterized in that: include: Communications interfaces, processors, and memory; The processor calls the program instructions in the memory to perform the following actions: Based on the critical path, nodes obtain timestamps by bidirectionally exchanging time information packets; Calculate the propagation delay based on the acquired timestamp, and use the propagation delay and timestamp to construct a timestamp data pair at the same time point; According to the synchronization clock value maintained by the reference node and the clock value of the node to be synchronized, a linear relationship model is constructed between the two; Based on the linear relationship model, the logical clock drift and the logical clock offset are estimated using the least square method; Determining an estimated delay of the node to be synchronized based on the timestamp data pair; Compare the logical clock offset and the estimated delay. If the estimated delay is smaller than the logical clock offset, correct both the logical clock drift and the logical clock offset. Otherwise, only the logical clock offset is corrected.

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