Concealed conductor layer stack and method for producing same

By using lamination and blind via filling electroplating technology, the problem of fabricating the hidden conductor layer was solved, enabling a more refined layout of I/O interfaces within the substrate, thus meeting the development needs of high-speed and highly integrated electronic products.

CN119893884BActive Publication Date: 2026-05-29SHANGHAI MEADVILLE SCI & TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI MEADVILLE SCI & TECH
Filing Date
2025-01-21
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

In existing technologies, it is difficult to fabricate multiple hidden conductor layers, making it difficult to achieve fine-grained circuit layout and interconnection of more I/O interfaces within a limited area.

Method used

By providing two first concealed conductor layer structures and one second concealed conductor layer structure, the inner concealed conductor layer and the outer concealed conductor layer are laminated together to form blind vias and fill the entire board with electroplated layers. The excess parts are etched away, and the steps are repeated until the required number of layers is reached.

Benefits of technology

It enables the interconnection and operation of more I/O interfaces within a limited area, adapts to the increasingly sophisticated requirements of substrate wiring design, and improves the integration and reliability of the packaging structure.

✦ Generated by Eureka AI based on patent content.

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    Figure CN119893884B_ABST
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Abstract

The application provides a hidden conductor layer stack structure and a preparation method thereof. The method comprises the following steps: firstly, a first hidden conductor layer structure is prepared, which comprises an inner hidden conductor layer and at least one additional layer; secondly, a second hidden conductor layer structure is formed on a double-sided copper-clad carrier plate, which comprises an outer hidden conductor layer; thirdly, two first hidden conductor layer structures are respectively pressed on the opposite surfaces of the second hidden conductor layer structure; fourthly, a detachable copper foil is peeled off from the center carrier plate to obtain two intermediate structures; fifthly, a blind hole is formed on the intermediate structure; sixthly, a full-plate electroplating layer is formed to fill the blind hole; seventhly, the full-plate electroplating layer and the detachable copper foil outside the blind hole are etched until the outer hidden conductor layer is exposed; and finally, the hidden conductor layer stack structure is prepared. The package structure has more I / O interfaces for interconnection and operation in a limited area, and meets the demand of gradually precise substrate wiring design.
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