Semiconductor structure, forming method thereof and memory

Abstract

The invention relates to a semiconductor structure, a forming method thereof and a memory, and the forming method comprises the steps: forming an initial semiconductor structure, the initial semiconductor structure comprises a substrate and word line structures, the substrate comprises a plurality of semiconductor columns distributed at intervals and a plurality of insulating parts located between two adjacent semiconductor columns, the word line structure extends along the direction in which the plurality of semiconductor columns are distributed at intervals and wraps the periphery of each semiconductor column; the insulating parts are located on the word line structures, the ends, away from the word line structures, of the insulating parts are higher than the ends of the semiconductor columns, and bit line grooves are defined by the two adjacent insulating parts and the semiconductor columns between the two adjacent insulating parts; forming a barrier layer covering the side wall of the bit line trench; forming a conductive material layer in the bit line trench with the barrier layer; performing primary heat treatment on the conductive material layer to form a bit line structure; forming a contact hole which penetrates through the insulating part and exposes the word line structure; forming an insulating layer on the hole wall of the contact hole; and forming a word line contact structure in the contact hole with the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. However, during the DRAM manufacturing process, structural defects are prone to occur due to process limitations, and the product yield is low.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, and a memory, which can reduce leakage and improve product yield.

[0005] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising:

[0006] An initial semiconductor structure is formed, the initial semiconductor structure comprising a substrate and a word line structure, the substrate comprising a plurality of semiconductor pillars distributed at intervals and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extends along the direction in which the plurality of semiconductor pillars are distributed at intervals and covers the periphery of each semiconductor pillar; the insulating portion is located on the word line structure, and an end of the insulating portion away from the word line structure is higher than an end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween define a bit line groove;

[0007] forming a barrier layer covering the sidewalls of the bit line trench;

[0008] forming a conductive material layer in the bit line trench having the barrier layer;

[0009] Performing a heat treatment on the conductive material layer to form a bit line structure;

[0010] forming a contact hole penetrating the insulating portion and exposing the word line structure;

[0011] forming an insulating layer on the hole wall of the contact hole;

[0012] A word line contact structure is formed in the contact hole having the insulating layer.

[0013] For example, the forming of a barrier layer covering the sidewall of the bit line trench includes:

[0014] forming a barrier material layer on the sidewalls and bottom of the bit line trench;

[0015] The barrier material layer is processed by a reverse sputtering process so that the thickness of the barrier material layer at the end close to the semiconductor column is greater than the thickness of the barrier material layer at the side away from the semiconductor column;

[0016] The barrier material layer is etched back to expose the top surface of the semiconductor column, and the end of the barrier material layer away from the semiconductor column is lower than the surface of the insulating portion away from the word line structure, and the remaining barrier material layer is used as the barrier layer; the surface of the bit line structure away from the semiconductor column is flush with the end of the barrier layer away from the semiconductor column.

[0017] For example, the thickness of the barrier layer is 1 nm to 3 nm; the material of the barrier layer includes titanium nitride or tantalum nitride.

[0018] For example, the forming method further comprises:

[0019] forming a passivation layer on a surface of a structure formed by the barrier layer, the bit line structure and the insulating portion;

[0020] The surface of the passivation layer is chemically mechanically polished to make the surface of the passivation layer flush with the surface of the insulating portion away from the word line structure.

[0021] For example, the step of performing a heat treatment on the conductive material layer to form a bit line structure includes:

[0022] Heat-treating the conductive material layer at a preset temperature so that metal ions in the conductive material layer diffuse into the semiconductor column to form a first conductive layer at the interface between the semiconductor column and the conductive material layer; using the conductive material layer after the heat treatment as a second conductive layer;

[0023] The preset temperature is less than 450°C.

[0024] For example, forming the initial semiconductor structure includes:

[0025] Providing a substrate, the substrate comprising a plurality of first grooves spaced apart and distributed along a first direction, and an insulating material filling the first grooves;

[0026] Etching the substrate to form a plurality of second grooves spaced apart along a second direction, wherein the second direction intersects the first direction, and each of the second grooves and each of the first grooves divides the substrate into a plurality of semiconductor pillars;

[0027] Etching back the insulating material to form an insulating portion;

[0028] forming a word line structure extending along the first direction and covering the periphery of each of the semiconductor pillars spaced apart along the first direction, wherein the word line structure is located on the insulating portion, and a surface thereof away from the insulating portion is lower than a surface of the semiconductor pillar away from the bottom of the first trench;

[0029] Doping a region of the semiconductor column that is not covered by the word line structure and the insulating portion to form a source region;

[0030] forming a capacitor structure on the source region;

[0031] The substrate is etched at a side of the substrate away from the capacitor structure to form the bit line trench.

[0032] According to one aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0033] An initial semiconductor structure includes a substrate and a word line structure, wherein the substrate includes a plurality of semiconductor pillars distributed at intervals and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extends along the direction in which the plurality of semiconductor pillars are distributed at intervals and covers the periphery of each semiconductor pillar; the insulating portion is located on the word line structure, and an end of the insulating portion away from the word line structure is higher than an end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween define a bit line groove;

[0034] a barrier layer covering the sidewalls of the bit line trench;

[0035] a bit line structure at least partially located within the bit line trench having the barrier layer;

[0036] A word line contact structure, penetrating through the insulating portion and contacting and connecting with the word line structure;

[0037] An insulating layer is located between the word line contact structure and the barrier layer, the bit line structure and the semiconductor column.

[0038] For example, the thickness of the barrier layer at the end portion close to the semiconductor pillar is greater than the thickness of the barrier layer at the end portion away from the semiconductor pillar.

[0039] For example, the material of the barrier layer includes titanium nitride or tantalum nitride, and the thickness of the barrier layer includes 1 nm to 3 nm.

[0040] For example, the bit line structure includes a first conductive layer and a second conductive layer, the first conductive layer is located at the top of the semiconductor column, the barrier layer is in contact with the first conductive layer near the end of the semiconductor column, and the second conductive layer is located in the bit line groove having the barrier layer and in contact with the surface of the first conductive layer.

[0041] For example, the semiconductor structure further includes:

[0042] The passivation layer is located on the surface of the bit line structure, and the surface of the passivation layer away from the bit line structure is flush with the surface of the insulating portion away from the word line structure.

[0043] For example, the surface of the word line structure away from the insulating part is lower than the surface of the semiconductor column away from the bit line groove, the area in the semiconductor column not covered by the word line structure and the insulating part is the source region, and the initial semiconductor structure also includes: a capacitor structure formed on the source region.

[0044] According to one aspect of the present disclosure, a memory is provided, comprising any one of the semiconductor structures described above.

[0045] For example, the memory further includes: a peripheral circuit bonded to the word line contact structure of the semiconductor structure.

[0046] The semiconductor structure, its formation method, and memory disclosed in the present invention, since the insulating layer is located between the bit line structure and the word line contact structure, the bit line structure and the word line contact structure can be insulated and isolated by the insulating layer, which helps to reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure; at the same time, since the sidewalls of the bit line groove are covered with a barrier layer (that is, a barrier layer is also provided between the insulating layer and the bit line structure), the barrier layer can prevent metal ions in the bit line structure from diffusing into the insulating layer and the word line contact structure in contact with the insulating layer, which helps to further reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure and improve product yield.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0049] Figure 1Flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0050] Figure 2 FIG. 4 is a top view of an initial semiconductor structure in an embodiment of the present disclosure.

[0051] Figure 3 Schematic diagram of an initial semiconductor structure in an embodiment of the present disclosure.

[0052] Figure 4 FIG. 1 is a schematic diagram of an embodiment of the present disclosure in which the substrate is turned upside down after the capacitor structure is formed.

[0053] Figure 5 It is a schematic diagram of the structure after completing step S120 in the embodiment of the present disclosure.

[0054] Figure 6 It is a schematic diagram of the structure after completing step S310 in the embodiment of the present disclosure.

[0055] Figure 7 It is a schematic diagram of the structure after completing step S130 in the embodiment of the present disclosure.

[0056] Figure 8 It is a schematic diagram of the structure after completing step S140 in the embodiment of the present disclosure.

[0057] Fig. 9 It is a schematic diagram of the structure after completing step S420 in the embodiment of the present disclosure.

[0058] Fig.10 It is a schematic diagram of the structure after completing step S150 in the embodiment of the present disclosure.

[0059] Fig.11 It is a schematic diagram of the structure after completing step S160 in the embodiment of the present disclosure.

[0060] Fig.12 It is a schematic diagram of the structure after completing step S170 in the embodiment of the present disclosure.

[0061] Fig.13 Schematic diagram of a memory in an embodiment of the present disclosure.

[0062] Description of reference numerals:

[0063] 1. Initial semiconductor structure; 11. Substrate; 111. Semiconductor pillar; 111a. Source region; 112. Insulating portion; 12. Word line structure; 13. Gate oxide layer; 101. Bit line groove; 102. Contact hole; 2. Barrier layer; 210. Barrier material layer; 3. Conductive material layer; 4. Bit line structure; 41. First conductive layer; 42. Second conductive layer; 5. Insulating layer; 6. Word line contact structure; 61. Titanium nitride layer; 62. Tungsten layer; 7. Passivation layer; 100. Semiconductor structure; 200. Peripheral circuit; x, first direction; y, second direction. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0065] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0066] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "one," "the," or "said" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0067] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. Such a substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. In addition, the substrate may include one or more semiconductor materials.

[0068] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying structure or superstructure, or may have a range that is less than the underlying structure or superstructure. In addition, a layer may be an area of ​​a homogeneous or non-homogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it.

[0069] The terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0070] The present disclosure provides a method for forming a semiconductor structure. Figure 1 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 1 As shown, the forming method includes steps S110 to S170, wherein:

[0071] Step S110, forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate and a word line structure, the substrate comprising a plurality of semiconductor pillars spaced apart and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extending along a direction in which the plurality of semiconductor pillars are spaced apart and covering the periphery of each semiconductor pillar; the insulating portion being located above the word line structure, and an end of the insulating portion away from the word line structure being higher than an end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween defining a bit line groove;

[0072] Step S120, forming a barrier layer covering the sidewalls of the bit line trench;

[0073] Step S130, forming a conductive material layer in the bit line trench having the barrier layer;

[0074] Step S140, performing a heat treatment on the conductive material layer to form a bit line structure;

[0075] Step S150, forming a contact hole penetrating the insulating portion and exposing the word line structure;

[0076] Step S160, forming an insulating layer on the hole wall of the contact hole;

[0077] Step S170 , forming a word line contact structure in the contact hole having the insulating layer.

[0078] In the method for forming a semiconductor structure disclosed in the present invention, since the insulating layer is located between the bit line structure and the word line contact structure, the bit line structure and the word line contact structure can be insulated and isolated by the insulating layer, which helps to reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure; at the same time, since the sidewalls of the bit line groove are covered with a barrier layer (that is, a barrier layer is also provided between the insulating layer and the bit line structure), the barrier layer can prevent metal ions in the bit line structure from diffusing into the insulating layer and the word line contact structure in contact with the insulating layer, which helps to further reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure and improve product yield.

[0079] The steps and specific details of the method for forming a semiconductor structure disclosed in the present invention are described in detail below:

[0080] like Figure 1 As shown, in step S110, an initial semiconductor structure is formed, the initial semiconductor structure includes a substrate and a word line structure, the substrate includes a plurality of spaced semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extends along the direction in which the plurality of semiconductor pillars are spaced apart, and is coated on the periphery of each semiconductor pillar; the insulating portion is located above the word line structure, and the end of the insulating portion away from the word line structure is higher than the end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween define a bit line groove.

[0081] like Figure 2As shown, the substrate 11 may include a plurality of semiconductor pillars 111 distributed in an array, and each semiconductor pillar 111 is distributed in the form of rows and / or columns. For example, the substrate 11 may include a plurality of semiconductor groups, each semiconductor group includes a plurality of semiconductor pillars 111 distributed at intervals along a first direction x, and each semiconductor group is distributed at intervals along a second direction y. Wherein, the second direction y intersects with the first direction x, for example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that verticality may be absolutely vertical or approximately vertical, and there will inevitably be deviations during the manufacturing process. In the present disclosure, the angle deviation may be caused by the manufacturing process limitation, so that the angle between the first direction x and the second direction y has a certain deviation. As long as the angle deviation between the first direction x and the second direction y is within a preset range, the first direction x can be considered to be perpendicular to the second direction y. For example, the preset range can be 10°, that is, when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, the first direction x and the second direction y can be considered to be perpendicular.

[0082] like Figure 3 As shown, the insulating portion 112 may be located between two semiconductor pillars 111 that are adjacently distributed along the first direction x, and may fill the gap between the two semiconductor pillars 111 that are adjacently distributed. In some embodiments of the present disclosure, there may be a plurality of insulating portions 112, and an insulating portion 112 may be provided between every two semiconductor pillars 111 that are adjacently distributed along the first direction x. For example, the insulating portion 112 may be in a strip shape and may extend along the second direction y, and a plurality of insulating portions 112 may be distributed at intervals along the first direction x.

[0083] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 and Figure 3 As shown, the word line structure 12 may be in a strip shape, which may extend along the first direction x, and may be coated on the periphery of each semiconductor pillar 111 spaced apart along the first direction x, and a gate oxide layer 13 is formed between the word line structure 12 and the semiconductor pillar 111. The insulating portion 112 may be located above the word line structure 12 and may contact the word line structure 12. In some embodiments of the present disclosure, the end of the insulating portion 112 away from the word line structure 12 is higher than the end of the semiconductor pillar 111, and two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween jointly define a bit line trench 101.

[0084] In an exemplary embodiment of the present disclosure, the surface of the word line structure 12 away from the insulating portion 112 is lower than the surface of the semiconductor column 111 away from the bit line groove 101, and the area of ​​the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 can be ion doped to form a source region 111a, and a capacitor structure (not shown in the figure) can be formed on the source region 111a.

[0085] In an exemplary embodiment of the present disclosure, forming the initial semiconductor structure 1 (ie, step S110) may include steps S210 to S270, wherein:

[0086] Step S210 , providing a substrate 11 , wherein the substrate 11 comprises a plurality of first grooves spaced apart along a first direction x, and an insulating material filling the first grooves.

[0087] The substrate 11 may include a base, which may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. The shape and material of the base are not particularly limited here.

[0088] The substrate may be etched to form a plurality of first grooves spaced apart along the first direction x and extending along the second direction y, and an insulating material may be filled in the first grooves by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the insulating material may fill each first groove, and the insulating material may be silicon oxide. It should be noted that the substrate and the insulating material may together constitute the substrate 11.

[0089] Step S220 , etching the substrate 11 to form a plurality of second grooves spaced apart along a second direction y, wherein the second direction y intersects the first direction x, and each of the second grooves and each of the first grooves divides the substrate 11 into a plurality of semiconductor pillars 111 .

[0090] The structure formed by the substrate and the insulating material can be etched to form a plurality of second grooves spaced apart along the second direction y and extending along the first direction x. It should be noted that the depth of the second groove is different from that of the first groove. For example, the depth of the second groove is less than that of the first groove. The second grooves and the first grooves can together divide the substrate into a plurality of semiconductor pillars 111.

[0091] In some embodiments of the present disclosure, an insulating material may be filled in the second trenches, and the insulating material may fill each second trench. It should be noted that the insulating material filled in the second trenches may be the same as the insulating material filled in the first trenches.

[0092] Step S230 , etching back the insulating material to form an insulating portion 112 .

[0093] The insulating material may be etched back to expose a portion of the sidewalls of the semiconductor pillars 111 , and the insulating material remaining between the semiconductor pillars 111 spaced apart along the first direction x after the back etching may be used as the insulating portion 112 .

[0094] Step S240, forming a word line structure 12 extending along the first direction x and covering the periphery of each of the semiconductor pillars 111 spaced apart along the first direction x, wherein the word line structure 12 is located on the insulating portion 112, and a surface thereof away from the insulating portion 112 is lower than a surface of the semiconductor pillar 111 away from the bottom of the first trench.

[0095] In an exemplary embodiment of the present disclosure, before forming the word line structure 12, a gate oxide layer 13 may be formed on the sidewall surface of the semiconductor pillar 111 exposed on the upper part of the insulating portion 112. For example, the gate oxide layer 13 may be formed on the surface of the semiconductor pillar 111 by in-situ water vapor oxidation or atomic layer deposition. After forming the gate oxide layer 13, the word line structure 12 may be formed, and the word line structure 12 may cover the surface of the gate oxide layer 13. That is, the gate oxide layer 13 is provided between the word line structure 12 and the semiconductor pillar 111.

[0096] Step S250 , doping the region of the semiconductor pillar 111 that is not covered by the word line structure 12 and the insulating portion 112 to form a source region 111 a .

[0097] After forming the word line structure 12, the region of the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 may be ion doped to form a source region 111a. For example, the region of the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 may be p-type doped to form a p-type doped region. For example, a p-type doping material may be doped into the semiconductor column 111, and the p-type doping material may be an element in the III main group of the periodic table, for example, boron, and of course, other elements, which are not listed here one by one.

[0098] Step S260: forming a capacitor structure on the source region 111 a.

[0099] A capacitor structure may be formed on the source region 111a, and the capacitor structure may include a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, wherein the lower electrode layer is in contact with the source region 111a, the capacitor dielectric layer is located on the surface of the lower electrode layer, and the upper electrode layer is located on the surface of the capacitor dielectric layer. The material of the lower electrode layer and the upper electrode layer may be titanium nitride, and the material of the capacitor dielectric layer may be a dielectric material with a relatively high dielectric constant.

[0100] Step S270 , etching the substrate 11 at a side of the substrate 11 away from the capacitor structure to form the bit line trench 101 .

[0101] After forming the capacitor structure, the substrate 11 can be turned upside down, so that the capacitor structure is downward relative to the word line structure 12, and the insulating portion 112 is upward relative to the word line structure 12. At this time, the original bottom surface of the substrate 11 is upward, and the original top surface is downward. Figure 4 shown.

[0102] Please continue to see Figure 3 As shown, after the substrate 11 is flipped over, the substrate 11 can be chemically mechanically polished on the side of the substrate 11 away from the capacitor structure to expose the end of the insulating portion 112 away from the word line structure 12; the base is then etched to form a bit line groove 101 between adjacent insulating portions 112 spaced apart along the first direction x.

[0103] like Figure 1 As shown, in step S120 , a barrier layer 2 is formed to cover the sidewalls of the bit line trench 101 .

[0104] like Figure 5 As shown, the barrier layer 2 may be a thin film covering the sidewalls (e.g., the insulating portion 112) of the bit line trench 101, or a coating covering the sidewalls of the bit line trench 101, and the specific form of the barrier layer 2 is not particularly limited. The bottom end of the barrier layer 2 may be in contact with the top end of the semiconductor pillar 111. The material of the barrier layer 2 may be a material having an ion blocking function, for example, the material may be titanium nitride or tantalum nitride.

[0105] The thickness of the barrier layer 2 may include 1nm to 3nm, for example, it may be 1nm, 1.5nm, 2nm, 2.5nm or 3nm, and of course, it may be other thicknesses that are not listed here one by one. In some embodiments of the present disclosure, in the depth direction of the bit line groove 101, the thickness of each region of the barrier layer 2 may not be exactly the same. For example, the thickness of the end of the barrier layer 2 close to the semiconductor column 111 is greater than the thickness of the side away from the semiconductor column 111, so as to reduce the risk of metal ions in the conductive material layer subsequently formed inside the bit line groove 101 diffusing along the interface between the insulating portion 112 and the semiconductor column 111 to the word line structure 12 below the insulating portion 112 and the word line contact structure subsequently formed through the insulating portion 112, which helps to reduce the probability of bridging between the bit line structure and the word line structure 12 and the word line contact structure subsequently formed, thereby reducing the probability of leakage or short circuit, and improving product yield.

[0106] In an exemplary embodiment of the present disclosure, forming the barrier layer 2 covering the sidewall of the bit line trench 101 (and step S120) may include steps S310 to S330, wherein:

[0107] Step S310 , forming a barrier material layer 210 on the sidewalls and the bottom of the bit line trench 101 .

[0108] like Figure 6 As shown, the material of the blocking material layer 210 may be a material having an ion blocking function, for example, it may include titanium nitride or tantalum nitride. The blocking material layer 210 may be formed on the sidewall (for example, the insulating portion 112) and the bottom (for example, the top surface of the semiconductor column 111) of the bit line trench 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, for the sake of process, the blocking material layer 210 may also be formed on the top of the insulating portion 112 at the same time. That is, the blocking material layer 210 may be formed on the surface of the structure formed by the insulating portion 112 and the semiconductor column 111. The thickness of the blocking material layer 210 may include 1nm to 3nm, for example, the thickness may be 1nm, 1.5nm, 2nm, 2.5nm or 3nm, and of course, it may also be other thicknesses that are not listed here one by one.

[0109] Step S320 , treating the barrier material layer 210 by a reverse sputtering process, so that the thickness of the barrier material layer 210 at the end close to the semiconductor column 111 is greater than the thickness at the side away from the semiconductor column 111 .

[0110] The blocking material layer 210 can be processed by a reverse sputtering process. During this process, at least a portion of the blocking material layer 210 at the bottom of the bit line groove 101 can be sputtered onto the side wall of the bit line groove 101, so that the end of the blocking material layer 210 covering the side wall of the bit line groove 101 close to the semiconductor column 111 shows a material accumulation phenomenon. At this time, the thickness of the end of the blocking material layer 210 covering the side wall of the bit line groove 101 close to the semiconductor column 111 is greater than the thickness on the side away from the semiconductor column 111.

[0111] In step S330, the blocking material layer 210 is etched back to expose the top surface of the semiconductor column 111, and the end of the blocking material layer 210 away from the semiconductor column 111 is lower than the surface of the insulating portion 112 away from the word line structure 12, and the remaining blocking material layer 210 is used as the blocking layer 2; the surface of the bit line structure away from the semiconductor column 111 is flush with the end of the blocking layer 2 away from the semiconductor column 111.

[0112] The barrier material layer 210 can be etched back to expose the surface of the semiconductor pillar 111 at the bottom of the bit line trench 101. In this process, the barrier material layer 210 located at the top of the insulating portion 112 can also be removed at the same time, so that the barrier material layers 210 in different bit line trenches 101 are disconnected from each other, and the end of the barrier material layer 210 away from the semiconductor pillar 111 is lower than the surface of the insulating portion 112 away from the word line structure 12, and the remaining barrier material layer 210 in the bit line trench 101 after the back etching can be used as the barrier layer 2. In the embodiment of the present disclosure, the structure after completing step S330 is as follows Figure 5 shown.

[0113] like Figure 1 As shown, in step S130 , a conductive material layer 3 is formed in the bit line trench 101 having the barrier layer 2 .

[0114] like Figure 7 As shown, the material of the conductive material layer 3 may be a metal or a non-metal with good conductive properties, for example, it may be cobalt (Co). The conductive material may be filled in the bit line trench 101 having the barrier layer 2 by chemical vapor deposition, physical vapor deposition or atomic layer deposition (i.e., the conductive material is in contact with the top surface of the semiconductor pillar 111), and the conductive material may fill the bit line trench 101. The conductive material may then be etched back so that the surface of the conductive material is flush with the end of the barrier layer 2 away from the semiconductor pillar 111, and the conductive material remaining in the bit line trench 101 after the back etching may be used as the conductive material layer 3.

[0115] like Figure 1 As shown, in step S140 , the conductive material layer 3 is subjected to a heat treatment to form a bit line structure 4 .

[0116] In an exemplary embodiment of the present disclosure, the conductive material layer 3 may be heat treated at a preset temperature, and the preset temperature may be less than 450° C. For example, it may be 450° C., 440° C., 430° C., 420° C., 410° C. or 400° C., and of course, it may be other temperatures, which are not listed here.

[0117] Under the effect of the preset temperature, the metal ions in the conductive material layer 3 can diffuse into the semiconductor column 111, and then form a first conductive layer 41 at the interface between the semiconductor column 111 and the conductive material layer 3; for example, when the material of the semiconductor column 111 is silicon and the material of the conductive material layer 3 is cobalt (Co), the material of the first conductive layer 41 can be cobalt silicide (CoSi). The conductive material layer 3 that has not reacted after the heat treatment can be used as the second conductive layer 42 (whose material is still cobalt (Co)), and the second conductive layer 42 and the first conductive layer 41 together constitute the bit line structure 4. In the embodiment of the present disclosure, the structure after completing step S140 is as follows: Figure 8 shown.

[0118] It should be noted that in the present disclosure, only one heat treatment is required in the process of forming the bit line structure 4. In the bit line structure 4, the resistance of the second conductive layer 42 is relatively low. Even if the resistance of the first conductive layer 41 is relatively high, the resistance of the bit line structure 4 can be reduced as a whole by combining the second conductive layer 42 with the first conductive layer 41. Compared with the existing solution of forming CoSi by the first heat treatment and then forming CoSi2 with relatively low resistance by the second heat treatment, the present disclosure can save one heat treatment process while ensuring that the bit line structure 4 has a lower resistance, which helps to simplify the process and reduce manufacturing costs.

[0119] In an exemplary embodiment of the present disclosure, after forming the bit line structure 4, the method for forming the semiconductor structure 100 of the present disclosure may further include step S410 and step S420, wherein:

[0120] Step S410 , forming a passivation layer 7 on the surface of the structure formed by the barrier layer 2 , the bit line structure 4 and the insulating portion 112 .

[0121] A passivation layer 7 may be formed on the surface of the structure formed by the barrier layer 2, the bit line structure 4 and the insulating portion 112 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the passivation layer 7 may fill the remaining gap in the bit line trench 101. The material of the passivation layer 7 may be an insulating material, and the surface of the bit line structure 4 may be insulated and isolated by the passivation layer 7 to reduce the probability of leakage or short circuit between the bit line structure 4 and other structures formed subsequently. For example, the material of the passivation layer 7 may be silicon nitride.

[0122] Step S420 , chemically mechanically polishing the surface of the passivation layer 7 , so that the surface of the passivation layer 7 is flush with the surface of the insulating portion 112 away from the word line structure 12 .

[0123] In some embodiments of the present disclosure, the surface of the passivation layer 7 may be planarized by chemical mechanical polishing. During this process, the surface of the insulating portion 112 may be polished synchronously to make the surface of the passivation layer 7 flush with the surface of the insulating portion 112, so as to provide a flat process reference for subsequent processes. In the embodiment of the present disclosure, the structure after completing step S420 is as follows: Fig. 9 shown.

[0124] like Figure 1 As shown, in step S150 , a contact hole 102 is formed penetrating the insulating portion 112 and exposing the word line structure 12 .

[0125] like Fig.10As shown, a contact hole 102 penetrating the insulating portion 112 and exposing the word line structure 12 can be formed by an etching process. In a direction parallel to the substrate 11, the cross-section of the contact hole 102 can be circular, elliptical, rectangular, polygonal or irregular, which is not particularly limited here. The number of the contact holes 102 can be one or more, which is not particularly limited here.

[0126] like Figure 1 As shown, in step S160 , an insulating layer 5 is formed on the hole wall of the contact hole 102 .

[0127] The thickness of the insulating layer 5 may be less than 4 nm, for example, it may be 4 nm, 3.5 nm, 3 nm, 2.5 nm or 2 nm, etc., and the thickness of the insulating layer 5 is not particularly limited here. The insulating layer 5 may be formed on the inner wall of the contact hole 102 so that the bit line structure 4 and the word line contact structure are insulated and isolated by the insulating layer 5, which helps to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure subsequently formed in the contact hole 102. In the embodiment of the present disclosure, the structure after completing step S160 is as follows: Fig.11 shown.

[0128] In some embodiments of the present disclosure, in the first direction x, the relatively distributed hole walls in the contact hole 102 may be formed by the semiconductor pillar 111, the bit line structure 4 and the passivation layer 7, and the insulating layer 5 may cover the side walls of the semiconductor pillar 111, the bit line structure 4 and the passivation layer 7. For example, in the process of forming the insulating layer 5, for the convenience of the process, the insulating layer 5 may cover the bottom of the contact hole 102 (i.e., the surface of the word line structure 12) at the same time, and then the insulating layer 5 at the bottom of the contact hole 102 may be removed by etching to expose the surface of the word line structure 12, so that the word line contact structure subsequently formed in the contact hole 102 can contact the word line structure 12, and then the word line structure 12 is electrically led out.

[0129] In an exemplary embodiment of the present disclosure, the material of the insulating layer 5 may be silicon nitride. When the material of the blocking layer 2 is titanium nitride or tantalum nitride, since the materials of the insulating layer 5 and the blocking layer 2 are both nitrides, the insulating layer 5 and the blocking layer 2 have better adhesion, and the interface between the insulating layer 5 and the blocking layer 2 is more reliable. Even if the insulating layer 5 on the hole wall is damaged to a certain extent when etching back the insulating layer 5 at the bottom of the contact hole 102, making it weaker, its barrier effect on metal ions can also be guaranteed, reducing the probability of metal ions diffusing from the bit line structure 4 to the word line structure 12, further reducing the probability of leakage or short circuit, and improving product yield.

[0130] like Figure 1 As shown, in step S170 , a word line contact structure 6 is formed in the contact hole 102 having the insulating layer 5 .

[0131] like Fig.12 As shown, the word line contact structure 6 can be formed in the contact hole 102 with the insulating layer 5 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. That is, the insulating layer 5 is located between the bit line structure 4 and the word line contact structure 6, and the bit line structure 4 and the word line contact structure 6 can be insulated and isolated by the insulating layer 5, which helps to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6; at the same time, since the side wall of the bit line groove 101 is covered with a barrier layer 2 (that is, a barrier layer 2 is also provided between the insulating layer 5 and the bit line structure 4), the barrier layer 2 can prevent the metal ions in the bit line structure 4 from diffusing into the insulating layer 5 and the word line contact structure 6 in contact with the insulating layer 5, which helps to further reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6, and improve the product yield.

[0132] In some embodiments of the present disclosure, the material of the word line contact structure 6 may be a conductive material, for example, it may include titanium nitride, tungsten or a combination thereof. For example, the word line contact structure 6 may include a titanium nitride layer 61 and a tungsten layer 62, wherein the titanium nitride layer 61 may conformally cover the sidewalls and bottom of the contact hole 102, and the tungsten layer 62 may be located on the surface of the titanium nitride layer 61 and may fill the contact hole 102; the titanium nitride layer 61 may prevent the tungsten in the tungsten layer 62 from diffusing into other surrounding structures, which helps to improve device reliability.

[0133] It should be noted that, although the steps of the method for forming the semiconductor structure 100 in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0134] The present disclosure also provides a semiconductor structure, such as Fig.12 As shown, the semiconductor structure 100 may include an initial semiconductor structure 1, a barrier layer 2, a bit line structure 4, a word line contact structure 6 and an insulating layer 5, wherein:

[0135] The initial semiconductor structure 1 includes a substrate 11 and a word line structure 12. The substrate 11 includes a plurality of semiconductor pillars 111 that are spaced apart and a plurality of insulating portions 112 that are respectively located between two adjacent semiconductor pillars 111. The word line structure 12 extends in a direction in which the plurality of semiconductor pillars 111 are spaced apart and covers the periphery of each semiconductor pillar 111. The insulating portion 112 is located on the word line structure 12, and an end of the insulating portion 112 that is away from the word line structure 12 is higher than an end of the semiconductor pillar 111. Two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween define a bit line trench 101.

[0136] The barrier layer 2 covers the sidewalls of the bit line trench 101;

[0137] The bit line structure 4 is at least partially located in the bit line trench 101 having the barrier layer 2;

[0138] The word line contact structure 6 passes through an insulating portion 112 and is in contact with the word line structure 12;

[0139] The insulating layer 5 is located between the word line contact structure 6 and the barrier layer 2 , the bit line structure 4 and the semiconductor pillar 111 .

[0140] In the semiconductor structure 100 disclosed in the present invention, since the insulating layer 5 is located between the bit line structure 4 and the word line contact structure 6, the bit line structure 4 and the word line contact structure 6 can be insulated and isolated by the insulating layer 5, which helps to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6; at the same time, since the side wall of the bit line groove 101 is covered with the barrier layer 2 (that is, the barrier layer 2 is also provided between the insulating layer 5 and the bit line structure 4), the barrier layer 2 can prevent metal ions in the bit line structure 4 from diffusing into the insulating layer 5 and the word line contact structure 6 in contact with the insulating layer 5, which helps to further reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6 and improve the product yield.

[0141] The various parts and specific details of the semiconductor structure 100 disclosed in the present invention are described in detail below:

[0142] like Figure 2 As shown, the substrate 11 may include a plurality of semiconductor pillars 111 distributed in an array, and each semiconductor pillar 111 is distributed in the form of rows and / or columns. For example, the substrate 11 may include a plurality of semiconductor groups, each semiconductor group includes a plurality of semiconductor pillars 111 distributed at intervals along a first direction x, and each semiconductor group is distributed at intervals along a second direction y. Wherein, the second direction y intersects with the first direction x, for example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that verticality may be absolutely vertical or approximately vertical, and there will inevitably be deviations during the manufacturing process. In the present disclosure, the angle deviation may be caused by the manufacturing process limitation, so that the angle between the first direction x and the second direction y has a certain deviation. As long as the angle deviation between the first direction x and the second direction y is within a preset range, the first direction x can be considered to be perpendicular to the second direction y. For example, the preset range can be 10°, that is, when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, the first direction x and the second direction y can be considered to be perpendicular.

[0143] like Figure 3As shown, the insulating portion 112 may be located between two semiconductor pillars 111 that are adjacently distributed along the first direction x, and may fill the gap between the two semiconductor pillars 111 that are adjacently distributed. In some embodiments of the present disclosure, there may be a plurality of insulating portions 112, and an insulating portion 112 may be provided between every two semiconductor pillars 111 that are adjacently distributed along the first direction x. For example, the insulating portion 112 may be in a strip shape and may extend along the second direction y, and a plurality of insulating portions 112 may be distributed at intervals along the first direction x.

[0144] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 and Figure 3 As shown, the word line structure 12 may be in a strip shape, which may extend along the first direction x, and may be coated on the periphery of each semiconductor pillar 111 spaced apart along the first direction x, and a gate oxide layer 13 is formed between the word line structure 12 and the semiconductor pillar 111. The insulating portion 112 may be located above the word line structure 12 and may contact the word line structure 12. In some embodiments of the present disclosure, the end of the insulating portion 112 away from the word line structure 12 is higher than the end of the semiconductor pillar 111, and two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween jointly define a bit line trench 101.

[0145] In an exemplary embodiment of the present disclosure, the surface of the word line structure 12 away from the insulating portion 112 is lower than the surface of the semiconductor column 111 away from the bit line groove 101, and the area of ​​the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 can be ion doped to form a source region 111a, and a capacitor structure (not shown in the figure) can be formed on the source region 111a.

[0146] like Figure 5 As shown, the barrier layer 2 may be a thin film covering the sidewalls (e.g., the insulating portion 112) of the bit line trench 101, or a coating covering the sidewalls of the bit line trench 101, and the specific form of the barrier layer 2 is not particularly limited. The bottom end of the barrier layer 2 may be in contact with the top end of the semiconductor pillar 111. The material of the barrier layer 2 may be a material having an ion blocking function, for example, the material may be titanium nitride or tantalum nitride.

[0147] The thickness of the barrier layer 2 may include 1nm to 3nm, for example, it may be 1nm, 1.5nm, 2nm, 2.5nm or 3nm, and of course, it may be other thicknesses that are not listed here one by one. In some embodiments of the present disclosure, in the depth direction of the bit line groove 101, the thickness of each region of the barrier layer 2 may not be exactly the same. For example, the thickness of the end of the barrier layer 2 close to the semiconductor column 111 is greater than the thickness of the side away from the semiconductor column 111, so as to reduce the risk of metal ions in the conductive material layer 3 subsequently formed inside the bit line groove 101 diffusing along the interface between the insulating portion 112 and the semiconductor column 111 to the word line structure 12 below the insulating portion 112 and the word line contact structure subsequently formed through the insulating portion 112, which helps to reduce the probability of bridging between the bit line structure 4 and the word line structure 12 and the word line contact structure subsequently formed, thereby reducing the probability of leakage or short circuit, and improving product yield.

[0148] like Figure 8 As shown, the bit line structure 4 may be at least partially located in the bit line trench 101 having the barrier layer 2. For example, the bit line structure 4 may include a first conductive layer 41 and a second conductive layer 42, wherein the second conductive layer 42 may be located in the bit line trench 101 above the semiconductor pillar 111, and the material of the second conductive layer 42 may be a metal material, for example, its material may be cobalt (Co). The first conductive layer 41 may be an interface layer formed between the second conductive layer 42 and the semiconductor pillar 111 by the diffusion of metal ions (for example, cobalt (Co)) in the second conductive layer 42 into the semiconductor pillar 111. That is, the first conductive layer 41 may be located on the top of the semiconductor pillar 111, the barrier layer 2 is in contact with the first conductive layer 41 near the end of the semiconductor pillar 111, and the second conductive layer 42 is located in the bit line trench 101 having the barrier layer 2 and in contact with the surface of the first conductive layer 41. When the material of the semiconductor pillar 111 is silicon, the material of the first conductive layer 41 may be metal silicide (such as cobalt silicide (CoSi)), the material of the second conductive layer 42 may be metal (such as cobalt (Co)), and the first conductive layer 41 and the second conductive layer 42 include the same metal.

[0149] In an exemplary embodiment of the present disclosure, Fig. 9 As shown, the semiconductor structure 100 of the present disclosure may further include a passivation layer 7, which may be located on the surface of the bit line structure 4. The passivation layer 7 may fill the remaining gap in the bit line trench 101, and its surface away from the bit line structure 4 is flush with the surface of the insulating portion 112 away from the word line structure 12. The material of the passivation layer 7 may be an insulating material, and the surface of the bit line structure 4 may be insulated and isolated by the passivation layer 7 to reduce the probability of leakage or short circuit between the bit line structure 4 and other structures formed subsequently. For example, the material of the passivation layer 7 may be silicon nitride.

[0150] like Fig.12As shown, the word line contact structure 6 may pass through an insulating portion 112 and be in contact with the word line structure 12. In a direction parallel to the substrate 11, the cross-section of the word line contact structure 6 may be circular, elliptical, rectangular, polygonal or irregular, which is not particularly limited here. In some embodiments of the present disclosure, the material of the word line contact structure 6 may be a conductive material, for example, it may include titanium nitride, tungsten or a combination thereof. For example, the word line contact structure 6 may include a titanium nitride layer 61 and a tungsten layer 62, wherein the titanium nitride layer 61 may be conformally coated on the bottom and sidewalls of the tungsten layer 62, and the titanium nitride layer 61 may be in contact with the surface of the word line structure 12, and the titanium nitride layer 61 may prevent the tungsten in the tungsten layer 62 from diffusing into other surrounding structures, which helps to improve the reliability of the device.

[0151] In an exemplary embodiment of the present disclosure, an insulating layer 5 may be provided between the word line contact structure 6 and the barrier layer 2, the bit line structure 4, and the semiconductor pillar 111. The thickness of the insulating layer 5 may be less than 4 nm, for example, it may be 4 nm, 3.5 nm, 3 nm, 2.5 nm, or 2 nm, etc., and the thickness of the insulating layer 5 is not particularly limited herein. The insulating layer 5 may be located on the sidewall of the word line contact structure 6, so that the bit line structure 4 and the word line contact structure 6 are insulated and isolated by the insulating layer 5, which helps to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6.

[0152] In an exemplary embodiment of the present disclosure, the material of the insulating layer 5 may be silicon nitride. When the material of the blocking layer 2 is titanium nitride or tantalum nitride, since the materials of the insulating layer 5 and the blocking layer 2 are both nitrides, the insulating layer 5 and the blocking layer 2 have better adhesion, and the interface between the insulating layer 5 and the blocking layer 2 is more reliable. Even if the insulating layer 5 on the hole wall is damaged to a certain extent when etching back the insulating layer 5 at the bottom of the contact hole 102, making it weaker, its barrier effect on metal ions can also be guaranteed, reducing the probability of metal ions diffusing from the bit line structure 4 to the word line structure 12, further reducing the probability of leakage or short circuit, and improving product yield.

[0153] The present disclosure also provides a memory device, such as Fig.13 As shown, the memory may include the semiconductor structure 100 in any of the above embodiments, and its specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure 100 and the formation method of the semiconductor structure 100, which will not be repeated here.

[0154] In some embodiments of the present disclosure, the memory of the present disclosure may further include a peripheral circuit 200 , and the peripheral circuit 200 may be bonded to the word line contact structure 6 in the semiconductor structure 100 of the present disclosure.

[0155] For example, during the manufacturing process, the peripheral circuit 200 can be processed separately from the semiconductor structure 100, that is, the peripheral circuit 200 can be formed on a substrate, and then the substrate carrying the peripheral circuit 200 can be coupled to the word line contact structure 6 in the semiconductor structure 100 of the present invention by bonding, so that the peripheral circuit 200 is electrically connected to the word line structure 12 in the semiconductor structure 100, so as to control the word line structure 12 to be opened or closed through the peripheral circuit 200.

[0156] For example, the memory may be a 4F2 3D dynamic random access memory (DRAM) or a static random access memory (SRAM), etc. Of course, other storage devices may also be used, which are not listed here one by one.

[0157] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: An initial semiconductor structure is formed, wherein the initial semiconductor structure includes a substrate and a word line structure, wherein the substrate includes a plurality of semiconductor pillars distributed at intervals and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, wherein the word line structure extends in a direction in which the plurality of semiconductor pillars are distributed at intervals and covers the periphery of each semiconductor pillar; wherein the insulating portion is located on the word line structure, and an end of the insulating portion away from the word line structure is higher than an end of the semiconductor pillar, and a bit line groove is defined by two adjacent insulating portions and the semiconductor pillar therebetween; forming a barrier layer covering the sidewalls of the bit line trench; forming a conductive material layer in the bit line trench having the barrier layer; Performing a heat treatment on the conductive material layer to form a bit line structure; forming a contact hole penetrating the insulating portion and exposing the word line structure; forming an insulating layer on the hole wall of the contact hole; A word line contact structure is formed in the contact hole having the insulating layer.

2. The forming method according to claim 1, characterized in that: The forming of a barrier layer covering the sidewall of the bit line trench comprises: forming a barrier material layer on the sidewalls and bottom of the bit line trench; The barrier material layer is processed by a reverse sputtering process so that the thickness of the barrier material layer at the end close to the semiconductor column is greater than the thickness of the barrier material layer at the side away from the semiconductor column; The barrier material layer is etched back to expose the top surface of the semiconductor column, and the end of the barrier material layer away from the semiconductor column is lower than the surface of the insulating portion away from the word line structure, and the remaining barrier material layer is used as the barrier layer; the surface of the bit line structure away from the semiconductor column is flush with the end of the barrier layer away from the semiconductor column.

3. The forming method according to claim 2, characterized in that: The thickness of the barrier layer is 1 nm to 3 nm; the material of the barrier layer includes titanium nitride or tantalum nitride.

4. The forming method according to claim 2, characterized in that: The forming method further comprises: forming a passivation layer on a surface of a structure formed by the barrier layer, the bit line structure and the insulating portion; The surface of the passivation layer is chemically mechanically polished to make the surface of the passivation layer flush with the surface of the insulating portion away from the word line structure.

5. The forming method according to any one of claims 1 to 4, characterized in that: The step of performing a heat treatment on the conductive material layer to form a bit line structure comprises: Heat-treating the conductive material layer at a preset temperature so that metal ions in the conductive material layer diffuse into the semiconductor column to form a first conductive layer at the interface between the semiconductor column and the conductive material layer; using the conductive material layer after the heat treatment as a second conductive layer; The preset temperature is less than 450°C.

6. The forming method according to any one of claims 1 to 4, characterized in that: Forming the initial semiconductor structure includes: Providing a substrate, the substrate comprising a plurality of first grooves spaced apart and distributed along a first direction, and an insulating material filling the first grooves; Etching the substrate to form a plurality of second grooves spaced apart along a second direction, wherein the second direction intersects the first direction, and each of the second grooves and each of the first grooves divides the substrate into a plurality of semiconductor pillars; Etching back the insulating material to form an insulating portion; forming a word line structure extending along the first direction and covering the periphery of each of the semiconductor pillars spaced apart along the first direction, wherein the word line structure is located on the insulating portion, and a surface thereof away from the insulating portion is lower than a surface of the semiconductor pillar away from the bottom of the first trench; Doping a region of the semiconductor column that is not covered by the word line structure and the insulating portion to form a source region; forming a capacitor structure on the source region; The substrate is etched at a side of the substrate away from the capacitor structure to form the bit line trench.

7. A semiconductor structure, characterized in that: include: An initial semiconductor structure includes a substrate and a word line structure, wherein the substrate includes a plurality of semiconductor pillars distributed at intervals and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extends along the direction in which the plurality of semiconductor pillars are distributed at intervals and covers the periphery of each semiconductor pillar; the insulating portion is located on the word line structure, and an end of the insulating portion away from the word line structure is higher than an end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween define a bit line groove; a barrier layer covering the sidewalls of the bit line trench; a bit line structure at least partially located within the bit line trench having the barrier layer; A word line contact structure, penetrating through the insulating portion and contacting and connecting with the word line structure; An insulating layer is located between the word line contact structure and the barrier layer, the bit line structure and the semiconductor column.

8. The semiconductor structure according to claim 7, characterized in that: The thickness of the barrier layer at an end portion close to the semiconductor pillar is greater than the thickness of the barrier layer at a side away from the semiconductor pillar.

9. The semiconductor structure according to claim 7, characterized in that: The material of the barrier layer includes titanium nitride or tantalum nitride, and the thickness of the barrier layer includes 1 nm to 3 nm.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The bit line structure includes a first conductive layer and a second conductive layer, the first conductive layer is located at the top of the semiconductor column, the barrier layer is in contact with the first conductive layer near the end of the semiconductor column, and the second conductive layer is located in the bit line groove having the barrier layer and in contact with the surface of the first conductive layer.

11. The semiconductor structure according to claim 10, characterized in that: The semiconductor structure further comprises: The passivation layer is located on the surface of the bit line structure, and the surface of the passivation layer away from the bit line structure is flush with the surface of the insulating portion away from the word line structure.

12. The semiconductor structure according to claim 10, characterized in that The surface of the word line structure away from the insulating portion is lower than the surface of the semiconductor column away from the bit line trench, and the area of ​​the semiconductor column not covered by the word line structure and the insulating portion is a source region, and the initial semiconductor structure further includes: A capacitor structure is formed on the source region.

13. A memory, characterized in that: A semiconductor structure comprising any one of claims 7 to 12.

14. The memory according to claim 13, characterized in that: The memory also includes: The peripheral circuit is bonded to the word line contact structure of the semiconductor structure.

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