Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a semiconductor layer, the semiconductor layer comprises a plurality of semiconductor columns which extend in the second direction and are distributed in an array mode in the first direction and the third direction, and every two of the first direction, the second direction and the third direction intersect. The method for manufacturing the semiconductor structure comprises the following steps: forming a first gate structure extending along a third direction on the side wall of a semiconductor column; forming a second gate structure extending along the first direction on the side wall of the semiconductor column, wherein the second gate structure and the first gate structure are arranged at an interval along the second direction; and forming bit lines connected to the semiconductor pillars and extending in the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for manufacturing the semiconductor structure, a memory, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the storage density of semiconductor structures increases, the number of storage units increases, the size decreases, and the spatial density increases, which makes the capacitance between adjacent components (such as adjacent bit lines) increase, which has a great impact on the performance of semiconductor structures. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The semiconductor layer includes a plurality of semiconductor pillars extending along a second direction and distributed in an array along a first direction and a third direction, wherein the first direction, the second direction and the third direction intersect each other, and the method includes: forming a first gate structure extending along the third direction on the sidewall of the semiconductor pillar; forming a second gate structure extending along the first direction on the sidewall of the semiconductor pillar, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and forming a bit line connected to the semiconductor pillar and extending along the first direction.

[0005] In one embodiment, the bit line is adjacent to the first gate structure along the second direction, and the method includes: forming a first gate lead-out structure and a bit line lead-out structure respectively connected to the first gate structure and the bit line from a first side of the semiconductor layer; and forming a second gate lead-out structure connected to the second gate structure from a second side of the semiconductor layer opposite to the first side.

[0006] In one embodiment, a first gate structure extending along the third direction is formed on the sidewall of the semiconductor column, including: forming a plurality of initial semiconductor columns extending along the first direction and the second direction in the semiconductor layer; forming a plurality of first trenches passing through the initial semiconductor columns and extending along the third direction and arranged along the first direction, wherein the plurality of first trenches divide the initial semiconductor columns into a plurality of semiconductor columns extending along the second direction; and forming the first gate structure and the isolation layer in the first trenches extending along the third direction and adjacently distributed along the second direction.

[0007] In one embodiment, the method further includes: forming a second trench passing through the semiconductor pillar and extending along a third direction; and forming an isolation structure in the second trench.

[0008] In one embodiment, the first gate structure and the isolation layer extending along the third direction and adjacently distributed along the second direction are formed in the first trench, including: forming a first gate dielectric layer extending along the third direction in the first trench; forming a first gate layer on the surface of the first gate dielectric layer, wherein the first gate layer and the first gate dielectric layer are adjacently distributed along the first direction, and the first gate structure includes the first gate layer and the first gate dielectric layer; and forming the isolation layer on the surface of the first gate structure.

[0009] In one embodiment, a plurality of the initial semiconductor columns extending along the first direction and the second direction are formed in the semiconductor layer, including: a plurality of isolation columns extending along the first direction and the second direction are formed in the semiconductor layer, wherein the plurality of isolation columns divide a portion of the semiconductor layer into a plurality of the initial semiconductor columns, and the initial semiconductor columns and the isolation columns are alternately arranged along the third direction.

[0010] In one embodiment, forming a second gate structure extending along the first direction on the sidewall of the semiconductor column includes: forming the second gate structure extending along the first direction on at least one sidewall of a first sidewall and a second sidewall of the semiconductor column that are opposite to each other along the third direction.

[0011] In one embodiment, the method includes: forming a third trench passing through the isolation layer and the isolation column and extending along the first direction; and forming the second gate structure through the third trench.

[0012] In one embodiment, the second gate structure includes a first sub-gate structure and a second sub-gate structure, and the second gate structure extending along the first direction is formed on the sidewall of the semiconductor column, including: forming the first sub-gate structure extending along the first direction on at least one sidewall of the first sidewall and the second sidewall of the semiconductor column that are opposite to each other along the third direction; and forming the second sub-gate structure on at least one sidewall of the third sidewall and the fourth sidewall of the semiconductor column that are opposite to each other along the first direction.

[0013] In one embodiment, the method includes: forming a third trench passing through the isolation layer and the isolation column and extending along the first direction, and a fourth trench passing through the isolation layer and extending along the third direction; and forming the first sub-gate structure and the second sub-gate structure via the third trench and the fourth trench, respectively.

[0014] In one embodiment, the bit line is connected to a first end of the semiconductor column, and the method further includes: forming a capacitor connected to a second end of the semiconductor column, wherein the second end is located on a side of the semiconductor column away from the first end.

[0015] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a plurality of semiconductor pillars extending along a second direction and arranged in an array along a first direction and a third direction, wherein the first direction, the second direction and the third direction intersect each other; a first gate structure located on the sidewall of the semiconductor pillar and extending along the third direction; a second gate structure located on the sidewall of the semiconductor pillar and extending along the first direction, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and a bit line connected to the semiconductor pillar and extending along the first direction.

[0016] In one embodiment, the second gate structure is located on at least one sidewall of a first sidewall and a second sidewall of the semiconductor pillar that are opposite to each other along the third direction.

[0017] In one embodiment, the second gate structure includes: a first sub-gate structure located on at least one side wall of a first side wall and a second side wall of the semiconductor column that are opposite to each other along the third direction; and a second sub-gate structure located on at least one side wall of a third side wall and a fourth side wall of the semiconductor column that are opposite to each other along the first direction.

[0018] In one embodiment, the first gate structure is located on at least one sidewall of a third sidewall and a fourth sidewall of the semiconductor pillar that are opposite to each other along the first direction.

[0019] In one embodiment, the semiconductor structure further includes: an isolation structure located between two adjacent semiconductor pillars arranged along the first direction.

[0020] In one embodiment, the first gate structure includes a first gate dielectric layer located on the sidewall of the semiconductor column and a first gate layer located outside the first gate dielectric layer; and the second gate structure includes a second gate dielectric layer located on the sidewall of the semiconductor column and a second gate layer located outside the second gate dielectric layer.

[0021] In one embodiment, the isolation structure includes a conductive layer and / or an air gap layer.

[0022] In one embodiment, the bit line is connected to a first end of the semiconductor column, and the semiconductor structure further includes: a capacitor connected to a second end of the semiconductor column, wherein the second end is located on a side of the semiconductor column away from the first end.

[0023] In one embodiment, the semiconductor structure includes a plurality of first gate structures and a plurality of second gate structures, wherein, in response to turning on a preset first gate structure among the plurality of first gate structures and a preset second gate structure among the plurality of second gate structures to address a preset semiconductor column among the plurality of semiconductor columns and a preset bit line connected to the preset semiconductor column, the preset bit line is placed in a sensing state and a bit line adjacent to the preset bit line is placed in a non-sensing state.

[0024] On the other hand, the present application provides a memory, which includes: a memory cell array, including the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0025] Another aspect of the present application provides a storage system, which includes at least one memory; and a controller coupled to the semiconductor structure and used to control the memory to store data.

[0026] In one or more embodiments of the present application, by forming a first gate structure and a second gate structure on the side wall of the semiconductor column, the semiconductor column can be connected to the two gate structures (i.e., the first gate structure and the second gate structure), which is conducive to controlling the conduction of the semiconductor column by at least two gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0028] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0029] Figure 2 and Figure 3 They are partial structural schematic diagrams of a semiconductor layer provided according to an exemplary embodiment of the present application on a plane formed by a first direction and a third direction and on a plane formed by a third direction and a second direction;

[0030] Figure 4 and Figure 5 are schematic diagrams of structures for forming an initial semiconductor column and an isolation column according to an exemplary embodiment of the present application, wherein: Figure 5for Figure 4 Schematic diagram of a partial cross section along the AA direction;

[0031] Figure 6 and Figure 7 Schematic diagrams of the structure of the first groove formed on the plane formed in the first direction and the second direction and the plane formed in the third direction and the first direction according to the exemplary embodiment of the present application, respectively, wherein: Figure 7 for Figure 6 Schematic diagram of a partial cross section along the BB direction;

[0032] Figure 8 and Fig. 9 are schematic diagrams of structures for forming a first dielectric layer and a third dielectric layer according to exemplary embodiments of the present application, wherein: Fig. 9 for Figure 8 Schematic diagram of a partial cross section along the BB direction;

[0033] Fig.10 and Fig.11 is a schematic diagram of a structure for forming a first gate dielectric layer and a first gate layer according to an exemplary embodiment of the present application, wherein: Fig.11 for Fig.10 Schematic diagram of a partial cross section along the BB direction;

[0034] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a second dielectric layer, an isolation layer and a through hole according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 Schematic diagram of a partial cross section along the BB direction;

[0035] Fig.14 is a partial structural schematic diagram of a first gate structure provided according to an exemplary embodiment of the present application;

[0036] Fig.15 and Fig.16 is a schematic diagram of a structure for forming an isolation structure and a barrier layer according to an exemplary embodiment of the present application, wherein: Fig.16 for Fig.15 Schematic diagram of a partial cross section along the BB direction;

[0037] Fig.17 for Fig.15 Schematic diagram of a partial cross section along the CC direction;

[0038] Fig.18 for Fig.17 Schematic diagram of a partial cross section along the DD direction;

[0039] Fig.19 and Fig. 20They are schematic diagrams of structures for forming a third groove according to exemplary embodiments of the present application, wherein: Fig. 20 for Fig.19 Schematic diagram of a partial cross section along the DD direction;

[0040] Fig.21 and Fig. 22 They are schematic diagrams of structures for forming a second gate structure according to an exemplary embodiment of the present application, wherein: Fig. 22 for Fig.21 Schematic diagram of a partial cross section along the DD direction;

[0041] Fig.23 and Fig.24 are schematic diagrams of structures for forming a third trench and a fourth trench according to another exemplary embodiment of the present application, wherein: Fig.24 for Fig.23 Schematic diagram of a partial cross section along the DD direction;

[0042] Figure 25 to Figure 27 are schematic diagrams of structures for forming a second gate structure according to another exemplary embodiment of the present application, wherein: Fig.26 for Fig.25 Schematic diagram of a partial cross section along the DD direction, Fig. 27 for Fig.25 Schematic diagram of a partial cross section along the EE direction;

[0043] Fig.28 is a schematic diagram of a structure for forming a capacitor according to an exemplary embodiment of the present application;

[0044] Fig.29 For the general Fig.28 Schematic diagram of the structure after the structure is flipped 180° and thinned;

[0045] Figure 30 to Figure 32 It is a schematic diagram of a part of the structure of a semiconductor structure after forming a bit line according to an exemplary embodiment of the present application on a plane formed by a first direction X and a second direction Z, a plane formed by the first direction X and a third direction Y, and a plane formed by the third direction Y and the second direction Z;

[0046] Fig.33 is a schematic block diagram of a memory according to an exemplary embodiment of the present application;

[0047] Fig.34 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0048] Fig.35A and Fig.35B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0050] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first gate structure discussed in this application may also be referred to as the second gate structure, the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0051] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0052] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0053] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0054] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0056] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0057] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0058] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0059] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0060] The semiconductor layer may include a plurality of semiconductor pillars extending along the second direction and distributed in an array along the first direction and the third direction, wherein the first direction, the second direction and the third direction intersect each other. Figure 1As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a first gate structure extending along a third direction on a sidewall of a semiconductor pillar; S1200, forming a second gate structure extending along a first direction on the sidewall of the semiconductor pillar, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and S1300, forming a bit line connected to the semiconductor pillar and extending along the first direction. Steps S1100 to S1300 will be described in detail below.

[0061] In the exemplary embodiment of the present application, Figure 6 and Figure 7 As shown, the semiconductor layer 1100 may include a plurality of semiconductor pillars 1110 extending along the second direction Z and distributed in an array along the first direction X and the third direction Y. The first direction X, the second direction Z, and the third direction Y may intersect each other.

[0062] The material of the semiconductor layer 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0063] For example, the plurality of semiconductor pillars 1110 may be formed by removing a portion of the semiconductor layer 1100. In other words, the portion of the semiconductor layer 1100 that is not removed may include the plurality of semiconductor pillars 1110. Therefore, the semiconductor pillars 1110 may have the same material as the portion of the semiconductor layer 1100 that is not removed, such as single crystal silicon.

[0064] Exemplarily, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose four sidewalls thereof. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a plan view (e.g., in an XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0065] In the exemplary embodiment of the present application, Fig.12 and Fig.13 As shown, a first gate structure 1200 extending along a third direction Y may be formed on the sidewall of the semiconductor pillar 1110 .

[0066] The first gate structure 1200 may be located on the sidewall of the semiconductor pillar 1110 and may extend along the third direction Y. The first gate structure 1200 may include a first gate dielectric layer 1210 and a first gate layer 1220. The first gate dielectric layer 1210 may be located on the sidewall of the semiconductor pillar 1110. The first gate layer 1220 may be located on the inner side of the first gate dielectric layer 1210, such as on the inner side surface of the first gate dielectric layer 1210.

[0067] For example, the first gate structure 1200 may further include a dielectric layer (including a first dielectric layer 1230 and a third dielectric layer 1240) and a second dielectric layer 1250. The dielectric layer may be located at the first gate structure 1200 near the first end 1111 of the semiconductor pillar 1110, wherein the third dielectric layer 1240 may surround a portion of the first dielectric layer 1230, and the first gate layer 1220 and the first gate dielectric layer 1210 may be located on the dielectric layer. The second dielectric layer 1250 may be located on the first dielectric layer 1230 and may be located on the surface of the first gate layer 1220.

[0068] For example, two adjacent first gate structures 1200 may be symmetrically distributed along the second direction Z. The first dielectric layer 1230, the second dielectric layer 1250, and the third dielectric layer 1240 in the two partially symmetrical first gate structures 1200 are continuous. In other words, the first dielectric layer 1230 in the two partially symmetrical first gate structures 1200 may be connected to form an integral structure, the second dielectric layer 1250 in the two first gate structures 1200 may be connected to form an integral structure, and the third dielectric layer 1240 in the two first gate structures 1200 may be connected to form an integral structure. Fig.14 As shown, a partial structural diagram of a first gate structure 1200 is shown.

[0069] By way of example, the semiconductor pillar 1110 and the first gate structure 1200 may be used together to form a vertical transistor, wherein the semiconductor pillar 1110 may be used to form an active region of multiple channels in the vertical transistor. By way of example, the first gate structure 1200 may be located on at least one sidewall of the semiconductor pillar 1110, i.e., the semiconductor pillar 1110 may be at least partially surrounded by the first gate structure 1200. For example, the semiconductor pillar 1110, the first gate dielectric layer 1210, and the first gate layer 1220 may be radially arranged in this order from the center of the vertical transistor. By way of example, the first gate dielectric layer 1210 may surround and contact the semiconductor pillar 1110. The first gate layer 1220 may surround and contact the first gate dielectric layer 1210. The first gate layer 1220 may be a composite layer structure.

[0070] It should be understood that Fig.12 and Fig.13The situation in which the first gate structure 1200 is located on at least two sidewalls of the semiconductor pillar 1110 is only an example and is not specifically limited. Fig.15 and Fig.16 An example in which the first gate structure 1200 is located on a sidewall of the semiconductor pillar 1110 is shown.

[0071] In one embodiment of the present application, Fig.12 and Fig.13 As shown, the first gate structure 1200 may be located on multiple sidewalls of the semiconductor column 1110, and the semiconductor column 1110 and the first gate structure 1200 may be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0072] In another embodiment of the present application, Fig.15 and Fig.16 As shown, the first gate structure 1200 may be located on a side wall of the semiconductor column 1110, and the semiconductor column 1110 and the first gate structure 1200 may be used together to form a single-gate transistor. For example, the single-gate transistors adjacent to each other along the first direction X may be arranged symmetrically. By providing single-gate transistors, the present application can significantly increase the density of the semiconductor column 1110 in the first direction X and reduce the difficulty of the manufacturing process. In addition, the symmetrically distributed single-gate transistors may have a larger process window, which is conducive to reducing the spacing between the bit lines, word lines and transistors formed subsequently.

[0073] like Figures 2 to 13 As shown, the present application provides a process step diagram for forming a first gate structure 1200 extending along a third direction Y on the sidewall of a semiconductor pillar 1110. It should be understood that the process for forming the first gate structure 1200 provided in the present application is only an example and is not specifically limited. In the actual process, the process for forming the first gate structure 1200 can be reasonably set according to actual needs.

[0074] like Figures 2 to 13 As shown, forming a first gate structure 1200 extending along a third direction Y on the sidewall of the semiconductor pillar 1110 may include: forming a plurality of initial semiconductor pillars 1130 ( Figure 4 and Figure 5); forming a plurality of first trenches passing through the initial semiconductor column 1110 and extending along the third direction Y and arranged along the first direction X, wherein the plurality of first trenches divide the initial semiconductor column 1110 into a plurality of semiconductor columns 1110 extending along the second direction Z ( Figure 6 and Figure 7 ); and forming a first gate structure 1200 and an isolation layer 1300 extending along the third direction Y and adjacently distributed along the second direction Z on the sidewall of the semiconductor column 1110 via the first trench ( Fig.12 and Fig.13 ).

[0075] Figure 2 and Figure 3 1 and 2 are partial structural schematic diagrams of the semiconductor layer 1100 provided according to an exemplary embodiment of the present application on a plane formed by the first direction X and the third direction Y and on a plane formed by the third direction Y and the second direction Z. For example, Figure 3 As shown, a first dielectric layer 1141 and a second dielectric layer 1142 stacked in sequence may be formed on the surface of the semiconductor layer 1100. For example, the first dielectric layer 1141 and the second dielectric layer 1142 may be etched to form a patterned mask.

[0076] The material of the first dielectric layer 1141 may include an oxide such as silicon oxide. The material of the second dielectric layer 1142 may include a nitride such as silicon nitride. In an exemplary embodiment, the first dielectric layer 1141 and the second dielectric layer 1142 may be deposited by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 1141 may be formed by oxidizing the surface of the semiconductor layer 1100 by an oxidation process such as oxidation.

[0077] Figure 4 and Figure 5 are schematic diagrams of structures for forming an initial semiconductor column 1130 and an isolation column 1150 according to an exemplary embodiment of the present application, wherein: Figure 5 for Figure 4 A partial cross-sectional view along the AA direction. For example, Figure 4 and Figure 5 As shown, a plurality of initial semiconductor pillars 1130 extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100 .

[0078] For example, a plurality of isolation columns 1150 extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100, wherein the plurality of isolation columns 1150 may divide a portion of the semiconductor layer 1100 into a plurality of initial semiconductor columns 1130. The initial semiconductor columns 1130 and the isolation columns 1150 may be alternately arranged along the third direction Y. For example, a plurality of grooves (not shown) extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100; and the isolation columns 1150 may be formed in the grooves, wherein the semiconductor layer 1100 that is not removed forms the initial semiconductor columns 1130.

[0079] Exemplarily, the second dielectric layer 1142, the first dielectric layer 1141, and the semiconductor layer 1100 may be etched by an etching process to form a groove and an initial semiconductor pillar 1130. For example, the second dielectric layer 1142 and the first dielectric layer 1141 may be etched by a photolithography process to form a patterned mask, wherein the second dielectric layer 1142 may be used as a bottom anti-reflective layer for photolithography, and the first dielectric layer 1141 may be used as a hard mask; then, the semiconductor layer 1100 is etched by one or more dry etching and / or wet etching processes using the patterned mask as a mask to form a groove in the semiconductor layer 1100, wherein the semiconductor layer 1100 that is not removed may form the initial semiconductor pillar 1130.

[0080] By way of example, the material of the isolation column 1150 may include, but is not limited to, an insulating material such as oxide. By way of example, the isolation column 1150 may be formed by depositing an insulating material in the groove by, for example, a thin film deposition process, so that adjacent initial semiconductor columns 1130 are isolated by the isolation column 1150. In addition, a planarization process such as a mechanical grinding process may be performed to remove the insulating material on the surface of the second dielectric layer 1142.

[0081] Figure 6 and Figure 7 Schematic diagrams of the structure of the first groove 100 formed on the plane formed by the first direction X and the second direction Z and the plane formed by the third direction Y and the first direction X according to an exemplary embodiment of the present application, wherein: Figure 7 for Figure 6 A partial cross-sectional schematic diagram along the BB direction. For example, Figure 6 and Figure 7 As shown, a plurality of first trenches 100 may be formed passing through the initial semiconductor pillar 1130 and extending along the third direction Y and arranged along the first direction X, wherein the plurality of first trenches 100 may divide the initial semiconductor pillar 1130 into a plurality of semiconductor pillars 1110 extending along the second direction Z.

[0082] For example, one or more dry etching and / or wet etching processes may be used to etch and form the first trench 100. The first trench 100 may divide the initial semiconductor pillar 1130 into a plurality of semiconductor pillars 1110. The present application forms the semiconductor pillars 1110 by etching the semiconductor layer 1100, so the semiconductor pillars 1110 may have the same material as the semiconductor layer 1100 and may extend along the second direction Z in the semiconductor layer 1100.

[0083] Figures 8 to 13 It is a process step diagram for forming a first gate structure 1200 and an isolation layer 1300 provided in the present application.

[0084] like Figures 8 to 13 As shown, a first gate structure 1200 and an isolation layer 1300 extending along the third direction Y and adjacently distributed along the second direction Z can be formed on the sidewall of the semiconductor pillar 1110 via the first trench 100. Exemplarily, the first gate structure 1200 can be formed in the first trench 100 near the first end 1111 of the semiconductor pillar 1110, and the isolation layer 1300 can be formed on the surface of the first gate structure 1200. Exemplarily, two symmetrically distributed first gate structures 1200 can be formed in the first trench 100, wherein Fig.14 A partial structural schematic diagram of a first gate structure 1200 is shown.

[0085] Exemplarily, a first gate structure 1200 and an isolation layer 1300 extending along a third direction Y and adjacently distributed along a second direction Z are formed on the sidewall of a semiconductor pillar 1110 via the first trench 100, which may include: forming a first gate dielectric layer 1210 extending along a third direction Y on the sidewall of the semiconductor pillar 1110 via the first trench 100; forming a first gate 1220 layer on the surface of the first gate dielectric layer 1210, wherein the first gate layer 1220 and the first gate dielectric layer 1210 may be adjacently distributed along the first direction X, and the first gate structure 1200 includes the first gate layer 1220 and the first gate dielectric layer 1210; and forming an isolation layer 1300 on the surface of the first gate structure 1200.

[0086] Specifically, Figure 8 and Fig. 9 are schematic diagrams of structures for forming a first dielectric layer 1230 and a third dielectric layer 1240 according to exemplary embodiments of the present application, wherein: Fig. 9 for Figure 8 A partial cross-sectional schematic diagram along the BB direction. For example, Figure 8 and Fig. 9As shown, a first dielectric layer 1230 may be formed in a region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110; and a portion of the first dielectric layer 1230 may be removed along the second direction Z. For example, one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, may be used to deposit and form the first dielectric layer 1230. The material of the first dielectric layer 1230 includes but is not limited to silicon oxide. Exemplarily, before forming the first dielectric layer 1230, a third dielectric layer 1240 may be deposited on a portion of the sidewall of the first trench 100 to partially fill the first trench 100. Exemplarily, a portion of the first dielectric layer 1230 may be removed along the second direction Z, so that the remaining first dielectric layer 1230 covers the bottom surface of the first trench 100.

[0087] Fig.10 and Fig.11 is a schematic diagram of a structure of forming a first gate dielectric layer 1210 and a first gate layer 1220 according to an exemplary embodiment of the present application, wherein: Fig.11 for Fig.10 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.10 and Fig.11 As shown, a first gate dielectric layer 1210 extending along a third direction Y can be formed in a region of the first trench 100 close to the first end 1111 of the semiconductor pillar 1110; and a first gate layer 1220 can be formed on the surface of the first gate dielectric layer 1210, wherein the first gate layer 1220 and the first gate dielectric layer 1210 are adjacently distributed along the first direction X.

[0088] By way of example, the first gate dielectric layer 1210 may be a portion of a continuous third dielectric layer 1240 formed on the sidewalls of the semiconductor pillar 1110 extending along the second direction Z. The first gate dielectric layer 1210 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first gate dielectric layer 1210 may include silicon oxide, i.e., a gate oxide. By way of example, a wet oxidation and / or dry oxidation process, such as an in-situ steam oxidation process, may be performed to form the first gate dielectric layer 1210 in a region of the first trench 100 near the first end 1111 of the semiconductor pillar 1110.

[0089] Then, a first gate layer 1220 may be formed on the surface of the first gate dielectric layer 1210. Exemplarily, the first gate layer 1220 may be formed by depositing one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and titanium nitride TiN on the surface of the first gate dielectric layer 1210 through one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof to form the first gate layer 1220. For example, TiN and W may be deposited in sequence to form the first gate layer 1220, wherein TiN may surround W.

[0090] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a second dielectric layer 1250, an isolation layer 1300 and a through hole 200 according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.12 As shown, a portion of the first gate layer 1220 may be removed along the second direction Z, such as removing portion W, to form a first gap (not shown); a second gap (not shown) may be formed along the second direction Z through the first gate layer 1220 to expose the first dielectric layer 1230, such as removing TiN exposed at the bottom to expose the first dielectric layer 1230; and a second dielectric layer 1250 may be formed in the first gap and the second gap. Exemplarily, the third dielectric layer 1240, the first dielectric layer 1230, the second dielectric layer 1250, the first gate dielectric layer 1210, and the first gate layer 1220 that is not removed may be used to form the first gate structure 1200. Specifically, Fig.14 A partial structural schematic diagram of a first gate structure 1200 is shown, and the third dielectric layer 1240, the first dielectric layer 1230, the second dielectric layer 1250, the first gate dielectric layer 1210 and the first gate layer 1220 that is not removed in the first trench 100 can be used to form at least two symmetrically distributed first gate structures 1200. The first gate layer 1220 can extend along the third direction Y, and its portion corresponding to the semiconductor pillar 1110 can be used as a first gate electrode; the remaining portion can be used as a first word line for connecting the first gate electrode to a peripheral circuit, so as to transmit electrical signals between the first gate electrode and the peripheral circuit.

[0091] For example, the second gap may be formed by an etching process such as punch-down etching, dry etching and / or wet etching to form two disconnected first gate structures 1200 in the first trench 100. For example, a bottom punch-down etching process may be used to disconnect the first gate structure 1200 at the bottom of the first trench 100 until the first dielectric layer 1230 is exposed.

[0092] For example, Fig.12As shown, an isolation layer 1300 may be formed on the surface of the first gate structure 1200. In other words, the isolation layer 1300 may be formed on the surfaces of the first gate dielectric layer 1210, the first gate layer 1220, and the second dielectric layer 1250. In the present application, the first gate structure 1200 may be located in a region of the first trench 100 close to the first end 1111 of the semiconductor pillar 1110, and the isolation layer 1300 may be located in a region of the first trench 100 close to the second end 1112 of the semiconductor pillar 1110.

[0093] Exemplarily, the isolation layer 1300 and the second dielectric layer 1250 may be formed in the same process step. Exemplarily, one or more thin film deposition processes may be used to deposit the second dielectric layer 1250 and the isolation layer 1300 in the first gap, the second gap, and the first trench 100, near the second end 1112 of the semiconductor pillar 1110. In other words, the second dielectric layer 1250 and the isolation layer 1300 may be deposited in the remaining space of the first trench 100. The second dielectric layer 1250 and the isolation layer 1300 may include the same material, such as any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second dielectric layer 1250 and the isolation layer 1300 may include silicon oxide. In addition, a planarization process such as a mechanical grinding process may be performed to remove the isolation layer 1300, the second dielectric layer 1142, and the first dielectric layer 1141 on the top surface of the semiconductor pillar 1110.

[0094] For example, Fig.13 As shown, a through hole 200 penetrating the first gate dielectric layer 1210 and the first gate layer 1220 along the second direction Z may be formed to separate the annular first gate structure 1200 in the first trench 100 into at least two parts. For example, two through holes 200 with a certain interval may be formed in each annular first gate structure 1200 to separate the annular first gate structure 1200 into two parts. In other words, the two through holes 200 separate the annular first gate dielectric layer 1210 into two parts, and separate the first gate layer 1220 into two parts.

[0095] It should be understood that the present application does not specifically limit the size and / or position of the through hole 200 , and the size and / or position of the through hole 200 may be arbitrarily set according to the actual process to separate the first gate structure 1200 in the first trench 100 into two parts.

[0096] Fig.15 and Fig.16 1 is a schematic diagram of a structure for forming an isolation structure 1400 and a barrier layer 1500 according to an exemplary embodiment of the present application, wherein: Fig.16 for Fig.15 A partial cross-sectional schematic diagram along the BB direction. For example, Fig.15 and Fig.16 As shown, a second trench (not shown) is formed passing through the semiconductor pillar 1110 and extending along the third direction Y; and an isolation structure 1400 is formed in the second trench. In other words, the formed isolation structure 1400 divides each semiconductor pillar 1110 into two semiconductor pillars 1110, that is, the isolation structure 1400 can be located between two adjacent semiconductor pillars 1110 arranged along the first direction X.

[0097] By way of example, the second trench may be formed by etching using one or more dry etching and / or wet etching processes, and the isolation structure 1400 and / or the barrier layer 1500 may be formed by using one or more thin film deposition processes. The second trench may divide each semiconductor pillar 1110 into two semiconductor pillars 1110. By way of example, the isolation structure 1400 may be formed in the second trench near the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 may be formed on the surface of the isolation structure 1400. That is, the isolation structure 1400 may be located in a region of the second trench near the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 may be located in a region of the second trench near the second end 1112 of the semiconductor pillar 1110. In other words, the height of the isolation structure 1400 may be substantially the same as that of the first gate structure 1200, and the height of the barrier layer 1500 may be substantially the same as that of the isolation layer 1300.

[0098] Exemplarily, the isolation structure 1400 may include a conductive layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or a conductive layer (such as a metal material layer) may be formed in the second trench according to the spacing of the semiconductor pillars 1110, such as the size of the second trench along the first direction X. The barrier layer 1500 may include an insulating layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or an insulating layer (such as an oxide material layer) may be formed on the surface of the isolation structure 1400 according to the spacing of the semiconductor pillars 1110, such as the size of the second trench along the first direction X.

[0099] For example, if the isolation structure 1400 includes a conductive layer, an isolation lead structure (not shown) connected to the isolation structure 1400 may be formed. In the present application, the isolation lead structure may be grounded or a certain fixed potential may be applied to the isolation lead structure, so that the isolation structure 1400 can electrically insulate adjacent semiconductor pillars 1110 and reduce coupling between adjacent semiconductor pillars 1110.

[0100] Fig.17 for Fig.15 Schematic diagram of a partial cross section along the CC direction. Fig.18 for Fig.17 Schematic diagram of a partial cross section along the DD direction. Figures 19 to 22It is a process step diagram for forming a second gate structure 1600 provided in the present application. Figure 23 to Figure 27 1 is another process step diagram for forming the second gate structure 1600 provided by the present application. It should be understood that the process for forming the second gate structure 1600 provided by the present application is only an example and is not specifically limited. In the actual process, the process for forming the second gate structure 1600 can be reasonably set according to actual needs.

[0101] In an exemplary embodiment of the present application, Fig.21 and Fig. 22 As shown, a second gate structure 1600 extending along the first direction X may be formed on the sidewall of the semiconductor pillar 1110 , wherein the second gate structure 1600 and the first gate structure 1200 are spaced apart along the second direction Z.

[0102] Exemplarily, forming the second gate structure 1600 extending along the first direction X on the sidewall of the semiconductor pillar 1110 may include: forming the second gate structure 1600 extending along the first direction X on at least one sidewall of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110 that are opposite to each other along the third direction Y. Exemplarily, as Figures 19 to 22 As shown, a third trench 300 ( Fig.19 and Fig. 20 ); and forming a second gate structure 1600 ( Fig.21 and Fig. 22 ).

[0103] Specifically, Fig.19 and Fig. 20 They are schematic diagrams of the structure of forming the third trench 300 according to an exemplary embodiment of the present application, wherein: Fig. 20 for Fig.19 A partial cross-sectional view along the DD direction. For example, Fig.19 and Fig. 20 As shown, a third trench 300 may be formed that passes through the isolation layer 1300 and the isolation column 1150 and extends along the first direction X. By way of example, the third trench 300 and the first gate structure 1200 may be spaced apart along the second direction Z. In other words, the third trench 300 and the first gate structure 1200 are not connected, and the two may be spaced apart by the isolation layer 1300. By way of example, the third trench 300 may be formed by etching using one or more dry etching and / or wet etching processes.

[0104] Fig.21 and Fig. 22 They are schematic diagrams of structures for forming a second gate structure 1600 according to an exemplary embodiment of the present application, wherein: Fig. 22for Fig.21 Schematic diagram of a partial cross section along the DD direction. Fig.21 and Fig. 22 As shown, the second gate structure 1600 may be formed through the third trench 300. For example, the second gate structure 1600 extending along the first direction X may be formed on at least one sidewall of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110 that are opposite to each other along the third direction Y. For example, Fig.21 and Fig. 22 It is shown that the second gate structure 1600 may be formed on both the first sidewall 1113 and the second sidewall 1114 .

[0105] For example, the second gate structure 1600 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located outside the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are sequentially arranged along the third direction Y.

[0106] Exemplarily, the second gate dielectric layer 1610 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second gate dielectric layer 1610 may include silicon oxide, i.e., a gate oxide. The second gate layer 1620 may include any suitable conductive material, such as a metal and / or a metal compound. For example, the second gate layer 1620 may include metal tungsten.

[0107] Exemplarily, the second gate layer 1620 may be formed by depositing a conductive material in the third trench 300 ; then the second gate dielectric layer 1610 may be formed by removing the conductive material on at least one of the first sidewall 1113 and the second sidewall 1114 , and depositing a dielectric material.

[0108] Exemplarily, two symmetrically distributed second gate structures 1600 may be formed in the third trench 300. For example, two second gate layers 1620 may be formed by filling the third trench with a dielectric material 1630 and isolating the conductive material. Exemplarily, the second gate layer 1620 may extend along the first direction X, and its portion corresponding to the semiconductor column 1110 may serve as a second gate electrode; and its remaining portion may serve as a second word line for connecting the second gate electrode to a peripheral circuit, so as to transmit electrical signals between the second gate electrode and the peripheral circuit. In the present application, the first gate structure 1200 and the second gate structure 1600 work together to realize the conduction of the semiconductor column 1110.

[0109] In another exemplary embodiment of the present application, Figure 25 to Figure 27As shown, the second gate structure 1600 may include a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2. Forming the second gate structure 1600 extending along the first direction X on the sidewall of the semiconductor column 1110 may include: forming the first sub-gate structure 1600-1 extending along the first direction X on at least one sidewall of the first sidewall 1113 and the second sidewall 1114 of the semiconductor column 1110 that are opposite to each other along the third direction Y ( Fig.25 and Fig.26 ); and forming a second sub-gate structure 1600-2 ( Fig.25 and Fig. 27 ). For example, Figure 23 to Figure 27 As shown, a third trench 300 passing through the isolation layer 1300 and the isolation column 1150 and extending along the first direction X, and a fourth trench 400 passing through the isolation layer 1300 and extending along the third direction Y may be formed. Fig.23 and Fig.24 ); a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2 are formed respectively through the third trench 300 and the fourth trench 400 ( Figure 25 to Figure 27 ).

[0110] Specifically, Fig.23 and Fig.24 are schematic diagrams of structures for forming a third trench 300 and a fourth trench 400 according to an exemplary embodiment of the present application, wherein: Fig.24 for Fig.23 A partial cross-sectional view along the DD direction. For example, Fig.23 and Fig.24 As shown, a third trench 300 is formed passing through the isolation layer 1300 and the isolation column 1150 and extending along the first direction X, and a fourth trench 400 is formed passing through the isolation layer 1300 and extending along the third direction Y. Exemplarily, the third trench 300 and the fourth trench 400 may be spaced apart from the first gate structure 1200 along the second direction Z. In other words, the third trench 300 (or the fourth trench 400) and the first gate structure 1200 are not connected, and the two may be spaced apart by the isolation layer 1300. Exemplarily, the third trench 300 and the fourth trench 400 may be formed by etching using one or more dry etching and / or wet etching processes.

[0111] Figure 25 to Figure 27 They are schematic diagrams of structures for forming a second gate structure 1600 according to an exemplary embodiment of the present application, wherein: Fig.26 for Fig.25 Schematic diagram of a partial cross section along the DD direction, Fig. 27 for Fig.25Schematic diagram of a partial cross section along the EE direction. Figure 25 to Figure 27 As shown, a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2 may be formed respectively through the third trench 300 and the fourth trench 400. For example, the first sub-gate structure 1600-1 extending along the first direction X may be formed on at least one of the first sidewalls 1113 and the second sidewalls 1114 of the semiconductor pillar 1110 that are opposite to each other along the third direction Y; and the second sub-gate structure 1600-2 may be formed on at least one of the third sidewalls 1115 and the fourth sidewalls 1116 of the semiconductor pillar 1110 that are opposite to each other along the first direction X. For example, Fig.25 and Fig.26 It is shown that a first sub-gate structure 1600 - 1 may be formed on both the first sidewall 1113 and the second sidewall 1114 , and Fig.25 and Fig. 27 It is shown that the second sub-gate structure 1600 - 2 may be formed on both the third sidewall 1115 and the fourth sidewall 1116 .

[0112] For example, the first sub-gate structure 1600-1 and / or the second sub-gate structure 1600-2 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located on the outer surface of the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are sequentially distributed from the center to the outside.

[0113] Exemplarily, the second gate layer 1620 can be formed by depositing a conductive material in the third trench 300 and / or the fourth trench 400; then the second gate dielectric layer 1610 can be formed by removing the conductive material on at least one of the first sidewall 1113, the second sidewall 1114, the third sidewall 1115 and the fourth sidewall 1116, and depositing a dielectric material.

[0114] By way of example, two symmetrical first sub-gate structures 1600-1 may be formed in the third trench 300. For example, two second gate layers 1620 may be formed by filling the third trench with a dielectric material 1630 and isolating the conductive material. By way of example, the second gate layer 1620 may extend along the first direction X, and a portion thereof corresponding to the semiconductor pillar 1110 may be used as a second gate electrode; and a remaining portion thereof may be used as a first word line for connecting the second gate electrode to a peripheral circuit, thereby transmitting electrical signals between the first gate electrode and the peripheral circuit.

[0115] In the exemplary embodiment of the present application, Fig.28As shown, a capacitor 1700 connected to the second end 1112 of the semiconductor pillar 1110 may be formed. The capacitor 1700 may include a first electrode (not shown) connected to the second end 1112 of the semiconductor pillar 1110, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. Exemplarily, the capacitor 1700 may be a vertical capacitor in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0116] Fig.29 For the general Fig.28 A schematic diagram of a structure in which the structure is flipped 180° and then thinned. In an exemplary embodiment of the present application, Fig.29 As shown, a portion of the semiconductor layer 1100 may be removed from a side away from the semiconductor pillar 1110 until the first end 1111 of the semiconductor pillar 1110 is exposed.

[0117] Figure 30 to Figure 32 It is a partial structural diagram of a semiconductor structure after forming a bit line 1800 provided according to an exemplary embodiment of the present application on a plane formed by a first direction X and a second direction Z, a plane formed by the first direction X and a third direction Y, and a plane formed by the third direction Y and the second direction Z.

[0118] In the exemplary embodiment of the present application, Figure 30 to Figure 32 As shown, a bit line 1800 connected to the semiconductor pillar 1110 and extending along the first direction X may be formed. For example, the bit line 1800 may be formed at the first end 1111 of the semiconductor pillar 1110 , that is, the bit line 1800 may be connected to the first end 1111 of the semiconductor pillar 1110 and extend along the first direction X.

[0119] In the present application, a preset first gate structure in a plurality of first gate structures 1200 and a preset second gate structure in a plurality of second gate structures 1600 can be turned on to address a preset semiconductor column in a plurality of semiconductor columns 1110 and a preset bit line 1800 connected to the preset semiconductor column, so that the preset bit line 1800 is in a sensing state, and the bit line adjacent to the preset bit line 1800 is in a non-sensing state. Specifically, when the preset first gate structure and the preset second gate structure are turned on, the other first gate structures adjacent to the preset first gate structure are turned off, and the other second gate structures adjacent to the preset second gate structure are turned off. At this time, only the preset bit line is in a sensing state, and the other bit lines adjacent to the preset bit line can be connected to a fixed voltage, so that the coupling phenomenon between the preset bit line and the other adjacent bit lines is reduced, which is conducive to reducing the interference between adjacent bit lines. For example, in the present application, the potential amplitude of the preset bit line in the sensing state can be increased to 150mV, which greatly improves the sensing strength of the semiconductor structure.

[0120] In the exemplary embodiment of the present application, Fig.30 As shown, the bit line 1800 may be adjacent to the first gate structure 1200 along the second direction Z. For example, a first gate lead-out structure 1910 and a bit line lead-out structure 1920 (eg, a side close to the first end 1111 of the semiconductor pillar 1110) respectively connected to the first gate structure 1200 and the bit line 1800 may be formed from a first side of the semiconductor layer 1100 (eg, a side close to the first end 1111 of the semiconductor pillar 1110). Fig.30 ); and forming a second gate lead-out structure 1930 ( 1930 ) connected to the second gate structure 1600 from a second side of the semiconductor layer 1100 opposite to the first side (eg, a side close to the second end 1112 of the semiconductor pillar 1110) Fig.32 ). For example, the first gate lead-out structure 1910, the bit line lead-out structure 1920, and the second gate lead-out structure 1930 may be used to respectively realize the connection between the first gate structure 1200, the bit line 1800, and the second gate structure 1600 and an external circuit.

[0121] Figure 30 to Figure 32 It is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present application on a plane formed by a first direction X and a second direction Z, a plane formed by the first direction X and a third direction Y, and a plane formed by the third direction Y and the second direction Z. The semiconductor structure includes a plurality of semiconductor pillars 1110, a first gate structure 1200, a second gate structure 1600, and a bit line 1800.

[0122] The plurality of semiconductor pillars 1110 may extend along the second direction Z and be distributed in an array along the first direction X and the third direction Y, wherein the first direction X, the second direction Z, and the third direction Y intersect each other.

[0123] Exemplarily, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose four sidewalls thereof. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a plan view (e.g., in an XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0124] The material of the semiconductor pillar 1110 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0125] The first gate structure 1200 may be located on the sidewall of the semiconductor pillar 1110 and extend along the third direction Y. The first gate structure 1200 may include a first gate dielectric layer 1210 and a first gate layer 1220. The first gate dielectric layer 1210 may be located on the sidewall of the semiconductor pillar 1110. The first gate layer 1220 may be located on the inner side of the first gate dielectric layer 1210, such as on the inner surface of the first gate dielectric layer 1210.

[0126] The first gate dielectric layer 1210 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the first gate dielectric layer 1210 may include silicon oxide, i.e., a gate oxide. The first gate layer 1220 may include any suitable conductive material, for example, may include one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and titanium nitride TiN.

[0127] Exemplarily, the first gate structure 1200 may further include a dielectric layer (including a first dielectric layer 1230 and a third dielectric layer 1240) and a second dielectric layer 1250. The dielectric layer may be located at the first gate structure 1200 near the first end 1111 of the semiconductor pillar 1110, wherein the third dielectric layer 1240 may surround a portion of the first dielectric layer 1230, and the first gate layer 1220 and the first gate dielectric layer 1210 may be located on the dielectric layer. The second dielectric layer 1250 may be located on the first dielectric layer 1230 and may be located on the surface of the first gate layer 1220. The first dielectric layer 1230, the third dielectric layer 1240, and the second dielectric layer 1250 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0128] For example, two adjacent first gate structures 1200 may be symmetrically distributed along the second direction Z. The first dielectric layer 1230, the second dielectric layer 1250, and the third dielectric layer 1240 in the two partially symmetrical first gate structures 1200 are continuous. In other words, the first dielectric layer 1230 in the two partially symmetrical first gate structures 1200 may be connected to form an integral structure, the second dielectric layer 1250 in the two first gate structures 1200 may be connected to form an integral structure, and the third dielectric layer 1240 in the two first gate structures 1200 may be connected to form an integral structure. Fig.14 As shown, a partial structural diagram of a first gate structure 1200 is shown.

[0129] By way of example, the semiconductor pillar 1110 and the first gate structure 1200 may be used together to form a vertical transistor, wherein the semiconductor pillar 1110 may be used to form an active region of multiple channels in the vertical transistor. By way of example, the first gate structure 1200 may be located on at least one sidewall of the semiconductor pillar 1110, i.e., the semiconductor pillar 1110 may be at least partially surrounded by the first gate structure 1200. For example, the semiconductor pillar 1110, the first gate dielectric layer 1210, and the first gate layer 1220 may be radially arranged in this order from the center of the vertical transistor. By way of example, the first gate dielectric layer 1210 may surround and contact the semiconductor pillar 1110. The first gate layer 1220 may surround and contact the first gate dielectric layer 1210.

[0130] In one embodiment of the present application, reference may be made to Fig.12 and Fig.13 As shown, the first gate structure 1200 may be located on multiple sidewalls of the semiconductor column 1110, and the semiconductor column 1110 and the first gate structure 1200 may be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0131] In another embodiment of the present application, reference may be made to Fig.15 and Fig.16As shown, the first gate structure 1200 may be located on a side wall of the semiconductor column 1110, and the semiconductor column 1110 and the first gate structure 1200 may be used together to form a single-gate transistor. For example, the single-gate transistors adjacent to each other along the first direction X may be arranged symmetrically. By providing single-gate transistors, the present application can significantly increase the density of the semiconductor column 1110 in the first direction X and reduce the difficulty of the manufacturing process. In addition, the symmetrically distributed single-gate transistors may have a larger process window, which is conducive to reducing the spacing between the bit lines, word lines and transistors formed subsequently.

[0132] Exemplarily, the semiconductor structure may further include an isolation layer 1300 located on the surface of the first gate structure. In other words, the isolation layer 1300 may be located on the surfaces of the first gate dielectric layer 1210, the first gate layer 1220, and the second dielectric layer 1250. In the present application, the first gate structure 1200 may be located in a region of the first trench 100 close to the first end 1111 of the semiconductor pillar 1110, and the isolation layer 1300 may be located in a region of the first trench 100 close to the second end 1112 of the semiconductor pillar 1110.

[0133] The second dielectric layer 1250 and the isolation layer 1300 may include the same material, such as any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second dielectric layer 1250 and the isolation layer 1300 may include silicon oxide.

[0134] In the exemplary embodiment of the present application, the semiconductor structure may further include an isolation structure 1400 and a barrier layer 1500. The isolation structure 1400 may be located between two adjacent semiconductor pillars 1110 arranged along the first direction X. The barrier layer 1500 may be located on the surface of the isolation structure 1400. That is, the isolation structure 1400 may be located in a region of the second trench close to the first end 1111 of the semiconductor pillar 1110, and the barrier layer 1500 may be located in a region of the second trench close to the second end 1112 of the semiconductor pillar 1110. In other words, the height of the isolation structure 1400 may be substantially the same as that of the first gate structure 1200, and the height of the barrier layer 1500 may be substantially the same as that of the isolation layer 1300.

[0135] Exemplarily, the isolation structure 1400 may include a conductive layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or a conductive layer (such as a metal material layer) may be formed in the second trench according to the spacing of the semiconductor pillars 1110, such as the size of the second trench along the first direction X. The barrier layer 1500 may include an insulating layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or an insulating layer (such as an oxide material layer) may be formed on the surface of the isolation structure 1400 according to the spacing of the semiconductor pillars 1110, such as the size of the second trench along the first direction X.

[0136] For example, if the isolation structure 1400 includes a conductive layer, an isolation lead structure (not shown) connected to the isolation structure 1400 may be formed. In the present application, the isolation lead structure may be grounded or a certain fixed potential may be applied to the isolation lead structure, so that the isolation structure 1400 can electrically insulate adjacent semiconductor pillars 1110 and reduce coupling between adjacent semiconductor pillars 1110.

[0137] The second gate structure 1600 may be located on the sidewall of the semiconductor pillar 1110 and extend along the first direction X, wherein the second gate structure 1600 and the first gate structure 1200 may be spaced apart along the second direction Z.

[0138] In an exemplary embodiment of the present application, reference may be made to Fig.21 and Fig. 22 As shown, the second gate structure 1600 may be located on at least one of the first sidewall 1113 and the second sidewall 1114 of the semiconductor pillar 1110 that are opposite to each other along the third direction Y. The second gate structure 1600 is not connected to the first gate structure 1200 and may be separated by the isolation layer 1300 .

[0139] For example, the second gate structure 1600 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located outside the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are sequentially arranged along the third direction Y.

[0140] Exemplarily, the second gate dielectric layer 1610 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the second gate dielectric layer 1610 may include silicon oxide, i.e., a gate oxide. The second gate layer 1620 may include any suitable conductive material, such as a metal and / or a metal compound. For example, the second gate layer 1620 may include metal tungsten.

[0141] Exemplarily, at least two adjacent second gate structures 1600 may be symmetrically distributed. The semiconductor structure may further include a dielectric material 1630 located between at least two adjacent second gate structures 1600 to separate adjacent second gate layers 1620. Exemplarily, the second gate layer 1620 may extend along the first direction X, and its portion corresponding to the semiconductor column 1110 may serve as a second gate electrode; the remaining portion thereof may serve as a second word line for connecting the second gate electrode to a peripheral circuit, thereby transmitting electrical signals between the second gate electrode and the peripheral circuit. In the present application, the first gate structure 1200 and the second gate structure 1600 work together to achieve conduction of the semiconductor column 1110.

[0142] In another exemplary embodiment of the present application, reference may be made to Figure 25 to Figure 27 As shown, the second gate structure 1600 may include a first sub-gate structure 1600-1 and a second sub-gate structure 1600-2. The first sub-gate structure 1600-1 may be located on at least one sidewall of the first sidewall 1113 and the second sidewall 1114 of the semiconductor column 1110 that are opposite to each other along the third direction Y. The second sub-gate structure 1600-2 may be located on at least one sidewall of the third sidewall 1115 and the fourth sidewall 1116 of the semiconductor column 1110 that are opposite to each other along the first direction X. For example, Fig.25 and Fig.26 It is shown that a first sub-gate structure 1600 - 1 may be formed on both the first sidewall 1113 and the second sidewall 1114 , and Fig.25 and Fig. 27 It is shown that the second sub-gate structure 1600 - 2 may be formed on both the third sidewall 1115 and the fourth sidewall 1116 .

[0143] For example, the first sub-gate structure 1600-1 may pass through the isolation layer 1300 and the isolation column 1150 and extend along the first direction X. The second sub-gate structure 1600-2 may pass through the isolation layer 1300 and extend along the third direction Y. The first sub-gate structure 1600-1 (or the second sub-gate structure 1600-2) and the first gate structure 1200 are not connected, and the two may be separated by the isolation layer 1300.

[0144] For example, the first sub-gate structure 1600-1 and / or the second sub-gate structure 1600-2 may include a second gate dielectric layer 1610 and a second gate layer 1620. The second gate dielectric layer 1610 may be located on the sidewall of the semiconductor pillar 1110, and the second gate layer 1620 may be located on the outer surface of the second gate dielectric layer 1610. For example, the semiconductor pillar 1110, the second gate dielectric layer 1610, and the second gate layer 1620 are sequentially distributed from the center to the outside.

[0145] The bit line 1800 may be connected to the semiconductor pillar 1110 and extend along the first direction X. For example, the bit line 1800 may be connected to the first end 1111 of the semiconductor pillar 1110 and extend along the first direction X.

[0146] In the present application, a preset first gate structure in a plurality of first gate structures 1200 and a preset second gate structure in a plurality of second gate structures 1600 can be turned on to address a preset semiconductor column in a plurality of semiconductor columns 1110 and a preset bit line 1800 connected to the preset semiconductor column, so that the preset bit line 1800 is in a sensing state, and the bit line adjacent to the preset bit line 1800 is in a non-sensing state. Specifically, when the preset first gate structure and the preset second gate structure are turned on, the other first gate structures adjacent to the preset first gate structure are turned off, and the other second gate structures adjacent to the preset second gate structure are turned off. At this time, only the preset bit line is in a sensing state, and the other bit lines adjacent to the preset bit line can be connected to a fixed voltage, so that the coupling phenomenon between the preset bit line and the other adjacent bit lines is reduced, which is conducive to reducing the interference between adjacent bit lines. For example, in the present application, the potential amplitude of the preset bit line in the sensing state can be increased to 150mV, which greatly improves the sensing strength of the semiconductor structure.

[0147] In an exemplary embodiment of the present application, the semiconductor structure may further include a capacitor 1700 connected to the second end 1112 of the semiconductor column 1110, and the second end may be located on a side of the semiconductor column 1110 away from the first end 1111. The capacitor 1700 may include a first electrode (not shown) connected to the second end 1112 of the semiconductor column 1110, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. Exemplarily, the capacitor 1700 may be a vertical capacitor, in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0148] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0149] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0150] Fig.332 is a schematic block diagram of a memory 2000 according to an exemplary embodiment of the present application. The memory 2000 may include a memory cell array 2100 and a peripheral circuit 2200 .

[0151] The memory cell array 2100 and the peripheral circuit 2200 may be separately formed on different substrates and then bonded to form the memory 2000 .

[0152] The peripheral circuit 2200 may be coupled to the memory cell array 2100. The peripheral circuit 2200 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed signal circuitry for facilitating the operation of the memory cell array 2100. For example, the peripheral circuit 2200 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0153] The memory cell array 2100 may include an array of memory cells (such as the semiconductor structure 1000 described above) using transistors as switches and selection devices. In some embodiments, the memory cell array 2100 includes a DRAM cell array. For ease of description, a DRAM cell array may be used as an example for describing the memory cell array 2100 in the content of the present application. However, it should be understood that the memory cell array 2100 is not limited to a DRAM cell array, and may include any other suitable type of memory cell array 2100 that can use transistors as switches and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array 2100, a magnetic memory cell array 2100, a spin transfer torque (STT) memory cell array 2100, to name just a few examples, or any combination thereof.

[0154] The memory cell array 2100 may be a DRAM device in which memory cells are provided in the form of a DRAM cell array. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as a pass transistor) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a one-transistor-one-capacitor (1T1C) cell. The DRAM cell may be refreshed, for example, by the peripheral circuit 2200 in the first semiconductor structure 102 to retain data.

[0155] Fig.34 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0156] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.34 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more memories 2000 (including a three-dimensional memory 14) and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memory 14.

[0157] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0158] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.35AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.34 The memory card connector 24 is coupled to the host 18 in the embodiment. Fig.35B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.34 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0159] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor layer includes a plurality of semiconductor pillars extending along a second direction and distributed in an array along a first direction and a third direction, wherein the first direction, the second direction and the third direction intersect each other, and the method includes: forming a first gate structure extending along the third direction on the sidewall of the semiconductor column; forming a second gate structure extending along the first direction on the sidewall of the semiconductor column, wherein the second gate structure and the first gate structure are spaced apart along the second direction; and A bit line connected to the semiconductor pillar and extending along the first direction is formed.

2. The method according to claim 1, characterized in that The bit line is adjacent to the first gate structure along the second direction, and the method includes: forming a first gate lead-out structure and a bit line lead-out structure connected to the first gate structure and the bit line, respectively, from a first side of the semiconductor layer; and A second gate lead-out structure connected to the second gate structure is formed from a second side of the semiconductor layer opposite to the first side.

3. The method according to claim 1, characterized in that: A first gate structure extending along the third direction is formed on the sidewall of the semiconductor column, comprising: forming a plurality of initial semiconductor pillars extending along the first direction and the second direction in the semiconductor layer; forming a plurality of first trenches extending along a third direction and arranged along the first direction through the initial semiconductor column, wherein the plurality of first trenches divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction; and The first gate structure and the isolation layer extending along the third direction and adjacently distributed along the second direction are formed on the sidewall of the semiconductor column through the first trench.

4. The method according to claim 3, characterized in that: The method further comprises: forming a second trench passing through the semiconductor pillar and extending along a third direction; and An isolation structure is formed in the second trench.

5. The method according to claim 3, characterized in that: The first gate structure and the isolation layer are formed on the sidewall of the semiconductor column via the first trench, the first gate structure and the isolation layer extending along the third direction and adjacently distributed along the second direction, comprising: forming a first gate dielectric layer extending along the third direction on the sidewall of the semiconductor column through the first trench; forming a first gate layer on a surface of the first gate dielectric layer, wherein the first gate layer and the first gate dielectric layer are adjacently distributed along the first direction, and the first gate structure includes the first gate layer and the first gate dielectric layer; and The isolation layer is formed on the surface of the first gate structure.

6. The method according to claim 3, characterized in that Forming a plurality of initial semiconductor pillars extending along the first direction and the second direction in the semiconductor layer, comprising: A plurality of isolation columns extending along the first direction and the second direction are formed in the semiconductor layer, wherein the plurality of isolation columns divide a portion of the semiconductor layer into a plurality of initial semiconductor columns, and the initial semiconductor columns and the isolation columns are alternately arranged along the third direction.

7. The method according to claim 6, characterized in that A second gate structure extending along the first direction is formed on the sidewall of the semiconductor column, comprising: The second gate structure extending along the first direction is formed on at least one sidewall of a first sidewall and a second sidewall of the semiconductor pillar that are opposite to each other along the third direction.

8. The method according to claim 7, characterized in that The method comprises: forming a third trench passing through the isolation layer and the isolation column and extending along the first direction; and The second gate structure is formed through the third trench.

9. The method according to claim 6, characterized in that The second gate structure includes a first sub-gate structure and a second sub-gate structure, and the second gate structure extending along the first direction is formed on the sidewall of the semiconductor column, including: forming the first sub-gate structure extending along the first direction on at least one of a first sidewall and a second sidewall of the semiconductor column that are opposite to each other along the third direction; and The second sub-gate structure is formed on at least one sidewall of a third sidewall and a fourth sidewall of the semiconductor column that are opposite to each other along the first direction.

10. The method according to claim 9, characterized in that The method comprises: forming a third trench passing through the isolation layer and the isolation column and extending along the first direction, and a fourth trench passing through the isolation layer and extending along the third direction; The first sub-gate structure and the second sub-gate structure are formed via the third trench and the fourth trench, respectively.

11. The method according to any one of claims 1 to 10, characterized in that The bit line is connected to the first end of the semiconductor column, and the method further includes: A capacitor is formed and connected to a second end of the semiconductor column, wherein the second end is located at a side of the semiconductor column away from the first end.

12. A semiconductor structure, characterized in that: include: A plurality of semiconductor pillars extending along the second direction and distributed in an array along the first direction and the third direction, wherein the first direction, the second direction and the third direction intersect each other; A first gate structure, located on a sidewall of the semiconductor column and extending along the third direction; a second gate structure, located on a sidewall of the semiconductor column and extending along the first direction, wherein the second gate structure and the first gate structure are spaced apart along the second direction; as well as The bit line is connected to the semiconductor column and extends along the first direction.

13. The semiconductor structure according to claim 12, characterized in that: The second gate structure is located on at least one sidewall of a first sidewall and a second sidewall of the semiconductor pillar that are opposite to each other along the third direction.

14. The semiconductor structure according to claim 12, characterized in that: The second gate structure comprises: a first sub-gate structure located on at least one sidewall of a first sidewall and a second sidewall of the semiconductor column that are opposite to each other along the third direction; and The second sub-gate structure is located on at least one side wall of the third side wall and the fourth side wall of the semiconductor column that are opposite to each other along the first direction.

15. The semiconductor structure according to claim 12, characterized in that: The first gate structure is located on at least one sidewall of a third sidewall and a fourth sidewall of the semiconductor column that are opposite to each other along the first direction.

16. The semiconductor structure according to claim 12, characterized in that The semiconductor structure further comprises: The isolation structure is located between two adjacent semiconductor pillars arranged along the first direction.

17. The semiconductor structure according to claim 12, characterized in that: The first gate structure includes a first gate dielectric layer located on the sidewall of the semiconductor pillar and a first gate layer located outside the first gate dielectric layer; and The second gate structure includes a second gate dielectric layer located on a sidewall of the semiconductor pillar and a second gate layer located outside the second gate dielectric layer.

18. The semiconductor structure according to claim 16, characterized in that The isolation structure includes a conductive layer and / or an air gap layer.

19. The semiconductor structure according to claim 12, characterized in that The bit line is connected to the first end of the semiconductor column, and the semiconductor structure further includes: The capacitor is connected to the second end of the semiconductor column, where the second end is located on a side of the semiconductor column away from the first end.

20. The semiconductor structure according to claim 12, wherein: The semiconductor structure includes a plurality of first gate structures and a plurality of second gate structures, wherein: In response to turning on a preset first gate structure among the multiple first gate structures and a preset second gate structure among the multiple second gate structures, a preset semiconductor column among the multiple semiconductor columns and a preset bit line connected to the preset semiconductor column are addressed, so that the preset bit line is in a sensing state and a bit line adjacent to the preset bit line is in a non-sensing state.

21. A memory, characterized in that: include: A memory cell array comprising a semiconductor structure as claimed in any one of claims 12 to 20; as well as The peripheral circuit is coupled to the memory cell array.

22. A storage system, characterized in that: include: at least one memory as claimed in claim 21; as well as The controller is coupled to the semiconductor structure and is used for controlling the memory to store data.

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