Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and the method comprises the following steps: forming a first plate of a high-voltage capacitor; forming at least one interlayer dielectric layer as a dielectric layer of the high-voltage capacitor on the first plate of the high-voltage capacitor, and each interlayer dielectric layer is formed with a conductive via, the conductive vias are communicated with each other and the first plate of the high-voltage capacitor as an outgoing channel of the first plate of the high-voltage capacitor; etching the interlayer dielectric layer to form a deep groove; forming a first plate of a silicon capacitor on the sidewall and the bottom of the deep groove, and the first plate of the silicon capacitor is communicated with the first plate of the high-voltage capacitor; forming a dielectric layer of the silicon capacitor on the sidewall and the bottom of the deep groove; forming a second plate of the silicon capacitor in the deep groove; and forming a second plate of the high-voltage capacitor on the top interlayer dielectric layer. The manufacturing of the high-voltage capacitor and the silicon capacitor is integrated in one process, the process steps are saved, the manufacturing cost is saved, and the product competitiveness is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In the chip design and manufacturing process, the process of designing multiple high-voltage functional devices on a single chip can improve product competitiveness.

[0003] High-voltage capacitors (HVCAP, voltage 1000V~6000V) can be integrated on functional semiconductor chips or packaged together with functional semiconductor chips as capacitive isolators for isolation of different voltage domains, including automotive isolation devices that allow safe transmission of electrical signals between different voltage domains.

[0004] Silicon capacitors (SICAP) use semiconductor deep trench technology, which can significantly improve the capacitance density and capacitance value compared to MOS capacitors, MIM capacitors, and other parallel plate capacitors, and can save a large amount of chip area. The actual area of a silicon capacitor is the surface area of the entire deep trench under the same layout area. Silicon capacitors have important applications in new energy vehicle battery management systems and drive systems due to their high stability, high reliability, high density, low thickness, low equivalent series inductance (ESL), and low equivalent series resistance (ESR).

[0005] The above two capacitors are capacitor devices with independent structure and function. Integrating high-voltage capacitors and silicon capacitors in the same process at a low cost to improve product competitiveness is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0006] The present application aims to provide a semiconductor device and a manufacturing method thereof, which integrates high-voltage capacitors and silicon capacitors in the same process, thereby saving process steps, reducing manufacturing costs, and improving product competitiveness.

[0007] To solve the above technical problems, according to a first aspect of the present application, a manufacturing method of a semiconductor device is provided, comprising the following steps:

[0008] forming a first plate of a high-voltage capacitor;

[0009] forming at least one interlayer dielectric layer on the first plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor, each interlayer dielectric layer being formed with a conductive via, and the conductive vias being in communication with each other and with the first plate of the high-voltage capacitor as an outgoing channel of the first plate of the high-voltage capacitor;

[0010] etching the interlayer dielectric layer to form a deep trench;

[0011] forming a first plate of a silicon capacitor on the sidewall and the bottom of the deep trench, the first plate of the silicon capacitor being in communication with the first plate of the high voltage capacitor; forming a dielectric layer of the silicon capacitor on the sidewall and the bottom of the deep trench, the dielectric layer of the silicon capacitor covering the first plate of the silicon capacitor; forming a second plate of the silicon capacitor in the deep trench, the second plate of the silicon capacitor filling the deep trench; and

[0012] forming a second plate of the high voltage capacitor on the interlayer dielectric layer of the top layer.

[0013] Optionally, the step of forming the first plate of the high voltage capacitor comprises:

[0014] providing a substrate, and forming a bottom layer interlayer dielectric layer on the substrate;

[0015] forming a first metal layer, the first metal layer covering part of the bottom layer interlayer dielectric layer;

[0016] forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the first metal layer and the bottom layer interlayer dielectric layer, and forming a conductive via in the first interlayer dielectric layer, the conductive via being in communication with the first metal layer;

[0017] forming a second metal layer, the second metal layer covering part of the first interlayer dielectric layer, and the second metal layer being in communication with the first metal layer through the conductive via, the second metal layer serving as the first plate of the high voltage capacitor.

[0018] Optionally, in a direction perpendicular to the substrate, the first plate of the high voltage capacitor covers part of the first metal layer.

[0019] Optionally, etching all the interlayer dielectric layers to form a deep trench exposing the first metal layer, the first plate of the silicon capacitor being in communication with the first plate of the high voltage capacitor through the first metal layer.

[0020] Optionally, a metal layer is further formed in each interlayer dielectric layer on the first plate of the high voltage capacitor, the metal layer being in communication with two adjacent conductive vias, the metal layer and the conductive vias together constituting a lead-out channel of the first plate of the high voltage capacitor.

[0021] Optionally, the substrate comprises a first region and a second region, a semiconductor structure being formed in the second region, the high voltage capacitor and the silicon capacitor being formed in the first region.

[0022] forming a plurality of interlayer dielectric layers in the second region, and forming a metal layer and a conductive via in each interlayer dielectric layer, the metal layer and the conductive via leading out a corresponding electrode of the semiconductor structure;

[0023] The first plate of the high-voltage capacitor is formed synchronously with the metal layer in the same layer in the second region, the dielectric layer of the high-voltage capacitor is formed synchronously with the interlayer dielectric layer in the same layer in the second region, and the lead-through channel is formed synchronously with the metal layer and the conductive via in the same layer in the second region.

[0024] Optionally, the method for etching the interlayer dielectric layer to form a deep groove comprises:

[0025] forming a photoresist layer on the interlayer dielectric layer of the top layer;

[0026] exposing and developing the photoresist layer to form a patterned photoresist layer;

[0027] using the patterned photoresist layer as a mask to etch all the interlayer dielectric layers until the first metal layer is exposed; and

[0028] removing the patterned photoresist layer.

[0029] Optionally, the second plate of the high-voltage capacitor is formed at the same time as the lead-out end of the first plate of the high-voltage capacitor, the lead-out end of the first plate of the silicon capacitor, and the lead-out end of the second plate of the silicon capacitor.

[0030] The method for forming the second plate of the high-voltage capacitor on the interlayer dielectric layer of the top layer comprises:

[0031] forming a conductive material layer covering the interlayer dielectric layer of the top layer;

[0032] etching the conductive material layer to expose part of the interlayer dielectric layer of the top layer, retaining the conductive material layer above the first plate of the high-voltage capacitor as the second plate of the high-voltage capacitor, retaining the conductive material layer on the lead-through channel as the first lead-out end of the first plate of the high-voltage capacitor and the first plate of the silicon capacitor, and retaining the conductive material layer on the second plate of the silicon capacitor as the second lead-out end of the second plate of the silicon capacitor.

[0033] Optionally, the materials of the first plate and the second plate of the high-voltage capacitor comprise copper, tungsten, aluminum, ruthenium, or cobalt, the material of the dielectric layer of the high-voltage capacitor comprises ethyl silicate, boron phosphorus silicon glass, or low dielectric constant material, the material of the first plate of the silicon capacitor comprises titanium nitride, the material of the second plate of the silicon capacitor comprises tungsten, and the dielectric layer of the silicon capacitor comprises a silicon nitride layer or a stack composed of silicon oxide-silicon nitride-silicon oxide.

[0034] To solve the above technical problems, according to the second aspect of the present application, there is further provided a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device as described above, and the semiconductor device comprises:

[0035] a first plate of a high voltage capacitor;

[0036] at least one interlayer dielectric layer on the first plate of the high voltage capacitor as a dielectric layer of the high voltage capacitor, and each of the interlayer dielectric layers is formed with a conductive via hole, the conductive via holes are communicated with each other and with the first plate of the high voltage capacitor as an outgoing channel of the first plate of the high voltage capacitor; a deep groove is formed in the interlayer dielectric layer and penetrates through the interlayer dielectric layer;

[0037] a first plate of a silicon capacitor on the sidewall and bottom of the deep groove, and the first plate of the silicon capacitor is communicated with the first plate of the high voltage capacitor;

[0038] a dielectric layer of the silicon capacitor on the sidewall and bottom of the deep groove and covering the first plate of the silicon capacitor;

[0039] a second plate of the silicon capacitor in the deep groove and filling the deep groove; and

[0040] a second plate of the high voltage capacitor on the top interlayer dielectric layer.

[0041] In summary, in the semiconductor device and the manufacturing method thereof provided by the present application, first, a first plate of a high voltage capacitor is formed, then at least one interlayer dielectric layer is formed on the first plate as a dielectric layer of the high voltage capacitor, each of the interlayer dielectric layers is formed with a conductive via hole, the conductive via holes are communicated with each other and with the first plate of the high voltage capacitor as an outgoing channel of the first plate of the high voltage capacitor, then a deep groove is etched in the interlayer dielectric layer, then a first plate of a silicon capacitor is formed on the sidewall and bottom of the deep groove, and the first plate of the silicon capacitor is communicated with the first plate of the high voltage capacitor; a dielectric layer of the silicon capacitor is formed on the sidewall and bottom of the deep groove, and the dielectric layer of the silicon capacitor covers the first plate of the silicon capacitor; a second plate of the silicon capacitor is formed in the deep groove, and the second plate of the silicon capacitor fills the deep groove, then a second plate of the high voltage capacitor is formed on the top interlayer dielectric layer. The present application integrates the manufacturing of the high voltage capacitor and the silicon capacitor in one process, saves the process steps, saves the manufacturing cost, and improves the product competitiveness.

[0042] Further, the first plate and the second plate of the silicon capacitor are made of conductive material, and ion implantation is not needed, thus getting rid of the limitation of ion implantation process, and the deposition process can uniformly deposit the conductive material on the inner wall of the deep groove, thus improving the uniformity of the first plate and reducing the parasitic resistance. Meanwhile, since the ion implantation process is not needed, more deep grooves can be accommodated in the interlayer dielectric layer, thus further increasing the integration level.

[0043] In addition, the dielectric layer of the silicon capacitor is made of ONO or silicon nitride, which can significantly improve the breakdown voltage of the silicon capacitor and avoid the breakdown of the weak position in the work due to dielectric defects and dielectric uniformity. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0045] Figures 2 to 8 is a structural diagram of each step of the method for manufacturing a semiconductor device according to an embodiment of the present application.

[0046] BRIEF DESCRIPTION OF DRAWINGS

[0047] 100 - substrate; 101 - first metal layer; 102 - second metal layer; 103 - third metal layer; 104 - fourth metal layer; 110 - bottom interlayer dielectric layer; 111 - first interlayer dielectric layer; 112 - second interlayer dielectric layer; 113 - third interlayer dielectric layer; 114 - fourth interlayer dielectric layer; 115 - fifth interlayer dielectric layer; 120 - patterned first photoresist layer; 121 - deep groove; 130 - patterned second photoresist layer; 140 - third lead-out end; 151 - first passivation layer; 152 - second passivation layer; 210 - first plate of high-voltage capacitor; 211 - conductive via; 212 - first lead-out end; 220 - second plate of high-voltage capacitor; 221 - third conductive material layer; 310 - first plate of silicon capacitor; 311 - first conductive material layer; 320 - dielectric layer of silicon capacitor; 321 - insulating material layer; 330 - second plate of silicon capacitor; 331 - second conductive material layer; 332 - second lead-out end. DETAILED DESCRIPTION

[0048] To make the purpose, advantages and features of the present application clearer, the following will further describe the present application in detail with reference to the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, different scales are sometimes used in the drawings to show different focuses.

[0049] As used in this disclosure, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this disclosure, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in this disclosure, the term "plurality" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. As used in this disclosure, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," are used merely for description and do not connote or imply relative importance or an ordering of the technical features being described. Thus, features defined with "first," "second," or "third" can include one or at least two of such features unless the content clearly dictates otherwise.

[0050] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 1 , the method for manufacturing a semiconductor device includes the following steps:

[0051] S1: forming a first plate of a high-voltage capacitor;

[0052] S2: forming at least one interlayer dielectric layer on the first plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor, each of the interlayer dielectric layers being formed with a conductive via, the conductive vias being in communication with each other and with the first plate of the high-voltage capacitor as an extraction channel of the first plate of the high-voltage capacitor;

[0053] S3: etching the interlayer dielectric layers to form a deep trench;

[0054] S4: forming a first plate of a silicon capacitor on the sidewalls and bottom of the deep trench, the first plate of the silicon capacitor being in communication with the first plate of the high-voltage capacitor; forming a dielectric layer of the silicon capacitor on the sidewalls and bottom of the deep trench, the dielectric layer of the silicon capacitor covering the first plate of the silicon capacitor; and forming a second plate of the silicon capacitor in the deep trench, the second plate of the silicon capacitor filling the deep trench; and

[0055] S5: forming a second plate of the high-voltage capacitor on the top interlayer dielectric layer.

[0056] Figures 2 to 8 is a structural diagram of each step of the method for manufacturing a semiconductor device according to an embodiment of the present application. Next, the method for manufacturing a semiconductor device according to an embodiment of the present application will be described in detail. Figure 1 , Figures 2 to 8 ​

[0057] In step S1, referring to Figure 2 A first plate 210 of a high voltage capacitor is formed.

[0058] In one embodiment of the present application, the step of forming the first plate 210 of the high voltage capacitor comprises:

[0059] First, step S11 is performed to provide a substrate 100, and a bottom interlayer dielectric layer 110 is formed on the substrate 100.

[0060] In the present embodiment, the substrate 100 can be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or can be a silicon-on-insulator or a germanium-on-insulator. Alternatively, the substrate 100 can be made of other materials, such as a III-V compound, for example, gallium arsenide. In one embodiment, the substrate 100 is a silicon substrate. The bottom interlayer dielectric layer 110 can be made of Tetra Ethyl Ortho Silicate (TEOS), Boro-phospho-silicate Glass (BPSG), or other suitable dielectric materials, such as a low dielectric constant material (low-k dielectric material), or any combination of these materials. The bottom interlayer dielectric layer 110 can be formed by any suitable process known to those skilled in the art, such as an atomic layer deposition process (ALD), a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or the like.

[0061] Next, step S12 is performed to form a first metal layer 101 on the bottom interlayer dielectric layer 110, the first metal layer 101 covering part of the bottom interlayer dielectric layer 110. The first metal layer 101 can be made of, but is not limited to, copper, tungsten, aluminum, ruthenium, or cobalt.

[0062] Then, step S13 is performed to form a first interlayer dielectric layer 111 on the first metal layer 101, the first interlayer dielectric layer 111 covering the first metal layer 101 and the bottom interlayer dielectric layer 110. The first interlayer dielectric layer 111 can be made of the same material and formed by the same process as the bottom interlayer dielectric layer 110, but is not limited thereto. Thereafter, the first interlayer dielectric layer 111 is etched to form a via hole exposing the first metal layer 101, and the via hole is filled with a conductive material to form a conductive via hole.

[0063] Next, step S14 is performed to form a second metal layer 102 on the first interlayer dielectric layer 111, the second metal layer 102 covering part of the first interlayer dielectric layer 111, and the second metal layer 102 being connected to the first metal layer 101 through the conductive via, the second metal layer 102 serving as the first plate 210 of the high voltage capacitor. In the present embodiment, please refer to Figure 2 As shown in FIG. 2, part of the second metal layer 102 serves as the first plate 210 of the high voltage capacitor, part of the second metal layer 102 serves as part of the lead-out channel of the first plate 210, and part of the second metal layer 102 is located in the region of the substrate 100 where the semiconductor structure is formed, which will be described in detail later.

[0064] In one embodiment, in the direction perpendicular to the substrate 100, the first plate 210 of the high voltage capacitor covers part of the first metal layer 101, i.e., the first plate 210 of the high voltage capacitor only partially overlaps the first metal layer 101, the first plate 210 of the high voltage capacitor, the dielectric layer of the high voltage capacitor to be formed later, and the second plate of the high voltage capacitor constitute the high voltage capacitor, the first metal layer 101 is used to connect the first plate 210 of the high voltage capacitor to the external circuit, and is used to connect to the first plate of the silicon capacitor to be formed later.

[0065] In another embodiment of the present application, the first metal layer 101 can also directly serve as the first plate of the high voltage capacitor without forming the second metal layer 102 on the first interlayer dielectric layer 111. The present application is not limited in this regard.

[0066] In step S2, please continue to refer to Figure 2 As shown in FIG. 2, at least one interlayer dielectric layer is formed on the first plate 210 of the high voltage capacitor as the dielectric layer of the high voltage capacitor, and a conductive via 211 is formed in each of the interlayer dielectric layers, the conductive vias 211 being connected to each other and to the first plate 210 as a lead-out channel of the first plate 210.

[0067] A metal layer (e.g., a third metal layer 103 and a fourth metal layer 104) is also formed in each of the interlayer dielectric layers on the first plate 210 of the high voltage capacitor, the metal layer connecting two adjacent conductive vias 211, and the metal layer and the conductive vias 211 together constituting the lead-out channel of the first plate 210 of the high voltage capacitor.

[0068] In the embodiment, the first plate 210 of the high-voltage capacitor is formed with three interlayer dielectric layers, for example, the second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114, but the number of the interlayer dielectric layers is not limited to three. Figures 2 to 8 In the substrate 100, the second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114 are not distinguished from each other.

[0069] In the embodiment, the substrate 100 includes a first region I and a second region II. The high-voltage capacitor and the subsequent silicon capacitor are formed in the first region I. The second region II is formed with a semiconductor structure, but the substrate 100 can include other regions. The first region I and the second region II are only exemplarily shown in the drawings. The semiconductor structure is, for example, an active device, such as a metal-oxide-semiconductor transistor device. The substrate 100 in the second region II is formed with multiple interlayer dielectric layers, and each of the interlayer dielectric layers is formed with a metal layer and a conductive via. The metal layer and the conductive via lead out corresponding electrodes of the semiconductor structure (for example, the gate, the source and the drain of the metal-oxide-semiconductor transistor). In the embodiment, the semiconductor structure is formed with four metal layers and five interlayer dielectric layers, for example, the bottom interlayer dielectric layer 110, the first interlayer dielectric layer 111, the second interlayer dielectric layer 112, the third interlayer dielectric layer 113 and the fourth interlayer dielectric layer 114, and the first metal layer 101, the second metal layer 102, the third metal layer 103 and the fourth metal layer 104. The five interlayer dielectric layers are made of the same material, and the four metal layers are made of the same material.

[0070] The substrate 100 in the second region II is formed with corresponding interlayer dielectric layers, metal layers and conductive vias, and the substrate 100 in the first region I is formed with the same interlayer dielectric layers, metal layers and conductive vias, Figure 2The same layer in different regions is not distinguished. For example, the first plate 210 of the high voltage capacitor is formed synchronously with the metal layer (for example, the second metal layer 102) in the same layer in the second region II, the dielectric layer of the high voltage capacitor is formed synchronously with the interlayer dielectric layer in the same layer in the second region II (in the second region II, three interlayer dielectric layers are formed on the second metal layer 102, the dielectric layer of the high voltage capacitor includes three interlayer dielectric layers, the number of interlayer dielectric layers included in the dielectric layer of the high voltage capacitor is the same as the number of interlayer dielectric layers on the second metal layer 102 in the second region II, and of course is not limited to three layers), and the lead channel is formed synchronously with the metal layer and the conductive via in the same layer in the second region II (that is, the lead channel is formed in the first region I at the same time when the corresponding electrode of the semiconductor structure is led out in the second region II, to lead out the first metal layer 101, which is equivalent to leading out the first plate 210).

[0071] Please refer to Figure 2 As shown in the figure, a bottom interlayer dielectric layer 110 is formed on the substrate 100, and a conductive via is formed in the bottom interlayer dielectric layer 110, which is only located in the second region II, for connecting the electrodes of the semiconductor structure, and then a plurality of first metal layers 101 in the same layer are formed, and the plurality of first metal layers 101 are located in different regions, for example, the first metal layer 101 located in the first region I is used as the connection layer of the first plate of the high voltage capacitor and the first plate of the silicon capacitor, and the first metal layer 101 located in the second region II is used to connect the conductive via to connect different electrodes of the semiconductor structure. Then a first interlayer dielectric layer 111 is formed, and then a plurality of conductive vias are formed in the first interlayer dielectric layer 111, different conductive vias connect different or same first metal layers 101, and the same layer interlayer dielectric layer (or the same layer metal layer or the conductive via in the same layer) formed in different regions of the substrate 100 is formed in the same step.

[0072] In this embodiment, a fifth interlayer dielectric layer 115 is further formed on the fourth interlayer dielectric layer 114, and the fifth interlayer dielectric layer 115 includes a silicon oxynitride layer and a silicon nitride layer which are sequentially located on the fourth interlayer dielectric layer 114, so as to improve the withstand voltage capacity of the high voltage capacitor.

[0073] In this embodiment, the material of the first plate 210 of the high-voltage capacitor is the same as that of the second metal layer 102, and the material of the dielectric layer of the high-voltage capacitor is determined by the material of the interlayer dielectric layer. For example, the material of the first plate 210 of the high-voltage capacitor includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and the material of the dielectric layer of the high-voltage capacitor can be ethyl silicate, boron phosphorus silicon glass, or other suitable dielectric materials, such as low-k dielectric materials or any combination of these materials.

[0074] In step S3, referring to Figure 3 The interlayer dielectric layer is etched to form a deep groove 121.

[0075] In an embodiment of the present application, a photoresist layer (for the sake of distinction from the photoresist layer to be formed later, it is referred to as the first photoresist layer in this embodiment) is formed on the top interlayer dielectric layer (i.e., the fifth interlayer dielectric layer 115), the first photoresist layer is exposed and developed to form a patterned first photoresist layer 120, and the patterned first photoresist layer 120 is used as a mask to etch all the interlayer dielectric layers to form a deep groove 121, and then the patterned first photoresist layer 120 is removed. In an embodiment, all the interlayer dielectric layers are etched to expose the first metal layer 101, i.e., the fifth interlayer dielectric layer 115, the fourth interlayer dielectric layer 114, the third interlayer dielectric layer 113, the second interlayer dielectric layer 112 and the first interlayer dielectric layer 111 (i.e., all the interlayer dielectric layers on the first metal layer 101) are etched to form a deep groove 121 exposing the first metal layer 101.

[0076] It should be noted that the deep groove 121, the lead-out channel and the first plate 210 of the high-voltage capacitor are located at different positions of the first region I, the position of the deep groove 121 has multiple layers of stacked interlayer dielectric layers, and the first plate 210 of the high-voltage capacitor is also only provided with multiple layers of stacked interlayer dielectric layers above it, and the position of the lead-out channel is not only provided with multiple layers of stacked interlayer dielectric layers, but also has a metal layer and a conductive via above the metal layer formed in each interlayer dielectric layer to connect the first metal layer 101 to the upper surface of the top interlayer dielectric layer.

[0077] In step S4, referring to Figure 4 and Figure 5As shown, a first plate 310 of a silicon capacitor is formed on the sidewall and bottom of the deep trench 121, and the first plate 310 of the silicon capacitor is in communication with the first plate 210 of the high-voltage capacitor; a dielectric layer 320 of the silicon capacitor is formed on the sidewall and bottom of the deep trench 121, and the dielectric layer 320 of the silicon capacitor covers the first plate 310 of the silicon capacitor; and a second plate 330 of the silicon capacitor is formed in the deep trench 121, and the second plate 330 of the silicon capacitor fills the deep trench.

[0078] In this embodiment, first, a first conductive material layer 311 is formed, which covers the sidewall and bottom of the deep trench 121 and covers the top surface of the fifth interlayer dielectric layer 115; then, an insulating material layer 321 is formed, which covers the sidewall and bottom of the deep trench 121 and covers the top surface of the fifth interlayer dielectric layer 115, i.e., the insulating material layer 321 covers the first conductive material layer 311; and then, a second conductive material layer 331 is formed, which fills the deep trench 121 and covers the fifth interlayer dielectric layer 115 (specifically, covers the insulating material layer 321 on the fifth interlayer dielectric layer 115), forming a structure as shown. Figure 4

[0079] Then, referring to Figure 5 As shown, planarization, such as chemical mechanical polishing, is performed until the fifth interlayer dielectric layer 115 is exposed (i.e., until the top layer of the interlayer dielectric layer is exposed), forming a first conductive layer covering the sidewall and bottom in the deep trench 121, an insulating layer covering the first conductive layer and covering the sidewall and bottom, and a second conductive layer filling the deep trench 121. The first conductive layer serves as the first plate 310 of the silicon capacitor, the insulating layer serves as the dielectric layer 320 of the silicon capacitor, and the second conductive layer serves as the second plate 330 of the silicon capacitor. It should be noted that when chemical mechanical polishing is stopped on the fifth interlayer dielectric layer 115, the loss of the fifth interlayer dielectric layer 115 needs to be controlled to prevent the thickness variation of the fifth interlayer dielectric layer 115 from affecting the withstand voltage performance of the high-voltage capacitor.

[0080] ​In an embodiment of the present application, the material of the first conductive material layer 311 includes, but is not limited to, titanium nitride, the material of the second conductive material layer 331 includes, but is not limited to, tungsten, and the material of the insulating material layer 321 includes a silicon nitride layer or a stack of silicon oxide-silicon nitride-silicon oxide, i.e., the material of the insulating material layer 321 includes, but is not limited to, silicon oxide-silicon nitride-silicon oxide (ONO) or silicon nitride, i.e., in the silicon capacitor, the material of the first plate 310 of the silicon capacitor includes, but is not limited to, titanium nitride, the material of the second plate 330 of the silicon capacitor includes, but is not limited to, tungsten, and the material of the dielectric layer 320 of the silicon capacitor includes, but is not limited to, ONO or silicon nitride. Of course, the materials of the layers in the silicon capacitor are not limited to the above, but can be any other suitable materials known to those skilled in the art. The first conductive material layer 311, the insulating material layer 321 and the second conductive material layer 331 can be formed by using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, etc.

[0081] In an embodiment of the present application, the first plate 310 and the second plate 330 of the silicon capacitor are made of conductive materials, and thus do not need to be ion implanted, thereby getting rid of the limitation of the ion implantation process. The deposition process can uniformly deposit the conductive materials on the inner wall of the deep trench 121, thereby improving the uniformity of the first plate and reducing the parasitic resistance. Meanwhile, since the ion implantation process is not needed to be performed, more deep trenches 121 can be accommodated in the interlayer dielectric layer, thereby further increasing the integration level.

[0082] In addition, the dielectric layer 320 of the silicon capacitor is made of ONO or silicon nitride, which can significantly improve the breakdown voltage of the silicon capacitor and avoid the breakdown of the weak position in the working due to the dielectric defects and the dielectric uniformity.

[0083] In step S5, please refer to Figure 7 to form the second plate 220 of the high-voltage capacitor on the top layer of the interlayer dielectric layer.

[0084] For example, first, please refer to Figure 6 to form a conductive material layer (in order to distinguish from the first conductive material layer and the second conductive material layer, it is referred to as the third conductive material layer 221 in this embodiment), which covers the top layer of the interlayer dielectric layer, specifically covers the fifth interlayer dielectric layer 115, and of course also covers the conductive via 211 and the silicon capacitor in the top layer of the interlayer dielectric layer.

[0085] Then, please refer to Figure 7As shown, the third conductive material layer 221 is etched to expose the top layer of interlayer dielectric layer. Specifically, a second photoresist layer is formed on the third conductive layer 221, the second photoresist layer is exposed and developed to form a patterned second photoresist layer 130, the third conductive material layer 221 is etched to expose part of the top layer of interlayer dielectric layer, and part of the third conductive material layer 221 is reserved. The third conductive material layer located directly above the first plate 210 of the high-voltage capacitor is reserved as the second plate 220 of the high-voltage capacitor, the third conductive material layer located on the lead-through channel is reserved as the first lead-through end 212 of the first plate 310 of the silicon capacitor and the first plate 210 of the high-voltage capacitor, the third conductive material layer located on the second plate 330 of the silicon capacitor is reserved as the second lead-through end 332 of the second plate 330 of the silicon capacitor, and the third conductive material layer on the conductive via in the second region II is also reserved as the third lead-through end 140 of the electrode of the semiconductor structure. Then, the patterned second photoresist layer 130 is removed.

[0086] In an embodiment of the present application, the material of the third conductive material layer 221 includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and can also be any other suitable material.

[0087] In addition, in the embodiment, the size of the remaining third conductive material layer 221 needs to be controlled when etching the third conductive material layer 221, so as to prevent the first plate 310 of the silicon capacitor from being short-circuited with the second plate 330 of the silicon capacitor.

[0088] Please refer to Figure 8 As shown, after forming the second plate 220 of the high-voltage capacitor, a passivation layer is further formed, the passivation layer covers the exposed top layer of interlayer dielectric layer and exposes the lead-through end. In an embodiment of the present application, please refer to Figure 8 As shown, the passivation layer includes a first passivation layer 151 and a second passivation layer 152, the material of the first passivation layer 151 includes silicon oxynitride, and the material of the second passivation layer 152 includes PI (polyimide). In other embodiments, only one passivation layer can be formed, and the passivation layer can be silicon oxynitride or PI.

[0089] The application provides a semiconductor device manufacturing method, which comprises the following steps: forming a first plate 210 of a high-voltage capacitor; forming at least one interlayer dielectric layer on the first plate 210 of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor, and forming a conductive via 211 in each of the interlayer dielectric layers, wherein the conductive vias 211 are in communication with each other and with the first plate 210 of the high-voltage capacitor as an outgoing channel of the first plate 210; etching all the interlayer dielectric layers to form a deep groove 121; forming a first plate 310 of a silicon capacitor on the sidewall and bottom of the deep groove 121, wherein the first plate 310 of the silicon capacitor is in communication with the first plate 210 of the high-voltage capacitor; forming a dielectric layer 320 of the silicon capacitor on the sidewall and bottom of the deep groove 121, wherein the dielectric layer 320 of the silicon capacitor covers the first plate 310 of the silicon capacitor; forming a second plate 330 of the silicon capacitor in the deep groove 121, wherein the second plate 330 of the silicon capacitor fills the deep groove 121; and forming a second plate 220 of the high-voltage capacitor on the top interlayer dielectric layer.

[0090] Correspondingly, the application further provides a semiconductor device manufactured by the semiconductor device manufacturing method.

[0091] Please refer to Figure 8 The semiconductor device comprises:

[0092] a first plate 210 of a high-voltage capacitor;

[0093] at least one interlayer dielectric layer on the first plate 210 of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor, and a conductive via 211 in each of the interlayer dielectric layers, wherein the conductive vias 211 are in communication with each other and with the first plate 210 of the high-voltage capacitor as an outgoing channel of the first plate 210 of the high-voltage capacitor; and a deep groove 121 formed in the interlayer dielectric layer and penetrating the interlayer dielectric layer;

[0094] a first plate 310 of a silicon capacitor on the sidewall and bottom of the deep groove 121, wherein the first plate 310 of the silicon capacitor is in communication with the first plate 210 of the high-voltage capacitor;

[0095] a dielectric layer 320 of the silicon capacitor on the sidewall and bottom of the deep groove 121 and covering the first plate 310 of the silicon capacitor;

[0096] a second plate 330 of the silicon capacitor in the deep groove 121 and filling the deep groove 121; and

[0097] The second plate 220 of the high-voltage capacitor is located on the interlayer dielectric layer of the top layer.

[0098] In an embodiment of the present application, the material of the first plate 310 of the silicon capacitor includes but is not limited to titanium nitride, and the material of the second plate 330 of the silicon capacitor includes but is not limited to tungsten. The first plate 310 of the silicon capacitor and the second plate 330 of the silicon capacitor are both made of conductive material and do not need to be ion implanted, thus getting rid of the limitation of ion implantation process. The deposition process can uniformly deposit the conductive material on the inner wall of the whole deep trench, thus improving the uniformity of the first plate and reducing the parasitic resistance. Meanwhile, since the ion implantation process is not needed to be performed, more deep trenches can be accommodated in the interlayer dielectric layer, thus further increasing the integration level.

[0099] In an embodiment of the present application, the material of the dielectric layer 320 of the silicon capacitor includes ONO or silicon nitride, which can significantly improve the breakdown voltage of the silicon capacitor and avoid the breakdown of the weak position in the work due to the dielectric defects and the dielectric uniformity.

[0100] In summary, in the semiconductor device and the manufacturing method thereof provided by the present application, first, the first plate of the high-voltage capacitor is formed. Then, at least one interlayer dielectric layer is formed on the first plate as the dielectric layer of the high-voltage capacitor. Each of the interlayer dielectric layers is formed with a conductive via hole. The conductive via holes are in communication with each other and with the first plate of the high-voltage capacitor to serve as the lead-through channel of the first plate of the high-voltage capacitor. Then, the interlayer dielectric layer is etched to form a deep trench. Then, a first conductive layer is formed on the sidewall and the bottom of the deep trench as the first plate of the silicon capacitor. The first plate of the silicon capacitor is in communication with the first plate of the high-voltage capacitor. An insulating layer is formed on the sidewall and the bottom of the deep trench. The insulating layer covers the first conductive layer as the dielectric layer of the silicon capacitor. A second conductive layer is formed in the deep trench. The second conductive layer fills the deep trench as the second plate of the silicon capacitor. Then, a third conductive layer is formed on the interlayer dielectric layer of the top layer as the second plate of the high-voltage capacitor. The present application integrates the manufacturing of the high-voltage capacitor and the silicon capacitor in one process, thus saving the process steps, saving the manufacturing cost and improving the product competitiveness.

[0101] Further, the first plate and the second plate of the silicon capacitor are both made of conductive material and do not need to be ion implanted, thus getting rid of the limitation of ion implantation process. The deposition process can uniformly deposit the conductive material on the inner wall of the whole deep trench, thus improving the uniformity of the first plate and reducing the parasitic resistance. Meanwhile, since the ion implantation process is not needed to be performed, more deep trenches can be accommodated in the interlayer dielectric layer, thus further increasing the integration level.

[0102] In addition, the dielectric layer of the silicon capacitor adopts ONO or silicon nitride, which can significantly improve the breakdown voltage of the silicon capacitor, and avoid the breakdown of the weak position in the working process caused by dielectric defects and dielectric uniformity.

[0103] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: forming a first plate of a high voltage capacitor; forming at least one interlayer dielectric layer on the first plate of the high voltage capacitor as a dielectric layer of the high voltage capacitor, each of the interlayer dielectric layers is formed with a conductive via, the conductive vias are in communication with each other and with the first plate of the high voltage capacitor to serve as an outgoing channel of the first plate of the high voltage capacitor; etching the interlayer dielectric layers to form a deep trench; forming a first plate of a silicon capacitor on the sidewall and bottom of the deep trench, the first plate of the silicon capacitor is in communication with the first plate of the high voltage capacitor; forming a dielectric layer of the silicon capacitor on the sidewall and bottom of the deep trench, the dielectric layer of the silicon capacitor covers the first plate of the silicon capacitor; forming a second plate of the silicon capacitor in the deep trench, the second plate of the silicon capacitor fills the deep trench; and forming a second plate of the high voltage capacitor on the interlayer dielectric layer of the top layer; and forming the second plate of the high voltage capacitor at the same time as forming the outgoing ends of the first plate of the high voltage capacitor and the first plate of the silicon capacitor, and the outgoing end of the second plate of the silicon capacitor; the first plate of the high voltage capacitor and the first plate of the silicon capacitor share the same outgoing channel and the same outgoing end.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The step of forming the first plate of the high voltage capacitor comprises: providing a substrate, forming a bottom interlayer dielectric layer on the substrate; forming a first metal layer, the first metal layer covers part of the bottom interlayer dielectric layer; forming a first interlayer dielectric layer, the first interlayer dielectric layer covers the first metal layer and the bottom interlayer dielectric layer; forming a conductive via in the first interlayer dielectric layer that communicates with the first metal layer; forming a second metal layer, the second metal layer covers part of the first interlayer dielectric layer, and the second metal layer communicates with the first metal layer through the conductive via, the second metal layer serves as the first plate of the high voltage capacitor.

3. The method of manufacturing a semiconductor device according to claim 2, wherein In a direction perpendicular to the substrate, the first plate of the high voltage capacitor covers part of the first metal layer.

4. The method of manufacturing a semiconductor device according to Claim 2, wherein Etching all the interlayer dielectric layers to form a deep trench that exposes the first metal layer, the first plate of the silicon capacitor is in communication with the first plate of the high voltage capacitor through the first metal layer.

5. The method of manufacturing a semiconductor device according to claim 4, wherein Each of the interlayer dielectric layers on the first plate of the high voltage capacitor is also formed with a metal layer, the metal layer communicates with two adjacent conductive vias, and the metal layer and the conductive vias together constitute the outgoing channel of the first plate of the high voltage capacitor.

6. The method of manufacturing a semiconductor device according to claim 5, wherein The substrate comprises a first region and a second region, a semiconductor structure is formed in the second region, the high voltage capacitor and the silicon capacitor are formed in the first region; forming a plurality of interlayer dielectric layers in the second region, and forming a metal layer and a conductive via in each of the interlayer dielectric layers, the metal layer and the conductive via lead out the corresponding electrodes of the semiconductor structure; The first plate of the high-voltage capacitor is formed synchronously with the metal layer in the same layer in the second region, the dielectric layer of the high-voltage capacitor is formed synchronously with the interlayer dielectric layer in the same layer in the second region, and the lead-through channel is formed synchronously with the metal layer and the conductive via in the same layer in the second region.

7. The method of fabricating a semiconductor device according to Claim 2, wherein The method for etching the interlayer dielectric layer to form the deep trench comprises: forming a photoresist layer on the interlayer dielectric layer of the top layer; exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask to etch all the interlayer dielectric layers until the first metal layer is exposed; and removing the patterned photoresist layer.

8. The method of fabricating a semiconductor device according to Claim 1, wherein The method for forming the second plate of the high-voltage capacitor on the interlayer dielectric layer of the top layer comprises: forming a conductive material layer covering the interlayer dielectric layer of the top layer; etching the conductive material layer to expose part of the interlayer dielectric layer of the top layer, retaining the conductive material layer above the first plate of the high-voltage capacitor as the second plate of the high-voltage capacitor, retaining the conductive material layer on the lead-through channel as the first lead-through end of the first plate of the high-voltage capacitor and the first plate of the silicon capacitor, and retaining the conductive material layer on the second plate of the silicon capacitor as the second lead-through end of the second plate of the silicon capacitor.

9. The method of fabricating a semiconductor device according to Claim 1, wherein The materials of the first and second plates of the high-voltage capacitor comprise copper, tungsten, aluminum, ruthenium or cobalt, the material of the dielectric layer of the high-voltage capacitor comprises ethyl silicate, boron phosphorus silicon glass or low dielectric constant material, the material of the first plate of the silicon capacitor comprises titanium nitride, the material of the second plate of the silicon capacitor comprises tungsten, and the dielectric layer of the silicon capacitor comprises a silicon nitride layer or a stack of silicon oxide-silicon nitride-silicon oxide.

10. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1 to 9, and comprises: a first plate of a high-voltage capacitor; at least one interlayer dielectric layer on the first plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor, each of the interlayer dielectric layers is formed with a conductive via, the conductive vias are in communication with each other and with the first plate of the high-voltage capacitor as a lead-through channel of the first plate of the high-voltage capacitor, and a deep trench is formed in the interlayer dielectric layer; a first plate of a silicon capacitor on the sidewall and bottom of the deep trench, the first plate of the silicon capacitor being in communication with the first plate of the high-voltage capacitor; a dielectric layer of the silicon capacitor on the sidewall and bottom of the deep trench and covering the first plate of the silicon capacitor; a second plate of the silicon capacitor in the deep trench and filling the deep trench; and a second plate of the high-voltage capacitor on the interlayer dielectric layer of the top layer.

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