Ring gate transistor and manufacturing method thereof

Abstract

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for improving the yield of the gate-all-around transistor and improving the working performance of the gate-all-around transistor under the condition that a nano-structure material included in the gate-all-around transistor contains germanium. The gate-all-around transistor comprises a semiconductor substrate, an active structure and a gate stack structure, wherein the active structure and the gate stack structure are arranged on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region. Each layer of nano structure comprises a first material part and a second material part arranged on at least one side of the first material part along the thickness direction of the semiconductor substrate. The first material part and the second material part are made of germanium-containing semiconductor materials, and the germanium content in the second material part is larger than that in the first material part. And along the width direction of the gate stack structure, the side wall of the first material part is recessed inwards relative to the side wall of the second material part. The thickness of the second material part is less than or equal to 2nm. And the gate stack structure surrounds the periphery of each layer of nano structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate-all-around transistor and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, ring-gate transistors have emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with planar transistors and fin field effect transistors, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect. In addition, compared with silicon materials, germanium-containing semiconductor materials have higher carrier mobility. Therefore, when germanium-containing semiconductor materials are used to manufacture the channel region included in the ring-gate transistor, it is beneficial to improve the conduction characteristics of the channel region included in the ring-gate transistor.

[0003] However, the yield of the above-mentioned all-around gate transistor formed by the existing manufacturing method is low, which is not conducive to improving the working performance of the all-around gate transistor. Summary of the invention

[0004] The object of the present invention is to provide a ring-gate transistor and a manufacturing method thereof, which is used to improve the yield of the ring-gate transistor when the nanostructure material included in the ring-gate transistor contains germanium, thereby improving the working performance of the ring-gate transistor.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a ring-gate transistor, which includes: a semiconductor substrate, and an active structure and a gate stack structure arranged on the semiconductor substrate. The active structure includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region, and the channel region includes at least one layer of nanostructure. Each layer of nanostructure includes a first material portion, and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate. The materials of the first material portion and the second material portion are both germanium-containing semiconductor materials, and the germanium content in the second material portion is greater than the germanium content in the first material portion. Along the width direction of the gate stack structure, the sidewall of the first material portion is concave inward relative to the sidewall of the second material portion. The thickness of the second material portion is less than or equal to 2nm. The gate stack structure surrounds the periphery of each layer of nanostructure.

[0006] In the case of adopting the above technical solution, in the channel region included in the ring-gate transistor provided by the present invention, each layer of the nanostructure includes a first material part and a second material part. The first material part and the second material part are both germanium-containing semiconductor materials. Compared with silicon materials, germanium-containing semiconductor materials have higher carrier mobility. Therefore, the first material part and the second material part formed by the germanium-containing semiconductor material have higher carrier conduction characteristics, which is beneficial to improve the conductivity of the channel region and improve the driving ability of the ring-gate transistor. In addition, the germanium content in the second material part is greater than the germanium content in the first material part. Compared with the roughly the same germanium content in each part of the nanostructure, the presence of the second material part can further improve the carrier conduction characteristics of the nanostructure. Secondly, along the width direction of the gate stack structure, the side wall of the first material part is concave inward relative to the side wall of the second material part, indicating that in the process of manufacturing the ring-gate transistor, the etchant for etching the sacrificial layer (or the mask structure such as the sacrificial layer and the sacrificial gate) has an etching effect on the first material part, and the etching effect on the first material part is greater than the etching effect on the second material part. Therefore, the second material part arranged on both sides of the first material part along the thickness direction of the semiconductor substrate can isolate the two sides of the first material part from the outside world, reduce the influence of the above-mentioned etchant on the first material part, and facilitate the selective release of the nanostructure to have a larger carrier conduction area. In addition, the second material part is only arranged on both sides of the first material part along the thickness direction of the semiconductor substrate, and there is no second material part between the two sides of the first material part along the width direction and the gate stack structure. At this time, the first semiconductor layer used to manufacture the first material part and the second semiconductor layer used to manufacture the second material part can be directly epitaxially grown on the semiconductor substrate, which is highly compatible with the existing manufacturing process, will not increase the manufacturing difficulty of the ring-gate transistor, and improve the yield of the ring-gate transistor.

[0007] In one example, the material of the first material portion is Si 1-x Ge x , the material of the second material part is Si 1-y Ge y . Among them, 0<x<1, x<y≤1, (yx)≥0.15.

[0008] In one example, a sidewall edge line of the first material portion along a width direction of the gate stack structure is an arc line.

[0009] In one example, the thickness of the second material portion is less than or equal to 1 nm.

[0010] In one example, in the same nanostructure, the second material portion is disposed on both sides of the first material portion along the thickness direction of the semiconductor substrate.

[0011] In one example, the ring-gate transistor also includes a gate sidewall. The gate sidewall is arranged on both sides of the gate stack structure along the length direction. The active structure also includes a connection area arranged between the channel region and the source region and the drain region respectively. The connection area is continuous with the channel region. Wherein, along the width direction of the gate stack structure, the ratio of the minimum width of the second material part included in the channel region to the width of the second material part included in the connection area is greater than or equal to 0.95 and less than or equal to 1; and / or, the ratio of the minimum width of the first material part included in the channel region to the width of the first material part included in the connection area is greater than or equal to 0.8 and less than 1.

[0012] In a second aspect, the present invention provides a method for manufacturing a ring-gate transistor, the method for manufacturing a ring-gate transistor comprising: first, providing a semiconductor substrate. Next, forming an active structure on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region, and the channel region comprises at least one layer of nanostructure. Each layer of nanostructure comprises a first material portion, and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate. The materials of the first material portion and the second material portion are both germanium-containing semiconductor materials, and the germanium content in the second material portion is greater than the germanium content in the first material portion. Next, a surrounding gate stack structure is formed on the periphery of each layer of nanostructure. Along the width direction of the gate stack structure, the sidewall of the first material portion is recessed inward relative to the sidewall of the second material portion. The thickness of the second material portion is less than or equal to 2nm.

[0013] In one example, an active structure is formed on a semiconductor substrate, including: forming a fin-shaped structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin-shaped structure includes sacrificial layers and semiconductor stacks that are alternately stacked. Among the sacrificial layers and semiconductor stacks that are alternately stacked, the film layer located at the bottom is a sacrificial layer. The semiconductor stack includes a first semiconductor layer and a second semiconductor layer located on both sides of the first semiconductor layer along its own thickness. Next, a mask structure is formed across the fin-shaped structure. Next, the portion of the fin-shaped structure exposed outside the mask structure is processed to form a source region and a drain region. Next, at least a portion of the mask structure is removed; and the remaining sacrificial layer is removed so that the remaining first semiconductor layer forms a first material portion, and the remaining second semiconductor layer forms a second material portion, to obtain a channel region.

[0014] In one example, the material of the first material portion is Si 1-x Ge x , the material of the second material part is Si 1-y Ge y , the material of the sacrificial layer is Si 1-z Ge z . Among them, z<x<1, x<y≤1, 0≤z, (yx)≥0.15, (yz)≥0.3.

[0015] In one example, in the alternately stacked sacrificial layers and semiconductor layers, the film layer at the top is the sacrificial layer.

[0016] In one example, after removing the remaining sacrificial layer and before obtaining the channel region, the method for manufacturing the ring-gate transistor further includes: using a sacrificial oxidation process to round off the remaining first semiconductor layer and the remaining second semiconductor layer to reduce the surface roughness of the channel region.

[0017] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 A schematic longitudinal cross-sectional view of a portion of the structure of a gate-all-around transistor in the related art;

[0020] Figure 2 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 1 ;

[0021] Figure 3 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 2 ;

[0022] Figure 4 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 3 ;

[0023] Figure 5 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 4 ;

[0024] Figure 6 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 5 ;

[0025] Figure 7 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 6 ;

[0026] Figure 8 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 7 ;

[0027] Fig. 9 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 8 ;

[0028] Fig.10 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 9 ;

[0029] Fig.11 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 ;

[0030] Fig.12 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 one;

[0031] Fig.13 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 two;

[0032] Fig.14 Schematic diagram of the structure of the gate-all-around transistor during the manufacturing process provided by the embodiment of the present invention Figure 10 three.

[0033] Figure numerals: 11 is a semiconductor substrate, 12 is a gate stack structure, 13 is a source region, 14 is a drain region, 15 is a channel region, 16 is a nanostructure, 17 is a first material portion, 18 is a second material portion, 19 is a gate sidewall, 20 is a connection region, 21 is a shallow trench isolation structure, 22 is an interlayer dielectric layer, 23 is a fin structure, 24 is a sacrificial layer, 25 is a semiconductor stack, 26 is a first semiconductor layer, 27 is a second semiconductor layer, and 28 is a mask structure. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0035] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0036] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] With the development of semiconductor technology, ring-gate transistors have emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with planar transistors and fin field effect transistors, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect. In addition, compared with silicon materials, germanium-containing semiconductor materials have higher carrier mobility. Therefore, when germanium-containing semiconductor materials are used to manufacture the channel region included in the ring-gate transistor, it is beneficial to improve the conduction characteristics of the channel region included in the ring-gate transistor.

[0040] However, the yield of the above-mentioned ring-gate transistor formed by the existing manufacturing method is low. Specifically, in the actual manufacturing process, after forming a fin-shaped structure including alternating stacked sacrificial layers and channel layers, it is necessary to form a sacrificial gate and a gate sidewall across the fin-shaped structure. However, the etchant used to etch the material used to manufacture the sacrificial gate and the gate sidewall has a low etching selectivity for the channel layer containing germanium (especially the channel layer with a high germanium content in the material), and is prone to etching losses, resulting in poor quality of the nanostructure formed based on the channel layer containing germanium, and even device failure and reduced yield. When the etching selectivity between the channel layer with a low germanium content and the silicon material is not high, the size of the released nanostructure is quite different from the designed nanostructure, such as Figure 1 As shown, the range shown in the dotted box is the size of the designed nanostructure, while the actually obtained nanostructure 16 is an ellipse within the dotted box, resulting in a poor morphology of the nanostructure 16 and a small carrier conduction area.

[0041] In order to solve the above technical problems, an embodiment of the present invention provides a ring-gate transistor and a manufacturing method thereof. In the channel region included in the ring-gate transistor provided by the embodiment of the present invention, each layer of the nanostructure includes a first material portion and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate, and the germanium content in the second material portion is greater than the germanium content in the first material portion, so as to improve the conductivity of the channel region while improving the yield of the ring-gate transistor.

[0042] In a first aspect, an embodiment of the present invention provides a gate-all-around transistor. Fig.13 and Fig.14 As shown, the ring-gate transistor includes: a semiconductor substrate 11, and an active structure and a gate stack structure 12 arranged on the semiconductor substrate 11. The active structure includes a source region 13, a drain region 14 and a channel region 15. The channel region 15 is arranged between the source region 13 and the drain region 14, and the channel region 15 includes at least one layer of nanostructure 16. Each layer of nanostructure 16 includes a first material portion 17, and a second material portion 18 arranged on at least one side of the first material portion 17 along the thickness direction of the semiconductor substrate 11. The materials of the first material portion 17 and the second material portion 18 are both germanium-containing semiconductor materials, and the germanium content in the second material portion 18 is greater than the germanium content in the first material portion 17. Along the width direction of the gate stack structure 12, the sidewall of the first material portion 17 is concave inward relative to the sidewall of the second material portion 18. The thickness of the second material portion 18 is less than or equal to 2nm. The gate stack structure 12 surrounds the periphery of each layer of nanostructure 16.

[0043] When the above technical solution is adopted, Figures 2 to 14As shown, in the channel region 15 included in the ring-gate transistor provided by the embodiment of the present invention, each layer of the nanostructure 16 includes a first material portion 17 and a second material portion 18. The first material portion 17 and the second material portion 18 are both germanium-containing semiconductor materials. Compared with silicon materials, germanium-containing semiconductor materials have higher carrier mobility. Therefore, the first material portion 17 and the second material portion 18 formed by the germanium-containing semiconductor material have higher carrier conduction characteristics, which is beneficial to improving the conductivity of the channel region 15 and improving the driving ability of the ring-gate transistor. In addition, the germanium content in the second material portion 18 is greater than the germanium content in the first material portion 17. Compared with the roughly same germanium content in each part of the nanostructure 16, the existence of the second material portion 18 can further improve the carrier conduction characteristics of the nanostructure 16. Secondly, along the width direction of the gate stack structure 12, the side wall of the first material part 17 is concave inward relative to the side wall of the second material part 18, indicating that in the process of manufacturing the ring-gate transistor, the etchant for etching the sacrificial layer 24 (or the mask structure 28 such as the sacrificial layer 24 and the sacrificial gate) has an etching effect on the first material part 17, and the etching effect on the first material part 17 is greater than the etching effect on the second material part 18. Therefore, the second material part 18 arranged on both sides of the first material part 17 along the thickness direction of the semiconductor substrate 11 can isolate the two sides of the first material part 17 from the outside world, reduce the influence of the above-mentioned etchant on the first material part 17, and facilitate the selective release of the nanostructure 16 to have a larger carrier conduction area (wherein, Fig.14 The dashed box in the middle shows the size of the designed nanostructure, ranging from Fig.14 It can be seen that the size of the nanostructure 16 actually manufactured in the ring-gate transistor provided by the embodiment of the present invention is slightly different from the size of the designed nanostructure). In addition, the second material portion 18 is only arranged on both sides of the first material portion 17 along the thickness direction of the semiconductor substrate 11, and there is no second material portion 18 between the two sides of the first material portion 17 and the gate stack structure 12 along the width direction. At this time, the first semiconductor layer 26 for manufacturing the first material portion 17 and the second semiconductor layer 27 for manufacturing the second material portion 18 can be directly epitaxially grown on the semiconductor substrate 11, which is highly compatible with the existing manufacturing process, does not increase the manufacturing difficulty of the ring-gate transistor, and improves the yield of the ring-gate transistor.

[0044] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate formed with some structures. For example: when the ring-gate transistor provided in the embodiment of the present invention is a transistor of the second layer or higher layer in the semiconductor device, the semiconductor substrate includes a semiconductor structure located below the active structure and the gate stack structure, etc.

[0045] For the above active structure, the active structure includes a source region, a drain region and a channel region. Fig.14 As shown, the source region 13 and the drain region 14 are arranged on the semiconductor substrate 11 in a direction parallel to the surface of the semiconductor substrate 11. The channel region 15 is arranged between the source region 13 and the drain region 14, and the channel region 15 includes at least one layer of nanostructure 16. The embodiment of the present invention does not specifically limit the number of layers of the nanostructure 16 included in the channel region 15. The nanostructure may include only a single layer of nanostructure, or Fig.14 As shown, it may also include multiple layers of nanostructures 16 spaced apart and distributed along the thickness direction of the semiconductor substrate 11 .

[0046] Each layer of nanostructure includes a first material portion and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate. Specifically, the second material portion can be arranged only on one side of the first material portion along the thickness direction of the semiconductor substrate, and the second material portion can be arranged on the upper side or the lower side of the first material portion along the thickness direction of the semiconductor substrate. When the channel region includes multiple layers of nanostructures, and the second material portion in at least two layers of nanostructures is arranged only on one side of the first material portion along the thickness direction of the semiconductor substrate, in different layers of nanostructures including only a single layer of second material portion, different second material portions can be arranged on the same side of the corresponding first material portion along the thickness direction, or can be arranged on different sides of the corresponding first material portion. For example: the channel region includes three layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate, and the number of layers of different layers of nanostructures is sequentially sorted in the direction away from the semiconductor substrate, wherein the second layer of nanostructures and the third layer of nanostructures can include only a single layer of second material portion, the second material portion in the second layer of nanostructures can be arranged below the first material portion, and the second material portion in the third layer can be arranged above the second material portion.

[0047] Or, if Fig.14 As shown, in at least one layer of nanostructure 16, the second material portion 18 can be arranged on both sides of the first material portion 17 along the thickness direction of the semiconductor substrate 11 to further improve the carrier conduction characteristics of the nanostructure 16 and further improve the driving performance of the ring-gate transistor.

[0048] When the channel region includes multiple layers of nanostructures, the proportion of the nanostructures including the double-layer second material portion in all nanostructures can be set according to actual needs and is not specifically limited here.

[0049] In terms of materials, the materials of the source region and the drain region may include any semiconductor material such as silicon, silicon germanium or germanium.

[0050] As for the above-mentioned channel region, the materials of the first material part and the second material part can be any semiconductor material containing germanium, such as germanium silicon or germanium, as long as the germanium content in the second material part is greater than the germanium content in the first material part. As for the ratio of the germanium content in the first material part and the second material part, and the difference in the germanium content in the two materials, it can be determined according to the requirements for the driving performance of the ring-gate transistor in the actual application scenario, etc., and no specific limitation is made here.

[0051] For example, the material of the first material part may be Si 1-x Ge x , the material of the second material part can be Si 1-y Ge y . Wherein, 0<x<1, x<y≤1, (yx)≥0.15. For example, the material of the first material part can be Si 0.8 Ge 0.2 、Si 0.7 Ge 0.3 、Si 0.6 Ge 0.4 or Si 0.5 Ge 0.5 The material of the second material part can be Si 0.1 Ge 0.9 、Si 0.15 Ge 0.85 、Si 0.2 Ge 0.8 、Si 0.25 Ge 0.75 、Si 0.3 Ge 0.7 or Si 0.35 Ge 0.65 wait.

[0052] In terms of appearance, Fig.13 As shown, along the width direction of the gate stack structure 12, the sidewall of the first material part 17 can be in an arc shape or a fold line shape relative to the sidewall of the second material part 18. When the sidewall edge of the first material part 17 along the width direction of the gate stack structure 12 is an arc, the surface roughness of the nanostructure 16 along the width direction is small, which is conducive to further improving the carrier conduction characteristics of the nanostructure 16.

[0053] As for the dimensions of the first material portion and the second material portion, the thickness of the second material portion can be any value less than or equal to 2nm. For example, the thickness of the second material portion can be 0.1nm, 0.2nm, 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm.

[0054] Optionally, the thickness of the second material portion is less than or equal to 1 nm.

[0055] As for the width of the first material portion and the second material portion, they can be set according to the germanium content in the materials of the first material portion and the second material portion and actual needs, and are not specifically limited here.

[0056] For example, Fig.14 As shown, the above-mentioned ring-gate transistor may also include a gate spacer 19. The gate spacer 19 is arranged on both sides of the gate stack structure 12 along the length direction to isolate the gate stack structure 12 from other conductive structures to ensure that the ring-gate transistor has stable electrical characteristics. In this case, the active structure also includes a connection area 20 arranged between the channel region 15 and the source region 13 and the drain region 14 respectively. The connection area 20 is continuous with the channel region 15. In this case, along the width direction of the gate stack structure 12, the minimum width of the second material portion 18 included in the channel region 15 and the width of the second material portion 18 included in the connection area 20 may be greater than or equal to 0.95 and less than or equal to 1; and / or, the minimum width of the first material portion 17 included in the channel region 15 and the width of the first material portion 17 included in the connection area 20 may be greater than or equal to 0.8 and less than 1. It can be understood that, in the case where the gate-all-around transistor further includes a gate spacer 19, the width of the portion of the active structure surrounded by the gate spacer 19 (i.e., the connection area 20) is not affected by the corresponding etchant when removing the mask structure 28 such as the sacrificial gate and the sacrificial layer 24. Based on this, when the ratio of the minimum width of the first material portion 17 and / or the second material portion 18 to the width of the corresponding first material portion 17 and / or the corresponding second material portion 18 in the connection area 20 is within the above range, after the nanostructure 16 is released, the proportion of the first material portion 17 and / or the second material portion 18 lost along the width direction is small, which is conducive to making the nanostructure 16 have a relatively large conduction area.

[0057] The material of the gate sidewall may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0058] For the above-mentioned gate stack structure, the gate stack structure surrounds the periphery of each layer of nanostructure. Fig.14 As shown, the gate stack structure 12 may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the periphery of each layer of nanostructures 16 included in the channel region 15 and covers the portion of the semiconductor substrate 11 corresponding to the gate formation region. The gate is located on the gate dielectric layer.

[0059] Among them, in the gate stack structure, the material of the gate dielectric layer can be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3, and the material of the gate can be a conductive material such as TiN, TaN or TiSiN.

[0060] In some cases, such as Figures 9 to 14As shown, the ring-gate transistor provided by the embodiment of the present invention may also include a shallow trench isolation structure 21 and / or an interlayer dielectric layer 22. The above-mentioned shallow trench isolation structure 21 is located on the semiconductor substrate 11, and is used to isolate different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 21 can be set according to actual conditions. The above-mentioned interlayer dielectric layer 22 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 12, which is used to protect the source area 13 and the drain area 14 from being affected by operations such as etching and cleaning when at least part of the mask structure 28 and the sacrificial layer 24 are removed.

[0061] The material of at least one of the shallow trench isolation structure and the interlayer dielectric layer may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0062] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Figures 2 to 14 The manufacturing process is described by a stereoscopic view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the ring-gate transistor includes the following steps:

[0063] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above and will not be described in detail here.

[0064] Next, if Figures 2 to 13 As shown, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 13, a drain region 14 and a channel region 15. The channel region 15 is arranged between the source region 13 and the drain region 14, and the channel region 15 includes at least one layer of nanostructure 16. Each layer of nanostructure 16 includes a first material portion 17 and a second material portion 18 arranged on at least one side of the first material portion 17 along the thickness direction of the semiconductor substrate 11. The materials of the first material portion 17 and the second material portion 18 are both germanium-containing semiconductor materials, and the germanium content in the second material portion 18 is greater than the germanium content in the first material portion 17.

[0065] Specifically, the materials and specific structural morphology of each part in the active structure can be referred to in the previous text and will not be repeated here.

[0066] Exemplarily, the above-mentioned forming of an active structure on a semiconductor substrate may include the steps of:

[0067] like Figures 2 to 4 As shown, a fin structure 23 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 23 includes a sacrificial layer 24 and a semiconductor stack 25 that are alternately stacked. Among the sacrificial layers 24 and the semiconductor stack 25 that are alternately stacked, the film layer located at the bottom is the sacrificial layer 24. The semiconductor stack 25 includes a first semiconductor layer 26, and a second semiconductor layer 27 located on both sides of the first semiconductor layer 26 along its own thickness.

[0068] Specifically, in the above-mentioned semiconductor stack, the first semiconductor layer is at least used to manufacture the first material part included in the nanostructure in the channel region. Therefore, the material and thickness of each first semiconductor layer and the number of layers of the semiconductor stack included in the fin structure can be determined based on the material and thickness of the first material part included in each layer of the nanostructure in the manufactured ring-gate transistor and the number of layers of the nanostructure included in the channel region.

[0069] The above-mentioned second semiconductor layer is at least used to manufacture the second material part included in the nanostructure in the channel region, so the material and thickness of each second semiconductor layer can be determined according to the material and thickness of the second material part included in each layer of the nanostructure in the manufactured ring-gate transistor, as well as the number of layers and formation position of the second material part included in each layer of the nanostructure. It can be understood that the number of layers of the second semiconductor layer included in each semiconductor stack is greater than or equal to the number of layers of the second material part included in the corresponding layer of the nanostructure, and the thickness of the second semiconductor layer is greater than the thickness of the second material part. Among them, the difference in thickness of the second semiconductor layer and the second material part can be determined according to the actual manufacturing process, and is not specifically limited here.

[0070] As for the sacrificial layer, each layer of the nanostructure will be released later by selectively removing the remaining sacrificial layer, so the material of the sacrificial layer can be any semiconductor material different from the first semiconductor layer and the second semiconductor layer.

[0071] For example, the material of the first semiconductor layer may be Si 1-x Ge x The material of the second semiconductor layer can be Si 1- y Ge y The material of the sacrificial layer can be Si 1-z Ge z . Wherein, z<x<1, x<y≤1, 0≤z, (yx)≥0.15, (yz)≥0.3. In this case, the sacrificial layer has a large etching selectivity ratio with the first semiconductor layer and the second semiconductor layer, respectively, which is beneficial for the nanostructure to have a large conduction area after the nanostructure is released. Among them, the difference in germanium content in the first semiconductor layer, the second semiconductor layer and the sacrificial layer can be determined according to the driving performance, yield and manufacturing process difficulty of the manufactured ring-gate transistor in the actual application scenario, and is not specifically limited here.

[0072] For example, the material of the sacrificial layer can be Si, Si 0.95 Ge 0.05 or Si 0.9 Ge 0.1 The material of the first semiconductor layer can be Si 0.8 Ge 0.2、Si 0.7 Ge 0.3 、Si 0.6 Ge 0.4 or Si 0.5 Ge 0.5 The material of the second semiconductor layer can be Si 0.1 Ge 0.9 、Si 0.15 Ge 0.85 、Si 0.2 Ge 0.8 、Si 0.25 Ge 0.75 、Si 0.3 Ge 0.7 or Si 0.35 Ge 0.65 wait.

[0073] In addition, in the fin structure, e.g. Figure 4 As shown, in the sacrificial layer 24 and the semiconductor stack 25 that are alternately stacked, the film layer at the top layer can be a sacrificial layer or a semiconductor stack 25. Among them, when the film layer at the top layer of the sacrificial layer and the semiconductor stack that are alternately stacked is a sacrificial layer and the material of the sacrificial layer is silicon, the process window can be increased, and it can be more compatible with the existing manufacturing process of the fin field effect transistor or the ring gate transistor including the silicon channel (such as the polysilicon etching process, which is easier to stop on the silicon sacrificial layer), which can reduce the difficulty of manufacturing the ring gate transistor provided by the embodiment of the present invention and improve the yield of the manufactured ring gate transistor.

[0074] In the actual manufacturing process, Figure 2 As shown, epitaxy or other processes can be used to form a sacrificial layer 24, a first semiconductor layer 26, and a second semiconductor layer 27 on the semiconductor substrate 11 according to the relative position relationship of each film layer in the fin structure. Then, as shown in FIG. Figure 3 As shown, the sacrificial layer 24, the first semiconductor layer 26, the second semiconductor layer 27 and a portion of the semiconductor substrate 11 may be etched by photolithography and etching to form a fin. Figure 4 As shown, a shallow trench isolation structure 21 is formed on a semiconductor substrate 11 by using processes such as deposition and etching. The material of the shallow trench isolation structure 21 can refer to the above. Secondly, the top height of the shallow trench isolation structure 21 is less than or equal to the bottom height of the sacrificial layer 24 located at the bottom layer, and the part of the fin exposed outside the shallow trench isolation structure 21 is a fin-shaped structure 23.

[0075] Alternatively, when the semiconductor substrate is a semiconductor substrate such as silicon on insulator containing a buried oxide layer, the above-mentioned shallow trench isolation structure may not be formed, and the sacrificial layer, the first semiconductor layer and the second semiconductor layer may be directly etched. In this case, the fin formed on the semiconductor substrate is a fin-shaped structure.

[0076] Next, if Figure 5 and Figure 6 As shown, a mask structure 28 is formed across the fin structure 23 .

[0077] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a protective role in the subsequent mask.

[0078] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here.

[0079] Next, if Figure 7 and Figure 8 As shown, the portion of the fin structure exposed outside the mask structure 28 is processed to form a source region 13 and a drain region 14 .

[0080] For example, Figure 7 As shown, a dry etching or wet etching process may be used to remove the portion of the fin structure exposed outside the mask structure 28; and Figure 8 As shown, an epitaxial process is used to form a source region 13 and a drain region 14 on both sides of the remaining fin structure.

[0081] Alternatively, diffusion or ion implantation or other processes may be used to perform doping treatment on the portion of the fin structure exposed outside the mask structure to form a source region and a drain region.

[0082] Next, if Fig. 9 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 22 covering the semiconductor substrate 11. The top of the interlayer dielectric layer 22 is flush with the top of the mask structure 28. The material of the interlayer dielectric layer 22 can refer to the above.

[0083] Next, if Figures 10 to 12 As shown, dry etching or wet etching processes can be used to remove at least part of the mask structure; and the remaining sacrificial layer 24 can be removed so that the remaining first semiconductor layer 26 forms the first material portion 17, and the remaining second semiconductor layer 27 forms the second material portion 18, thereby obtaining the channel region 15.

[0084] Specifically, the scope of mask structure removal can be determined according to the specific structure of the mask structure, as long as the remaining fin structure can be exposed. For example, when the mask structure only includes a sacrificial gate (or only includes a sacrificial layer and a gate oxide layer), the mask structure needs to be completely removed. Another example: when the mask structure can include a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, and only part of the mask structure is removed.

[0085] Alternatively, the channel region may be obtained after removing the remaining sacrificial layer. Fig.12 As shown in FIG. 1 , after removing the remaining sacrificial layer, the surfaces of the remaining first semiconductor layer and the second semiconductor layer are relatively rough. Fig.13 As shown, a process such as sacrificial oxidation can be used to smooth the remaining first semiconductor layer and the remaining second semiconductor layer to reduce the surface roughness of the channel region 15 and further improve the working performance of the manufactured all-around gate transistor.

[0086] Next, if Fig.14 As shown, atomic layer deposition and other processes can be used to form a surrounding gate stack structure 12 around each layer of nanostructure 16. Along the width direction of the gate stack structure 12, the sidewall of the first material part 17 is concave inward relative to the sidewall of the second material part 18. The thickness of the second material part 18 is less than or equal to 2nm.

[0087] Among them, the specific structure and materials of the gate stack structure can be referred to in the previous text and will not be repeated here.

[0088] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0089] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0090] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A gate-all-around transistor, characterized in that: include: A semiconductor substrate, and an active structure and a gate stack structure disposed on the semiconductor substrate; The active structure includes a source region, a drain region and a channel region; the channel region is arranged between the source region and the drain region, and the channel region includes at least one layer of nanostructure; each layer of nanostructure includes a first material portion, and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate; the materials of the first material portion and the second material portion are both germanium-containing semiconductor materials, and the germanium content in the second material portion is greater than the germanium content in the first material portion; along the width direction of the gate stack structure, the sidewall of the first material portion is concave inward relative to the sidewall of the second material portion; the thickness of the second material portion is less than or equal to 2nm; The gate stack structure surrounds the periphery of each layer of the nanostructure.

2. The gate-all-around transistor according to claim 1, characterized in that: The material of the first material part is Si 1-x Ge x , the material of the second material part is Si 1-y Ge y ; Among them, 0<x<1, x<y≤1, (yx)≥0.

15.

3. The gate-all-around transistor according to claim 1, wherein: The sidewall edge line of the first material portion along the width direction of the gate stack structure is an arc line.

4. The gate-all-around transistor according to claim 1, wherein: The thickness of the second material portion is less than or equal to 1 nm; And / or, in the same nanostructure, the second material portion is arranged on both sides of the first material portion along the thickness direction of the semiconductor substrate.

5. The gate-all-around transistor according to claim 1, wherein: The gate-all-around transistor further includes a gate spacer; the gate spacer is arranged on both sides of the gate stack structure along the length direction; the active structure further includes a connection region arranged between the channel region and the source region and the drain region respectively; the connection region is integrally continuous with the channel region; Along the width direction of the gate stack structure, the ratio of the minimum width of the second material part included in the channel region to the width of the second material part included in the connection region is greater than or equal to 0.95 and less than or equal to 1; and / or the ratio of the minimum width of the first material part included in the channel region to the width of the first material part included in the connection region is greater than or equal to 0.8 and less than 1.

6. A method for manufacturing a gate-all-around transistor, characterized in that: include: Providing a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region and a channel region; the channel region is arranged between the source region and the drain region, and the channel region includes at least one layer of nanostructure; each layer of nanostructure includes a first material portion and a second material portion arranged on at least one side of the first material portion along the thickness direction of the semiconductor substrate; the materials of the first material portion and the second material portion are both germanium-containing semiconductor materials, and the germanium content in the second material portion is greater than the germanium content in the first material portion; A surrounding gate stack structure is formed at the periphery of each layer of the nanostructure; along the width direction of the gate stack structure, the side wall of the first material part is concave inward relative to the side wall of the second material part; the thickness of the second material part is less than or equal to 2nm.

7. The method for manufacturing a gate-all-around transistor according to claim 6, wherein: The active structure is formed on the semiconductor substrate, comprising: A fin-shaped structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin-shaped structure includes a sacrificial layer and a semiconductor stack arranged alternately in layers; among the sacrificial layer and the semiconductor stack arranged alternately in layers, the film layer located at the bottom is the sacrificial layer; the semiconductor stack includes a first semiconductor layer and a second semiconductor layer located on both sides of the first semiconductor layer along its thickness; forming a mask structure spanning over the fin-shaped structure; Processing the portion of the fin structure exposed outside the mask structure to form the source region and the drain region; At least a portion of the mask structure is removed; and the remaining sacrificial layer is removed, so that the remaining first semiconductor layer forms the first material portion, and the remaining second semiconductor layer forms the second material portion, to obtain the channel region.

8. The method for manufacturing a gate-all-around transistor according to claim 7, characterized in that: The material of the first material part is Si 1-x Ge x , the material of the second material part is Si 1-y Ge y The material of the sacrificial layer is Si 1-z Ge z ; Among them, z<x<1, x<y≤1, 0≤z, (yx)≥0.15, (yz)≥0.

3.

9. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: In the alternately stacked sacrificial layers and semiconductor layers, the film layer located at the top layer is the sacrificial layer.

10. The method for manufacturing a gate-all-around transistor according to claim 7, wherein: After removing the remaining sacrificial layer and before obtaining the channel region, the method for manufacturing the gate-all-around transistor further includes: The remaining first semiconductor layer and the remaining second semiconductor layer are rounded by using a sacrificial oxidation process to reduce the surface roughness of the channel region.

Images