Thin film transistor, preparation method thereof and array substrate
By using a material with a high proportion of indium elements in the first active layer of the thin film transistor, the problem of poor performance and reliability of traditional thin film transistors is solved, and higher carrier mobility and conductivity are achieved to meet the driving needs of high-fine panels.
Patent Information
- Application Number
- CN202510107421.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-04-25
AI Technical Summary
Traditional thin film transistors have high in-film defect problems, resulting in poor performance and reliability, which cannot meet the driving needs of high-fine panels.
By providing a first channel region in the first active layer of the thin film transistor, the proportion of indium elements in the preparation material is greater than 50% to improve carrier mobility and thus improve conductivity and reliability.
It effectively reduces in-film defects, improves carrier mobility of thin film transistors, improves conductivity and reliability, and enables it to meet the driving requirements of high-fine panels.
Smart Images
Figure CN119894056A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a preparation method thereof, and an array substrate. Background Art
[0002] With the continuous development of science and technology, the demand for high-definition panels with high image resolution has become a trend in the industry. This requires the thin-film transistors in the display panels to have higher performance and higher reliability. Traditional thin-film transistors have a high degree of intra-film defects, resulting in poor performance and reliability, and thus cannot meet the driving requirements of high-definition panels. Summary of the invention
[0003] Based on this, it is necessary to provide a thin film transistor and a preparation method thereof, an array substrate and a display panel that can improve the performance and reliability of the thin film transistor in order to address the above technical problems.
[0004] In a first aspect, the present application provides a thin film transistor, comprising a first active layer, a gate, and a source-drain electrode layer stacked in sequence, wherein the gate is insulated from the first active layer and the source-drain electrode layer respectively;
[0005] The first active layer includes a first channel region, and the indium element accounts for more than 50% of the material used to prepare the first channel region.
[0006] In one embodiment, the preparation material of the first channel region includes at least any one of indium oxide, indium gallium oxide, indium zinc oxide, and indium tin oxide;
[0007] Optionally, the indium element accounts for more than 70% of the material used to prepare the first channel region.
[0008] In one embodiment, the proportion of metal-oxygen bonds in the first channel region is greater than 50%; and / or,
[0009] The metal-oxygen bond energy of the first channel region ranges from 524.5 eV to 534.5 eV;
[0010] Optionally, the proportion of metal-oxygen bonds in the first channel region is greater than 70%.
[0011] In one embodiment, the proportion of oxygen vacancies in the first channel region is less than 30%; and / or,
[0012] The bond energy of the oxygen vacancy in the first channel region ranges from 526 eV to 536 eV;
[0013] Optionally, the proportion of oxygen vacancies in the first channel region is less than 20%.
[0014] In one embodiment, the proportion of hydrogen-oxygen bonds in the first channel region is less than 20%; and / or,
[0015] The bond energy of the hydrogen-oxygen bond in the first channel region ranges from 527 eV to 537 eV;
[0016] Optionally, the proportion of hydrogen-oxygen bonds in the first channel region is less than 5%.
[0017] In one embodiment, the first channel region includes a crystalline oxide material layer.
[0018] In one of the embodiments, a second active layer is also included;
[0019] The second active layer is disposed on a surface of the first active layer facing the source-drain electrode layer, and / or the second active layer is disposed on a surface of the first active layer facing away from the source-drain electrode layer;
[0020] Optionally, the second active layer includes a second channel region, the second channel region is arranged on a side of the first channel region facing the source-drain layer, and / or the second channel region is arranged on a side of the first channel region facing away from the source-drain layer;
[0021] Optionally, the preparation material of the second channel region includes at least any one of indium gallium zinc oxide and gallium-doped zinc oxide;
[0022] Optionally, the carrier mobility of the first channel region is greater than the carrier mobility of the second channel region;
[0023] Optionally, the thickness of the second active layer is less than or equal to 200Å.
[0024] In a second aspect, the present application further provides an array substrate, comprising the thin film transistor described in any embodiment of the first aspect.
[0025] In a third aspect, the present application further provides a method for preparing a thin film transistor, comprising:
[0026] providing a substrate base plate;
[0027] forming a first active film on one side of the base substrate;
[0028] Annealing the first active film at a high temperature and patterning it to form a first active layer of the thin film transistor; the first active layer includes a first channel region, and the indium element accounts for more than 50% of the material prepared in the first channel region;
[0029] An insulating layer is prepared on a side of the first active layer away from the substrate, and a second metal layer is prepared on a side of the insulating layer away from the first active layer. The second metal layer is patterned to form a source and drain layer of the thin film transistor.
[0030] In one of the embodiments, after providing the base substrate, the method further includes: forming a first metal layer on one side of the base substrate, and patterning the first metal layer to form a gate of the thin film transistor;
[0031] After providing the base substrate, the method further includes: forming a second active film on one side of the base substrate; annealing the second active film at a high temperature and patterning the second active film to form a second active layer of the thin film transistor; the second active layer includes a second channel region.
[0032] In the thin film transistor and its preparation method, array substrate and display panel provided by the present application, the thin film transistor is provided to include a first active layer, a gate and a source-drain layer stacked in sequence, and the first active layer at least includes a first channel region, and the preparation material of the first channel region is provided to include indium element, and the proportion of indium element in the preparation material is set to be greater than 50%, so as to ensure that the first channel region includes a relatively large proportion of indium element, which is beneficial to improve the carrier mobility of the first channel region, and further beneficial to improve the conductive performance and reliability of the thin film transistor including the first active layer, so that the thin film transistor can meet the driving requirements of the high-precision panel to improve the resolution of the relevant display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0034] Figure 1 A schematic diagram of an array substrate provided in an embodiment of the present application;
[0035] Figure 2 Provided in the embodiments of this application Figure 1 Schematic diagram of the first cross section of AA';
[0036] Figure 3 Provided in the embodiments of this application Figure 1 Schematic diagram of the second cross section of AA';
[0037] Figure 4 Provided in the embodiments of this application Figure 1 Schematic diagram of the third cross section of AA';
[0038] Figure 5 Provided in the embodiments of this application Figure 1 Schematic diagram of the fourth cross section of AA';
[0039] Figure 6 Provided in the embodiments of this application Figure 1 Schematic diagram of the fifth cross section of AA';
[0040] Figure 7 A schematic diagram of a display panel provided in an embodiment of the present application;
[0041] Figure 8 A preparation flow chart of a thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION
[0042] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0043] As described in the background art, conventional thin film transistors have a high degree of intra-film defects, resulting in poor performance and reliability, and thus cannot meet the driving requirements of high-definition panels.
[0044] The applicant has found through research that crystalline oxide TFT (Thin Film Transistor) has greater potential than amorphous oxide TFT to reduce the defects within the film, so that the TFT can have better reliability; therefore, how to reduce the defects within the TFT film is the key to achieving high reliability and high mobility TFT.
[0045] Based on this, the present application provides a thin film transistor, which includes a first active layer, a gate layer and a source / drain layer stacked in sequence, wherein the preparation material of the first channel region in the first active layer includes an indium element, and the proportion of the indium element in the preparation material of the first channel region is set to be greater than 50%, so as to ensure that the first channel region includes a relatively large proportion of indium elements, thereby reducing the film defects in the first channel region, improving the carrier mobility in the first channel region, and further facilitating improving the conductivity and reliability of the thin film transistor including the first active layer.
[0046] Please refer to Figure 1-Figure 3The array substrate 100 provided in the present application includes a plurality of thin film transistors 10 arranged in an array; wherein the thin film transistor 10 includes a first active layer 111, a gate 12 and a source-drain electrode layer 13 stacked in sequence, and the gate 12 is insulated from the active layer 11 including the first active layer 111 and the source-drain electrode layer 13 respectively; the first active layer 111 includes a first channel region 91, and the proportion of indium in the preparation material of the first channel region 91 is greater than 50%.
[0047] For example, Figure 2 and Figure 3 As shown, the present application provides an optional structure of a thin film transistor 10, including an active layer 11, a gate 12 and a source-drain electrode layer 13 stacked in sequence, wherein the active layer 11 and the gate 12 are insulated, and the gate 12 and the source-drain electrode layer 13 are insulated; the source-drain electrode layer 13 includes a source electrode and a drain electrode, which are electrically connected to the injection region of the active layer 11 respectively, and the orthographic projection of the gate 12 on the plane where the substrate 21 for preparing the thin film transistor 10 is located at least partially overlaps with the orthographic projection of the active layer 11 on the plane where the substrate 21 is located; thereby, the thin film transistor 10 provided in the present application is formed by stacking the active layer 11, the gate 12 and the source-drain electrode layer 13 in a direction perpendicular to the plane where the substrate 21 is located.
[0048] The present application does not specifically limit whether the thin film transistor 10 has a top gate structure or a bottom gate structure. Figure 2 As shown, along the direction perpendicular to the plane of the substrate 21, the gate 12 in the thin film transistor 10 can be arranged between the active layer 11 and the source and drain layer 13, that is, the thin film transistor 10 is arranged as a top gate structure; Figure 3 As shown, the gate electrode 12 is disposed between the active layer 11 and the base substrate 21 in a direction perpendicular to the plane where the base substrate 21 is located, that is, the thin film transistor 10 is disposed as a bottom gate structure. For the multiple thin film transistors 10 included in the same array substrate 100, they can be configured as thin film transistors 10 including only top gate structures, thin film transistors 10 including only bottom gate structures, or thin film transistors 10 including both top gate structures and bottom gate structures, and the present application does not make specific limitations on this.
[0049] Among them, for the active layer 11 of the thin film transistor 10, the present application provides an optional setting method, that is, the active layer 11 includes at least a first active layer 111, and the first channel region 91 of the first active layer 111 is prepared by a preparation material containing indium elements, and the proportion of indium elements in the preparation material used to prepare the first channel region 91 is controlled to be greater than 50%. Through this setting, it is ensured that the first channel region 91 includes a relatively large proportion of indium elements. The high proportion of indium elements is conducive to improving the mobility of the prepared first channel region 91, and then it is conducive to improving the conductivity and reliability of the thin film transistor 10 including the first channel region 91, so that the thin film transistor 10 can meet the driving requirements of the high-precision panel to improve the resolution of the relevant display panel. At the same time, it is also conducive to ensuring that when the thin film transistor 10 is working, the light-emitting element driven by the thin film transistor 10 has stable illumination, which is conducive to improving the display effect of the display device including the thin film transistor 10.
[0050] The active layer 11 of the thin film transistor 10 provided in the present application includes a first active layer 111, but the present application does not limit the thin film transistor 10 to include only the first active layer 111. If necessary, the active layer 11 of the thin film transistor 10 may include other active layers in addition to the first active layer 111. The other active layers may be stacked with the first active layer 111 in a direction perpendicular to the plane of the substrate 21.
[0051] The thin film transistor 10 provided in the present application includes a first active layer 111, a gate electrode 12 and a source-drain electrode layer 13 which are stacked, and the preparation material of the first channel region 91 of the first active layer 111 includes indium element, and the proportion of indium element in the preparation material is set to be greater than 50%, so as to ensure that the first channel region 91 includes a relatively large proportion of indium element, which is beneficial to improve the carrier (electron) mobility of the first channel region 91, and further beneficial to improve the conductive performance and reliability of the thin film transistor 10 including the first active layer 111, so that the thin film transistor 10 can meet the driving requirements of the high-precision panel to improve the resolution of the relevant display panel.
[0052] Optionally, the proportion of indium in the preparation material of the first channel region 91 is greater than 70%. Setting the proportion of indium in the first channel region 91 to be large enough is beneficial to further improve the crystallization film forming effect of the first channel region 91 in the first active layer 111.
[0053] Please continue to refer to Figure 1-Figure 3 In an exemplary embodiment, the material used to prepare the first channel region 91 includes at least any one of indium oxide, indium gallium oxide, indium zinc oxide, and indium tin oxide.
[0054] Exemplarily, for the preparation material of the first active layer 111, especially the preparation material of the first channel region 91 of the first active layer 111, the present application provides several optional preparation materials, namely InO (indium oxide), InGaO (indium gallium oxide), InZnO (indium zinc oxide), and InSnO (indium tin oxide); in addition, the preparation material of the first channel region 91 of the first active layer 111 can also be any one of InO, InGaO, InZnO, and InSnO, plus additional minority elements as doping. That is, the crystalline oxide material layer (the first channel region 91 of the first active layer 111) of the thin film transistor 10 provided by the present application can be a single crystalline oxide channel.
[0055] Since the first channel region 91 of the first active layer 111 made of a material containing the indium element has better carrier mobility, the first active layer 111 prepared by using at least any one of indium oxide, indium gallium oxide, indium zinc oxide, and indium tin oxide can have relatively good (electron) mobility, which is beneficial to improving the conductivity and reliability of the thin film transistor 10 including the first active layer 111.
[0056] When preparing the first channel region 91 of the first active layer 111 using a preparation material including any one of indium oxide, indium gallium oxide, indium zinc oxide, and indium tin oxide, the preparation material is subjected to annealing and crystallization treatment to obtain a crystalline oxide material layer (the first channel region 91 of the first active layer 111).
[0057] Please continue to refer to Figure 1-Figure 3 In an exemplary embodiment, the metal-oxygen bonds (MO, M represents metal and O represents oxygen) in the first channel region 91 account for more than 50%; and / or the bond energy of the metal-oxygen bonds in the first channel region 91 ranges from 524.5 eV to 534.5 eV.
[0058] Exemplarily, for the first channel region 91 of the first active layer 111 included in the thin film transistor 10 provided in the present application, the proportion of metal-oxygen bonds therein can be selectively controlled to be above 50%, for example, the proportion of metal-oxygen bonds (metal-oxygen bonding) in the first channel region 91 can be controlled to be 51%, or 55%, or 70%, or 75%, etc.; optionally, the proportion of metal-oxygen bonds in the first channel region 91 can also be directly controlled to be above 70%. Among them, materials with metal-oxygen bonds are easier to extract electrons than materials without metal-oxygen bonds. Therefore, the present application improves the carrier mobility of the first active layer 111 by controlling the proportion of metal-oxygen bonds in the first channel region 91 to be sufficiently large, which is conducive to improving the conductivity and reliability of the thin film transistor 10 including the first active layer 111.
[0059] If the proportion of metal-oxygen bonding is small, there will be too many oxygen vacancies in the first channel region 91 of the first active layer 111 , which will cause more defects in the first channel region 91 and will be detrimental to the stability of the use of the related thin film transistor 10 .
[0060] Exemplarily, for the metal-oxygen bond (MO) included in the first channel region 91 of the first active layer 111, the bond energy value of the metal-oxygen bond can be set to 529.5eV±5eV, where "eV" is a unit of measurement for bond energy, which can be translated as electron volt or electron volt. If the bond energy value of the metal-oxygen bond is too small, the stability of the relevant first active layer 111 will be reduced, and if the bond energy value is too large, the energy of the first channel region 91 of the relevant first active layer 111 will be too low; therefore, the present application sets the bond energy value of the metal-oxygen bond in the first channel region 91 to 529.5eV±5eV, which is conducive to ensuring the stability and reliability of the thin film transistor 10 including the first active layer 111.
[0061] Please continue to refer to Figure 1-Figure 3 In an exemplary embodiment, the proportion of oxygen vacancies in the first channel region 91 is less than 30%; and / or the bond energy of the oxygen vacancies in the first channel region 91 ranges from 526 eV to 536 eV.
[0062] Exemplarily, for the first channel region 91 of the first active layer 111 included in the thin film transistor 10 provided in the present application, the proportion of oxygen vacancies therein can be selectively controlled to be less than 30%, for example, the proportion of oxygen vacancies in the first channel region 91 can be controlled to be 29%, or 25%, or 20%, or 15%, etc.; optionally, the proportion of oxygen vacancies in the first channel region 91 in the first active layer 111 can also be directly controlled to be less than 20%. Among them, the smaller the proportion of oxygen vacancies in the first channel region 91 is controlled, the more conducive it is to increase the proportion of metal-oxygen bonds in the first channel region 91, thereby facilitating the improvement of the electrical stability of the first active layer 111, thereby facilitating the reduction of the electrical characteristic drift of the thin film transistor 10 including the first active layer 111, and improving the conductivity and reliability of the thin film transistor 10 including the first active layer 111.
[0063] Exemplarily, for the oxygen vacancies (Vo) included in the first channel region 91, the bond energy value of the oxygen vacancies can be set to 531eV±5eV. If the bond energy value of the oxygen vacancies is too small, the stability of the relevant first channel region 91 will be reduced, and if the bond energy value is too large, the energy of the relevant first channel region 91 will be too low; therefore, the present application sets the bond energy value of the oxygen vacancies in the first channel region 91 to 531eV±5eV, which is conducive to ensuring the stability and reliability of the thin film transistor 10 including the first active layer 111.
[0064] Please continue to refer to Figure 1-Figure 3In an exemplary embodiment, the proportion of hydrogen-oxygen bonds in the first channel region 91 is less than 20%.
[0065] Exemplarily, for the first channel region 91 of the first active layer 111 included in the thin film transistor 10 provided in the present application, the effective substances therein may be selected to be controlled to account for more than 80%; to control the impurities in the first channel region 91, for example, the proportion of hydrogen-oxygen bonds is less than 20%; optionally, for example, the proportion of hydrogen-oxygen bonds in the first channel region 91 may be controlled to be 19%, or 15%, or 5%, or 2%, etc.; optionally, the proportion of hydrogen-oxygen bonds in the first channel region 91 may also be directly controlled to be less than 5%. Among them, the less the proportion of hydrogen-oxygen bonds in the first channel region 91 in the first active layer 111 is controlled, which is equivalent to controlling the less impurities in the first channel region 91, and the more conducive to improving the proportion of metal-oxygen bonds in the first channel region 91, thereby facilitating the improvement of the electrical stability of the first active layer 111, reducing the electrical characteristic drift of the thin film transistor 10 including the first active layer 111, and improving the conductivity and reliability of the thin film transistor 10 including the first active layer 111.
[0066] Exemplarily, for the hydrogen-oxygen bond (OH) included in the first channel region 91 in the first active layer 111, the bond energy value of the hydrogen-oxygen bond can be set to a range of 527eV-537eV, that is, 532eV±5eV. If the bond energy value of the hydrogen-oxygen bond is too small, the stability of the relevant first channel region 91 will be reduced, and if the bond energy value is too large, the energy of the relevant first channel region 91 will be too low; therefore, the present application sets the bond energy value of the hydrogen-oxygen bond in the first channel region 91 to 532eV±5eV, which is conducive to ensuring the stability and reliability of the thin film transistor 10 including the first active layer 111.
[0067] Please continue to refer to Figure 1-Figure 3 In an exemplary embodiment, the first channel region 91 includes a crystalline oxide material layer.
[0068] For example, for the first channel region 91 of the first active layer 111 included in the thin film transistor 10 provided in the present application, the first channel region 91 finally prepared can be a crystalline oxide material layer. Compared with amorphous oxide materials, crystalline oxide materials have a better effect of reducing defects in the film. Therefore, the thin film transistor 10 composed of the active layer 11 including the crystalline oxide material layer has better reliability.
[0069] Please refer to Figure 1 and Figure 4-Figure 6In an exemplary embodiment, the active layer 11 of the thin film transistor 10 further includes a second active layer 112; the second active layer 112 is disposed on a side of the first active layer 111 facing the source-drain electrode layer 13, and / or the second active layer 112 is disposed on a side of the first active layer 111 facing away from the source-drain electrode layer 13;
[0070] The second active layer 112 includes a second channel region 92 , which is disposed on a side of the first channel region 91 facing the source-drain layer 13 , and / or on a side of the first channel region 91 facing away from the source-drain layer 13 .
[0071] For example, for the active layer 11 of the thin film transistor 10 provided in the present application, in addition to the above-mentioned active layer 11 including the first active layer 111, several optional configurations are provided, in which the active layer 11 includes the first active layer 111 and the second active layer 112 stacked in a direction perpendicular to the plane where the substrate 21 is located; for example Figure 4 As shown, the second active layer 112 may be selectively disposed on a surface of the first active layer 111 facing the substrate 21; for example Figure 5 As shown, the second active layer 112 may be selectively disposed on a surface of the first active layer 111 facing the source-drain electrode layer 13; for example Figure 6 As shown, the first sub-second active layer 1121 can be selectively disposed on a surface of the first active layer 111 facing the base substrate 21 , and the second sub-second active layer 1122 can be disposed on a surface of the first active layer 111 facing the source-drain layer 13 .
[0072] Among them, along the direction perpendicular to the plane where the base substrate 21 is located, the thickness of the first active layer 111 or any second active layer 112 can be controlled to be 30Å-200Å; the symbol Å is transliterated as "angstrom", which can be called angstrom, and the foreign name is Ångstrom or ANG. For example, the thickness of the first active layer 111 or any second active layer 112 can be controlled to be 30Å, or 60Å, or 100Å, or 150Å, or 200Å, etc.; the thickness of the first active layer 111 or any second active layer 112 can be controlled to be as small as possible to reduce the thickness of the entire active layer 11, which is conducive to reducing the thickness of the entire array substrate 100, so as to ensure the thin design requirements of the array substrate 100, so as to be conducive to the thickness of the display device including the array substrate 100 to be as small as possible, meet the current user's demand for thin display devices, and enhance the user's experience of using related display devices.
[0073] In an exemplary embodiment, the preparation material of the second channel region 92 includes at least one of indium gallium zinc oxide and gallium-doped zinc oxide; the carrier mobility of the first channel region 91 is greater than the carrier mobility of the second channel region 92 .
[0074] Exemplarily, in the case where the active layer 11 includes a first active layer 111 and a second active layer 112, for the preparation of the second channel region 92 in the second active layer 112, the present application provides an optional preparation material of indium gallium zinc oxide (IGZO) or gallium doped zinc oxide (GZO); the proportion of indium element in IGZO is relatively small, and GZO does not include indium element; therefore, IGZO or GZO is used to prepare the second channel region 92 of the second active layer 112, and a material with a relatively high proportion of indium element is used to prepare the first channel region 91 of the first active layer 111. Combined with the fact that the carrier mobility of the first channel region 91 is greater than the carrier mobility of the second channel region 92, it is more conducive to improving the carrier mobility of the first active layer 111, and further conducive to improving the conductivity and reliability of the thin film transistor 10 including the first active layer 111, so that the thin film transistor 10 can meet the driving requirements of the high-precision panel to improve the resolution of the relevant display panel.
[0075] In addition, in addition to using IGZO or GZO to prepare the second channel region 92 of the second active layer 112, other oxides with lower indium content may also be used to prepare the second channel region 92 of the second active layer 112, which is not specifically limited in the present application.
[0076] The second active layer 112 may also serve as a protective layer to improve the service life and use effect of the thin film transistor 10 including the first active layer 111 .
[0077] Please refer to Figure 1-Figure 6 Based on the same inventive concept, the present application also provides an array substrate 100, which includes a plurality of thin film transistors 10. The thin film transistor 10 can be the thin film transistor 10 in any of the aforementioned embodiments, which will not be described in detail herein.
[0078] Please combine Figure 1-Figure 6 Reference Figure 7 Based on the same inventive concept, the present application also provides a display panel 200, which includes the aforementioned array substrate 100; wherein the array substrate 100 includes a plurality of thin film transistors 10, and the thin film transistors 10 can be the thin film transistors 10 in any of the aforementioned embodiments. The display panel 200 provided by the present application has high resolution and high contrast, and the power consumption is greatly reduced, so that the overall performance of the display panel 200 is greatly enhanced.
[0079] Based on the same inventive concept, the present application also provides a display device (not shown) including the display panel 200, and the display device may further include a touch module and other structures; the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, etc., and the embodiments disclosed in the present application are not limited to this. The display device has high resolution and high contrast, and greatly reduces power consumption while improving the display effect.
[0080] Please combine Figure 1-Figure 6 Reference Figure 8 Based on the same inventive concept, the present application also provides a method for preparing a thin film transistor 10, comprising steps 101 to 104, wherein:
[0081] Step 101, providing a substrate 21;
[0082] Step 102, forming a first active film on one side of the base substrate 21;
[0083] Step 103, annealing the first active film at a high temperature and patterning it to form a first active layer 111 of the thin film transistor 10; the first active layer 111 includes a first channel region 91, and the indium element accounts for more than 50% of the material prepared in the first channel region 91;
[0084] Step 104 , preparing an insulating layer on the side of the first active layer 111 away from the substrate 21 , preparing a second metal layer on the side of the insulating layer away from the first active layer 111 , and patterning the second metal layer to form a source and drain layer 13 of the thin film transistor 10 .
[0085] The temperature of the high temperature annealing can be set to be greater than 350° C. (degrees Celsius) to ensure the effect and rate of forming the first active layer.
[0086] The method for preparing the thin film transistor 10 also provided in the present application may further include a method for preparing the gate 12 in the thin film transistor 10: forming a first metal layer on one side of the base substrate 21, and patterning the first metal layer to form the gate 12 of the thin film transistor.
[0087] The present application does not specifically limit whether the gate 12 is prepared before or after the active layer 11 ; the preparation of an insulating layer may be further included between the preparation of the gate 12 and the active layer 11 .
[0088] The method for preparing the thin film transistor 10 also provided in the present application may further include a method for preparing the second active layer 112 further included in the active layer 11 of the thin film transistor 10: forming a second active film on one side of the base substrate 21; annealing the second active film at a high temperature and patterning it to form the second active layer 112 of the thin film transistor; the second active layer includes a second channel region 92.
[0089] The present application does not specifically limit the preparation order of the first active layer 111 and the second active layer 112. For example, the second active layer 112 may be prepared before the first active layer 111, or the first active layer 111 may be prepared before the second active layer 112. When two layers of the second active layer 112 are required, one layer of the second active layer 112 may be prepared first, then one layer of the first active layer 111, and then one layer of the second active layer 112. Optionally, the high-temperature annealing and patterning of the first active film and the second active film may be performed separately or combined based on demand, and the present application does not specifically limit this.
[0090] For example, the application provides Figure 2 The thin film transistor shown in the figure may be manufactured in a method of the thin film transistor corresponding to step 201 to step 211, wherein:
[0091] Step 201, providing a substrate;
[0092] Step 202: Prepare a buffer layer (such as Figure 2 Buffer layer 22);
[0093] Step 203, forming an oxide active layer (first active film) by PVD (Physical Vapor Deposition) on a side of the buffer layer away from the substrate;
[0094] Step 204, annealing the first active film at high temperature;
[0095] Step 205, etching the first active film after high temperature annealing with yellow light to pattern the first active film to form a first active layer of at least one thin film transistor;
[0096] Step 206, preparing a first insulating layer on a side of the first active layer away from the substrate;
[0097] Step 207, preparing a first metal layer on a side of the first insulating layer away from the substrate;
[0098] Step 208, patterning the first metal layer to form a gate of the thin film transistor;
[0099] Step 209, preparing a second insulating layer on a side of the gate away from the substrate;
[0100] Step 210, forming a second metal layer on a side of the second insulating layer away from the substrate;
[0101] Step 211 , patterning the second metal layer to form a source and drain electrode layer of the thin film transistor, that is, forming a source and a drain electrode of the thin film transistor.
[0102] For example, the application provides Figure 3 The thin film transistor shown in the figure may be manufactured in a method of the thin film transistor corresponding to step 301 to step 311, wherein:
[0103] Step 301, providing a substrate;
[0104] Step 302, preparing a first metal layer on one side of the substrate;
[0105] Step 303, patterning the first metal layer to form a gate of the thin film transistor;
[0106] Step 304, preparing a first insulating layer on a side of the gate away from the substrate;
[0107] Step 305, forming a PVD film-forming oxide active layer (first active film) on a side of the first insulating layer away from the substrate;
[0108] Step 306, annealing the first active film at high temperature;
[0109] Step 307, etching the first active film after high temperature annealing with yellow light to pattern the first active film to form a first active layer of at least one thin film transistor;
[0110] Step 308, preparing a second insulating layer on a side of the first active layer away from the substrate;
[0111] Step 309, preparing a third insulating layer on the side of the second insulating layer away from the substrate; wherein step 309 can be used as a planarization layer, or can be omitted based on demand;
[0112] Step 310, preparing a second metal layer on a side of the third insulating layer away from the substrate;
[0113] Step 311 , patterning the second metal layer to form a source and drain electrode layer of the thin film transistor, that is, forming a source and a drain electrode of the thin film transistor.
[0114] For example, the application provides Figure 4 The thin film transistor shown in the figure may be manufactured in a method of manufacturing the thin film transistor corresponding to step 401 to step 411, wherein:
[0115] Step 401, providing a substrate;
[0116] Step 402, preparing a buffer layer on one side of the substrate;
[0117] Step 403, forming an IGZO film (second active film) by PVD on the side of the buffer layer away from the substrate, and then forming an oxide active layer (first active film) by PVD; that is, the thin film transistor can be a two-layer channel, the lower layer is a low-mobility oxide material, and IGZO can be selected;
[0118] Step 404, annealing the active film (including the first active film and the second active film) at high temperature;
[0119] Step 405, etching the active film after high temperature annealing with yellow light to pattern the active film to form a first active layer and a second active layer of at least one thin film transistor;
[0120] Step 406, preparing a first insulating layer on a side of the first active layer away from the substrate;
[0121] Step 407, forming a first metal layer on a side of the first insulating layer away from the substrate;
[0122] Step 408, patterning the first metal layer to form a gate of the thin film transistor;
[0123] Step 409, preparing a second insulating layer on a side of the gate away from the substrate;
[0124] Step 410, forming a second metal layer on a side of the second insulating layer away from the substrate;
[0125] Step 411 , patterning the second metal layer to form a source and drain electrode layer of the thin film transistor, that is, forming a source and a drain electrode of the thin film transistor.
[0126] For example, the application provides Figure 5 The thin film transistor shown in the figure may be manufactured in a method of manufacturing the thin film transistor corresponding to step 501 to step 511, wherein:
[0127] Step 501, providing a substrate;
[0128] Step 502, preparing a buffer layer on one side of the substrate;
[0129] Step 503, PVD an oxide active layer (first active film) is formed on the side of the buffer layer away from the substrate, and then PVD forms an IGZO film (second active film); that is, the thin film transistor can be a two-layer channel, the upper layer is a low-mobility oxide material, and IGZO can be selected;
[0130] Step 504, annealing the IGZO (second active film) and the first active film at high temperature;
[0131] Step 505, etching the active film (including the first active film and the second active film) after high temperature annealing with yellow light to pattern the active film to form a first active layer and a second active layer of at least one thin film transistor;
[0132] Step 506, preparing a first insulating layer on a side of the second active layer away from the substrate;
[0133] Step 507, forming a first metal layer on a side of the first insulating layer away from the substrate;
[0134] Step 508, patterning the first metal layer to form a gate of the thin film transistor;
[0135] Step 509, preparing a second insulating layer on a side of the gate away from the substrate;
[0136] Step 510, forming a second metal layer on a side of the second insulating layer away from the substrate;
[0137] Step 511 , patterning the second metal layer to form a source and drain electrode layer of the thin film transistor, that is, forming a source and a drain electrode of the thin film transistor.
[0138] The above steps 503 to 505 may be implemented by executing steps 531 to 535, wherein:
[0139] Step 531, forming an oxide active layer (first active film) by PVD on a side of the buffer layer away from the substrate;
[0140] Step 532, annealing the first active film at high temperature;
[0141] Step 533, etching the first active film after high temperature annealing with yellow light to pattern the first active film to form a first active layer of at least one thin film transistor;
[0142] Step 534, forming an IGZO film (a second active film) by PVD on a side of the first active layer away from the substrate;
[0143] Step 535 , high temperature annealing and yellow photoetching of the second active film to pattern the second active film to form a second active layer of at least one thin film transistor.
[0144] The preparation of the first active layer and the second active layer is realized through steps 531 to 535, which can avoid the problem of mismatch between the annealing temperature of the crystalline oxide and the IGZO, avoid increasing the defects of the IGZO, and avoid affecting the film quality of the crystalline material.
[0145] For example, the application provides Figure 6 The thin film transistor shown in the figure may be manufactured in a method of the thin film transistor corresponding to step 601 to step 611, wherein:
[0146] Step 601, providing a substrate;
[0147] Step 602, preparing a buffer layer on one side of the substrate;
[0148] Step 603, forming a first IGZO film (first sub-second active film) by PVD on the side of the buffer layer away from the substrate, and then forming an oxide active layer (first active film) by PVD, and then forming a second IGZO film (second sub-second active film) by PVD; that is, the thin film transistor can be a three-layer channel, and the upper and lower layers are low-mobility oxide materials, and IGZO can be selected;
[0149] Step 604, annealing the second IGZO, the active film and the first IGZO (the second sub-second active film, the first active film and the first sub-second active film) at a high temperature;
[0150] Step 605, etching and patterning the active films (the second sub-second active film, the first active film and the first sub-second active film) by yellow light to form a second sub-second active layer, a first active layer and a first sub-second active layer;
[0151] Step 606, forming a first insulating layer on a side of the second sub-second active layer away from the substrate;
[0152] Step 607, forming a first metal layer on a side of the first insulating layer away from the substrate;
[0153] Step 608, patterning the first metal layer to form a gate of the thin film transistor;
[0154] Step 609, preparing a second insulating layer on a side of the gate away from the substrate;
[0155] Step 610, forming a second metal layer on a side of the second insulating layer away from the substrate;
[0156] Step 611 , patterning the second metal layer to form a source and drain electrode layer of the thin film transistor, that is, forming a source and a drain electrode of the thin film transistor.
[0157] The above steps 603 to 605 may be implemented by executing steps 631 to 636, wherein:
[0158] Step 631, forming a first IGZO film (first sub-second active film) by PVD on a side of the buffer layer away from the substrate;
[0159] Step 632, forming an oxide active layer (first active film) by PVD on a side of the first IGZO away from the substrate;
[0160] Step 633, annealing the first active film and the first sub-second active film at a high temperature;
[0161] Step 634, etching the first active film and the first sub-second active film after high temperature annealing with yellow light to pattern the first active film and the first sub-second active film to form a first active layer and a first sub-second active layer of at least one thin film transistor;
[0162] Step 635, forming a second IGZO film (a second sub-second active film) by PVD on a side of the first active layer away from the substrate;
[0163] Step 636 , high temperature annealing and yellow photolithography to pattern the second sub-second active film to form a second sub-second active layer of at least one thin film transistor.
[0164] The preparation of the first active layer and the second active layer (the first sub-second active layer and the second sub-second active layer) is achieved through steps 631 to 636, which can avoid the problem of mismatch in annealing temperature between the crystalline oxide and the second sub-IGZO (upper IGZO), avoid increasing IGZO defects, and avoid affecting the film quality of the crystalline material.
[0165] In the process flow of preparing thin film transistors in the present application, a high temperature annealing crystallization process is first performed, and then a patterning process is performed. The related effect is that the oxide that crystallizes first has better stability and is less susceptible to subsequent yellow light organic contamination.
[0166] In the process flow of preparing thin film transistors, the present application first performs high-temperature annealing and crystallization, and then forms an upper IGZO film. The related effect is that the suitable annealing temperatures for the crystalline oxide and the low-mobility IGZO material are different, which can avoid the problem of increased defects due to differences in process windows.
[0167] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.
[0168] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0169] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A thin film transistor, characterized in that: It comprises a first active layer, a gate and a source-drain electrode layer which are stacked in sequence, wherein the gate is insulated from the first active layer and the source-drain electrode layer respectively; The first active layer includes a first channel region, and the indium element accounts for more than 50% of the material used to prepare the first channel region.
2. The thin film transistor according to claim 1, characterized in that: The preparation material of the first channel region includes at least any one of indium oxide, indium gallium oxide, indium zinc oxide, and indium tin oxide; Optionally, the indium element accounts for more than 70% of the material used to prepare the first channel region.
3. The thin film transistor according to claim 1 or 2, characterized in that: The proportion of metal-oxygen bonds in the first channel region is greater than 50%; and / or, The metal-oxygen bond energy of the first channel region ranges from 524.5 eV to 534.5 eV; Optionally, the proportion of metal-oxygen bonds in the first channel region is greater than 70%.
4. The thin film transistor according to claim 1 or 2, characterized in that: The proportion of oxygen vacancies in the first channel region is less than 30%; and / or, The bond energy of the oxygen vacancy in the first channel region ranges from 526 eV to 536 eV; Optionally, the proportion of oxygen vacancies in the first channel region is less than 20%.
5. The thin film transistor according to claim 1 or 2, characterized in that: The proportion of hydrogen-oxygen bonds in the first channel region is less than 20%; and / or, The bond energy of the hydrogen-oxygen bond in the first channel region ranges from 527 eV to 537 eV; Optionally, the proportion of hydrogen-oxygen bonds in the first channel region is less than 5%.
6. The thin film transistor according to claim 1, characterized in that: The first channel region includes a layer of crystalline oxide material.
7. The thin film transistor according to claim 1, characterized in that: Also comprising a second active layer; The second active layer is disposed on a surface of the first active layer facing the source-drain electrode layer, and / or the second active layer is disposed on a surface of the first active layer facing away from the source-drain electrode layer; Optionally, the second active layer includes a second channel region, the second channel region is arranged on a side of the first channel region facing the source-drain layer, and / or the second channel region is arranged on a side of the first channel region facing away from the source-drain layer; Optionally, the preparation material of the second channel region includes at least any one of indium gallium zinc oxide and gallium-doped zinc oxide; Optionally, the carrier mobility of the first channel region is greater than the carrier mobility of the second channel region; Optionally, the thickness of the second active layer is less than or equal to 200Å.
8. An array substrate, characterized in that: Comprising a thin film transistor as described in any one of claims 1 to 7.
9. A method for preparing a thin film transistor, characterized in that: include: providing a substrate base plate; forming a first active film on one side of the base substrate; Annealing the first active film at a high temperature and patterning it to form a first active layer of the thin film transistor; the first active layer includes a first channel region, and the indium element accounts for more than 50% of the material prepared in the first channel region; An insulating layer is prepared on a side of the first active layer away from the substrate, and a second metal layer is prepared on a side of the insulating layer away from the first active layer. The second metal layer is patterned to form a source and drain layer of the thin film transistor.
10. The method for preparing a thin film transistor according to claim 9, characterized in that: After providing the base substrate, the method further includes: forming a first metal layer on one side of the base substrate, and patterning the first metal layer to form a gate of the thin film transistor; After providing the base substrate, the method further includes: forming a second active film on one side of the base substrate; annealing the second active film at a high temperature and patterning the second active film to form a second active layer of the thin film transistor; the second active layer includes a second channel region.