Super-junction MOSFET device and preparation method thereof
By forming a doped region in communication with the body region on the upper surface of the isolation region of the superjunction MOSFET device, and changing the gate drain parasitic capacitance to the gate source parasitic capacitance, the problem of poor shutdown oscillation improvement in the prior art is solved, and the switching oscillation and breakdown resistance of the device are improved.
Patent Information
- Application Number
- CN202311344805.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-17
- Publication Date
- 2025-04-25
AI Technical Summary
After the introduction of the polysilicon grid structure, the existing super junction MOSFET devices have poor effect on shutting down oscillation improvement.
By setting an isolation region between two first conductivity type columns adjacent to the Y direction and forming a second conductivity type doping region in communication with the body region on the upper surface of the isolation region, the gate drain parasitic capacitance Cgd generated by the isolation region setting is converted into a gate source parasitic capacitance Cgs.
The gate-source parasitic capacitance Cgs of the device is improved, the ratio of the gate-drain parasitic capacitance Cgd of the device is reduced to the gate-source parasitic capacitance Cgs of the device is reduced, the gate peak voltage value of the device is improved, the switching oscillation and breakdown resistance is improved, and the overall performance is improved.
Smart Images
Figure CN119894058A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a super junction MOSFET device and a preparation method thereof. Background Art
[0002] As the breakdown voltage increases, the resistivity and thickness of the epitaxial layer in the vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) need to increase, resulting in a large on-resistance of the device. The relationship between on-resistance and breakdown voltage is: R∝BV 2.5 , which is commonly referred to as the 'silicon limit'. In order to reduce the on-resistance of the device or break through the silicon limit, super junction technology (charge compensation technology: Chen Xingbi, Semiconductor Power Devices, Publication No.: CN1056018A, 1991) is often used. The relationship between the on-resistance and the breakdown voltage in the super junction MOSFET device is: Where, the breakdown voltage BV = E C t pillar .
[0003] The introduction of the super junction structure causes severe oscillation of the device when it is turned off. At present, in order to improve the turn-off oscillation of the device, the distribution of the polysilicon gate of the device is usually adjusted, such as Figure 1 , Figure 2 and Figure 3 As shown in the figure, they are the structural schematic diagram of the super junction MOSFET device, Figure 1 Schematic diagram of the cross-sectional structure of the AA surface of the superjunction MOSFET device and Figure 1 A schematic diagram of the cross-sectional structure of the super junction MOSFET device on the BB plane includes a semiconductor structure 01, a substrate 011, a buffer zone 012, a first conductive type column 013, a second conductive type column 014, a body region 015, a source region 0151, an isolation region 016, a gate structure 02, a gate dielectric layer 021 and a gate conductive layer 022. The second conductive type column is provided along the Y direction as a first conductive type isolation region for ion implantation to isolate the second conductive type column, and a gate structure is formed above the isolation region to obtain a polysilicon mesh (Mesh Poly) structure, thereby increasing the gate-source parasitic capacitance C in the device. gs purpose, but the gate-source parasitic capacitance C gs As the device's Miller capacitance C increases, gd It also increases synchronously, resulting in poor improvement of the turn-off oscillation.
[0004] Therefore, there is an urgent need to find a super junction MOSFET device that can improve the turn-off oscillation effect of the device. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a super junction MOSFET device and a preparation method thereof, which are used to solve the problem that the introduction of a polysilicon gate structure into the super junction MOSFET device in the prior art has a poor improvement effect on the turn-off oscillation of the device.
[0006] To achieve the above objectives and other related objectives, the present invention provides a super junction MOSFET device, comprising:
[0007] A semiconductor structure, comprising a first conductive type substrate, a first conductive type buffer zone, a first conductive type column, a second conductive type column, a second conductive type body region, a first conductive type source region and an isolation region, wherein the buffer zone is stacked on the upper surface of the substrate, the first conductive type column and the second conductive type column are located on the upper surface of the buffer zone and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns are arranged at intervals along the Y direction, the body region is located on the upper surface of the second conductive type column, the sidewall of the body region in the X direction protrudes from the sidewall of the second conductive type column, the source region is located on the upper surface layer of the body region, the sidewall of the source region is spaced from the sidewall of the body region by a preset distance, the upper surface of the first conductive type column is flush with the upper surface of the body region, the isolation region is located between two adjacent second conductive type columns along the Y direction, and the X direction is perpendicular to the Y direction;
[0008] A second conductive type doped region, located on an upper surface layer of the isolation region, the doped region being connected to the body region;
[0009] A gate structure, located on the upper surface of the first conductive type column and the doped region;
[0010] A source, a drain and a gate, wherein the source is electrically connected to the source region, the drain is electrically connected to the substrate, and the gate is electrically connected to the gate structure.
[0011] Optionally, the doping concentration of the buffer zone is lower than the doping concentration of the first conductive type column, and the doping concentration of the substrate is higher than the doping concentration of the buffer zone.
[0012] Optionally, the conductivity type of the isolation region is the same as the conductivity type of the first conductivity type column.
[0013] Optionally, a bottom surface of the isolation region is flush with a bottom surface of the first conductive type column, and an upper surface of the isolation region is flush with an upper surface of the first conductive type column.
[0014] Optionally, a size of the isolation region in the Y direction is the same as a distance between two adjacent second conductive type pillars in the Y direction.
[0015] Optionally, on the same straight line parallel to the X direction, at least one second conductive type column is spaced between two adjacent isolation regions.
[0016] Optionally, the doped region exceeds the gate structure by no more than 3 μm in the Y direction.
[0017] Optionally, the overlapping size of the projections of two adjacent doping regions in the Y direction is not greater than the size of the gate structure in the X direction.
[0018] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer and the gate conductive layer are sequentially stacked on an upper surface of the first conductive type column, and the gate is electrically connected to the gate conductive layer.
[0019] The present invention also provides a method for manufacturing a super junction MOSFET device, comprising the following steps:
[0020] A semiconductor structure is provided, the semiconductor structure comprising a first conductive type substrate, a first conductive type buffer zone, a first conductive type column, a second conductive type column, a second conductive type body region, a first conductive type source region and an isolation region, wherein the buffer zone is stacked on the upper surface of the substrate, the first conductive type column and the second conductive type column are located on the upper surface of the buffer zone and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns are arranged at intervals along the Y direction, the body region is located on the upper surface of the second conductive type column, the sidewall of the body region along the X direction protrudes from the sidewall of the second conductive type column, the source region is located on the upper surface layer of the body region, the sidewall of the source region is spaced from the sidewall of the body region by a preset distance, the upper surface of the first conductive type column is flush with the upper surface of the body region, the isolation region is located between two adjacent second conductive type columns along the Y direction, and the X direction and the Y direction are perpendicular to each other;
[0021] forming a second conductive type doped region on the upper surface layer of the isolation region, wherein the doped region is connected to the body region;
[0022] forming a gate structure on the upper surfaces of the first conductive type column and the doped region;
[0023] A source electrode electrically connected to the source region is formed, a gate electrode electrically connected to the gate structure is formed, and a drain electrode electrically connected to the substrate is formed.
[0024] As described above, the super junction MOSFET device and the method for manufacturing the same of the present invention are provided by providing the isolation region in the region between two adjacent first conductive type columns in the Y direction to isolate a plurality of first conductive type columns in the Y direction, and providing the doped region connected to the body region and having the same conductive type on the upper surface of the isolation region, so that the gate-drain parasitic capacitance C generated by the provision of the isolation region gd Transformed into gate-source parasitic capacitance C gs , which in turn increases the gate-source parasitic capacitance C of the device gs , while reducing the gate-drain parasitic capacitance C of the device gd The gate-source parasitic capacitance C gs The ratio of the gate voltage of the device is reduced, the switching oscillation of the device is improved, the anti-breakdown capability of the device is enhanced, and the performance of the device is improved; due to the setting of the doping region, and the connection between the doping region and the body region, the effective doping concentration of the body region is increased, and the on-resistance of the body region is reduced, which effectively inhibits the opening of the parasitic transistor in the device and improves the UIS (unclamped inductive switching) capability of the device; in addition, during the operation of the device, due to the depletion of carrier diffusion in the doping region, the gate-drain parasitic capacitance C of the device is increased. gd Further reducing the gate-source parasitic capacitance C gs Further increase and then further improve the turn-off oscillation of the device, enhance the performance of the device, and have high industrial application value. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 Shown is a schematic diagram of the structure of a super junction MOSFET device.
[0026] Figure 2 Display as Figure 1 Schematic diagram of the cross-sectional structure of the AA plane of the super junction MOSFET device.
[0027] Figure 3 Display as Figure 1 Schematic diagram of the cross-sectional structure of the BB surface of the super junction MOSFET device.
[0028] Figure 4 Shown is a schematic structural diagram of a super junction MOSFET device of the present invention.
[0029] Figure 5 Display as Figure 4 Schematic diagram of the cross-sectional structure of the CC plane of the super junction MOSFET device.
[0030] Figure 6 Display as Figure 4Schematic diagram of the cross-sectional structure of the DD surface of the super junction MOSFET device.
[0031] Figure 7 Display as Figure 4 Schematic diagram of the cross-sectional structure of the EE surface of the super junction MOSFET device.
[0032] Figure 8 Display as Figure 4 Schematic diagram of the cross-sectional structure of the FF surface of the super junction MOSFET device.
[0033] Fig. 9 It is a schematic diagram of the top surface structure after forming the doped region in the method for preparing the super junction MOSFET device of the present invention.
[0034] Fig.10 Display as Fig. 9 Schematic diagram of the cross-sectional structure of the CC surface of the middle structure.
[0035] Fig.11 Display as Fig. 9 Schematic diagram of the cross-sectional structure of the DD plane of the middle structure.
[0036] Fig.12 Display as Fig. 9 Schematic diagram of the cross-sectional structure of the EE surface of the medium structure.
[0037] Fig.13 Display as Fig. 9 Schematic diagram of the cross-sectional structure of the FF surface of the middle structure.
[0038] Description of Figure Numbers
[0039] 01 Semiconductor Structure
[0040] 011 Substrate
[0041] 012 Buffer
[0042] 013 First conductivity type column
[0043] 014 Second conductivity type column
[0044] 015 Body Area
[0045] 0151 Source Area
[0046] 016 Quarantine
[0047] 02 Gate structure
[0048] 021 Gate dielectric layer
[0049] 022 Gate conductive layer
[0050] 1 Semiconductor structure
[0051] 11 Substrate
[0052] 12 Buffer
[0053] 13 First conductivity type column
[0054] 14 Second conductivity type column
[0055] 15 Body Area
[0056] 151 Source Area
[0057] 16 Quarantine
[0058] 2 Gate structure
[0059] 21. Gate dielectric layer
[0060] 22. Gate conductive layer
[0061] 3 Doping region DETAILED DESCRIPTION
[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0063] See also Figures 4 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0064] Embodiment 1
[0065] This embodiment provides a super junction MOSFET device, such as Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown in the figure, they are respectively a schematic diagram of the structure of the super junction MOSFET, Figure 4 Schematic diagram of the cross-sectional structure of the CC surface of the super junction MOSFET device. Figure 4 Schematic diagram of the cross-sectional structure of the DD surface of the super junction MOSFET device. Figure 4 Schematic diagram of the cross-sectional structure of the EE surface of the superjunction MOSFET device Figure 4The cross-sectional structure diagram of the FF surface of the super MOSFET device in FIG. 1 includes a semiconductor structure 1, a gate structure 2, a second conductive type doped region 3, a source (not shown), a drain (not shown) and a gate (not shown), wherein the semiconductor structure 1 includes a first conductive type substrate 11, a first conductive type buffer region 12, a first conductive type column 13, a second conductive type column 14, a second conductive type body region 15, a first conductive type source region 151 and an isolation region 16, the buffer region 12 is stacked on the upper surface of the substrate 11, the first conductive type column 13 and the second conductive type column 14 are located on the upper surface of the buffer region 12 and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns 14 are arranged at intervals along the Y direction, and the body region 15 is located on the upper surface of the second conductive type column 14. surface, the sidewall of the body region 15 in the X direction protrudes from the sidewall of the second conductive type column 14, the source region 151 is located on the upper surface layer of the body region 15, the sidewall of the source 151 region is spaced a preset distance from the sidewall of the body region 15, the upper surface of the first conductive type column 13 is flush with the upper surface of the body region 15, the isolation region 16 is located between two adjacent second conductive type columns 14 along the Y direction, and the X direction is perpendicular to the Y direction; the doped region 3 is located on the upper surface layer of the isolation region 16, and the doped region 3 is connected to the body region 15; the gate structure 2 is located on the upper surface of the first conductive type column 13 and the doped region 3; the source is electrically connected to the source region 151, the drain is electrically connected to the substrate 11, and the gate is electrically connected to the gate structure 2.
[0066] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.
[0067] Specifically, the substrate 11 is made of silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.
[0068] Specifically, the substrate 11 forms an ohmic contact with the drain. Under the condition of ensuring device performance and forming an ohmic contact between the substrate 11 and the drain, the doping concentration of the substrate 11 can be selected according to actual conditions and is not limited here.
[0069] As an example, the doping concentration of the buffer region 12 is lower than the doping concentration of the first conductive type column 13 , and the doping concentration of the substrate 11 is higher than the doping concentration of the buffer region 12 .
[0070] Specifically, under the condition that the device performance is ensured and the doping concentration of the buffer zone 12 is lower than the doping concentration of the substrate 11 , the doping concentration of the buffer zone 12 can be selected according to actual conditions and is not limited here.
[0071] Specifically, the material of the buffer zone 12 includes polysilicon or other suitable semiconductor materials.
[0072] Specifically, while ensuring device performance, the size of the first conductive type column 13 along the X direction can be selected according to actual conditions and is not limited here; the doping concentration of the first conductive type column 13 can be selected according to actual conditions and is not limited here.
[0073] Specifically, while ensuring device performance, the size of the second conductive type column 14 along the X direction can be selected according to actual conditions and is no longer restricted here; the size of the second conductive type column 14 along the Y direction can be selected according to actual conditions and is no longer restricted here; the doping concentration of the second conductive type column 14 can be selected according to actual conditions and is no longer restricted here.
[0074] Specifically, under the condition of ensuring device performance, in the X direction, the distance between the sidewall of the body region 15 and the sidewall of the second conductive type column 14 can be selected according to actual conditions, and is not limited here. The thickness here refers to the distance between the upper surface of the body region 15 and the lower surface of the body region 15.
[0075] Specifically, the upper surface layer of the body region 15 is also provided with a second conductive type contact region (not shown) adjacent to the source region 151, the side walls of the contact region are adjacent to the side walls of the source region 151, the side walls of the source region 151 are away from the side walls of the contact region and are spaced a preset distance from the side walls of the body region 15, and the source is electrically connected to the contact region, and the contact type between the source region 151 and the contact region and the source is ohmic contact.
[0076] Specifically, under the condition of ensuring the device performance and the ohmic contact between the source region 151 and the source electrode, the doping concentration and thickness of the source region 151 can be selected according to the actual situation, and are not limited here; the distance between the side wall of the source region 151 away from the contact region and the side wall of the body region 15 can be selected according to the actual situation, and are not limited here. The thickness here refers to the distance between the bottom surface of the source region 151 and the upper surface of the source region 151.
[0077] Specifically, under the condition of ensuring the device performance and the ohmic contact between the contact region and the source electrode, the doping concentration and thickness of the contact region can be selected according to actual conditions, and are not limited here.
[0078] As an example, the conductivity type of the isolation region 16 is the same as the conductivity type of the first conductivity type pillar 13 .
[0079] Specifically, a plurality of isolation regions 16 for isolating the second conductive type columns 14 are provided in the Y direction to isolate a plurality of second conductive type columns 14 of a preset length, so as to optimize the gate-source parasitic capacitance C in the device. gs The gate-drain parasitic capacitance C of the device gd The ratio between them.
[0080] As an example, the bottom surface of the isolation region 16 is flush with the bottom surface of the first conductive type column 13 , and the top surface of the isolation region 16 is flush with the top surface of the first conductive type column 13 .
[0081] As an example, on the same straight line parallel to the X direction, there is at least one second conductive type column 14 between two adjacent isolation regions 16 .
[0082] Specifically, on the same straight line parallel to the X direction, the second conductive type column 14 is spaced between two adjacent isolation regions 16 to facilitate the connection between the doped region 3 and the body region 15, thereby reducing the impact of the isolation region 16 on device performance.
[0083] As an example, the size of the isolation region 16 in the Y direction is the same as the distance between two adjacent second conductive type pillars 14 in the Y direction.
[0084] Specifically, the isolation region 16 is a region where the second conductive type doping is not performed between two adjacent second conductive type columns 14 in the Y direction during the process of forming the second conductive type column 14 and the body region 15, and the edge of the isolation region 16 in the X direction is spaced a preset distance from the two adjacent body regions 15 of the isolation region 16 in the X direction, that is, the edge of the isolation region 16 in the X direction does not extend into the two adjacent body regions 15 in the X direction.
[0085] Specifically, the size of the isolation region 16 in the X direction is not less than the size of the body region 15 in the X direction, and the edge of the isolation region 16 in the X direction does not extend into the two adjacent body regions 15 in the X direction.
[0086] Specifically, under the condition that the device performance is guaranteed and the edge of the isolation region 16 in the X direction does not extend into the two adjacent body regions 15 in the X direction, the size of the isolation region 16 in the X direction can be selected according to actual conditions, and is not limited here. In this embodiment, the size of the isolation region 16 in the X direction is the same as the size of the body region 15 in the X direction.
[0087] Specifically, under the condition of ensuring device performance, the doping concentration of the isolation region 16 may also be higher or lower than the doping concentration of the first conductive type column 13. In this embodiment, the doping concentration of the isolation region 16 is the same as the doping concentration of the first conductive type column 13.
[0088] Specifically, under the condition of ensuring the device performance and the connection between the doping region 3 and the body region 15, the sidewalls of the doping region 3 in the X direction and the Y direction can be extended to the body region 15 around the isolation region 16 at the same time, or partially extended to the body region 15 around the isolation region 16. The shape, thickness and doping concentration of the doping region 3 can be selected according to actual conditions and are not limited here. The thickness here refers to the distance between the bottom surface and the upper surface of the doping region 3. In this embodiment, the sidewalls of the doping region 3 in the X direction and the Y direction extend to the body region 15 around the isolation region 16 at the same time.
[0089] As an example, the doping region 3 exceeds the gate structure 2 by no more than 3 μm in the Y direction.
[0090] Specifically, the doping region 3 exceeds the gate structure 2 so that the doping region 3 is connected to the body region 15 in the Y direction, that is, the edge of the doping region 3 in the Y direction extends to the body region 15 on both sides of the isolation region 16 in the Y direction.
[0091] Specifically, the size of the gate structure 2 in the Y direction is not greater than the size of the isolation region 16 , and is located on the upper surface of the doping region 3 , and the vertical projection of the side wall of the gate structure 2 located above the isolation region 16 in the Y direction does not exceed the edge of the isolation region 16 .
[0092] As an example, the overlapping size of the projections of two adjacent doping regions 3 in the Y direction is not greater than the size of the gate structure 2 in the X direction.
[0093] As an example, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 . The gate dielectric layer 21 and the gate conductive layer 22 are sequentially stacked on the upper surface of the first conductive type column 13 , and the gate is electrically connected to the gate conductive layer 22 .
[0094] Specifically, the gate dielectric layer 21 is made of silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0095] Specifically, under the condition of ensuring the device performance, the thickness and size of the gate dielectric layer 21 can be selected according to actual conditions and are not limited here.
[0096] Specifically, the gate conductive layer 22 is made of polysilicon or other suitable conductive materials. In this embodiment, polysilicon is used as the gate conductive layer 22 .
[0097] Specifically, the gate structure 2 is also provided above the isolation region 16 , and the gate structure 2 above the isolation region 16 is connected to the gate structure 2 above the first conductive type column 13 .
[0098] Specifically, the gate structure 2 is disposed above the doped region 3 to increase the gate-source parasitic capacitance C of the device. gs , reducing the turn-off oscillation of the device.
[0099] Specifically, the gate structure 2 located on the surface of the doped region 3 is connected to the gate structure 2 located on the upper surface of the first conductive type column 13 , and both ends of the gate structure located on the upper surface of the first conductive type column 13 along the X direction extend to above the source region 151 .
[0100] Specifically, under the condition that the doping region 3 is connected to the body region 15, the gate-source parasitic capacitance C in the device can be adjusted by adjusting the size of the doping region 3 in the X direction and the Y direction. gs The gate-drain parasitic capacitance C gd In this embodiment, the doped region 3 is connected to the body region 15 in both the X direction and the Y direction. Since the source is electrically connected to the body region, the gate-drain parasitic capacitance C generated by the isolation region 16 can be gd All converted into gate-source parasitic capacitance C gs .
[0101] Specifically, the device is further provided with an interlayer dielectric layer (not shown) covering the doped region 3 , the exposed surface of the gate structure 2 , and the upper surface of the semiconductor structure 1 .
[0102] Specifically, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.
[0103] Specifically, under the condition of ensuring the performance of the device, the thickness of the interlayer dielectric layer can be selected according to actual conditions and is not limited here.
[0104] Specifically, the interlayer dielectric layer is further provided with a source contact hole and a gate contact hole (not shown) penetrating the interlayer dielectric layer, the bottom surface of the source contact hole exposes the source region 151 and the contact region, and the bottom surface of the gate contact hole exposes the gate conductive layer 22.
[0105] Specifically, the source fills the source contact hole, and the gate fills the gate contact hole.
[0106] Specifically, the drain electrode covers the lower surface of the substrate 11 and forms an ohmic contact with the substrate 11 .
[0107] Specifically, the material of the source electrode includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the drain electrode includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the gate electrode includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.
[0108] Specifically, by providing the doping region 3 whose edge extends into the body region 15 and is connected to the body region 15 on the upper surface layer of the isolation region 16, the doping region 3 has the same doping type as the body region 15, so that the gate-drain parasitic capacitance C generated by the provision of the isolation region 16 gd Transformed into gate-source parasitic capacitance C gs , which in turn increases the gate-source parasitic capacitance C of the device gs , improves the switching oscillation of the device and reduces the C gd With C gs The ratio between them can reduce the peak voltage value of the gate in the device, improve the impact resistance of the device, and enhance the performance of the device.
[0109] Specifically, since the doping region 3 connected to the body region 15 is arranged on the upper surface layer of the isolation region 16 of the device, compared with the device in which the doping region 3 is not arranged in the isolation region, the arrangement of the doping region 3 leads to an increase in the effective doping concentration of the body region 15, which in turn can reduce the on-resistance at the body region 15, effectively inhibit the turning on of the parasitic transistor (NPN transistor) in the device, and improve the UIS capability of the device.
[0110] The super junction MOSFET device of this embodiment optimizes the structure of the device, sets the isolation region 16 between two adjacent first conductive type columns 13 in the Y direction, and sets the doping region 3 on the upper surface of the isolation region 16. The doping region 3 is connected to the body region 15 and has the same doping type, so that the gate-drain parasitic capacitance C generated by the setting of the isolation region 16 is gd Transformed into gate-source parasitic capacitance C gs , which in turn increases the gate-source parasitic capacitance C of the device gs , improve the switching oscillation of the device and reduce the C gd With C gsThe ratio between them is increased, thereby reducing the peak voltage value of the gate in the device and improving the impact resistance of the device; due to the setting of the doping region 3, the effective doping concentration of the body region 15 is increased, thereby reducing the on-resistance at the body region 15, effectively suppressing the turning on of the parasitic transistor in the device, improving the UIS capability of the device, and improving the performance of the device.
[0111] Embodiment 2
[0112] This embodiment provides a method for preparing a super junction MOSFET device, comprising the following steps:
[0113] S1: Provide a semiconductor structure, the semiconductor structure comprising a first conductive type substrate, a first conductive type buffer zone, a first conductive type column, a second conductive type column, a second conductive type body region, a first conductive type source region, a second conductive type contact region and an isolation region, wherein the buffer zone is stacked on the upper surface of the substrate, the first conductive type column and the second conductive type column are located on the upper surface of the buffer zone and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns are arranged at intervals along the Y direction, the body region is located on the upper surface of the second conductive type column, the sidewall of the body region along the X direction protrudes from the sidewall of the second conductive type column, the source region is located on the upper surface layer of the body region, the sidewall of the source region is spaced from the sidewall of the body region by a preset distance, the upper surface of the first conductive type column is flush with the upper surface of the body region, the isolation region is located between two adjacent second conductive type columns along the Y direction, and the X direction and the Y direction are perpendicular to each other;
[0114] S2: forming a second conductive type doped region on the upper surface layer of the isolation region, wherein the doped region is connected to the body region;
[0115] S3: forming a gate structure on the upper surfaces of the first conductive type column and the doped region;
[0116] S4: forming a source electrode electrically connected to the source region, forming a gate electrode electrically connected to the gate structure, and forming a drain electrode electrically connected to the substrate.
[0117] See also Figures 9 to 13, performing the step S1 and the step S2: providing a semiconductor structure 1, the semiconductor structure 1 comprising a first conductive type substrate 11, a first conductive type buffer zone 12, a first conductive type column 13, a second conductive type column 14, a second conductive type body region 15, a first conductive type source region 151 and an isolation region 16, wherein the buffer zone 12 is stacked on the upper surface of the substrate 11, the first conductive type column 13 and the second conductive type column 14 are located on the upper surface of the buffer zone 12 and are alternately arranged in sequence along the X direction, a plurality of the second conductive type columns 14 are spaced apart along the Y direction, and the body region 15 is located The upper surface of the second conductive type column 14, the side wall of the body region 15 along the X direction protrudes from the side wall of the second conductive type column 14, the source region 151 is located on the upper surface layer of the body region 15, the side wall of the source region 151 is spaced apart from the side wall of the body region 15 by a preset distance, the upper surface of the first conductive type column 13 is flush with the upper surface of the body region 15, the isolation region 16 is located between two adjacent second conductive type columns 14 along the Y direction, and the X direction is perpendicular to the Y direction; a second conductive type doping region 3 is formed on the upper surface layer of the isolation region 16, and the doping region 3 is connected to the body region 15.
[0118] Specifically, while ensuring device performance, the size, thickness and shape of the substrate 11 can be selected according to actual conditions and are not limited here.
[0119] Specifically, while ensuring device performance, the size, thickness and shape of the buffer zone 11 can be selected according to actual conditions and are not limited here.
[0120] Specifically, under the condition of ensuring device performance, the height of the first conductive type column 13 can be selected according to actual conditions and is not limited here. The height here refers to the distance between the bottom surface of the first conductive type column 13 and the upper surface of the first conductive type column 13.
[0121] Specifically, under the condition of ensuring device performance, the distance between the upper surface of the second conductive type column 14 and the upper surface of the first conductive type column 13 can be selected according to actual conditions, and is not limited here.
[0122] Specifically, under the condition of ensuring device performance, the size, shape, doping concentration and thickness of the body region 15 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the upper surface of the body region 15 and the lower surface of the body region 15.
[0123] Specifically, the distance between the bottom surface of the second conductive type column 14 and the top surface of the body region 15 is the same as the distance between the bottom surface of the first conductive type column 13 and the top surface of the first conductive type column 13 .
[0124] Specifically, the upper surface layer of the body region 15 is also provided with a second conductive type contact region adjacent to the source region 151, the contact region is adjacent to the side wall of the source region 151 close to the side wall of the source region 151, and the side wall of the source region 151 away from the contact region is spaced a preset distance from the side wall of the body region 15.
[0125] Specifically, while ensuring device performance, the size and shape of the source region 151 can be selected according to actual conditions and are not limited here; the size and shape of the contact region can be selected according to actual conditions and are not limited here.
[0126] Specifically, Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 As shown, they are schematic diagrams of the top surface structure of the doped region 3, Fig. 9 Schematic diagram of the cross-sectional structure of the CC surface of the middle structure, Fig. 9 Schematic diagram of the cross-sectional structure of the DD plane of the middle structure, Fig. 9 Schematic diagram of the cross-sectional structure of the EE surface of the middle structure and Fig. 9 The method for forming the doping region 3 includes ion implantation or other suitable methods. In this embodiment, boron ions are implanted into the preset area in the isolation region 16 by an ion implantation process to obtain the doping region 3.
[0127] Specifically, perform step S3 and step S4: form a gate structure 2 on the upper surface of the first conductive type column 13 and the doped region 3; form a source electrode electrically connected to the source region 151, form a gate electrode 6 electrically connected to the gate structure 2, and form a drain electrode electrically connected to the substrate 11.
[0128] Specifically, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, and the formation of the gate structure 2 includes the following steps: forming a gate dielectric material layer (not shown) of a preset thickness and a gate conductive material layer (not shown) of a preset thickness in sequence on the upper surface of the semiconductor structure 1, and forming a patterned shielding layer (not shown) on the upper surface of the gate conductive material layer; etching the gate conductive material layer and the gate dielectric material layer in sequence based on the patterned shielding layer to obtain the gate structure 2.
[0129] Specifically, the method of forming the gate dielectric material layer includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods.
[0130] Specifically, the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0131] Specifically, the method of forming the shielding layer and patterning the shielding layer is a conventional photoresist coating, exposure and development process, which will not be described in detail here.
[0132] Specifically, the method of etching the gate conductive material layer includes dry etching, wet etching or other suitable methods; the method of etching the gate dielectric material layer includes dry etching, wet etching or other suitable methods.
[0133] Specifically, while ensuring device performance, the thickness of the gate conductive layer 22 can be selected according to actual conditions and is not limited here; in the X direction, the distance between the endpoint of the gate structure 2 and the edge of the source region 151 (that is, the size of the gate structure 2 located directly above the source region 151 along the X direction) can be selected according to actual conditions and is not limited here.
[0134] Specifically, after forming the gate structure 2, the step of removing the shielding layer is also included; the method of removing the shielding layer is a commonly used photoresist layer stripping method, which will not be described here.
[0135] Specifically, the gate structure 2 is also formed above the isolation region 16, the gate structure 2 located above the isolation region 16 is connected to the gate structure 2 located above the first conductive type column 13, and the vertical projection of the side wall of the gate structure 2 along the Y direction does not exceed the edge of the isolation region 16 along the Y direction.
[0136] Specifically, the dimension of the doped region 3 in the Y direction beyond the edge of the gate structure 2 is not greater than 3 μm, and the edge of the doped region 3 in the Y direction extends to the body region 15 on both sides of the isolation region 16 in the Y direction, and the overlapping dimension of the projections of the two adjacent doped regions 3 in the Y direction in the Y direction is not greater than the dimension of the gate structure 2 in the X direction.
[0137] Specifically, after forming the gate structure 2 and before forming the source and the gate, a step of forming an interlayer dielectric layer is also included, and the interlayer dielectric layer covers the exposed surfaces of the gate structure 2 and the doped region 3 and the upper surface of the semiconductor structure.
[0138] Specifically, the method of forming the interlayer dielectric layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0139] Specifically, after forming the interlayer dielectric layer and before forming the source and the gate, the step of forming a source contact hole and a gate contact hole is also included, the bottom surface of the gate contact hole exposes the gate conductive layer 22, and the bottom surface of the source contact hole exposes the source region 151 and the contact region.
[0140] Specifically, the method of forming the gate contact hole includes dry etching, wet etching or other suitable methods; the method of forming the source contact hole includes dry etching, wet etching or other suitable methods.
[0141] Specifically, while ensuring device performance, the opening size of the source contact hole can be selected according to actual conditions and is not limited here; the opening size of the gate contact hole can be selected according to actual conditions and is not limited here.
[0142] Specifically, the source electrode fills the source contact hole, and a method of forming the source electrode includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0143] Specifically, the gate fills the gate contact hole, and a method of forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0144] Specifically, the drain covers the bottom surface of the substrate 11, and the method of forming the drain includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0145] Specifically, the doping region 3 having the same doping type as the body region 15 is formed on the upper surface layer of the isolation region 16, the doping region 3 is connected to the body region 15, the source is electrically connected to the body region 15, and in the device, the capacitance between the gate and the body region 15 serves as the gate-source parasitic capacitance C gs , and then convert the capacitance contributed by the isolation region 16 into the parasitic capacitance between the gate and the body region 15, so that the capacitance between the body region 15 and the doped region 3 and the gate are both used as the gate-source parasitic capacitance C of the device. gs The gate-drain parasitic capacitance C generated by the formation of the isolation region 16 gd Transformed into gate-source parasitic capacitance C gs , which increases the gate-source parasitic capacitance C of the device gs , improving the device's turn-off oscillation.
[0146] Specifically, since the doped region 3 is formed on the upper surface layer of the isolation region 16, the doped region 3 is connected to the body region 15. During the operation of the device, the carriers in the doped region 3 will diffuse and be exhausted, further increasing the gate-source parasitic capacitance C of the device. gs , reduce the gate-drain parasitic capacitance C of the device gd , and the formation of the doped region 3 has no effect on the conductive channel of the device, and thus will not lead to an increase in the on-resistance of the device.
[0147] The method for preparing the super junction MOSFET device of this embodiment forms the doped region 3 on the upper surface layer of the isolation region 16, and the doped region 3 is connected to the body region 15, so that the gate-drain parasitic capacitance C generated in the isolation region 16 is gd Transformed into gate-source parasitic capacitance C gs , the turn-off oscillation of the device is improved, and the carrier diffusion and exhaustion in the doping region 3 will further reduce the gate-drain parasitic capacitance C of the device. gd , improve the gate-source parasitic capacitance C of the device gs .
[0148] In summary, the super junction MOSFET device and the preparation method thereof of the present invention improve the structure of the device, separate a plurality of first conductive type columns in the Y direction through the isolation region, and set a doped region on the upper surface layer of the isolation region, the doped region is connected to the body region in the X direction and has the same conductive type, so that the gate-drain parasitic capacitance C generated by the setting of the isolation region gd Transformed into gate-source parasitic capacitance C gs , which in turn increases the gate-source parasitic capacitance C in the device gs , while reducing the gate-drain parasitic capacitance C of the device gd The gate-source parasitic capacitance C gs The ratio of the gate voltage to the gate voltage of the device is reduced, the switching oscillation of the device is improved, the device's anti-breakthrough capability is enhanced, and the device's performance is improved; due to the setting of the doping region, the effective doping concentration of the body region is increased, and the on-resistance of the body region is reduced, which effectively inhibits the opening of the parasitic transistor in the device and improves the UIS capability of the device; during the operation of the device, due to the depletion of carrier diffusion in the doping region, the gate-drain parasitic capacitance C of the device is further reduced. gd , improve the gate-source parasitic capacitance C of the device gs , further improving the turn-off oscillation of the device and improving the performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0149] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A super junction MOSFET device, characterized in that: include: A semiconductor structure, comprising a first conductive type substrate, a first conductive type buffer zone, a first conductive type column, a second conductive type column, a second conductive type body region, a first conductive type source region and an isolation region, wherein the buffer zone is stacked on the upper surface of the substrate, the first conductive type column and the second conductive type column are located on the upper surface of the buffer zone and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns are arranged at intervals along the Y direction, the body region is located on the upper surface of the second conductive type column, the sidewall of the body region in the X direction protrudes from the sidewall of the second conductive type column, the source region is located on the upper surface layer of the body region, the sidewall of the source region is spaced a preset distance from the sidewall of the body region, and the The upper surface of the first conductive type column is flush with the upper surface of the body region, the isolation region is located between two adjacent second conductive type columns along the Y direction, and the X direction is perpendicular to the Y direction; A second conductive type doped region, located on an upper surface layer of the isolation region, the doped region being connected to the body region; A gate structure, located on the upper surface of the first conductive type column and the doped region; A source, a drain and a gate, wherein the source is electrically connected to the source region, the drain is electrically connected to the substrate, and the gate is electrically connected to the gate structure.
2. The super junction MOSFET device according to claim 1, characterized in that: The doping concentration of the buffer region is lower than the doping concentration of the first conductive type column, and the doping concentration of the substrate is higher than the doping concentration of the buffer region.
3. The super junction MOSFET device according to claim 1, characterized in that: The conductivity type of the isolation region is the same as the conductivity type of the first conductivity type pillar.
4. The super junction MOSFET device according to claim 1, characterized in that: The bottom surface of the isolation region is flush with the bottom surface of the first conductive type column, and the top surface of the isolation region is flush with the top surface of the first conductive type column.
5. The super junction MOSFET device according to claim 1, characterized in that: The size of the isolation region in the Y direction is the same as the distance between two adjacent second conductive type pillars in the Y direction.
6. The super junction MOSFET device according to claim 1, characterized in that: On the same straight line parallel to the X direction, at least one second conductive type column is spaced between two adjacent isolation regions.
7. The super junction MOSFET device according to claim 1, characterized in that: The doping region exceeds the gate structure by no more than 3 μm in the Y direction.
8. The super junction MOSFET device according to claim 1, characterized in that: The overlapping size of the projections of the two adjacent doping regions in the Y direction is not greater than the size of the gate structure in the X direction.
9. The super junction MOSFET device according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer and the gate conductive layer are sequentially stacked on the upper surface of the first conductive type column, and the gate is electrically connected to the gate conductive layer.
10. A method for preparing a super junction MOSFET device, characterized in that: The following steps are involved: A semiconductor structure is provided, the semiconductor structure comprising a first conductive type substrate, a first conductive type buffer zone, a first conductive type column, a second conductive type column, a second conductive type body region, a first conductive type source region and an isolation region, wherein the buffer zone is stacked on the upper surface of the substrate, the first conductive type column and the second conductive type column are located on the upper surface of the buffer zone and are alternately arranged in sequence along the X direction, a plurality of second conductive type columns are arranged at intervals along the Y direction, the body region is located on the upper surface of the second conductive type column, the sidewall of the body region along the X direction protrudes from the sidewall of the second conductive type column, the source region is located on the upper surface layer of the body region, the sidewall of the source region is spaced from the sidewall of the body region by a preset distance, the upper surface of the first conductive type column is flush with the upper surface of the body region, the isolation region is located between two adjacent second conductive type columns along the Y direction, and the X direction and the Y direction are perpendicular to each other; forming a second conductive type doped region on the upper surface layer of the isolation region, wherein the doped region is connected to the body region; forming a gate structure on the upper surfaces of the first conductive type column and the doped region; A source electrode electrically connected to the source region is formed, a gate electrode electrically connected to the gate structure is formed, and a drain electrode electrically connected to the substrate is formed.