Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a plurality of pixel unit columns which are sequentially arranged in the first direction, each pixel unit column comprises a plurality of pixel units which are sequentially arranged in the second direction, and the first direction is perpendicular to the second direction; each pixel unit comprises a first area, a second area and a third area which are sequentially arranged in the second direction; wherein the first region comprises a source electrode, the second region comprises a grid electrode layer, a semiconductor layer and a cushion block protruding in the third direction, the third region comprises a drain electrode, the third direction is perpendicular to the first direction and the second direction, and the cushion block, the semiconductor layer and the grid electrode layer are sequentially arranged in the third direction. According to the technical scheme, the channel length of the thin film transistor can be prolonged under the condition that the plane area is not increased, so that the uniformity of the thin film transistor is improved, and the performance of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel and a display device. Background Art

[0002] Since the beginning of the 20th century, people have made amazing achievements in the development of electronics. As one of the most important inventions, the transistor has changed the landscape of the entire technology industry since its invention. As the "heart" of the electronic world, transistors have greatly improved the performance of computers, communications, and consumer electronics, while being smaller in size and consuming less power. Among the many transistor technologies, the thin film transistor (TFT) is particularly noteworthy. It is made using thin film technology and controls the flow of current by changing the electric field rather than relying on current to control the current, which gives the thin film transistor the advantages of low power consumption and high speed.

[0003] When thin film transistors are used in display devices, in order to ensure the high performance of the display device, the uniformity of the thin film transistors must be high enough, because the uniformity directly affects the quality of the display. Therefore, how to improve the uniformity of thin film transistors is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above problems, the present application provides a display panel and a display device, which can extend the channel length of the thin film transistor without increasing the planar area, thereby improving the uniformity of the thin film transistor and enhancing the performance of the display panel.

[0005] In a first aspect, a display panel is provided, comprising: a plurality of pixel unit columns arranged in sequence along a first direction, the pixel unit columns comprising a plurality of pixel units arranged in sequence along a second direction, the first direction being perpendicular to the second direction; the pixel unit comprising a first region, a second region and a third region arranged in sequence along the second direction; wherein the first region comprises a source, the second region comprises a gate layer, a semiconductor layer and a pad protruding along a third direction, the third region comprises a drain, the third direction is perpendicular to the first direction and the second direction, and in the third direction, the pad, the semiconductor layer and the gate layer are arranged in sequence.

[0006] In combination with the first aspect, in certain implementations of the first aspect, in the third direction, a size of the spacer is less than or equal to 10 μm.

[0007] In combination with the first aspect, in certain implementations of the first aspect, the material of the spacer includes at least one of mixed silicon oxide and silicon nitride, polyimide, and polysiloxane.

[0008] In combination with the first aspect, in some implementations of the first aspect, the first region includes a first via, and the third region includes a second via; in the second direction, the first via and the second via are located on both sides of the gate layer.

[0009] In combination with the first aspect, in some implementations of the first aspect, the pad is disposed in an overlapping region of a data line and a gate line, the data line includes at least one of a source line or a drain line, and the gate line is located in the gate layer.

[0010] In combination with the first aspect, in certain implementations of the first aspect, in the third direction, the spacer overlaps with a projection of the gate layer in the third direction.

[0011] In combination with the first aspect, in some implementations of the first aspect, the second area includes a first part, a second part and a third part; the first part is arranged along the first direction, and the second part and the third part are arranged along the second direction.

[0012] In combination with the first aspect, in some implementations of the first aspect, the pad includes a first sub-pad and a second sub-pad, the first sub-pad is arranged in an overlapping area between the second part and the gate layer, and the second sub-pad is arranged in an overlapping area between the third part and the gate layer.

[0013] In combination with the first aspect, in some implementations of the first aspect, the spacer is disposed in an overlapping region between the first portion and the gate layer.

[0014] In combination with the first aspect, in some implementations of the first aspect, the second area includes a first part and a second part; the first part is arranged along the first direction, and the second part is arranged along the second direction.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the first region and the third region include a first conductor layer, the pixel unit also includes a buffer layer, and the buffer layer is located between the pad and the semiconductor layer; in the second direction, the first conductor layer of the first region, the pad, and the first conductor layer of the third region are arranged in sequence.

[0016] In combination with the first aspect, the second region further includes a gate layer; when a material of the gate layer is different from a material of the source electrode, the pixel unit further includes a first insulating layer, and the first insulating layer is located between the gate layer and the source electrode.

[0017] In combination with the first aspect, in some implementations of the first aspect, the material of the buffer layer and the first insulating layer includes SiNx or SiO x At least one of , 0<x≤2.

[0018] In combination with the first aspect, in some implementations of the first aspect, the third region further includes a second conductor layer, and in the third direction, the second conductor layer is connected to the drain.

[0019] In combination with the first aspect, in some implementations of the first aspect, the third region further includes a second conductive layer, and in the third direction, the second conductive layer is connected to the semiconductor layer.

[0020] In combination with the first aspect, in some implementations of the first aspect, the second area has a protrusion in the third direction.

[0021] In combination with the first aspect, in certain implementations of the first aspect, in the third direction, the pixel units have the same size in the first region, the second region, and the third region.

[0022] In a second aspect, a display device is provided, comprising a housing forming a receiving cavity; and a display panel in any possible implementation of the first aspect, wherein the display panel provides display content for the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the drawings without paying creative work.

[0024] Figure 1 A schematic structural diagram of a display panel according to an embodiment of the present application;

[0025] Figure 2 This is a schematic structural diagram of a pixel unit according to an embodiment of the present application;

[0026] Figure 3 For along Figure 2 Sectional view of AA';

[0027] Figure 4 This is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0028] Figure 5 This is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0029] Figure 6 This is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0030] Figure 7 This is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0031] Figure 8 for Figure 7 A partial enlarged view of the middle A area;

[0032] Fig. 9 This is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0033] Fig.10 This is a schematic structural diagram of a pixel unit according to another embodiment of the present application;

[0034] Fig.11 This is a schematic structural diagram of a pixel unit according to another embodiment of the present application;

[0035] Reference numerals:

[0036] Display panel-100, semiconductor layer-110, first conductor layer-120;

[0037] Pixel unit-200, first region-210, first through hole-2101, source-211, first via-hole-212, second region-220, pad-221, first sub-pad-2211, second sub-pad-2212, first portion-222, second portion-223, third portion-224, protrusion-225, third region-230, second through hole-2301, drain-231, second via-hole-232, second conductor layer-233, buffer layer-240, gate layer-250, first insulating layer-260, second insulating layer-270, flat layer-280;

[0038] The first direction is X, the second direction is Y, and the third direction is Z. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0040] The "range" disclosed in the present application is defined in the form of a lower limit and an upper limit, and a given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of a specific range. The range defined in this way includes the endpoint values, and can be arbitrarily combined, that is, any lower limit can be combined with any upper limit to form a range. For example, if the range of 60-120 and 80-110 is listed for a specific parameter, it is understood that the range of 60-110 and 80-120 is also expected. In addition, if the minimum range values ​​1 and 2 are listed, and if the maximum range values ​​3, 4 and 5 are listed, the following ranges can all be expected: 1-3, 1-4, 1-5, 2-3, 2-4 and 2-5. In the present application, unless otherwise specified, the numerical range "ab" represents the abbreviation of any real number combination between a and b, wherein a and b are real numbers. For example, the numerical range "0-5" represents that all real numbers between "0-5" have been fully listed herein, and "0-5" is just the abbreviation of these numerical combinations. In addition, when a parameter is expressed as an integer ≥ 2, it is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0041] If not otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0042] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0043] The terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one, two or more. The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0044] References to "one embodiment", "some embodiments", "an example" or "some examples" described in this specification mean that a particular feature, structure or characteristic described in conjunction with the example is included in one or more examples of the present application. Thus, the phrases "in one embodiment", "in some other examples", "in some other examples", etc. appearing at different places in this specification do not necessarily all refer to the same example, but mean "one or more but not all examples", unless otherwise specifically emphasized. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different description objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0046] The present application embodiments will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0047] In related technologies, thin film transistors often use a nearly planar design. When the channel length needs to be extended to ensure the characteristics of the thin film transistor, the design area is often increased. However, facing the design requirements of high pixel density (Pixel Per Inch), increasing the area of ​​the thin film transistor no longer meets the requirements. Therefore, how to ensure that the thin film transistor has a sufficiently long channel length within a limited area to ensure the performance of the thin film transistor and avoid the short channel effect is a technical problem that needs to be solved urgently.

[0048] In view of the above problems, the present application provides a display panel and a display device. The display panel includes a spacer protruding along a third direction, so that the channel length of the thin film transistor can be extended without increasing the planar area of ​​the thin film transistor, thereby improving the uniformity of the thin film transistor and improving the performance of the display panel.

[0049] When mentioned below, the channel length refers to the length of the portion between the source and the drain and overlapping the gate.

[0050] If mentioned below, the short channel effect refers to a series of phenomena affecting the thin film transistors that occur as the channel length of the thin film transistors decreases, thereby affecting the operating efficiency and display quality of the display panel and the display device.

[0051] The display panel and the display device described in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] Figure 1 FIG. 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present application. Figure 1 As shown, the display panel 100 includes a pixel unit column sequentially arranged along a first direction X, and the pixel unit column includes a plurality of pixel units 200 sequentially arranged along a second direction Y. The first direction X is perpendicular to the second direction Y.

[0053] For example, the first direction X is as follows: Figure 1 As shown, the first direction X may also be referred to as the length direction of the display panel 100 or the display device.

[0054] For example, the second direction Y is as follows: Figure 1 As shown, the second direction Y may also be referred to as the width direction of the display panel 100 or the display device.

[0055] In the display panel 100, it has pixel units 200 repeatedly arranged along a first direction X and a second direction Y. If mentioned below, a column of pixel units or a pixel unit column refers to a plurality of pixel units 200 sequentially arranged in the second direction Y, and a row of pixel units or a pixel unit row refers to a plurality of pixel units 200 sequentially arranged in the first direction X.

[0056] In the display panel 100 , unless otherwise specified, each of the plurality of pixel units 200 has the same structure.

[0057] Figure 2 is a schematic structural diagram of a pixel unit according to an embodiment of the present application, Figure 3 For along Figure 2 The cross-sectional view of AA' in FIG. Figure 3 As shown, the pixel unit 200 includes a first area 210, a second area 220 and a third area 230 arranged along the second direction Y.

[0058] That is, in Figure 3 In the embodiment, along the second direction Y, the first region 210 , the second region 220 and the third region 230 are arranged in sequence, or it can be said that the second region 220 is arranged between the first region 210 and the third region 230 .

[0059] Among them, the first region 210 includes a source 211, the second region 220 includes a gate layer 250, a semiconductor layer 110 and a pad 221 protruding along a third direction Z, and the third region 230 includes a drain 231, and the third direction Z is perpendicular to the first direction X and the second direction Y; in the third direction Z, the pad 221, the semiconductor layer 110 and the gate layer 250 are arranged in sequence.

[0060] For example, the third direction Z is as follows Figure 3 As shown, the third direction Z may also be referred to as a height direction or a thickness direction of the display panel 100 or the display device.

[0061] Unless otherwise specified, the display panel 100 includes a substrate layer, the substrate layer includes a display area and a non-display area, and the pixel unit 200 is disposed on one side of the display area.

[0062] Along the third direction Z, the pad 221, the semiconductor layer 110, and the gate layer 250 are sequentially arranged, which means that the semiconductor layer 110 is arranged on the side of the pad 221 away from the substrate layer. That is, it can be said that the gate layer 250 and the semiconductor layer 110 are located above the pad 221, or the pad 221 is located below the semiconductor layer 110 and the gate layer 250. It can also be said that from top to bottom, the gate layer 250, the semiconductor layer 110, and the pad 221 are sequentially arranged.

[0063] It should be noted here that the “upper”, “lower”, “left” and “right” described in the embodiments of the present application are relative and do not constitute a limitation on the actual product.

[0064] As described above, the channel length refers to the distance between the source 211 and the drain 231 and overlapping with the gate layer 250; more specifically, the channel length refers to the length of the portion between the source 211 and the drain 231 and overlapping with the gate layer 250.

[0065] The first region 210 includes a source 211, the second region 220 includes a semiconductor layer 110, a spacer 221 and a gate layer 250, and the third region 230 includes a drain 231, that is, the overlapping length of the semiconductor layer 110 and the gate layer 250 in the second region 220 can be called the channel length, that is, the length of the semiconductor layer 110 affects the channel length.

[0066] The spacer 221 protrudes along the third direction Z, and the gate layer 250 and the semiconductor layer 110 are located above the spacer 221. Therefore, compared with a planar design, the protruding semiconductor layer 110 has a longer overlapping length with the gate layer 250, that is, the channel length can be increased.

[0067] In the above scheme, the display panel 100 includes a plurality of pixel units 200 arranged along a first direction X and a second direction Y, and the pixel unit 200 includes a first region 210, a second region 220 and a third region 230. The second region 220 includes a pad 221, a semiconductor layer 110 and a gate layer 250. The pad 221 is arranged below the semiconductor layer 110 and has a protrusion along the third direction Z. The protrusion of the pad 221 can extend the overlapping length of the semiconductor layer 110 and the gate layer 250, that is, the channel length can be extended. By providing a pad 221 with a certain thickness in the second region 220 between the first region 210 including the source electrode 211 and the third region 230 including the drain electrode 231, the channel length can be extended and the uniformity of the thin film transistor can be improved, thereby improving the performance of the display panel 100 and the display device.

[0068] In addition, the above discussion is that the channel length can be extended when the footprint of the thin film transistor in the pixel unit 200 remains unchanged. When the width-to-length ratio of the thin film transistor is constant, the footprint of the thin film transistor can also be reduced through the above solution.

[0069] It should be noted that the semiconductor layer 110 may be disposed not only in the second region 220 , but also in the first region 210 and the third region 230 , but the spacer 221 is only disposed in the second region 220 .

[0070] In some embodiments, in the third direction Z, a size of the spacer 221 is less than or equal to 10 μm.

[0071] In the above solution, by making the size of the spacer 221 in the third direction Z less than or equal to 10 μm, the channel length can be effectively extended without increasing the production difficulty.

[0072] Specifically, in the third direction Z, the size of the spacer 221 may be 1 μm, 4 μm, 6 μm, 8 μm, 10 μm or any value within the above range.

[0073] In some embodiments, the material of the spacer includes at least one of mixed silicon dioxide and nitrogen dioxide, polyimide, and polysiloxane.

[0074] In the above solution, by making the material of the spacer include at least one of mixed silicon oxide and silicon nitride, polyimide and polysiloxane, the channel length can be effectively extended without affecting the function of the thin film transistor.

[0075] It should be noted here that the mixed silicon oxide and silicon nitride refers to a mixed material formed by alternate deposition of silicon oxide and silicon nitride, wherein the silicon oxide may be silicon dioxide and the silicon nitride may be nitrogen dioxide.

[0076] Figure 4 FIG. 1 is a schematic diagram of the structure of a display panel according to another embodiment of the present invention. Figure 4 As shown, in some embodiments, the first region 210 includes a first via hole 212 , and the third region 230 includes a second via hole 232 ; in the second direction Y, the first via hole 212 and the second via hole 232 are located on both sides of the gate layer 250 .

[0077] The two sides of the gate layer 250 are located at different sides of the gate layer 250. Therefore, it can also be said that the first via hole 212 and the second via hole 232 are located at different sides of the gate layer 250.

[0078] In the above solution, in the second direction Y, the first via hole 212 and the second via hole 232 are located on both sides of the gate layer 250 , which can reduce the risk of short circuit when designing with high PPI requirements.

[0079] Figure 5 FIG. 1 is a schematic diagram of the structure of a display panel according to another embodiment of the present application. Figure 5 As shown, the first via hole 212 and the second via hole 232 may also be disposed on the same side of the gate layer 250 .

[0080] It should be noted here that Figure 4 and Figure 5 Each pixel unit 200 shown in the figure includes only one thin film transistor, but in the current display panel 100, each pixel unit 200 may include more than one thin film transistor. When each pixel unit 200 includes multiple thin film transistors, the number of gate layers 250 will be consistent with the number of thin film transistors. Therefore, when each pixel unit 200 includes multiple thin film transistors, the position design of the first via hole 212 and the second via hole 232 can also meet the above requirements.

[0081] Figure 6 FIG. 1 is a schematic diagram of the structure of a display panel according to another embodiment of the present invention. Figure 6 As shown, in some embodiments, the pad 221 is disposed in the overlapping area of ​​the data line 300 (Date line) and the gate line (Gate line), the data line 300 includes at least one of a source line or a drain line, and the gate line is located in the gate layer 250.

[0082] The data line 300 includes a source line or a drain line, so it can be said that the data line 300 is a line that provides a signal to the source 211 or the drain 231. Specifically, the source line is a line electrically connected to the source 211, and the drain line is a line electrically connected to the drain 231.

[0083] The gate line is located in the gate layer 250, and the pad 221 is disposed in the overlapping region of the gate line and the data line 300. In this case, the pad 221 can be referred to as a block-shaped pad 221.

[0084] In the above solution, the pad 221 is arranged directly at the overlapping area of ​​the Gate line and the Date line, so that the overlapping capacitance between the Gate line and the Date line can be reduced while the channel length is extended.

[0085] Please continue to refer to Figure 4 In some embodiments, in the third direction Z, the spacer 221 coincides with the projection of the gate layer 250 .

[0086] At this time, in the third direction Z, the position of the spacer 221 in the display panel 100 substantially coincides with the position of the gate layer 250 , and the spacer 221 at this time can be referred to as a strip-shaped spacer 221 .

[0087] In the above solution, the spacer 221 is located in the same position as the gate layer 250 , so that the semiconductor layer 110 has not only a climbing section but also a section parallel to the gate layer 250 , which can further extend the channel length.

[0088] Figure 7 is a schematic structural diagram of a display panel according to another embodiment of the present application, Figure 8 for Figure 7 A partial enlarged view of area A in the middle. Figure 8 As shown, in some embodiments, the second region 220 includes a first portion 222, a second portion 223 and a third portion 224; the first portion 222 is disposed along a first direction X, and the second portion 223 and the third portion 224 are disposed along a second direction Y.

[0089] Among the three parts of the second region 220 , the second part 223 is connected to the first region 210 , the third part 224 is connected to the third region 230 , and the first part 222 connects the second part 223 and the third part 224 .

[0090] It should be understood that the first part 222 is arranged along the first direction X, which means that the size of the first part 222 in the first direction X is greater than or equal to the size in the second direction Y; similarly, the second part 223 and the third part 224 are arranged along the second direction Y, which means that the size of the second part 223 and the third part 224 in the second direction Y is greater than or equal to the size in the first direction X.

[0091] In the above scheme, by making the second area 220 of each pixel unit 200 include a first part 222 arranged along the first direction X and a second part 223 and a third part 224 arranged along the second direction Y, and the second area 220 has a pad 221 protruding along the third direction Z, the channel length can be extended, thereby improving the display quality of the display panel 100.

[0092] Please combine Figure 7 and Figure 8 In some embodiments, the pad 221 includes a first subpad 2211 and a second subpad 2212 . The first subpad 2211 is disposed in an overlapping region between the second portion 223 and the gate layer 250 , and the second subpad 2212 is disposed in an overlapping region between the third portion 224 and the gate layer 250 .

[0093] That is to say, the pad 221 has two separate parts, one part is arranged in the overlapping area of ​​the second part 223 and the gate layer 250, and the other part is arranged in the overlapping area of ​​the third part 224 and the gate layer 250. In this way, the channel forms a "convex-concave-convex" path, which can further extend the channel length while keeping the area unchanged.

[0094] Fig. 9 FIG. 1 is a schematic diagram of the structure of a display panel according to another embodiment of the present application. Fig. 9 As shown, in some embodiments, the spacer 221 is disposed in an overlapping region between the first portion 222 and the gate layer 250 .

[0095] The spacer 221 is disposed in the overlapping region of the first portion 222 and the gate layer 250 , so that the channel forms a “concave-convex-concave” path, which can further extend the channel length while keeping the area unchanged.

[0096] In the above scheme, when the second area 220 includes the first part 222, the second part 223 and the third part 224, the channel path presents a "convex-concave-convex" or "concave-convex-concave" shape, which can further extend the channel path and help to further improve the performance of the display panel 100.

[0097] Please continue to refer to Figure 6 In some embodiments, the second region 220 includes a first portion 222 and a second portion 223 , wherein the first portion 222 is disposed along the first direction X, and the second portion 223 is disposed along the second direction Y.

[0098] It should be noted that the first area 210 and the third area 230 need to be connected through the second area 220, so the first part 222 and the second part 223 are also connected. More specifically, the first part 222 is connected to the third area 230, the first part 222 is connected to the second part 223, and the second part 223 is connected to the first area 210.

[0099] In the above scheme, by making the second area 220 of each pixel unit 200 include a first part 222 arranged along the first direction X and a second part 223 arranged along the second direction Y, and the second area 220 has a pad 221 protruding along the third direction Z, the channel length can be extended, thereby improving the display quality of the display panel 100.

[0100] Please continue to refer to Figure 3 In some embodiments, the first region 210 and the third region 230 include a first conductor layer 120, and the pixel unit 200 further includes a buffer layer 240, and the buffer layer 240 is located between the pad 221 and the semiconductor layer 110; in the second direction Y, the first conductor layer 120 of the first region 210, the pad 221, and the first conductor layer 120 of the third region 230 are arranged in sequence.

[0101] In the second direction Y, the spacer 221 is disposed between the first conductor layer 120 in the first region 210 and the first conductor layer 120 in the third region 230 .

[0102] In the third direction Z, the spacer 221 , the buffer layer 240 and the semiconductor layer 110 are sequentially arranged, which can also be referred to as the buffer layer 240 being arranged above the spacer 221 , or the spacer 221 being arranged between the first conductor layers 120 .

[0103] When the first conductor layer 120 is patterned first and then the pad 221 is patterned, if the material of the first conductor layer 120 is an easily oxidized conductor material, such as copper, the buffer layer 240 can be provided to protect the first conductor layer 120. When the pad 221 is patterned first and then the first conductor layer 120 is patterned, the roughness difference of the raised pad 221 will affect the channel characteristics, and the buffer layer 240 can be provided to ensure that the surface of the pad 221 is smooth and fine.

[0104] In the above solution, by disposing the buffer layer 240 on the spacer 221 , the performance of the display panel 100 can be further improved.

[0105] In some embodiments, when the material of the gate layer 250 is different from the material of the source electrode 211 , the pixel unit 200 further includes a first insulating layer 260 , and the first insulating layer 260 is located between the gate layer 250 and the source electrode 211 .

[0106] In the embodiments of the present application, unless otherwise specified, the materials of the source 211 and the drain 231 should remain consistent, and in the third direction X, the source 211 and the drain 231 are located on the same level. Therefore, the first insulating layer 260 is located between the gate layer 250 and the source 211, which means that the first insulating layer 260 is located between the gate layer 250 and the drain 231.

[0107] When the materials of the source electrode 211 , the drain electrode 231 and the gate layer 250 are different, a first insulating layer 260 needs to be disposed between the two to prevent short circuits and control the conductivity of the channel.

[0108] When the source electrode 211 and the drain electrode 231 are made of the same material, the first insulating layer 260 may not be disposed therebetween.

[0109] In the above solution, when the material of the gate layer 250 is different from that of the source electrode 211 , by providing a first insulating layer 260 between the source electrode 211 and the gate layer 250 , short circuit can be prevented and the conductivity of the channel can be controlled to ensure the normal performance of the display panel 100 .

[0110] Of course, insulating layers may be disposed between other film layers as needed. For example, a second insulating layer 270 may be disposed between the gate layer 250 and the semiconductor layer 110 .

[0111] In some embodiments, the material of the buffer layer 240 and the first insulating layer 260 includes SiN x or SiO x At least one of , 0<x≤2.

[0112] In the above solution, by making the materials of the buffer layer 240 and the first insulating layer 260 include SiN x or SiO x At least one of the following conditions, and 0<x≤2, can ensure the normal operation of the display panel 100.

[0113] Specifically, SiN x It can be SiN or Si3N4, SiO x It can be SiO2.

[0114] In some embodiments, the third region 230 further includes a second conductor layer 233 . In the third direction Z, the second conductor layer 233 is connected to the drain electrode 231 .

[0115] When the second conductor layer 233 is connected to the drain electrode 231 , the second conductor layer 233 is connected to the semiconductor layer 110 in a manner of being bridged by the drain electrode 231 .

[0116] In the above solution, the second conductor layer 233 is connected to the semiconductor layer 110 by means of a cross-connection of the drain electrode 231 , and this process is relatively mature.

[0117] Fig.10 FIG. 1 is a schematic diagram of the structure of a pixel unit according to another embodiment of the present invention. Fig.10 As shown, in some embodiments, the third region 230 includes a second conductor layer 233 , and in the third direction Z, the second conductor layer 233 is connected to the semiconductor layer 110 .

[0118] That is to say, in this embodiment, the second conductor layer 233 can be directly connected to the semiconductor layer 110 by direct drilling, which can save the material for making the source electrode 211 and the drain electrode 231 to reduce the cost. However, when the hole is drilled deeper, poor overlap is likely to occur. In the actual production process, the user can select the connection method between the second conductor layer 233 and the semiconductor layer 110 as needed.

[0119] It should be noted here that when direct drilling is used to connect the second conductor layer 233 to the semiconductor layer 110 , the first through hole 2101 obtained in the first region 210 and the second through hole 2301 obtained in the third region 230 are equivalent to the source 211 and the drain 231 .

[0120] Please continue to refer to Figure 3 In some embodiments, the second region 220 has a protrusion 225 in the third direction Z.

[0121] In the third direction Z, the second area 220 has the protrusion 225, which means that compared with the first area 210 and the third area 230, the second area 220 has a protruding piece, and the protrusion 225 can serve as a supporting structure during box assembly.

[0122] In the above solution, by making the second region 220 of the pixel unit 200 have the protrusion 225 in the third direction Z, the protrusion 225 can serve as a supporting structure during cell assembly to improve the installation accuracy of the display device.

[0123] Fig.11 FIG. 1 is a schematic diagram of the structure of a pixel unit according to another embodiment of the present application. Fig.11 As shown, in the third direction Z, the sizes of the pixel unit 200 in the first region 210 , the second region 220 and the third region 230 are the same.

[0124] Whether the second region 220 has the protrusion 225 in the third direction Z can be achieved by adjusting the flat layer 280 .

[0125] An embodiment of the present application further provides a display device, comprising a display panel in any of the above-mentioned possible implementation modes.

[0126] The display device may be a display device such as an OLED display, and any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. including these display devices.

[0127] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are only examples, and the embodiments having the same structure as the technical idea and exerting the same effect within the scope of the technical solution of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the main purpose of the present application, various modifications that can be thought of by those skilled in the art to the embodiments and other methods of combining some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel unit columns sequentially arranged along a first direction, wherein the pixel unit columns include a plurality of pixel units sequentially arranged along a second direction, wherein the first direction is perpendicular to the second direction; The pixel unit includes a first region, a second region and a third region sequentially arranged along the second direction; in, The first region includes a source electrode, the second region includes a gate layer, a semiconductor layer and a pad protruding along a third direction, and the third region includes a drain electrode, and the third direction is perpendicular to the first direction and the second direction; In the third direction, the spacer, the semiconductor layer and the gate layer are arranged in sequence.

2. The display panel according to claim 1, characterized in that: In the third direction, a size of the spacer is less than or equal to 10 μm.

3. The display panel according to claim 1, characterized in that: The material of the spacer includes at least one of mixed silicon oxide and silicon nitride, polyimide, and polysiloxane.

4. The display panel according to claim 1, characterized in that: The first region includes a first via hole, and the third region includes a second via hole; In the second direction, the first via hole and the second via hole are located at two sides of the gate layer.

5. The display panel according to claim 4, characterized in that: The pad is disposed in an overlapping region of a data line and a gate line, the data line includes at least one of a source line or a drain line, and the gate line is located in the gate layer.

6. The display panel according to claim 4, characterized in that: In the third direction, the spacer overlaps with a projection of the gate layer.

7. The display panel according to claim 4, characterized in that: The second region includes a first portion, a second portion, and a third portion; The first portion is disposed along the first direction, and the second portion and the third portion are disposed along the second direction.

8. The display panel according to claim 7, characterized in that: The pad includes a first sub-pad and a second sub-pad. The first sub-pad is disposed in an overlapping region between the second portion and the gate layer, and the second sub-pad is disposed in an overlapping region between the third portion and the gate layer.

9. The display panel according to claim 7, characterized in that: The spacer is disposed in an overlapping region of the first portion and the gate layer.

10. The display panel according to claim 1, characterized in that: The second region includes a first portion and a second portion; The first portion is disposed along the first direction, and the second portion is disposed along the second direction.

11. The display panel according to claim 1, characterized in that: The first region and the third region include a first conductor layer, and the pixel unit further includes a buffer layer, and the buffer layer is located between the spacer and the semiconductor layer; In the second direction, the first conductor layer in the first region, the spacer, and the first conductor layer in the third region are arranged in sequence.

12. The display panel according to claim 11, characterized in that: When the material of the gate layer is different from that of the source electrode, the pixel unit further includes a first insulating layer, and the first insulating layer is located between the gate layer and the source electrode.

13. The display panel according to claim 12, characterized in that: The materials of the buffer layer and the first insulating layer include SiN x or SiO x At least one of , 0<x≤2.

14. The display panel according to any one of claims 1 to 13, characterized in that: The third region further includes a second conductor layer, and in the third direction, the second conductor layer is connected to the drain.

15. The display panel according to any one of claims 1 to 13, characterized in that: The third region further includes a second conductive layer, and in the third direction, the second conductive layer is connected to the semiconductor layer.

16. The display panel according to any one of claims 1 to 13, characterized in that: The second region has a protrusion in the third direction.

17. The display panel according to any one of claims 1 to 13, characterized in that: In the third direction, the pixel units have the same size in the first region, the second region and the third region.

18. A display device, characterized in that: include: A housing, forming a receiving cavity; and The display panel according to any one of claims 1 to 17, wherein the display panel is accommodated in the accommodating cavity to provide display content to the display device.

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