Vertical differential inductor structure and preparation method thereof

Abstract

The invention provides a vertical differential inductor structure and a preparation method thereof, the structure comprises two inductor units, and each inductor unit comprises at least one vertical spiral coil, a first connecting end and a second connecting end. According to the vertical spiral coil, the area of a single-layer inductor is reduced through a metal layer stacking forming mode. The first connecting ends of the two inductor units are connected to the first tap or the two second taps respectively, and the second connecting ends of the two inductor units are connected to the two second taps or the first tap respectively. The two inductor units are symmetrical relative to the vertical plane where the first tap is located to form the differential inductor structure, the quality factor and the anti-interference capacity of the inductor structure are improved, and the inductor structure has a high Q value while the occupied chip area is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical differential inductor structure and a preparation method thereof. Background Art

[0002] Inductors are an indispensable and important component of RF (Radio Frequency) integrated circuits or other analog circuits. Transformers, filters and other devices based on inductors play an important role in filtering, impedance matching, current isolation and other important functions in high-performance RF circuits. Therefore, inductors are widely used in RF integrated circuits and other analog circuits. Since the traditional solenoid inductor structure is not suitable for integrated circuits, planar spiral inductors are widely used as the core inductor device in RF integrated circuits.

[0003] With the improvement of semiconductor process technology, the characteristic size of the chip continues to decrease, but the inductance value required by the circuit has not decreased, and the requirement for the quality factor (Q value) of the inductor is increasing day by day.

[0004] Currently, the general way to improve the inductor quality factor is to increase the number of turns of the planar spiral inductor, which means that the area of ​​the inductor in the chip increases, which limits the layout of other devices in the chip.

[0005] Therefore, how to improve the quality factor of the inductor while reducing the chip area occupied by the inductor has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0006] The present invention provides a vertical radio frequency inductor structure and a preparation method thereof, aiming to improve the quality factor and anti-interference capability of the inductor while reducing the chip area occupied by the inductor.

[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a vertical differential inductor structure, comprising:

[0008] A substrate having an interlayer dielectric layer formed thereon;

[0009] Two inductance units, located in and on the interlayer dielectric layer, each of the inductance units comprising at least one vertical spiral coil, a first connection end and a second connection end;

[0010] The vertical spiral coil comprises: a first metal layer, an intermediate connection metal layer, and a second metal layer which are electrically connected in sequence through conductive vias, the first metal layer being the N / 2th metal layer or the N / 2+1th metal layer among N metal layers located in and on the interlayer dielectric layer, the second metal layer being the top metal layer or the bottom metal layer among the N metal layers, and the metal layers are stacked in sequence from bottom to top, N being an integer and N≥2;

[0011] The first connection end is connected to the first metal layer of the first vertical spiral coil of each of the inductor units, and the second connection end is connected to the second metal layer of the last vertical spiral coil of each of the inductor units or the first metal layer of the last vertical spiral coil;

[0012] a first tap and two second taps, the first connection end of each of the inductance units is connected to the first tap, and the second connection end of each of the inductance units is respectively connected to the corresponding second tap; or, the first connection end of each of the inductance units is respectively connected to the corresponding second tap, and the second connection end of each of the inductance units is connected to the first tap;

[0013] The second tap is used for inputting a signal, and the first tap is used for outputting a signal;

[0014] The structures of the two inductance units are symmetrical with respect to the vertical plane where the first tap is located; wherein N is an even number and N≥2.

[0015] Optionally, the inductor unit includes a vertical spiral coil, and the second connection end is connected to the second metal layer of the corresponding vertical spiral coil.

[0016] Optionally, the inductor unit includes two vertical spiral coils, and the second connecting end is connected to the first metal layer of the last vertical spiral coil;

[0017] The second metal layers of the vertical spiral coils of the inductor unit are electrically connected.

[0018] Optionally, the inductor unit includes two or more odd-numbered vertical spiral coils, and the second connection end is connected to the second metal layer of the last vertical spiral coil;

[0019] The inductor unit includes two or more even-numbered vertical spiral coils, and the second connecting end is connected to the first metal layer of the last vertical spiral coil;

[0020] The inductor unit includes more than two vertical spiral coils, and the first vertical spiral coil to the last vertical spiral coil in each inductor unit are electrically connected in sequence through the first metal layer of each vertical spiral coil and the second metal layer of each vertical spiral coil.

[0021] Optionally, the bottom metal layer of the vertical spiral coil is located in the interlayer dielectric layer;

[0022] The vertical differential inductor structure also includes a metal interlayer dielectric layer;

[0023] The top metal layer, the first metal layer and the middle connection metal layer of each of the vertical spiral coils are all located in the intermetallic dielectric layer;

[0024] The i-th metal layer of the vertical spiral coil is located in the i-1-th intermetallic dielectric layer;

[0025] The i-1th conductive through hole of the vertical spiral coil is located in the i-1th intermetallic dielectric layer;

[0026] The (i-1)th intermetallic dielectric layer is located on the (i-2)th intermetallic dielectric layer, wherein i is an integer and N≥i≥2.

[0027] Optionally, the first metal layer and the second metal layer of each of the vertical spiral coils are the N / 2th metal layer and the top metal layer respectively;

[0028] Both ends of the k-th metal layer of the vertical spiral coil are connected to a k-th conductive via, and each of the k-th conductive vias is connected to a k+1-th conductive via, wherein k is an integer and N / 2>k≥1;

[0029] One end of the N / 2 metal layer of the vertical spiral coil is connected to one end of the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2+1 metal layer is connected to the N / 2-1 conductive via through an N / 2 conductive via;

[0030] Both ends of the l-th metal layer of the vertical spiral coil are connected to an l-1-th conductive via, and each of the l-1-th conductive vias is connected to an l-2-th conductive via, wherein l is an integer and N>l>N / 2+1;

[0031] The top metal layer of the vertical spiral coil is connected to an N-1th layer conductive via, and each of the N-1th layer conductive vias is connected to an N-2th layer conductive via.

[0032] Optionally, the first metal layer and the second metal layer of each of the vertical spiral coils are the N / 2+1th metal layer and the bottom metal layer respectively;

[0033] The bottom metal layer of the vertical spiral coil is connected to a first-layer conductive via, and the first-layer conductive via is connected to a second-layer conductive via;

[0034] Both ends of the m-th metal layer of the vertical spiral coil are connected to the m-th conductive vias, and each of the m-th conductive vias is connected to the m+1-th conductive via, wherein m is an integer and N / 2-1≥m>1;

[0035] One end of the N / 2 metal layer of the vertical spiral coil is connected to the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2 metal layer is connected to the N / 2+1 conductive via through an N / 2 conductive via;

[0036] Both ends of the nth metal layer are connected to an n-1th conductive via, and each of the n-1th conductive vias is connected to an n-2th conductive via, wherein n is an integer and N≥n>N / 2+1.

[0037] Optionally, the thickness of each metal layer in the N metal layers is in the range of

[0038] The spacing between the N metal layers ranges from 140um to 1400um.

[0039] Optionally, the height range of each of the conductive vias is

[0040] The minimum diameter of each of the conductive through holes is in the range of 0.12 um to 0.16 um.

[0041] According to a second aspect of the present invention, a method for preparing a vertical differential inductor is provided, which is used to prepare the vertical differential inductor structure mentioned above, and the method comprises:

[0042] Providing a substrate, wherein an interlayer dielectric layer is filled on the substrate;

[0043] Two inductance units, a first tap and two second taps in or on the interlayer dielectric layer;

[0044] Wherein, each of the inductance units includes at least one vertical spiral coil, a first connection end and a second connection end, the first connection end of each of the inductance units is connected to the first tap, and the second connection end of each of the inductance units is respectively connected to the corresponding second taps; or, the first connection end of each of the inductance units is respectively connected to the corresponding second taps, and the second connection end of each of the inductance units is connected to the first tap.

[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0046] The present invention provides a vertical differential inductor structure and a preparation method thereof, the structure comprising two inductor units, each of which comprises at least one vertical spiral coil, a first connection end and a second connection end. The vertical spiral coil is formed by stacking metal layers, thereby reducing the area of ​​a single-layer inductor. In addition, the first connection ends of the two inductor units are both connected to a first tap or are respectively connected to two second taps, and the second connection ends of the two inductor units are respectively connected to two second taps or are both connected to the first tap. The two inductor units are symmetrical with respect to the vertical plane where the first tap is located to form a differential inductor structure, thereby improving the quality factor and anti-interference ability of the inductor structure, so that the inductor structure of the present invention has a higher Q value while reducing the chip area occupied. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 is a schematic diagram of the three-dimensional structure of a vertical differential inductor structure in the first embodiment of the present invention;

[0049] Figure 2 It is a front cross-sectional schematic diagram corresponding to a method for preparing a vertical differential inductor structure in the first embodiment of the present invention;

[0050] Figure 3 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a second embodiment of the present invention;

[0051] Figure 4 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a third embodiment of the present invention;

[0052] Figure 5 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a fourth embodiment of the present invention;

[0053] Figure 6 It is a front cross-sectional schematic diagram corresponding to another method for preparing the vertical differential inductor structure in the first embodiment of the present invention;

[0054] Figure 7-Figure 20 A schematic diagram of a vertical differential inductor structure corresponding to each step of a method for preparing a vertical differential inductor structure of the present invention;

[0055] Fig.21 It is a schematic diagram of a vertical differential inductor structure corresponding to another method for preparing a vertical differential inductor structure of the present invention.

[0056] Description of reference numerals:

[0057] 100-substrate;

[0058] 200-interlayer dielectric layer;

[0059] 1000-inductor unit;

[0060] 300-vertical spiral coil;

[0061] 400-intermetal dielectric layer;

[0062] 311-first metal layer;

[0063] 312- second metal layer;

[0064] 313-the third metal layer;

[0065] 314- fourth metal layer;

[0066] 315- fifth metal layer;

[0067] 316-sixth metal layer;

[0068] 321-first layer conductive via;

[0069] 322-second layer conductive via;

[0070] 323-third conductive via layer;

[0071] 324-fourth layer conductive via;

[0072] 325- fifth layer conductive via;

[0073] 330-first tap;

[0074] 340 - second tap;

[0075] 401-first intermetallic dielectric layer;

[0076] 402-a second intermetallic dielectric layer;

[0077] 403-third intermetallic dielectric layer;

[0078] 404--the fourth intermetallic dielectric layer;

[0079] 405--Fifth intermetallic dielectric layer;

[0080] IN-input signal;

[0081] OUT-output signal. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0084] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0085] As described in the background art, the present invention aims to solve the technical problem of improving the Q value and anti-interference capability of an inductor while reducing the chip area occupied by the inductor.

[0086] In the prior art, in order to increase the Q value of the inductor, the method is to increase the number of turns of the planar spiral inductor. This method has at least the following technical problems:

[0087] 1) The problem of large area of ​​planar spiral inductors has not been fundamentally solved, and due to the low inductor-to-coil area ratio (l-density), a larger area inductor is still required.

[0088] 2) Eddy current loss is prone to occur between the layers of coils in a planar spiral inductor. Eddy current loss will cause proximity effect and skin effect, thereby reducing the Q value of the inductor.

[0089] 3) Planar spiral inductors have serious signal distortion in high-frequency circuits.

[0090] In view of this, the present invention provides a vertical differential inductor structure, which may include:

[0091] A substrate having an interlayer dielectric layer formed thereon;

[0092] Two inductance units, located in and on the interlayer dielectric layer, each of the inductance units comprising at least one vertical spiral coil, a first connection end and a second connection end;

[0093] The vertical spiral coil may include: a first metal layer, an intermediate connection metal layer, and a second metal layer that are electrically connected in sequence through conductive vias, the first metal layer being the N / 2th metal layer or the N / 2+1th metal layer among N metal layers located in and on the interlayer dielectric layer, the second metal layer being the top metal layer or the bottom metal layer among the N metal layers, and the metal layers are stacked in sequence from bottom to top, N being an integer and N≥2;

[0094] The first connection end is connected to the first metal layer of the first vertical spiral coil of each of the inductor units, and the second connection end is connected to the second metal layer of the last vertical spiral coil of each of the inductor units or the first metal layer of the last vertical spiral coil;

[0095] a first tap and two second taps, the first connection end of each of the inductance units is connected to the first tap, and the second connection end of each of the inductance units is respectively connected to the corresponding second tap; or, the first connection end of each of the inductance units is respectively connected to the corresponding second tap, and the second connection end of each of the inductance units is connected to the first tap;

[0096] The two second taps are used for inputting signals, and the first tap is used for outputting signals;

[0097] The structures of the two inductance units are symmetrical with respect to the vertical plane where the first tap is located; wherein N is an even number and N≥2.

[0098] The vertical differential inductor structure provided by an embodiment of the present invention includes two inductor units, each of which includes at least one vertical spiral coil, a first connection end, and a second connection end. The vertical spiral coil is formed by stacking metal layers, thereby reducing the area of ​​a single-layer inductor. In addition, the first connection ends of the two inductor units are both connected to the first tap or are respectively connected to two second taps, and the second connection ends of the two inductor units are respectively connected to the two second taps or are both connected to the first tap. The two inductor units are symmetrical with respect to the vertical plane where the first tap is located to form a differential inductor structure, thereby improving the quality factor and anti-interference ability of the inductor structure, so that the inductor structure of the present invention has a higher Q value while reducing the chip area occupied.

[0099] Furthermore, the vertical differential inductor structure provided by the present invention avoids signal distortion of the vertical differential inductor structure in the radio frequency circuit through differential design.

[0100] Furthermore, the metal layers of the vertical differential inductor structure provided by the present invention are isolated by an intermetallic dielectric layer and the thickness of each metal layer, the thickness of each conductive through-hole and the distance between each metal layer are reasonably set to avoid eddy current loss between the metal layers, thereby avoiding the proximity effect and skin effect caused by eddy current loss, thereby improving the Q value of the inductor.

[0101] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the following, in conjunction with the accompanying drawings, takes the vertical spiral coil including six metal layers as an example to describe a specific embodiment of the present invention in detail. Of course, it should be understood that the present invention is not limited to this, and each of the vertical spiral coils can include any greater than or equal to two metal layers.

[0102] Figure 1 is a schematic diagram of the three-dimensional structure of a vertical differential inductor structure in the first embodiment of the present invention; Figure 2 It is a front cross-sectional schematic diagram corresponding to a method for preparing a vertical differential inductor structure in the first embodiment of the present invention; Figure 3 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a second embodiment of the present invention; Figure 4 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a third embodiment of the present invention; Figure 5 is a schematic diagram of a three-dimensional structure of a vertical differential inductor structure in a fourth embodiment of the present invention; Figure 6 It is a front cross-sectional schematic diagram corresponding to another method for preparing the vertical differential inductor structure in the first embodiment of the present invention.

[0103] Please refer to Figure 1 Combined with Figure 2 A first embodiment of the present invention provides a vertical differential inductor structure, which may include:

[0104] A substrate 100 is provided with an interlayer dielectric layer 200 formed thereon.

[0105] Two inductor units 1000 are located in and on the interlayer dielectric layer 200 , and each of the inductor units 1000 includes a vertical spiral coil 300 , a first connection end, and a second connection end.

[0106] The vertical spiral coil 300 may include: a first metal layer, an intermediate connecting metal layer, and a second metal layer that are electrically connected in sequence through conductive vias, the first metal layer being the N / 2th metal layer among the N metal layers located in and on the interlayer dielectric layer, the second metal layer being the top metal layer among the N metal layers, and the metal layers are stacked in sequence from bottom to top, N is an even number and N≥2.

[0107] The first connection end is connected to the first metal layer of the first vertical spiral coil 300 of each of the inductor units 1000 , and the second connection end is connected to the first metal layer of the last vertical spiral coil 300 .

[0108] A first tap 330 and two second taps 340 , the first connection end of each of the inductor units 1000 is connected to the first tap 330 , and the second connection end of each of the inductor units is respectively connected to the corresponding second tap 340 .

[0109] The two second taps 340 are used for inputting a signal IN, and the first tap 330 is used for outputting a signal OUT.

[0110] The structures of the two inductor units 1000 are symmetrical with respect to the vertical plane where the first tap 330 is located.

[0111] For ease of description, in the following embodiments, the metal layer N of the vertical spiral coil is 6.

[0112] In this embodiment, please refer to Figure 2 The vertical spiral coil 300 may include a first metal layer 311 , a second metal layer 312 , a third metal layer 313 , a fourth metal layer 314 , a fifth metal layer 315 and a sixth metal layer 316 .

[0113] In this embodiment, the first metal layer is the third metal layer 313, the second metal layer is the top metal layer (sixth metal layer 316), and the intermediate connecting metal layer is other metal layers in the N-layer metal layer other than the first metal layer and the second metal layer, that is, the intermediate connecting metal layer includes the first metal layer 311, the second metal layer 312, the fourth metal layer 314 and the fifth metal layer 315.

[0114] In some embodiments, the thickness of each metal layer in the N metal layers ranges from

[0115] If the thickness of each metal layer is too small, the resistance of the vertical differential inductor structure will increase, resulting in increased loss in the circuit. If the thickness of each metal layer is too high, the vertical differential inductor structure will occupy a large area in the chip, affecting the thickness of other devices. The vertical differential inductor structure has a small resistance and occupies a small area in the chip.

[0116] In some embodiments, the spacing between the metal layers may range from 140 um to 1400 um.

[0117] If the distance between the metal layers is too small, the proximity effect and skin effect of the vertical differential inductor will increase, affecting the quality factor Q value of the vertical differential inductor structure. If the distance between the metal layers is too large, the area occupied by the vertical differential inductor structure in the chip will increase. Therefore, by setting the spacing between the metal layers in the range of 140um to 1400um, the vertical differential inductor structure occupies a smaller area in the chip and has a higher Q value.

[0118] In some embodiments, the height range of the conductive vias in each layer is The minimum diameter of each of the conductive through holes is in the range of 0.12 um to 0.16 um.

[0119] If the diameter of each conductive via is too small, the process will be difficult to implement. If the diameter of each conductive via is too large, the vertical differential inductor structure will occupy a large area in the chip. , so that the preparation process of the vertical differential inductor structure is easy to implement and occupies a small area in the chip.

[0120] In some embodiments, please refer to Figure 2 The bottom metal layer (ie, the first metal layer 311 ) of the vertical spiral coil 300 is located in the interlayer dielectric layer 200 .

[0121] In this embodiment, the vertical differential inductor structure may further include a metal interlayer dielectric layer. The top metal layer (sixth metal layer 316), the first metal layer (third metal layer 313) and the intermediate connection metal layer (first metal layer 311, second metal layer 312, fourth metal layer 314, fifth metal layer 315) of each vertical spiral coil 300 are all located in the metal interlayer dielectric layer.

[0122] In this embodiment, the metal interlayer dielectric layer is a multi-layer structure, including N-1 layers of gold interlayer dielectric layers.

[0123] Specifically, the metal interlayer dielectric layer includes five gold interlayer dielectric layers.

[0124] In this embodiment, the i-th metal layer of the vertical spiral coil is located in the i-1-th intermetallic dielectric layer.

[0125] Specifically, the second metal layer 312, the third metal layer 313, the fourth metal layer 314, the fifth metal layer 315 and the sixth metal layer 316 are respectively located in the first intermetallic dielectric layer 401, the second intermetallic dielectric layer 402, the third intermetallic dielectric layer 403, the fourth intermetallic dielectric layer 404 and the fifth intermetallic dielectric layer 405.

[0126] In this embodiment, the i-1th conductive through hole of the vertical spiral coil is located in the i-1th intermetallic dielectric layer.

[0127] Specifically, the first layer conductive via 321, the second layer conductive via 322, the third layer conductive via 323, the fourth layer conductive via 324 and the fifth layer conductive via 325 are respectively located in the first layer intermetallic dielectric layer 401, the second layer intermetallic dielectric layer 402, the third layer intermetallic dielectric layer 403, the fourth layer intermetallic dielectric layer 404 and the fifth layer intermetallic dielectric layer 405.

[0128] In this embodiment, the (i-1)th intermetallic dielectric layer is located on the (i-2)th intermetallic dielectric layer, wherein i is an integer and N≥i≥2.

[0129] Specifically, the first intermetallic dielectric layer 401, the second intermetallic dielectric layer 402, the third intermetallic dielectric layer 403, the fourth intermetallic dielectric layer 404 and the fifth intermetallic dielectric layer 405 are respectively located on the interlayer dielectric layer 200, the first intermetallic dielectric layer 401, the second intermetallic dielectric layer 402, the third intermetallic dielectric layer 403 and the fourth intermetallic dielectric layer 404.

[0130] In one embodiment, both ends of the k-th metal layer of each vertical spiral coil are connected to a k-th conductive via, and each of the k-th conductive vias is connected to a k+1-th conductive via, wherein k is an integer and N / 2>k≥1.

[0131] Specifically, when N=6, the k-th metal layer may include a first metal layer 311 and a second metal layer 312, wherein both ends of the first metal layer 311 are respectively connected to a first-layer conductive via 321, and both ends of the second metal layer 312 are respectively connected to a second-layer conductive via 322. Each of the first-layer conductive vias 321 is connected to a second-layer conductive via 322, and each of the second-layer conductive vias 322 is connected to a third-layer conductive via 323.

[0132] In one embodiment, one end of the N / 2 metal layer of each vertical spiral coil is connected to one end of the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2+1 metal layer is connected to an N / 2-1 conductive via through an N / 2 conductive via.

[0133] Specifically, when N=6, the N / 2th metal layer is the third metal layer 313, the N / 2th conductive via is the third conductive via 323, the N / 2+1th metal layer is the fourth via layer 321, and the N / 2-1th conductive via is the second conductive via.

[0134] In one embodiment, both ends of the l-th metal layer of each vertical spiral coil are connected to an l-1-th conductive via, and each of the l-1-th conductive vias is connected to an l-2-th conductive via, wherein l is an integer and N>l>N / 2+1;

[0135] Specifically, when N=6, the lth metal layer is the fifth metal layer 315 , the l-1th conductive via is the fourth conductive via 324 , and the l-2th conductive via is the third conductive via 323 .

[0136] In one embodiment, the top metal layer of each vertical spiral coil is connected to an N-1th layer conductive via, and the N-1th layer conductive via is connected to an N-2th layer conductive via.

[0137] Specifically, when N=6, the top metal layer (the sixth metal layer 316 ) of each of the vertical spiral coils 300 is connected to a fifth-layer conductive via 325 , and the fifth-layer conductive via 325 is connected to a fourth-layer conductive via 324 .

[0138] In the second embodiment, please refer to Figure 3 , the first connection end of each of the inductance units 1000 is respectively connected to the corresponding second tap 340 , and the second connection end of each of the inductance units 1000 is connected to the first tap 330 .

[0139] in, Figure 3 The other parts of the three-dimensional structure diagram of the vertical differential inductor structure shown in Figure 1 The three-dimensional structure of the vertical differential inductor structure shown in Figure 1 To: Figure 3 Please refer to the front cross-sectional diagram of the vertical differential inductor structure in Figure 2 , the present invention will not be described in detail here.

[0140] In the third embodiment, please refer to Figure 4Each of the inductor units 1000 includes two of the vertical spiral coils 300, and the second connection end is connected to the first metal layer of the last vertical spiral coil.

[0141] The second metal layers of the vertical spiral coils 300 of the inductor unit 1000 are electrically connected.

[0142] In this embodiment, the first metal layer is the N / 2th metal layer (the third metal layer 313 ), and the second metal layer is the top metal layer (the sixth metal layer 316 ).

[0143] in, Figure 4 The other parts of the three-dimensional structure diagram of the vertical differential inductor structure shown in Figure 1 The three-dimensional structure of the vertical differential inductor structure shown in Figure 1 To: Figure 4 Please refer to the front cross-sectional diagram of the vertical differential inductor structure in Figure 2 , the present invention will not be described in detail here.

[0144] In the fourth embodiment, please refer to Figure 5 , the inductor unit 1000 includes more than two odd-numbered vertical spiral coils 300 , and the second connection end is connected to the second metal layer of the last vertical spiral coil 300 ;

[0145] The inductor unit 1000 may include two or more even-numbered vertical spiral coils 300 , and the second connection end is connected to the first metal layer of the last vertical spiral coil 300 ;

[0146] The inductor unit 1000 may include more than two vertical spiral coils 300 , and the first vertical spiral coil to the last vertical spiral coil in each inductor unit 1000 are electrically connected in sequence through the first metal layer of each vertical spiral coil 300 and the second metal layer of each vertical spiral coil.

[0147] In this embodiment, the first metal layer is the N / 2th metal layer (the third metal layer 313 ), and the second metal layer is the top metal layer (the sixth metal layer 316 ).

[0148] In this embodiment, the first vertical spiral coil 300 of each inductor unit 1000 is the first vertical spiral coil 300 close to the first tap 330 , and the first vertical spiral coil of each inductor unit 1000 is the vertical spiral coil 300 close to the second tap 340 .

[0149] In this embodiment, Figure 5 The other parts of the three-dimensional structure schematic diagram of the vertical differential inductor structure are similar to Figure 1The three-dimensional structure of the vertical differential inductor structure shown in Figure 1 To: Figure 5 Please refer to the front cross-sectional diagram of the vertical differential inductor structure in Figure 2 , the present invention will not be described in detail here.

[0150] In the fifth embodiment, please refer to Figure 6 The vertical spiral coil 300 includes: the first metal layer, the intermediate connection metal layer and the second metal layer which are electrically connected in sequence through conductive through holes, the first metal layer is the N / 2+1th metal layer among the N metal layers located in and on the interlayer dielectric layer 200, the second metal layer is the bottom metal layer among the N metal layers, and the metal layers are stacked in sequence from bottom to top, N is an integer and N≥2.

[0151] In this embodiment, both ends of the mth metal layer of each vertical spiral coil are connected to the mth conductive via, and each mth conductive via is connected to the m+1th conductive via, where m is an integer and N / 2-1≥m>1.

[0152] Specifically, when N=6, the m-th metal layer is the second metal layer 312 , and the m-th conductive via is the second conductive via 322 .

[0153] In this embodiment, one end of the N / 2 metal layer of each vertical spiral coil is connected to the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2 metal layer is connected to the N / 2+1 conductive via through an N / 2 conductive via.

[0154] Specifically, the N / 2th metal layer is the third metal layer 313 , the N / 2+1th metal layer is the fourth metal layer 314 , the N / 2th conductive via is the third conductive via 323 , and the N / 2+1th conductive via is the fourth conductive via 324 .

[0155] In this embodiment, both ends of the nth metal layer are connected to an n-1th conductive via, and each of the n-1th conductive vias is connected to an n-2th conductive via, where n is an integer and N≥n>N / 2+1.

[0156] Specifically, when N=6, the nth metal layer may include a fifth metal layer 315 and a sixth metal layer 316, both ends of the fifth metal layer 315 are connected to a fourth conductive via 324, and both ends of the sixth metal layer 316 are connected to a fifth conductive via 325. The fourth conductive via 324 is connected to a third conductive via 323, and the fifth conductive via 325 is connected to a fourth conductive via 324.

[0157] In this embodiment, the vertical spiral coil 300 may include six metal layers, the first metal layer is the N / 2+1th metal layer (the fourth metal layer 314 ), and the second metal layer is the bottom metal layer (the first metal layer 311 ).

[0158] In this embodiment, Figure 6 The corresponding three-dimensional structural diagram of the vertical differential inductor structure is as follows: Figure 1 Schematic diagram of the three-dimensional structure, Figure 6 Front section diagram of other parts Figure 2 Similarly, the present invention will not be described in detail here.

[0159] Figure 7-Figure 20 It is a schematic diagram of a vertical differential inductor structure corresponding to each step of a method for preparing a vertical differential inductor structure of the present invention.

[0160] Accordingly, an embodiment of the present invention further provides a method for preparing a vertical differential inductor, which is used to prepare the above Figure 1 The vertical differential inductor structure shown in the embodiment.

[0161] Please refer to Figure 7 , a substrate 100 is provided, and an interlayer dielectric layer 200 is formed on the substrate 100.

[0162] The substrate 100 may be Si or SOI (Silicon On Insulator in English and Silicon On Insulator in Chinese). Of course, it should be understood that the present invention is not limited thereto.

[0163] Furthermore, two inductor units 1000 (eg, Figure 1 As shown), the first tap 330 (as Figure 1 ) and two second taps 340 (as shown Figure 1 shown).

[0164] Each of the inductor units 1000 includes at least one vertical spiral coil, a first connection end and a second connection end. The first connection end of each of the inductor units is connected to the first tap 330, and the second connection end of each of the inductor units 1000 is connected to the corresponding second tap 340.

[0165] For the specific structures of the two inductor units 1000, the first taps 330 and the two second taps 340, please refer to the description in the aforementioned vertical differential inductor structure embodiment, which will not be repeated here. Figures 8 to 20 Each relevant specific step is described in detail.

[0166] First, a first metal layer 311 of each of the vertical spiral coils is formed on the interlayer dielectric layer 200 .

[0167] In this embodiment, the upper surface of the first metal layer 311 is flush with the upper surface of the interlayer dielectric layer 200 .

[0168] The relevant specific steps will be combined Figures 8 to 10 Provide detailed explanation.

[0169] Please refer to Figure 8 A patterned first mask layer 351 is formed on the surface of the interlayer dielectric layer 200 , and the interlayer dielectric layer 200 is etched using the first mask layer 351 to form a first metal layer trench 352 in the interlayer dielectric layer 200 .

[0170] Specifically, the first mask layer 351 may be a photoresist layer. Of course, it should be understood that the first mask layer 351 may also be other mask materials, and the present invention is not limited thereto.

[0171] Please refer to Fig. 9 , remove the first mask layer 351.

[0172] Please refer to Fig.10 , forming a first metal layer 311 in the first metal layer trench.

[0173] In this embodiment, the method of forming the first metal layer may include: depositing a material for forming the first metal layer in the first metal layer groove 352 to form a first metal material layer.

[0174] Furthermore, the first metal material layer is planarized so that the upper surface of the first metal material layer is flush with the upper surface of the interlayer dielectric layer 200 , so as to form the first metal layer 311 .

[0175] The material of the first metal layer 311 includes at least one of Ta, TaN and Cu.

[0176] In this embodiment, the process for planarizing the first metal layer 311 is a chemical mechanical polishing (CMP) process. Of course, the present invention is not limited thereto, and those skilled in the art can select a suitable planarization process as needed.

[0177] Please refer to Fig.11 , a first intermetallic dielectric layer 401 is formed on the interlayer dielectric layer 200 .

[0178] Among them, the first intermetallic dielectric layer 401 can be TEOS (Tetraethyl Orthosilicate) or a low dielectric constant material. Of course, it should be understood that the present invention is not limited to this, and the first intermetallic dielectric layer 401 can be other materials that can suppress the eddy current effect between the metal layers.

[0179] In this embodiment, the dielectric constant of the low dielectric constant material is less than or equal to 15.

[0180] Please refer to Fig.12 , the second metal layer 312 and the first conductive via 321 of each of the vertical spiral coils are formed in the first intermetallic dielectric layer 401 .

[0181] In this embodiment, the specific process of forming the second metal layer 312 and the first conductive via 321 may refer to the aforementioned process of forming the first metal layer 311 , which will not be described in detail in this embodiment.

[0182] Please refer to Fig.13 , a second intermetallic dielectric layer 402 is formed on the first intermetallic dielectric layer 401 .

[0183] The second intermetallic dielectric layer 402 may be TEOS (Tetraethyl Orthosilicate) or a low dielectric constant material. Of course, it should be understood that the present invention is not limited thereto, and the second intermetallic dielectric layer 402 may be other materials capable of suppressing the eddy current effect between metal layers.

[0184] Please refer to Fig.14 The third metal layer 313 , the second conductive via 322 , and the first tap 330 of the first connection end of the two inductor units 1000 are formed in the second intermetallic dielectric layer 402 .

[0185] The upper surface of the third metal layer 313 is flush with the upper surface of the second intermetallic dielectric layer 402 , and the upper surface of the first tap 330 is flush with the upper surface of the second intermetallic dielectric layer 402 .

[0186] In this embodiment, for the specific process of forming the third metal layer 313, the first conductive through hole 322 and the first tap 330 of the vertical spiral coil in the second intermetallic dielectric layer 402, please refer to the aforementioned process of forming the first metal layer 311, which will not be repeated in this embodiment.

[0187] Please refer to Fig.15 , a third intermetallic dielectric layer 403 is formed on the second intermetallic dielectric layer 402 .

[0188] Among them, the third intermetallic dielectric layer 403 can be TEOS (Tetraethyl Orthosilicate) or a low dielectric constant material. Of course, it should be understood that the present invention is not limited to this, and the third intermetallic dielectric layer 403 can be other materials that can suppress the eddy current effect between each metal layer.

[0189] Please refer to Fig.16 , the fourth metal layer 314 and the third conductive via 323 of the vertical spiral coil are formed in the third intermetallic dielectric layer 403 .

[0190] In this embodiment, for the specific process of forming the fourth metal layer 314 of the vertical spiral coil and the third conductive via 323 in the third intermetallic dielectric layer, please refer to the aforementioned process of forming the first metal layer 311, which will not be repeated in this embodiment.

[0191] Please refer to Fig.17 , a fourth intermetallic dielectric layer 404 is formed on the third intermetallic dielectric layer 403 .

[0192] Among them, the fourth intermetallic dielectric layer 404 can be TEOS (Tetraethyl Orthosilicate) or a low dielectric constant material. Of course, it should be understood that the present invention is not limited to this, and the fourth intermetallic dielectric layer 404 can be other materials that can suppress the eddy current effect between each metal layer.

[0193] Please refer to Fig.18 , a fifth metal layer 315 of the vertical spiral coil and a fourth conductive via 324 are formed in the fourth intermetallic dielectric layer 404 .

[0194] In this embodiment, the fifth metal layer 315 and the fourth conductive via 324 of each vertical differential structure are formed in the fourth intermetallic dielectric layer 404. Please refer to the specific process of forming the first metal layer 311, which will not be repeated in this embodiment.

[0195] Please refer to Fig.19 , a fifth intermetallic dielectric layer 405 is formed on the fourth intermetallic dielectric layer 404 .

[0196] Among them, the fifth intermetallic dielectric layer 405 can be TEOS (Tetraethyl Orthosilicate) or a low dielectric constant material. Of course, it should be understood that the present invention is not limited to this, and the fifth intermetallic dielectric layer 405 can be other materials that can suppress the eddy current effect between each metal layer.

[0197] Please refer to Fig. 20 , the sixth metal layer 316 , the fifth conductive via 325 , and the two second taps of the second connection end of each of the vertical spiral coils are formed in the fifth intermetallic dielectric layer 405 .

[0198] In this embodiment, for the specific process of forming the sixth metal layer 316, the fifth conductive via 325 and the two second taps of the second connection end of each vertical spiral coil in the fifth intermetallic dielectric layer 405, please refer to the process of forming the first metal layer 311 mentioned above.

[0199] In some other embodiments, when forming the third metal layer 513, two inductor units (such as Figure 3 The two second taps 340 (as shown in FIG. Figure 3 ); and when forming the sixth metal layer 516, forming a first tap 330 (as shown in FIG. 1 ) of the second connection end of each of the inductor units 1000 in the fifth intermetallic dielectric layer 405. Figure 3 The specific process steps for forming each of the inductor units 10000 are the same as those in this embodiment and will not be described in detail herein.

[0200] In some other embodiments, when the third metal layer 513 is formed, the first tap 340 (eg, Figure 4 As shown) and the two second taps of the second connection end (as shown Figure 4 The specific process steps for forming each of the inductor units are the same as those in this embodiment and will not be described in detail herein.

[0201] Fig.21 It is a schematic diagram of a vertical differential inductor structure corresponding to another method for preparing a vertical differential inductor structure of the present invention.

[0202] Accordingly, an embodiment of the present invention further provides a method for preparing a vertical differential inductor, which is used to prepare the above Figure 1 The vertical differential inductor structure shown in the embodiment.

[0203] In another preparation method, when forming the first metal layer 311, two second taps 330 (such as Figure 1 When the fourth metal layer 314 is formed, a first tap 330 (as shown in FIG. 1 ) connected to the first connection end is formed. Figure 1 shown).

[0204] The present invention provides a vertical differential inductor structure and a preparation method thereof, the structure comprising two inductor units, each of which comprises at least one vertical spiral coil, a first connection end and a second connection end. The vertical spiral coil is formed by stacking metal layers, thereby reducing the area of ​​a single-layer inductor. In addition, the first connection ends of the two inductor units are both connected to a first tap or are respectively connected to two second taps, and the second connection ends of the two inductor units are respectively connected to two second taps or are both connected to the first tap. The two inductor units are symmetrical with respect to the vertical plane where the first tap is located to form a differential inductor structure, thereby improving the quality factor and anti-interference ability of the inductor structure, so that the inductor structure of the present invention has a higher Q value while reducing the chip area occupied.

[0205] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A vertical differential inductor structure, characterized in that: include: A substrate having an interlayer dielectric layer formed thereon; Two inductance units, located in and on the interlayer dielectric layer, each of the inductance units comprising at least one vertical spiral coil, a first connection end and a second connection end; The vertical spiral coil comprises: a first metal layer, an intermediate connection metal layer, and a second metal layer which are electrically connected in sequence through conductive vias, the first metal layer being the N / 2th metal layer or the N / 2+1th metal layer among N metal layers located in and on the interlayer dielectric layer, the second metal layer being the top metal layer or the bottom metal layer among the N metal layers, and the metal layers are stacked in sequence from bottom to top, N being an integer and N≥2; The first connection end is connected to the first metal layer of the first vertical spiral coil of each of the inductor units, and the second connection end is connected to the second metal layer of the last vertical spiral coil of each of the inductor units or the first metal layer of the last vertical spiral coil; a first tap and two second taps, the first connection end of each of the inductance units is connected to the first tap, and the second connection end of each of the inductance units is respectively connected to the corresponding second tap; or, the first connection end of each of the inductance units is respectively connected to the corresponding second tap, and the second connection end of each of the inductance units is connected to the first tap; The second tap is used for inputting a signal, and the first tap is used for outputting a signal; The structures of the two inductance units are symmetrical with respect to the vertical plane where the first tap is located; wherein N is an even number and N≥2.

2. The vertical differential inductor structure according to claim 1, wherein: The inductor unit includes a vertical spiral coil, and the second connecting end is connected to the second metal layer of the corresponding vertical spiral coil.

3. The vertical differential inductor structure according to claim 1, wherein: The inductor unit comprises two vertical spiral coils, and the second connecting end is connected to the first metal layer of the last vertical spiral coil; The second metal layers of the vertical spiral coils of the inductor unit are electrically connected.

4. The vertical differential inductor structure according to claim 1, wherein: The inductor unit includes two or more odd-numbered vertical spiral coils, and the second connection end is connected to the second metal layer of the last vertical spiral coil; The inductor unit includes two or more even-numbered vertical spiral coils, and the second connecting end is connected to the first metal layer of the last vertical spiral coil; The inductor unit includes more than two vertical spiral coils, and the first vertical spiral coil to the last vertical spiral coil in each inductor unit are electrically connected in sequence through the first metal layer of each vertical spiral coil and the second metal layer of each vertical spiral coil.

5. The vertical differential inductor structure according to claim 1, wherein: The bottom metal layer of the vertical spiral coil is located in the interlayer dielectric layer; The vertical differential inductor structure also includes a metal interlayer dielectric layer; The top metal layer, the first metal layer and the middle connection metal layer of each of the vertical spiral coils are all located in the intermetallic dielectric layer; The i-th metal layer of the vertical spiral coil is located in the i-1-th intermetallic dielectric layer; The i-1th conductive through hole of the vertical spiral coil is located in the i-1th intermetallic dielectric layer; The (i-1)th intermetallic dielectric layer is located on the (i-2)th intermetallic dielectric layer, wherein i is an integer and N≥i≥2.

6. The vertical differential inductor structure according to claim 1, wherein: The first metal layer and the second metal layer of each of the vertical spiral coils are the N / 2th metal layer and the top metal layer respectively; Both ends of the k-th metal layer of the vertical spiral coil are connected to a k-th conductive via, and each of the k-th conductive vias is connected to a k+1-th conductive via, wherein k is an integer and N / 2>k≥1; One end of the N / 2 metal layer of the vertical spiral coil is connected to one end of the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2+1 metal layer is connected to the N / 2-1 conductive via through an N / 2 conductive via; Both ends of the l-th metal layer of the vertical spiral coil are connected to an l-1-th conductive via, and each of the l-1-th conductive vias is connected to an l-2-th conductive via, wherein l is an integer and N>l>N / 2+1; The top metal layer of the vertical spiral coil is connected to an N-1th layer conductive via, and each of the N-1th layer conductive vias is connected to an N-2th layer conductive via.

7. The vertical differential inductor structure according to claim 1, wherein: The first metal layer and the second metal layer of each of the vertical spiral coils are the N / 2+1th metal layer and the bottom metal layer respectively; The bottom metal layer of the vertical spiral coil is connected to a first-layer conductive via, and the first-layer conductive via is connected to a second-layer conductive via; Both ends of the m-th metal layer of the vertical spiral coil are connected to the m-th conductive vias, and each of the m-th conductive vias is connected to the m+1-th conductive via, wherein m is an integer and N / 2-1≥m>1; One end of the N / 2 metal layer of the vertical spiral coil is connected to the corresponding N / 2+1 metal layer through an N / 2 conductive via, and the other end of the N / 2 metal layer is connected to the N / 2+1 conductive via through an N / 2 conductive via; Both ends of the nth metal layer are connected to an n-1th conductive via, and each of the n-1th conductive vias is connected to an n-2th conductive via, wherein n is an integer and N≥n>N / 2+1.

8. The vertical differential inductor structure according to claim 1, wherein: The thickness range of each metal layer in the N metal layers is The spacing between the N metal layers ranges from 140um to 1400um.

9. The vertical differential inductor structure according to claim 1, wherein: The height range of each of the conductive vias is The minimum diameter of each of the conductive through holes is in the range of 0.12 um to 0.16 um.

10. A method for preparing a vertical differential inductor structure, characterized in that: For preparing the vertical differential inductor structure according to any one of claims 1 to 9, the method comprises: Providing a substrate, wherein an interlayer dielectric layer is filled on the substrate; forming two inductor units, a first tap and two second taps in and on the interlayer dielectric layer; Wherein, each of the inductance units includes at least one vertical spiral coil, a first connection end and a second connection end, the first connection end of each of the inductance units is connected to the first tap, and the second connection end of each of the inductance units is respectively connected to the corresponding second taps; or, the first connection end of each of the inductance units is respectively connected to the corresponding second taps, and the second connection end of each of the inductance units is connected to the first tap.

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