Display device

Abstract

A display device capable of minimizing restrictions on selection of a material used in a bonding layer includes: a substrate; a transistor disposed on the substrate; a planarization layer disposed on the transistor; a first electrode disposed on the planarization layer to be connected to the transistor; an intermediate layer disposed on the first electrode; a second electrode disposed on the intermediate layer; a reflective layer disposed in the trench of the planarization layer and separated from the first electrode; and a bonding layer disposed between an inner wall of the trench and the reflective layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0142575, filed on October 24, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device capable of minimizing restrictions on selection of a material used in a bonding layer. Background Art

[0004] A head mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet so as to form a focal point at a distance close to the user's eyes. For example, a head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0005] A head-mounted display magnifies and displays an image displayed by a small display device by using a plurality of lenses. Therefore, a display device applied to a head-mounted display needs to provide a high-resolution image (e.g., an image with a resolution of 3000 pixels per inch (PPI) or more). For this reason, an organic light-emitting diode on silicon (OLEDoS) having a small-sized organic light-emitting display device with high resolution is being used as a display device applied to a head-mounted display. OLEDoS is a device that displays an image by disposing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the invention

[0006] Aspects of the present invention provide a display device capable of minimizing restrictions on selection of a material used in a bonding layer.

[0007] According to an embodiment, a display device includes: a substrate; a transistor on the substrate; a planarization layer on the transistor; a first electrode disposed on the planarization layer to be connected to the transistor; an intermediate layer on the first electrode; a second electrode disposed on the intermediate layer; a reflective layer disposed in a groove of the planarization layer and separated from the first electrode; and a bonding layer disposed between an inner wall of the groove and the reflective layer.

[0008] In an embodiment, the reflective layer is a floating electrode.

[0009] In an embodiment, the reflective layer does not overlap the transistor.

[0010] In an embodiment, the display device further comprises: a connecting electrode connecting the transistor and the first electrode.

[0011] In an embodiment, the reflective layer and the connecting electrode do not overlap each other.

[0012] In an embodiment, the bonding layer is in contact with the reflective layer.

[0013] In an embodiment, the bonding layer includes at least one of an organic layer and an inorganic layer including a titanium oxide layer, a titanium nitride layer, and an indium tin oxide (ITO) layer.

[0014] In an embodiment, the display device further comprises: an insulating layer disposed between the reflective layer and the first electrode.

[0015] In an embodiment, the insulating layer includes: a first insulating layer disposed on the reflective layer; and a second insulating layer disposed on the first insulating layer.

[0016] In an embodiment, the first electrode is connected to the connection electrode through a contact hole formed in the second insulating layer, the first insulating layer, and the planarization layer.

[0017] In an embodiment, the connection electrode is connected to one of a source region and a drain region of the transistor.

[0018] In an embodiment, the planarization layer includes SiO x .

[0019] In an embodiment, the first insulating layer includes SiN x .

[0020] In an embodiment, the second insulating layer includes SiO x .

[0021] In an embodiment, an area of ​​the first electrode is larger than an area of ​​the reflective layer.

[0022] In an embodiment, in a plan view, an edge of the reflective layer is surrounded by an edge of the first electrode.

[0023] In an embodiment, the first electrode is directly connected to the connecting electrode.

[0024] In an embodiment, the first electrode is in direct contact with the connecting electrode.

[0025] In an embodiment, the reflective layer comprises Ag.

[0026] In an embodiment, the display device further includes: a constant voltage line connected to the reflective layer and transmitting a constant voltage.

[0027] In an embodiment, the constant voltage line is disposed between the substrate and the reflective layer.

[0028] In the display device according to the embodiment, restrictions on selection of a material used in the bonding layer can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0030] Figure 1 is an exploded perspective view illustrating a display device according to an embodiment;

[0031] Figure 2 is a diagram illustrating Figure 1 An example layout diagram of a display panel shown in FIG.

[0032] Figure 3 is a block diagram illustrating a display device according to an embodiment;

[0033] Figure 4 is an equivalent circuit diagram illustrating a first pixel according to an embodiment;

[0034] Figure 5 is a plan view illustrating a display device according to an embodiment;

[0035] Figure 6 is a diagram illustrating a method according to an embodiment Figure 5 A cross-sectional view of the display device taken along line II';

[0036] Figure 7 is a diagram illustrating a method according to another embodiment Figure 5 A cross-sectional view of the display device taken along line II';

[0037] Figure 8 is a perspective view illustrating a head mounted display device according to an embodiment;

[0038] Fig. 9 is a diagram illustrating Figure 8 an exploded perspective view of an example of a head mounted display device; and

[0039] Fig.10 is a perspective view illustrating a head-mounted display device according to an embodiment. DETAILED DESCRIPTION

[0040] Hereinafter, the present invention will now be more fully described with reference to the accompanying drawings in which embodiments of the present invention are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art.

[0041] It will be understood that when a layer is referred to as being disposed "on," "connected to," or "coupled to" another element, layer, or substrate, it may be directly on that other element, layer, or substrate, or there may be intervening layers. Throughout the specification, like reference numerals refer to like components. In the drawings, the thickness of layers and regions are exaggerated for clarity. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0042] Although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teaching of one or more embodiments. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish the categories or groups of different elements. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0043] Unless otherwise specified, the illustrated embodiments should be understood as providing features of details of variations that can implement some of the disclosed methods in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0044] The features of various embodiments of the present invention may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Various embodiments may be practiced individually or in combination.

[0045] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0046] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0047] In addition, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and thus the first direction DR1, the second direction DR2, and the third direction DR3 may be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0048] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as, for example, XYZ, XY, YZ, or XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another (or other) element(s) as illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can include both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0050] The term used herein is for the purpose of describing a particular embodiment, and is not intended to be limited. As used herein, unless the context clearly indicates otherwise, the singular "one" and "the (described)" are intended to also include plural forms. Moreover, when used in this specification, the term "includes", "comprising" and / or its variations indicate the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but does not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It is also noted that, as used in this article, the term "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, and are so used to explain the measured values, calculated values ​​and / or the inherent deviations of the values ​​that will be recognized by those of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations, which are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specific illustrations of the regions, but rather include shape deviations caused by, for example, manufacturing. In this way, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not intended to be limiting as such.

[0052] According to the practice of the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, parts / or modules. It will be understood by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, parts and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, each block, unit, part and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units, parts and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules without departing from the scope of the invention.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an ideal or overly formal sense unless explicitly defined as such in this article.

[0054] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is an exploded perspective view of a display device according to an embodiment. Figure 2 is a diagram illustrating a method according to an embodiment Figure 1Layout diagram of an example of a display panel is shown in FIG. Figure 3 is a block diagram illustrating a display device according to an embodiment.

[0056] Reference Figure 1 and Figure 2 , the display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic diaries, electronic books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In addition, the display device 10 can be applied to smart watches, watch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0057] In an embodiment, the display device 10 includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0058] In an embodiment, the display panel 100 may be formed in a planar shape similar to a rectangular shape. For example, the display panel 100 may have a planar shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel 100 may be formed to be similar to other polygonal shapes, circular shapes, or elliptical shapes, without being limited to a rectangular shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the present invention is not limited thereto.

[0059] In an embodiment, Figure 2 As shown in FIG. 1 , the display panel 100 includes a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0060] In an embodiment, the display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines ECL, and a plurality of data lines DL.

[0061] In an embodiment, each of the plurality of pixels PX includes a light emitting element for emitting light. The plurality of pixels PX1, PX2, and PX3 may be arranged in a matrix in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines ECL may extend in the first direction DR1 and may be arranged in the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0062] In an embodiment, the plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines ECL include a plurality of first emission control lines ECL1 and a plurality of second emission control lines ECL2.

[0063] In an embodiment, the plurality of unit pixels UPX include a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 may include Figure 4 The plurality of pixel transistors shown in the figure may be formed by a semiconductor process and may be disposed on a semiconductor substrate. For example, the plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0064] In an embodiment, each of the plurality of pixels PX1, PX2, and PX3 may be connected to a corresponding one of the plurality of write scan lines GWL, a corresponding one of the plurality of control scan lines GCL, a corresponding one of the plurality of bias scan lines EBL, a corresponding one of the plurality of first emission control lines ECL1, a corresponding one of the plurality of second emission control lines ECL2, and a corresponding one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may allow the light emitting element to emit light according to the data voltage.

[0065] In an embodiment, the non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0066] In an embodiment, the scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 The scan driver 610 is shown disposed at the left side of the display area DAA and the emission driver 620 is disposed at the right side of the display area DAA, but the present invention is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed at both the left and right sides of the display area DAA.

[0067] In an embodiment, the scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate. For example, the plurality of scan transistors and the plurality of light emitting transistors may be formed by CMOS.

[0068] In an embodiment, the scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0069] In an embodiment, the emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line ECL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line ECL2.

[0070] In an embodiment, the data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate. For example, the plurality of data transistors may be formed by CMOS.

[0071] In an embodiment, the data driver 700 may receive digital video data DATA1 and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA1 into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, a plurality of pixels PX1, PX2, and PX3 may be selected by a write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixel among the plurality of pixels PX1, PX2, and PX3.

[0072] In an embodiment, the pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer and the polarizing plate.

[0073] In an embodiment, the heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface, for example, a rear surface, of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0074] In an embodiment, the circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1 The circuit board 300 is shown unfolded, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be opposite to the other end of the circuit board 300 connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member.

[0075] In an embodiment, the timing control circuit 400 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS intended for controlling the display panel 100 according to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA1 and the data timing control signal DCS to the data driver 700.

[0076] In an embodiment, the power supply circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. Figure 4 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0077] In an embodiment, each of the timing control circuit 400 and the power supply circuit 500 may be formed of an integrated circuit (IC) and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA1, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0078] Figure 4 is an equivalent circuit diagram illustrating a first pixel according to an embodiment.

[0079] In the examples and with reference to Figure 4 , the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line ECL1, the second emission control line ECL2, and the data line DL. In addition, the first pixel PX1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be a voltage lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0080] In an embodiment, the first pixel PX1 includes a plurality of transistors T1 to T6 , a light emitting element ED, a first capacitor C1 , and a second capacitor C2 .

[0081] In an embodiment, the light emitting element ED emits light according to the driving current Ids (or referred to as "source drain current") flowing through the channel of the first transistor T1. The amount of light emitted from the light emitting element ED may be proportional to the driving current Ids. The light emitting element ED may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element ED may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode (or a pixel electrode), and the second electrode of the light emitting element ED may be a cathode electrode (or a common electrode). The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the present invention is not limited thereto. For example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light emitting element ED may be a micro light emitting diode.

[0082] In an embodiment, the first transistor T1 may be a driving transistor for controlling a source-drain current Ids flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0083] In an embodiment, the second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 may be turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor C1 to the data line DL. As a result, the data voltage of the data line DL may be applied to the one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor C1.

[0084] In an embodiment, the third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Since the gate electrode and the drain electrode of the first transistor T1 are connected to each other, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0085] In an embodiment, the fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line ECL1 to connect the second node N2 to the third node N3. Therefore, the driving current Ids of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line ECL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0086] In an embodiment, the fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. As a result, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0087] In an embodiment, the sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line ECL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. As a result, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line ECL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0088] In an embodiment, the first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes the one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0089] In an embodiment, the second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0090] In the embodiment, the first node N1 is a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1 and the one electrode of the second capacitor C2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3 and the source electrode of the fourth transistor T4. The third node N3 is a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5 and the first electrode of the light emitting element ED.

[0091] In an embodiment, each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the present invention is not limited thereto. Each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. In another embodiment, each of some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and each of the other transistors may be an N-type MOSFET.

[0092] In the embodiment, although Figure 4 The first pixel PX1 is shown to include six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 4 The quantity shown in .

[0093] In addition, in the embodiment, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 may be the same as that of the reference Figure 4 The equivalent circuit diagram of the first pixel PX1 described above is substantially the same. Therefore, descriptions of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 will be omitted herein.

[0094] Figure 5 is a plan view illustrating a display device according to an embodiment.

[0095] In the embodiments and as Figure 5 As shown in FIG. 1 , the display device 10 may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may form a unit pixel UPX. In other words, the unit pixel UPX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3 disposed adjacent to each other.

[0096] In an embodiment, the first pixel PX1 to the third pixel PX3 of the unit pixel UPX may be pixels for providing light of different colors (or wavelengths). For example, the first pixel PX1 may provide light of a first color, the second pixel PX2 may provide light of a second color, and the third pixel PX3 may provide light of a third color. The first color may be any one of red, green, and blue, the second color may be any one of the above-mentioned red, green, and blue that is different from the first color, and the third color may be any one of the above-mentioned red, green, and blue that is different from the first color and the second color.

[0097] In an embodiment, the first pixel PX1 may include a first anode electrode AND1 and a first reflective layer RE1, the second pixel PX2 may include a second anode electrode AND2 and a second reflective layer RE2, and the third pixel PX3 may include a third anode electrode AND3 and a third reflective layer RE3.

[0098] In an embodiment, the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 may be disposed adjacent to each other. For example, the first anode electrode AND1 and the second anode electrode AND2 may be disposed adjacent to each other in the first direction DR1, the second anode electrode AND2 and the third anode electrode AND3 may be disposed adjacent to each other in the second direction DR2, and the third anode electrode AND3 and the first anode electrode AND1 may be disposed adjacent to each other in the second direction DR2.

[0099] In an embodiment, the first to third anode electrodes AND1 to AND3 may have different sizes. For example, the area of ​​the third anode electrode AND3 may be greater than the area of ​​the first anode electrode AND1 or the area of ​​the second anode electrode AND2. In another embodiment, the area of ​​the third anode electrode AND3 may be greater than the sum of the area of ​​the first anode electrode AND1 and the area of ​​the second anode electrode AND2. The third pixel PX3 including the third anode electrode AND3 may provide blue light, the first pixel PX1 including the first anode electrode AND1 may provide red light, and the second pixel PX2 including the second anode electrode AND2 may provide green light. As described above, when the third pixel PX3 provides blue light, the first pixel PX1 provides red light, and the second pixel PX2 provides green light, the area of ​​the second anode electrode AND2 may be greater than the area of ​​the first anode electrode AND1 and smaller than the area of ​​the third anode electrode AND3.

[0100] In an embodiment, a portion of the first anode electrode AND1 (e.g., an edge of the first anode electrode AND1), a portion of the second anode electrode AND2 (e.g., an edge of the second anode electrode AND2), and a portion of the third anode electrode AND3 (e.g., an edge of the third anode electrode AND3) may be formed by a pixel defining layer ( Figure 6 In other words, a portion of the first anode electrode AND1 (e.g., an edge of the first anode electrode AND1), a portion of the second anode electrode AND2 (e.g., an edge of the second anode electrode AND2), and a portion of the third anode electrode AND3 (e.g., an edge of the third anode electrode AND3) may partially overlap with the pixel defining layer PDL defining each of the emission areas EA1 to EA3 of the pixels PX1 to PX3.

[0101] In an embodiment, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be defined by areas of the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 that are exposed and not covered by the pixel defining layer PDL, respectively. In an embodiment, the first light emitting area EA1 may be a light emitting area of ​​a first pixel PX1 including the first anode electrode AND1, the second light emitting area EA2 may be a light emitting area of ​​a second pixel PX2 including the second anode electrode AND2, and the third light emitting area EA3 may be a light emitting area of ​​a third pixel PX3 including the third anode electrode AND3.

[0102] In an embodiment, the first anode electrode AND1 may be formed by a planarization layer ( Figure 6 The first contact hole CT1 of the planarization layer VA) is connected to the first connection electrode CE1 of the first pixel PX1, the second anode electrode AND2 may be connected to the second connection electrode CE2 of the second pixel PX2 through the second contact hole CT2 of the planarization layer VA, and the third anode electrode AND3 may be connected to the third connection electrode CE3 of the third pixel PX3 through the third contact hole CT3 of the planarization layer VA. In an embodiment, the first anode electrode AND1 may be directly connected to the first connection electrode CE1, the second anode electrode AND2 may be directly connected to the second connection electrode CE2, and the third anode electrode AND3 may be directly connected to the third connection electrode CE3. In other words, the first anode electrode AND1 may be in direct contact with the first connection electrode CE1, the second anode electrode AND2 may be in direct contact with the second connection electrode CE2, and the third anode electrode AND3 may be in direct contact with the third connection electrode CE3.

[0103] In an embodiment, the first reflective layer RE1, the second reflective layer RE2, and the third reflective layer RE3 may be disposed adjacent to each other. For example, in one embodiment, the first reflective layer RE1 and the second reflective layer RE2 may be disposed adjacent to each other in the first direction DR1, the second reflective layer RE2 and the third reflective layer RE3 may be disposed adjacent to each other in the second direction DR2, and the third reflective layer RE3 and the first reflective layer RE1 may be disposed adjacent to each other in the second direction DR2.

[0104] In an embodiment, the first to third reflective layers RE1 to RE3 may have different sizes. For example, the area of ​​the third reflective layer RE3 may be greater than the area of ​​the first reflective layer RE1 or the area of ​​the second reflective layer RE2. In another embodiment, the area of ​​the third reflective layer RE3 may be greater than the sum of the area of ​​the first reflective layer RE1 and the area of ​​the second reflective layer RE2.

[0105] In an embodiment, a portion of the first reflective layer RE1 (e.g., an edge of the first reflective layer RE1), a portion of the second reflective layer RE2 (e.g., an edge of the second reflective layer RE2), and a portion of the third reflective layer RE3 (e.g., an edge of the third reflective layer RE3) may be covered by the pixel defining layer PDL. In other words, a portion of the first reflective layer RE1 (e.g., an edge of the first reflective layer RE1), a portion of the second reflective layer RE2 (e.g., an edge of the second reflective layer RE2), and a portion of the third reflective layer RE3 (e.g., an edge of the third reflective layer RE3) may overlap with a portion of the pixel defining layer PDL defining the light emitting areas EA1 to EA3 of the respective pixels PX1 to PX3.

[0106] In an embodiment, the first reflective layer RE1, the second reflective layer RE2, and the third reflective layer RE3 may be floating electrodes. For example, the first reflective layer RE1, the second reflective layer RE2, and the third reflective layer RE3 may be electrodes that are not directly connected to any conductive layer and have a floating state.

[0107] In an embodiment, the first reflective layer RE1 may overlap the first anode electrode AND1. In a plan view, the area of ​​the first reflective layer RE1 may be smaller than the area of ​​the first anode electrode AND1. In a plan view, the edge of the first reflective layer RE1 may be surrounded by the edge of the first anode electrode AND1. In other words, in a plan view, the first reflective layer RE1 may be completely covered by the first anode electrode AND1.

[0108] In an embodiment, the second reflective layer RE2 may overlap with the second anode electrode AND2. In a plan view, the area of ​​the second reflective layer RE2 may be smaller than the area of ​​the second anode electrode AND2. In a plan view, the edge of the second reflective layer RE2 may be surrounded by the edge of the second anode electrode AND2. In other words, in a plan view, the second reflective layer RE2 may be completely covered by the second anode electrode AND2.

[0109] In an embodiment, the third reflective layer RE3 may overlap with the third anode electrode AND3. In a plan view, the area of ​​the third reflective layer RE3 may be smaller than the area of ​​the third anode electrode AND3. In a plan view, the edge of the third reflective layer RE3 may be surrounded by the edge of the third anode electrode AND3. In other words, in a plan view, the third reflective layer RE3 may be completely covered by the third anode electrode AND3.

[0110] In an embodiment, the reflective layer and the anode electrode of the same pixel are physically and / or electrically separated from each other. For example, the first reflective layer RE1 and the first anode electrode AND1 of the first pixel PX1 are separated from each other, and the second reflective layer RE2 and the second anode electrode AND2 of the second pixel PX2 are separated from each other, and the third reflective layer RE3 and the third anode electrode AND3 of the third pixel PX3 are separated from each other. In other words, the first anode electrode AND1 can be directly connected to the first connection electrode CE1 without passing through the first reflective layer RE1, the second anode electrode AND2 can be directly connected to the second connection electrode CE2 without passing through the second reflective layer RE2, and the third anode electrode AND3 can be directly connected to the third connection electrode CE3 without passing through the third reflective layer RE3.

[0111] Figure 6 is a diagram illustrating a method according to an embodiment of the present invention. Figure 5 A cross-sectional view of the display device taken along line II'.

[0112] In the embodiments and as Figure 6 and Figure 5 As shown in the figure, the display device 10 may include a substrate SUB, a transistor TR, an interlayer insulating layer ILD, a planarization layer VA, a first connection electrode CE1, a first reflective layer RE1, a first insulating layer INS1, a second insulating layer INS2, a first anode electrode AND1, a pixel defining layer PDL, an intermediate layer IL, a cathode electrode CAT, an encapsulation layer ENC, an adhesive layer ADL, a first color filter CF1, a second color filter CF2, a third color filter CF3 and a plurality of lenses LNS.

[0113] In an embodiment, the substrate SUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The substrate SUB may be a substrate doped with first type impurities.

[0114] In an embodiment, the well region W may be disposed on the substrate SUB (or inside the substrate SUB). The well region W may be a region doped with second type impurities. The second type impurities may be different from the first type impurities. In an embodiment, when the first type impurities are P type impurities, the second type impurities may be N type impurities. When the first type impurities are N type impurities, the second type impurities may be P type impurities.

[0115] In an embodiment, the source region S, drain region D, and channel region CH of the transistor TR may be disposed in the well region W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be disposed in the well region W. Each of the source region S and the drain region D may be a region doped with a first type of impurity. The gate electrode G of the transistor TR may overlap the well region W while crossing the well region W. When viewed in a plan view, the well region W crossing the gate electrode G may be defined as two regions, the source region S may be disposed in any one of the two regions, and the drain region D may be disposed in the other region. In other words, in the well region W, the source region S and the drain region D may be disposed at both sides of the gate electrode G, and the gate electrode G is interposed therebetween. The channel region CH of the transistor TR may be disposed in a region of the well region W that overlaps with the gate electrode G. Figure 6 The transistor TR shown in FIG. 1 may be, for example, Figure 4 The fourth transistor T4.

[0116] In an embodiment, the source region S may include a first lightly doped impurity region having an impurity concentration relatively lower than that of other portions of the source region S. In other words, a portion of the source region S may include impurities having a concentration lower than that of other portions of the source region S. The drain region D may include a second lightly doped impurity region having an impurity concentration relatively lower than that of other portions of the drain region D. In other words, a portion of the drain region D may include impurities having a concentration lower than that of other portions of the drain region D.

[0117] In an embodiment, the first lightly doped impurity region and the second lightly doped impurity region may be disposed adjacent to the channel region CH of the transistor TR. For example, the first lightly doped impurity region may be disposed adjacent to the channel region CH, thereby overlapping with a first sidewall of the gate electrode G disposed at one side of the gate electrode G, and the second lightly doped impurity region may be disposed adjacent to the channel region CH, thereby overlapping with a second sidewall of the gate electrode G disposed at the other side of the gate electrode G. As described above, the distance between the heavily doped impurity region of the source region S and the heavily doped impurity region of the drain region D may be increased by the first lightly doped impurity region and the second lightly doped impurity region. Since the distance is increased, the length of the channel region CH may be increased. Therefore, punch-through and hot carrier phenomena due to a short channel may be avoided.

[0118] In an embodiment, the source region S of each transistor TR may be connected to the anode electrode of the corresponding light emitting element through the metal layer ME. In an embodiment, the source region S of the transistor TR of the first pixel PX1 may be connected to the first anode electrode AND1 through the metal layer ME of the first pixel PX1, the source region S of the transistor TR of the second pixel PX2 may be connected to the second anode electrode AND2 through the metal layer ME of the second pixel PX2, and the source region S of the transistor TR of the third pixel PX3 may be connected to the third anode electrode AND3 through the metal layer ME of the third pixel PX3.

[0119] In an embodiment, an interlayer insulating layer ILD may be disposed on the substrate SUB. The interlayer insulating layer ILD may include a plurality of insulating layers stacked along the third direction DR3.

[0120] In an embodiment, the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 may be disposed on the interlayer insulating layer ILD. Each of the connection electrodes CE1 to CE3 may be connected to the metal layer ME through a contact hole penetrating the interlayer insulating layer ILD. In other words, each of the connection electrodes CE1 to CE3 may be connected to the source region S of the corresponding transistor TR through the above-mentioned metal layer ME and the contact hole. In an embodiment, each of the connection electrodes CE1 to CE3 may be connected to the drain region D of the transistor TR.

[0121] In an embodiment, a planarization layer VA may be disposed on the first connection electrode CE1, the second connection electrode CE2, the third connection electrode CE3, and the interlayer insulating layer ILD. For example, the planarization layer VA may be disposed between the substrate SUB and each of the reflective layers RE1 to RE3. Specifically, the planarization layer VA may be disposed between the interlayer insulating layer ILD and each of the reflective layers RE1 to RE3. In an embodiment, the planarization layer VA may include a groove TRC. In an embodiment, the groove TRC may be formed on the upper surface of the planarization layer VA to be disposed between the planarization layer VA and the first insulating layer INS1. In other words, a portion of the upper surface of the planarization layer VA may have a groove that is concavely recessed in a direction opposite to the third direction DR3, and the groove may be defined as the groove TRC of the planarization layer VA. The planarization layer VA may include SiO x .

[0122] In an embodiment, the reflective layer may be disposed inside the groove TRC of the planarization layer VA. For example, the first reflective layer RE1 may be disposed inside the groove TRC of the first pixel PX1, the second reflective layer RE2 may be disposed inside the groove TRC of the second pixel PX2, and the third reflective layer RE3 may be disposed inside the groove TRC of the third pixel PX3.

[0123] In an embodiment, the reflective layer may not overlap with the connection electrode of the pixel on which the reflective layer is disposed. In an embodiment, the first reflective layer RE1 of the first pixel PX1 may not overlap with the first connection electrode CE1 of the first pixel PX1 in the third direction DR3, the second reflective layer RE2 of the second pixel PX2 may not overlap with the second connection electrode CE2 of the second pixel PX2 in the third direction DR3, and the third reflective layer RE3 of the third pixel PX3 may not overlap with the third connection electrode CE3 of the third pixel PX3 in the third direction DR3.

[0124] In an embodiment, the reflective layer may not overlap with the transistor TR of the pixel on which the reflective layer is disposed. For example, the first reflective layer RE1 of the first pixel PX1 may not overlap with the transistor TR of the first pixel PX1 in the third direction DR3, the second reflective layer RE2 of the second pixel PX2 may not overlap with the transistor TR of the second pixel PX2 in the third direction DR3, and the third reflective layer RE3 of the third pixel PX3 may not overlap with the transistor TR of the third pixel PX3 in the third direction DR3.

[0125] In an embodiment, the first to third reflective layers RE1 to RE3 may each be a metal layer including a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or an alloy thereof. In an embodiment, each of the first to third reflective layers RE1 to RE3 may further include a metal oxide layer (e.g., a transparent conductive oxide layer) located above and / or below the above-mentioned metal layer. For example, each of the first to third reflective layers RE1 to RE3 may have a double-layer structure of ITO / Ag, Ag / ITO, ITO / Mg, Mg / ITO, or a triple-layer structure such as ITO / Ag / ITO.

[0126] In an embodiment, the bonding layer BL may be disposed along the inner wall of the groove TRC. In an embodiment, the bonding layer BL may be disposed between the inner wall of the groove TRC and the first reflective layer RE1. The bonding layer BL may contact the first reflective layer RE1 and the inner wall of the groove TRC. The bonding layer BL may improve the bonding strength between the first reflective layer RE1 and the planarization layer VA. The bonding layer BL may also be disposed between the inner wall of the groove of the second pixel PX2 and the second reflective layer RE2, and may also be disposed between the inner wall of the groove of the third pixel PX3 and the third reflective layer RE3. At the same time, the bonding layer BL is disposed to be separated from the first anode electrode AND1 to the third anode electrode AND3.

[0127] According to an embodiment, the first to third reflective layers RE1 to RE3 do not perform a function for electrically connecting the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3 and the first to third connection electrodes CE1 to CE3, respectively. For example, the first to third reflective layers RE1 to RE3 of one embodiment perform a reflection function, but do not perform a function of transmitting a signal (e.g., a data voltage) to the electrodes of the first to third anode electrodes AND1 to AND3. Accordingly, there is no need to consider the electrical characteristics of the bonding layer BL in contact with the first to third reflective layers RE1 to RE3. In other words, in a structure in which the reflective layer is connected to the anode electrode, in order to minimize the contact resistance between the reflective layer and the anode electrode, a bonding layer must be provided between the reflective layer and the anode electrode, and therefore, there is a limitation that the bonding layer must be limitedly selected from a material having both excellent conductivity and excellent adhesion.

[0128] However, according to an embodiment, although each of the first to third reflective layers RE1 to RE3 performs a reflective function, it does not play a role in transmitting signals from the first to third connection electrodes CE1 to CE3 to the electrodes of the first, second, and third reflective layers RE1, RE2, and RE3, respectively, and therefore, the bonding layer BL may be selected from various materials capable of maintaining adhesion between the reflective layer and the planarization layer VA. In other words, according to the display device 10 of one embodiment, it is possible to minimize restrictions on the selection of materials for forming the bonding layer BL. For example, in addition to a conductive material (e.g., a metal material), the bonding layer BL according to an embodiment may be formed of a non-conductive material. In an embodiment, the bonding layer BL may be formed of a material including titanium oxide (TiO x ) or titanium nitride (TiN x ) material. In addition, in an embodiment, the bonding layer BL may be formed as a double layer including an indium tin oxide (ITO) layer and a metal layer. Moreover, in an embodiment, the bonding layer BL may be formed of a material including an inorganic material or an organic material. In an embodiment, the bonding layer BL may include at least one of an organic layer and an inorganic layer including a titanium oxide layer, a titanium nitride layer, and an ITO layer. The above-mentioned organic layer and the inorganic layer including the titanium oxide layer, the titanium nitride layer, and the ITO layer may have excellent adhesion. Accordingly, the first to third reflective layers RE1 to RE3 are able to perform a reflective function and are well adhered to the planarization layer VA through the bonding layer BL.

[0129] In an embodiment, the first insulating layer INS1 may be disposed on the first reflective layer RE1, the second reflective layer RE2, the third reflective layer RE3, and the planarization layer VA. For example, the first insulating layer INS1 may be disposed between each reflective layer and each of the anode electrodes AND1 to AND3. The first insulating layer INS1 may include SiNx .

[0130] In an embodiment, the second insulating layer INS2 may be disposed on the first insulating layer INS1. For example, the second insulating layer INS2 may be disposed between the first insulating layer INS1 and each of the anode electrodes AND1 to AND3. The second insulating layer INS2 may include SiO x .

[0131] In an embodiment, the first light emitting element ED1 of the first pixel PX1 , the second light emitting element of the second pixel PX2 , and the third light emitting element of the third pixel PX3 may be disposed on the second insulating layer INS2 and the planarization layer VA.

[0132] In an embodiment, the first light emitting element ED1 may include a first anode electrode AND1 , an intermediate layer IL, and a cathode electrode CAT.

[0133] In an embodiment, the first anode electrode AND1 may be disposed on the second insulating layer INS2 and the planarization layer VA. The first anode electrode AND1 may be connected to the first connection electrode CE1 through a first contact hole CT1 penetrating the second insulating layer INS2, the first insulating layer INS1, and the planarization layer VA. Accordingly, the first anode electrode AND1 may be connected to the source region S of the transistor TR provided in the first pixel PX1.

[0134] In an embodiment, the second anode electrode AND2 may be disposed on the second insulating layer INS2 and the planarization layer VA. The second anode electrode AND2 may be connected to the second connection electrode CE2 through a second contact hole CT2 penetrating the second insulating layer INS2, the first insulating layer INS1, and the planarization layer VA. Accordingly, the second anode electrode AND2 may be connected to a source region of a transistor provided in the second pixel PX2.

[0135] In an embodiment, the third anode electrode AND3 may be disposed on the second insulating layer INS2 and the planarization layer VA. The third anode electrode AND3 may be connected to the third connection electrode CE3 through a third contact hole CT3 penetrating the second insulating layer INS2, the first insulating layer INS1, and the planarization layer VA. Accordingly, the third anode electrode AND3 may be connected to a source region of a transistor provided in the third pixel PX3.

[0136] In an embodiment, each of the first to third anode electrodes AND1 to AND3 may include a transparent conductive material. For example, each of the first to third anode electrodes AND1 to AND3 may include a transparent conductive oxide (TCO). For example, each of the first to third anode electrodes AND1 to AND3 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium tin zinc oxide (ITZO), tungsten oxide (W x O y ), titanium oxide (TiO 2 ) or magnesium oxide (MgO) or other transparent conductive materials. In an embodiment, each of the first anode electrode AND1 to the third anode electrode AND3 may have a thickness from approximately To about The thickness is within the range of , but the present invention is not limited thereto.

[0137] In an embodiment, the first light emitting element ED1 may provide white light. To this end, as an example, the intermediate layer IL of the first light emitting element ED1 may include a plurality of light emitting layers providing light of different colors, and the plurality of light emitting layers may be stacked in the third direction DR3. In an embodiment, the plurality of light emitting layers may include a first light emitting layer, a second light emitting layer, and a third light emitting layer stacked in the third direction DR3. White light may be generated by mixing light of different colors from the plurality of light emitting layers. At the same time, the intermediate layer IL may further include a charge generation layer. The charge generation layer may be disposed between adjacent light emitting layers. As described above, the intermediate layer IL may have a series structure including a plurality of light emitting layers and a charge generation layer.

[0138] In an embodiment, each of the light emitting layers of the intermediate layer IL may be an organic material layer including an organic material for emitting light of a predetermined color. For example, the organic material layer may include a host and a dopant. The organic material layer may include a material for emitting light of a predetermined color and may be formed using a phosphorescent material or a fluorescent material.

[0139] In an embodiment, the first light-emitting layer may provide light of a first color (e.g., red). To this end, the organic material layer of the first light-emitting layer may include a host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl)benzene (mCP) and may be a phosphorescent material including a dopant, the dopant including at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP (octaethylporphyrin platinum). In another embodiment, the organic material layer of the first light-emitting layer may include PBD:Eu(DBM) 3 The fluorescent material may be phenanthene or perylene, but is not limited thereto.

[0140] In an embodiment, the second light emitting layer may provide light of a second color (eg, green). To this end, the organic material layer of the second light emitting layer includes a host material including CBP or mCP, and may include an organic material including Ir(ppy) 3 (tris(2-phenylpyridine)iridium) as a dopant material. In another embodiment, the organic material layer of the second light-emitting layer may be a layer containing Alq 3 The fluorescent material may be tris(8-hydroxyquinoline)aluminum, but is not limited thereto.

[0141] In an embodiment, the third light emitting layer may provide light of a third color (eg, blue). To this end, the organic material layer of the third light emitting layer may include a host material including CBP or mCP and may include (4,6-F2ppy) 2 The phosphorescent material may be a dopant material of Irpic or L2BD111, but is not limited thereto.

[0142] In an embodiment, the second light-emitting element of the second pixel PX2 and the third light-emitting element of the third pixel PX3 may each have the same structure as the first light-emitting element ED1 described above. For example, in an embodiment, the second light-emitting element may include a second anode electrode AND2, an intermediate layer IL, and a cathode electrode CAT, and the intermediate layer IL of the second light-emitting element may include the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer described above. Similarly, the third light-emitting element may include a third anode electrode AND3, an intermediate layer IL, and a cathode electrode CAT, and the intermediate layer IL of the third light-emitting element may include the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer described above.

[0143] In an embodiment, a pixel defining layer PDL may be disposed on the first, second, and third anode electrodes AND1, AND2, and AND3.

[0144] In an embodiment, the pixel defining layer PDL may define the light emitting area of ​​each of the pixels PX1 to PX3 (e.g., the first light emitting area EA1 of the first pixel PX1, the second light emitting area EA2 of the second pixel PX2, and the third light emitting area EA3 of the third pixel PX3). To this end, the pixel defining layer PDL may be provided to expose a partial area of ​​each of the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3. The pixel defining layer PDL may cover the edges of the first anode electrode AND1, the second anode electrode AND2, and the third anode electrode AND3. The pixel defining layer PDL may be formed of an inorganic layer. In an embodiment, the pixel defining layer PDL may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0145] In an embodiment, the cathode electrode CAT may be disposed on the pixel defining layer PDL and the intermediate layer IL. For example, the cathode electrode CAT may be disposed on the intermediate layer IL of the first pixel PX1, the intermediate layer IL of the second pixel PX2, and the intermediate layer IL of the third pixel PX3 to overlap with the first anode electrode AND1, the second anode electrode AND2, the third anode electrode AND3, the first light emitting area EA1, the second light emitting area EA2, the third light emitting area EA3, and the pixel defining layer PDL. In a top emission structure, the cathode electrode CAT may be made of a transparent conductive material (TCO) capable of transmitting light such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the cathode electrode CAT is made of a semi-transmissive conductive material, the light output efficiency may be increased by a microcavity.

[0146] In an embodiment, the encapsulation layer ENC may be disposed on the cathode electrode CAT. The encapsulation layer ENC may cover the top surface and side surface of the first light emitting element ED1, the top surface and side surface of the second light emitting element, and the top surface and side surface of the third light emitting element, and may protect the first light emitting element ED1, the second light emitting element, and the third light emitting element. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the first light emitting element ED1, the second light emitting element, and the third light emitting element. The encapsulation layer ENC may include at least one inorganic layer for preventing oxygen or moisture from penetrating into the first light emitting element ED1, the second light emitting element, and the third light emitting element. In addition, the encapsulation layer ENC may include at least one organic layer for protecting the first light emitting element ED1, the second light emitting element, and the third light emitting element from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked along the third direction DR3 on the cathode electrode CAT. For example, the first inorganic encapsulation layer may be disposed on the cathode electrode CAT, the organic encapsulation layer may be disposed on the first inorganic encapsulation layer, and the second inorganic encapsulation layer may be disposed on the organic encapsulation layer. Each of the first inorganic encapsulation layer and the second inorganic encapsulation layer may be a plurality of layers in which a plurality of inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The organic layer may include at least any one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0147] In an embodiment, the adhesive layer ADL may be a layer for adhering the encapsulation layer ENC and the color filter layer (e.g., the first color filter CF1, the second color filter CF2, and the third color filter CF3) together. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0148] In an embodiment, the color filter layer may include color filters CF1, CF2, and CF3 of different colors. For example, the color filter layer may include a first color filter CF1 disposed to correspond to the first anode electrode AND1 and the first light emitting area EA1, a second color filter CF2 disposed to correspond to the second anode electrode AND2 and the second light emitting area EA2, and a third color filter CF3 disposed to correspond to the third anode electrode AND3 and the third light emitting area EA3.

[0149] In an embodiment, the first color filter CF1 can transmit light of a first color, for example, light in a red band. The red band can be in a range of approximately 600 nm to about 750 nm. Accordingly, the first color filter CF1 can transmit light of a first color among the light emitted from the first light emitting area EA1.

[0150] In an embodiment, the second color filter CF2 can transmit light of a second color, such as light in a green band. The green band can be in the range of approximately 480nm to about 560nm. Accordingly, the second color filter CF2 can transmit light of a second color among the light emitted from the second light emitting area EA2.

[0151] In an embodiment, the third color filter CF3 can transmit light of a third color, such as light in a blue band. The blue band can be in the range of approximately 370nm to about 460nm. Accordingly, the third color filter CF3 can transmit light of a third color among the light emitted from the third light emitting area EA3.

[0152] In an embodiment, a plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing a ratio of light directed to the front side of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0153] In an embodiment, although not shown in the drawings, a filling layer may be further provided on the plurality of lenses LNS. The filling layer may have a predetermined refractive index so that light travels in the third direction DR3 at an interface between the filling layer and the plurality of lenses LNS. In addition, the filling layer may be a planarization layer. The filling layer may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0154] In an embodiment, although not shown in the drawings, a cover layer may be further disposed on the filling layer. The cover layer may be a glass substrate or a polymer resin. When the cover layer is a glass substrate, it may be attached to the filling layer. In this case, the filling layer may be used to bond the cover layer. When the cover layer is a glass substrate, it may serve as a packaging substrate. When the cover layer is a polymer resin, it may be directly coated onto the filling layer.

[0155] In an embodiment, although not shown in the drawings, a polarizer may be further provided on one surface of the cover layer. The polarizer may be a structure for preventing visibility degradation caused by reflection of external light. The polarizer may include a linear polarizer and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the present invention is not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizer may be omitted.

[0156] Figure 7 is a diagram illustrating a method according to another embodiment Figure 5 A cross-sectional view of the display device taken along line II'.

[0157] Figure 7 The display device is with Figure 6 The display device of the present invention is different from the embodiment of the present invention, except that the first reflective layer RE1 is connected to the constant voltage line CVL, and the following description will mainly focus on this difference.

[0158] In the embodiments and as Figure 7 As shown in , a constant voltage line CVL transmitting a constant voltage may be provided on the insulating layer of the interlayer insulating layer ILD. For example, the constant voltage line CVL may be provided between the substrate SUB and each of the reflective layers RE1 to RE3. The constant voltage line CVL may be connected to the first reflective layer RE1. For example, the first reflective layer RE1 may be connected to the constant voltage line CVL through a fourth contact hole CT4 penetrating the insulating layer of the interlayer insulating layer ILD. Accordingly, the first reflective layer RE1 may receive a constant voltage from the constant voltage line CVL. Therefore, the first reflective layer RE1 may be prevented from floating.

[0159] In an embodiment, the constant voltage line CVL may be any one of a first driving voltage line VSL transmitting a first driving voltage VSS, a second driving voltage line VDL transmitting a second driving voltage VDD, and a third driving voltage line VIL transmitting a third driving voltage VINT.

[0160] In an embodiment, at least one of the second reflective layer RE2 and the third reflective layer RE3 may be connected to the above-mentioned constant voltage line CVL. For example, the first reflective layer RE1, the second reflective layer RE2, and the third reflective layer RE3 may be commonly connected to the constant voltage line CVL.

[0161] Figure 8 is a perspective view illustrating a head mounted display device according to an embodiment. Fig. 9 It is a graphic Figure 8 An exploded perspective view of an example of a head mounted display device.

[0162] In the examples and with reference to Figure 8 and Fig. 9 The head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector 1610.

[0163] In an embodiment, the first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 7The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0164] In an embodiment, the first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0165] In an embodiment, the middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0166] In an embodiment, the control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through the connector 1610. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector 1610.

[0167] In an embodiment, the control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In another embodiment, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0168] In an embodiment, the display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector 1610 therein. The housing cover 1200 is provided to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is disposed and a second eyepiece 1220 at which the user's right eye is disposed. Although in Figure 8 and Fig. 912 is a diagram showing that the first eyepiece 1210 and the second eyepiece 1220 are separately provided, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0169] In an embodiment, the first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0170] In an embodiment, the head-mounted band 1300 is used to fix the display device housing 1100 to the user's head so that a state in which the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are placed on the left eye and the right eye of the user, respectively, can be maintained. When the display device housing 1200 is implemented to be lightweight and compact, the head-mounted display device 1000 can be provided with Fig.10 The eyeglass frame shown in FIG. 1 is used to replace the headband 1300.

[0171] In an embodiment, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0172] Fig.10 is a perspective view illustrating a head-mounted display device according to an embodiment.

[0173] In the examples and with reference to Fig.10 The head mounted display device 1000_1 may be a glasses type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to the embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0174] In an embodiment, the display device housing 1200_1 may include a display device 10_3, an optical member 1060, and an optical path conversion member 1070. An image displayed on the display device 10_3 may be magnified by the optical member 1060, and may be provided to the right eye of the user through the right eye lens 1020 after its optical path is converted by the optical path conversion member 1070. As a result, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0175] Despite Fig.10 1030, but the present invention is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, in which case the image of the display device 10_3 may be provided to the left eye of the user. In another embodiment, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0176] The present invention should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and the present invention will be fully communicated to those skilled in the art. Although the present invention has been specifically shown and described with reference to embodiments of the present invention, it will be appreciated by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the present invention. Moreover, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: substrate; A transistor, disposed on the substrate; A planarization layer, disposed on the transistor; a first electrode disposed on the planarization layer to be connected to the transistor; An intermediate layer, disposed on the first electrode; A second electrode is disposed on the intermediate layer; a reflective layer, disposed in the groove of the planarization layer and separated from the first electrode; as well as The bonding layer is arranged between the inner wall of the groove and the reflective layer.

2. The display device according to claim 1, in, The reflective layer is a floating electrode.

3. The display device according to claim 1, in, The reflective layer does not overlap with the transistor.

4. The display device according to claim 1, further comprising: A connecting electrode connects the transistor and the first electrode.

5. The display device according to claim 4, in, The reflective layer and the connecting electrode do not overlap each other.

6. The display device according to claim 1, in, The bonding layer contacts the reflective layer.

7. The display device according to claim 1, in, The bonding layer includes at least one of an organic layer and an inorganic layer including a titanium oxide layer, a titanium nitride layer, and an indium tin oxide layer.

8. The display device according to claim 4, further comprising: The insulating layer is arranged between the reflective layer and the first electrode.

9. The display device according to claim 8, in, The insulating layer comprises: A first insulating layer, disposed on the reflective layer; and The second insulating layer is arranged on the first insulating layer.

10. The display device according to claim 9, in, The first electrode is connected to the connection electrode through a contact hole formed in the second insulating layer, the first insulating layer, and the planarizing layer.

11. The display device according to any one of claims 1 to 10, in, An area of ​​the first electrode is larger than an area of ​​the reflective layer.

12. The display device according to claim 11, in, In a plan view, an edge of the reflective layer is surrounded by an edge of the first electrode.

13. The display device according to claim 4, in, The first electrode is directly connected to the connection electrode.

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