Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. At least one pixel circuit is arranged in the array substrate. The pixel circuit comprises a driving transistor, a first compensation transistor and a second compensation transistor. Wherein the first compensation transistor is located in a data write-in branch in the pixel circuit, and the second compensation transistor is located in a light-emitting branch in the pixel circuit; the array substrate comprises a substrate and an active layer, the active layer is located on one side of the substrate; the active layer comprises a first channel region of the driving transistor, a second channel region of the first compensation transistor and a third channel region of the second compensation transistor; the first channel region, the second channel region and the third channel region are connected; the width-to-length ratio of the second channel region is the same as the width-to-length ratio of the third channel region. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the rapid development of display technology, the application of display products using organic light emitting devices (OLED) is becoming more and more widespread.

[0003] However, the performance of current OLED display panels needs to be improved. Summary of the invention

[0004] The present invention provides an array substrate and a display panel to improve the performance of the display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, wherein at least one pixel circuit is disposed in the array substrate, wherein the pixel circuit comprises a driving transistor, a first compensation transistor, and a second compensation transistor; wherein the first compensation transistor is located in a data writing branch in the pixel circuit, and the second compensation transistor is located in a light emitting branch in the pixel circuit;

[0006] The array substrate comprises:

[0007] substrate;

[0008] An active layer is located on one side of the substrate; the active layer includes a first channel region of the driving transistor, a second channel region of the first compensation transistor, and a third channel region of the second compensation transistor; the first channel region, the second channel region, and the third channel region are connected; and the width-to-length ratio of the second channel region is the same as the width-to-length ratio of the third channel region.

[0009] Optionally, the width of the second channel region is the same as the width of the third channel region, and the length of the second channel region is the same as the length of the third channel region; wherein the second channel region and the third channel region are arranged along a first direction; the first channel region and the second channel region are arranged along a second direction; and the first direction intersects with the second direction;

[0010] Optionally, the width of the first channel region, the width of the second channel region and the width of the third channel region are the same;

[0011] The length of the middle line between the first boundary line and the second boundary line of the first channel region is the length of the first channel region, and the width direction of the first channel region is perpendicular to the middle line; wherein the first boundary line and the second boundary line are arranged along the first direction, and the distance between the first boundary line and the middle line is the same as the distance between the second boundary line and the middle line.

[0012] Optionally, the array substrate further includes:

[0013] A first conductive layer is located on a side of the active layer away from the substrate; the gate of the driving transistor, the gate of the first compensation transistor and the gate of the second compensation transistor are located in the first conductive layer, and the gate of the driving transistor, the gate of the first compensation transistor and the gate of the second compensation transistor are connected.

[0014] Optionally, the pixel circuit further includes a data writing transistor; the active layer further includes a fourth channel region of the data writing transistor;

[0015] The array substrate further includes:

[0016] A first scanning line is located at a side of the active layer away from the substrate; an orthographic projection of the first scanning line on the substrate overlaps with an orthographic projection of the fourth channel region on the substrate;

[0017] Optionally, the active layer further includes a first electrode of the data writing transistor and a second electrode of the data writing transistor, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the first compensation transistor;

[0018] The active layer further includes a first electrode of the first compensation transistor and a second electrode of the first compensation transistor, and the active layer further includes a first electrode of the driving transistor; the second electrode of the first compensation transistor is connected to the first electrode of the driving transistor;

[0019] The active layer further includes a first electrode of the second compensation transistor and a second electrode of the second compensation transistor, the first electrode of the second compensation transistor is connected to a power line, and the second electrode of the second compensation transistor is connected to the first electrode of the driving transistor;

[0020] Optionally, the array substrate further includes:

[0021] The first conductive layer is located on a side of the active layer away from the substrate; the first scanning line is located on the first conductive layer.

[0022] Optionally, the pixel circuit further includes a threshold compensation transistor; the active layer further includes a fifth channel region, a first electrode of the threshold compensation transistor and a second electrode of the threshold compensation transistor; the active layer further includes a second electrode of the driving transistor;

[0023] The orthographic projection of the first scanning line on the substrate partially overlaps with the orthographic projection of the fifth channel region on the substrate;

[0024] The first electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the gate of the driving transistor;

[0025] Optionally, the array substrate further includes:

[0026] A first connecting line, located at a side of the first conductive layer away from the substrate, the first connecting line being connected between the second electrode of the threshold compensation transistor and the gate of the driving transistor;

[0027] Optionally, the first scanning line includes a main body portion and an extension portion; the main body portion extends along the second direction, and the extension portion extends along the first direction;

[0028] A portion where the main body overlaps with the active layer forms a first gate of the threshold compensation transistor, and a portion where the extension overlaps with the active layer forms a second gate of the threshold compensation transistor.

[0029] Optionally, the pixel circuit further includes a first reset transistor; the active layer further includes a sixth channel region of the first reset transistor, a first electrode of the first reset transistor, and a second electrode of the first reset transistor;

[0030] The array substrate further includes:

[0031] a second scanning line, located at a side of the active layer away from the substrate and extending along the second direction; an orthographic projection of the second scanning line on the substrate partially overlaps with an orthographic projection of the sixth channel region on the substrate;

[0032] A first reset signal line, located at a side of the second scan line away from the substrate and extending along the second direction;

[0033] A first electrode of the first reset transistor is connected to the first reset signal line, and a second electrode of the first reset transistor is connected to a second electrode of the threshold compensation transistor;

[0034] Optionally, the array substrate further includes:

[0035] a second connection line, located at a first side of the film layer where the first reset signal line is located, away from the substrate, the second connection line being connected between the first reset signal line and the first electrode of the first reset transistor;

[0036] Optionally, the sixth channel region includes a first sub-region and a second sub-region;

[0037] The first sub-region is connected to the second sub-region and extends along the first direction, and is arranged along the second direction;

[0038] The orthogonal projection of the second scan line on the substrate overlaps with the orthogonal projection of the first sub-region on the substrate to form a first gate of the first reset transistor, and the orthogonal projection of the second scan line on the substrate overlaps with the orthogonal projection of the second sub-region on the substrate to form a second gate of the first reset transistor;

[0039] Optionally, the array substrate further includes:

[0040] A second conductive layer is located on a side of the first conductive layer away from the substrate, and the first reset signal line is located on the second conductive layer;

[0041] A third conductive layer is located on a side of the second conductive layer away from the substrate, and the first connecting line and the second connecting line are located in the third conductive layer;

[0042] a fourth conductive layer, located at a side of the third conductive layer away from the substrate, wherein the data line and the power line are located in the fourth conductive layer;

[0043] Optionally, the active layer comprises polycrystalline silicon semiconductor material.

[0044] Optionally, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor; the active layer further includes a seventh channel region of the first light emission control transistor, a first electrode of the first light emission control transistor, and a second electrode of the first light emission control transistor; the active layer further includes an eighth channel region of the second light emission control transistor, a first electrode of the second light emission control transistor, and a second electrode of the second light emission control transistor;

[0045] The array substrate further includes:

[0046] a light emitting control line, located on a side of the active layer away from the substrate, wherein the orthographic projection of the light emitting control line on the substrate overlaps with the orthographic projection of the seventh channel region on the substrate, and the orthographic projection of the light emitting control line on the substrate overlaps with the orthographic projection of the eighth channel region on the substrate;

[0047] a power line, located at a side of the film layer where the light emitting control line is located away from the substrate; a first electrode of the first light emitting control transistor is connected to a first electrode of the second compensation transistor, and a second electrode of the first light emitting control transistor is connected to the power line;

[0048] The first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is connected to the first electrode of the light emitting element;

[0049] Optionally, the pixel circuit further includes a storage capacitor, the storage capacitor includes a first capacitor plate and a second capacitor plate; the gate of the driving transistor is reused as the first capacitor plate;

[0050] Optionally, the array substrate further comprises a first conductive layer and a second conductive layer which are stacked on the substrate; the light emitting control line and the first capacitor plate are located in the first conductive layer, and the second capacitor plate is located in the second conductive layer;

[0051] Preferably, the array substrate further comprises a power connection line, wherein the power connection line is connected between the second capacitor plate and the power line;

[0052] Preferably, the power connection line is arranged on the same layer as the second capacitor plate.

[0053] Optionally, the pixel circuit further includes a second reset transistor; the active layer further includes a ninth channel region of the second reset transistor, a first electrode of the second reset transistor, and a second electrode of the second reset transistor;

[0054] The array substrate further includes:

[0055] a third scanning line, located at a side of the active layer away from the substrate and extending along the second direction, wherein an orthographic projection of the third scanning line on the substrate partially overlaps an orthographic projection of the ninth channel region on the substrate;

[0056] A second reset signal line is located at a side of the film layer where the third scan line is located away from the substrate, a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to the first electrode of the light emitting element;

[0057] Optionally, an orthographic projection of the second reset signal line on the substrate at least partially overlaps with an orthographic projection of the third scan line on the substrate;

[0058] Optionally, the array substrate further includes:

[0059] A third connecting line is located at a side of the film layer where the third scanning line is located away from the substrate, and the third connecting line is connected between the first electrode of the second reset transistor and the second reset signal line;

[0060] Optionally, the third connection line is arranged on the same layer as the second reset signal line;

[0061] Optionally, the array substrate further comprises a first conductive layer, a second conductive layer and a third conductive layer which are located on the substrate and are stacked;

[0062] The third scan line is located in the first conductive layer, and the second reset signal line and the third connection line are located in the third conductive layer.

[0063] Optionally, the pixel circuit further includes a second reset transistor and a third reset transistor; the active layer further includes a ninth channel region of the second reset transistor, a first electrode of the second reset transistor, and a second electrode of the second reset transistor; the active layer further includes a tenth channel region of the third reset transistor, a first electrode of the third reset transistor, and a second electrode of the third reset transistor;

[0064] The array substrate further includes:

[0065] a third scanning line, located at a side of the active layer away from the substrate and extending along the second direction, wherein an orthographic projection of the third scanning line on the substrate overlaps with an orthographic projection of the ninth channel region on the substrate; and an orthographic projection of the third scanning line on the substrate overlaps with an orthographic projection of the tenth channel region on the substrate;

[0066] A second reset signal line is located at a side of the film layer where the third scan line is located away from the substrate, a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to the first electrode of the light emitting element;

[0067] a third reset signal line, located at a side of the film layer where the second reset signal line is located away from the substrate, a first electrode of the third reset transistor being connected to the third reset signal line, and a second electrode of the third reset transistor being connected to a first electrode of the first light emission control transistor;

[0068] Optionally, the array substrate further includes:

[0069] A third connecting line is located at a side of the film layer where the third scanning line is located away from the substrate, and the third connecting line is connected between the first electrode of the second reset transistor and the second reset signal line;

[0070] a fourth connecting line, located at a side of the film layer where the third scanning line is located away from the substrate, the fourth connecting line being connected between the second electrode of the third reset transistor and the first electrode of the first light emitting control transistor;

[0071] Optionally, the third connecting line and the fourth connecting line are arranged in the same layer;

[0072] Optionally, an orthographic projection of the third reset signal line on the substrate at least partially overlaps with an orthographic projection of the third scan line on the substrate;

[0073] Optionally, the array substrate further comprises a first conductive layer, a second conductive layer and a third conductive layer which are located on the substrate and are stacked;

[0074] The third scan line is located in the first conductive layer, the second reset signal line is located in the second conductive layer, and the third reset signal line, the third connecting line and the fourth connecting line are located in the third conductive layer.

[0075] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate described in any embodiment of the present invention.

[0076] According to the technical solution of the embodiment of the present invention, the first channel region of the driving transistor, the second channel region of the first compensation transistor and the third channel region of the second compensation transistor are connected, so that the channel region of the driving transistor can be extended, that is, the channel length can be compensated, so that the driving transistor can have a larger channel length in the light-emitting stage, so that different driving currents can be better generated, and gray scales can be better developed, thereby improving the display effect of the display panel. In addition, the width-to-length ratio of the second channel region is the same as the width-to-length ratio of the third channel region, so that the actual channel length of the driving transistor in the data writing stage and the light-emitting stage is consistent, so that the threshold voltage of the driving transistor in the light-emitting stage is consistent with the threshold voltage of the driving transistor in the data writing stage, avoiding the difference in the threshold voltage of the driving transistor in different stages, which is conducive to improving the compensation effect of the threshold voltage of the driving transistor, ensuring that the driving current generated by the driving transistor is independent of the threshold voltage of the driving transistor, thereby avoiding the influence of process fluctuations on the driving current of the driving transistor, avoiding the driving current fluctuation caused by the characteristics of the driving transistor, thereby improving the display effect of the display panel and improving the performance of the display panel.

[0077] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0079] Figure 1 It is a partial schematic diagram of an array substrate in the related art;

[0080] Figure 2 is a structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0081] Figure 3 is a schematic structural diagram of a first channel region and a second channel region provided by an embodiment of the present invention;

[0082] Figure 4 is a schematic structural diagram of a first channel region and a third channel region provided in an embodiment of the present invention;

[0083] Figure 5 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0084] Figure 6 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0085] Figure 7 is a schematic structural diagram of an active layer of an array substrate provided by an embodiment of the present invention;

[0086] Figure 8 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0087] Fig. 9 yes Figure 8 Cross-sectional view along the direction a1-a2;

[0088] Fig.10 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0089] Fig.11 yes Fig.10 Cross-sectional view along the b1-b2 direction;

[0090] Fig.12 yes Fig.10 Cross-sectional view along the b3-b4 direction;

[0091] Fig.13 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0092] Fig.14is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0093] Fig.15 yes Fig.14 Cross-sectional view along the direction e1-e2;

[0094] Fig.16 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0095] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0096] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0097] As mentioned in the background technology, the existing display panel has the problem that the performance needs to be improved. The inventors have found that the reason for this problem is that the display panel includes an array substrate, and the array substrate is provided with a pixel circuit. The pixel circuit includes a driving transistor, and the driving transistor can generate a driving current to drive the light-emitting element to emit light. However, the threshold voltage of the driving transistor is prone to drift, so that the threshold voltage of the driving transistor is different at different stages, which affects the accuracy of the driving current generated by the driving transistor, affects the display effect of the display panel, and makes the performance of the display panel poor.

[0098] Figure 1 is a partial schematic diagram of an array substrate in the related art, such as Figure 1As shown, the array substrate includes a first transistor, and the first transistor can generate a driving current. The gate 11 of the first transistor covers the channel region 12 of the first transistor, and the distance between the orthographic projection of the gate 11 of the first transistor and the orthographic projection of the source 13 of the first transistor is greater than or equal to 0.5 microns, and the distance between the orthographic projection of the gate 11 of the first transistor and the orthographic projection of the drain 14 of the first transistor is greater than or equal to 0.5 microns, so as to avoid the gate 11 of the first transistor from overlapping with the active part outside its channel region, but this will easily affect the channel size of the first transistor when the process fluctuates, thereby affecting the threshold voltage of the first transistor, so that the threshold voltage of the first transistor is different at different stages, thereby affecting the compensation effect of the threshold voltage of the first transistor, so that the threshold voltage drift of the first transistor causes the fluctuation of the driving current generated by the first transistor, thereby affecting the luminous brightness of the light-emitting diode corresponding to the first transistor, thereby affecting the display effect of the display panel, and making the use performance of the display panel poor. Moreover, the channel size of the first transistor is fixed, and the channel size is small, which is not conducive to grayscale expansion, thereby affecting the display effect of the display panel, and making the use performance of the display panel poor.

[0099] In response to the above technical problems, the present invention provides an array substrate, in which at least one pixel circuit 100 is arranged, and the pixel circuit 100 includes a driving transistor T1, a first compensation transistor T2 and a second compensation transistor T3; wherein the first compensation transistor T2 is located in a data writing branch in the pixel circuit 100, and the second compensation transistor T3 is located in a light-emitting branch in the pixel circuit 100.

[0100] Figure 2 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present invention, with reference to Figure 2 , the array substrate comprises:

[0101] Substrate 110;

[0102] The active layer 120 is located on one side of the substrate 110; the active layer 120 includes a first channel region T11 of the driving transistor T1, a second channel region T21 of the first compensation transistor T2, and a third channel region T31 of the second compensation transistor T3; the first channel region T11, the second channel region T21, and the third channel region T31 are connected; the width-to-length ratio of the second channel region T21 is the same as the width-to-length ratio of the third channel region T31.

[0103] Among them, at least one pixel circuit 100 is provided in the array substrate, for example, a plurality of pixel circuits 100 are provided, and the plurality of pixel circuits 100 are arranged in an array. The pixel circuit 100 may be a 7T1C pixel circuit and its deformation. The driving transistor T1 may generate a driving current, thereby driving the light-emitting element to emit light. The pixel circuit 100 includes a data writing branch, that is, a branch for writing data voltage, the data writing branch may be connected between the data line and the driving transistor T1, and the data writing branch may include a data writing transistor and a first compensation transistor T2. The pixel circuit 100 also includes a light-emitting branch, that is, a branch for generating a driving current and driving the light-emitting element to emit light, and the light-emitting branch may be connected between the power line and the light-emitting element. The light-emitting branch may include a driving transistor and a second compensation transistor, and may also include a light-emitting control transistor, etc.

[0104] The substrate 110 has supporting, protecting and buffering functions, and the substrate 110 may be a flexible substrate or a hard substrate, which is not limited in this embodiment. The active layer 120 may include polysilicon semiconductor material or oxide semiconductor material, which is not limited in this embodiment.

[0105] Specifically, the first channel region T11, the second channel region T21 and the third channel region T31 are connected, and the first compensation transistor T2 is located in the data writing branch of the pixel circuit 100. When data is written, data is written to the driving transistor T1 through the first compensation transistor T2, so that when data is written, the first compensation transistor T2 can extend the channel region of the driving transistor T1, that is, compensate for the channel length. The second compensation transistor T3 is located in the light-emitting branch in the pixel circuit 100. When emitting light, that is, when the driving transistor T1 generates a driving current, the second compensation transistor T3 can extend the channel region of the driving transistor T1. That is, when data is written, the actual channel length of the driving transistor T1 is the length of the first channel region T11 plus the length of the second channel region T21. In the light-emitting stage, the actual channel length of the driving transistor T1 is the length of the first channel region T11 plus the length of the third channel region T31. In this way, the driving transistor T1 can have a larger channel length in the light-emitting stage, so that different driving currents can be better generated, gray scales can be better developed, and the display effect of the display panel can be improved.

[0106] By setting the width-to-length ratio of the second channel region T21 to be the same as that of the third channel region T31, the actual channel length of the driving transistor T1 in the data writing stage and the light emitting stage is consistent, so that the threshold voltage of the driving transistor T1 when emitting light is consistent with the threshold voltage when writing data, thereby avoiding the difference in the threshold voltage of the driving transistor T1 in different stages, thereby ensuring that the threshold voltage when threshold compensation is performed on the driving transistor T1 is the same as the threshold voltage when the driving transistor T1 generates a driving current, thereby ensuring the threshold compensation effect, so that the driving current generated by the driving transistor T1 is independent of the threshold voltage of the driving transistor T1. In this way, it is beneficial to improve the accuracy of the driving current generated by the driving transistor T1, thereby improving the display effect of the display panel and improving the performance of the display panel.

[0107] Specifically, when threshold compensation is performed on the driving transistor T1, the threshold voltage of the driving transistor T1 can be transmitted to the gate of the driving transistor T1, and the difference between the gate-source voltage of the driving transistor T1 is related to the threshold voltage, and the driving current generated by the driving transistor T1 is related to the difference between the gate-source voltage of the driving transistor T1 minus the threshold voltage of the driving transistor T1. By setting the width-to-length ratio of the second channel region T21 to be the same as the width-to-length ratio of the third channel region T31, the actual channel length of the driving transistor T1 in the data writing stage and in the light emitting stage is consistent, which can ensure that the threshold voltage transmitted to the gate of the driving transistor T1 when threshold compensation is performed is the same as the threshold voltage subtracted when the driving current is generated, thereby ensuring the compensation effect of the threshold voltage.

[0108] Furthermore, by connecting the first channel region T11, the second channel region T21 and the third channel region T31 together, the occupied area of ​​the driving transistor T1, the first compensation transistor T2 and the second compensation transistor T3 can be reduced, thereby reducing the occupied space of the pixel circuit, which is beneficial to improving the pixel density of the display panel formed by the array substrate, and further improving the performance of the display panel.

[0109] In the technical solution of this embodiment, the first channel region of the driving transistor, the second channel region of the first compensation transistor and the third channel region of the second compensation transistor are connected, so that the channel region of the driving transistor can be extended, that is, the channel length can be compensated, so that the driving transistor can have a larger channel length in the light-emitting stage, so that different driving currents can be better generated, and gray scales can be better developed, thereby improving the display effect of the display panel. In addition, the width-to-length ratio of the second channel region is the same as the width-to-length ratio of the third channel region, so that the actual channel length of the driving transistor in the data writing stage and the light-emitting stage is consistent, so that the threshold voltage of the driving transistor in the light-emitting stage is consistent with the threshold voltage of the driving transistor in the data writing stage, avoiding the difference in the threshold voltage of the driving transistor in different stages, which is conducive to improving the compensation effect of the threshold voltage of the driving transistor, ensuring that the driving current generated by the driving transistor is independent of the threshold voltage of the driving transistor, thereby avoiding the influence of process fluctuations on the driving current of the driving transistor, avoiding the driving current fluctuation caused by the characteristics of the driving transistor, thereby improving the display effect of the display panel and improving the performance of the display panel.

[0110] On the basis of the above technical solution, the structures of the first channel region T11 , the second channel region T21 and the third channel region T31 are further described below, but this is not intended to limit the present application.

[0111] Figure 3 is a schematic structural diagram of a first channel region and a second channel region provided in an embodiment of the present invention, Figure 4 is a schematic diagram of the structure of the first channel region and the third channel region provided in an embodiment of the present invention. Figure 3 and Figure 4 , a width W2 of the second channel region T21 is the same as a width W3 of the third channel region T31, and a length L2 of the second channel region T21 is the same as a length L3 of the third channel region T31; wherein, the second channel region T21 and the third channel region T31 are arranged along a first direction Y; the first channel region T11 and the second channel region T21 are arranged along a second direction X; and the first direction Y intersects with the second direction X.

[0112] Specifically, Figure 3 As shown, the length L2 of the second channel region T21 includes a portion along the first direction Y and a portion along the second direction X, and the width direction of the second channel region T21 is perpendicular to the length direction of the second channel region T21. Figure 4As shown, the length L3 of the third channel region T31 includes a portion along the first direction Y and a portion along the second direction X, and the width direction of the third channel region T31 is perpendicular to the length direction of the third channel region T31. By setting the width W2 of the second channel region T21 to be the same as the width W3 of the third channel region T31, and the length L2 of the second channel region T21 to be the same as the length L3 of the third channel region T31, the channel sizes of the second channel region T21 and the second channel region T22 are completely the same, so that the actual channel length of the driving transistor T1 is completely consistent in the data writing stage and the light emitting stage, thereby ensuring that the threshold voltage of the driving transistor T1 is the same in different stages, which is beneficial to improving the display effect of the display panel.

[0113] Optionally, refer to Figure 3 and Figure 4 , the width W1 of the first channel region T11, the width W2 of the second channel region T21, and the width W3 of the third channel region T31 are the same;

[0114] The length of the middle line A3 between the first boundary line A1 and the second boundary line A2 of the first channel region T11 is the length of the first channel region T11, and the width direction of the first channel region T11 is perpendicular to the middle line A3; wherein, the first boundary line A1 and the second boundary line A2 are arranged along the first direction Y, and the distance between the first boundary line A1 and the middle line A3 is the same as the distance between the second boundary line A2 and the middle line A3.

[0115] The middle line A3 is the median line of the first channel region T11, and the length of the middle line A3 is half of the sum of the length of the first boundary line A1 and the length of the second boundary line A2. The length of the middle line A3 is used to represent the length of the first channel region T11. The width direction of the first channel region T11 is perpendicular to the length direction, that is, the width direction of the first channel region T11 is perpendicular to the middle line A3.

[0116] Specifically, by setting the width W1 of the first channel region T11, the width W2 of the second channel region T21 and the width W3 of the third channel region T31 to be the same, the actual channel length of the driving transistor T1 can be the sum of the length of the first channel region T11, the length of the second channel region T21 and the length of the third channel region T31, thereby ensuring that the channel length of the driving transistor T1 is extended and facilitating the control of the magnitude of the driving current of the driving transistor T1.

[0117] On the basis of the above technical solutions, the film layer structure of the array substrate is described below, but it is not intended to limit the present application.

[0118] Figure 5 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 , the array substrate further comprises:

[0119] The first conductive layer M1 is located on a side of the active layer 120 away from the substrate 110; the gate T1_1 of the driving transistor T1, the gate T2_1 of the first compensation transistor T2 and the gate T3_1 of the second compensation transistor T3 are located in the first conductive layer M1, and the gate T1_1 of the driving transistor T1, the gate T2_1 of T2 and the gate T3_1 of the second compensation transistor T3 are connected.

[0120] Specifically, the gate T1_1 of the driving transistor T1, the gate T2_1 of the first compensation transistor T2 and the gate T3_1 of the second compensation transistor T3 can be connected as an integrated structure, which is easy to manufacture and can reduce the connecting lines, which is beneficial to reducing the occupied space of the pixel circuit 100 and further improving the pixel density of the display panel formed by the array substrate.

[0121] On the basis of the above-mentioned technical solutions, the structures that the array substrate may further include are described below, but are not intended to limit the present application.

[0122] Figure 6 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 6 , the pixel circuit 100 further includes a data writing transistor T4. Figure 6 As shown, the data writing transistor T4 is connected to the first compensation transistor T2 to form a data writing branch. The first electrode of the data writing transistor T4 is connected to the data line Data, the second electrode of the data writing transistor T4 is connected to the first electrode of the first compensation transistor T2, and the second electrode of the first compensation transistor T2 is connected to the first electrode of the driving transistor T1 to form a data writing branch. The gate of the first compensation transistor T2 is connected to the gate of the driving transistor T1.

[0123] Figure 7 is a schematic structural diagram of an active layer of an array substrate provided by an embodiment of the present invention, Figure 8 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 7 and Figure 8 , the active layer 120 further includes a fourth channel region T41 of the data writing transistor T4;

[0124] The array substrate also includes:

[0125] The first scan line S1 is located at a side of the active layer 120 away from the substrate 110 ; the orthographic projection of the first scan line S1 on the substrate 110 partially overlaps with the orthographic projection of the fourth channel region T41 on the substrate 110 .

[0126] Specifically, the orthographic projection of the first scan line S1 on the substrate 110 partially overlaps with the orthographic projection of the fourth channel region T41 on the substrate 110, forming the gate of the data write transistor T4. The first scan signal on the first scan line S1 can control the turn-on timing of the data write transistor T4. When the first compensation transistor T2 and the driving transistor T1 are turned on, and the first scan signal on the first scan line S1 controls the data write transistor T4 to be turned on, the data write transistor T4 transmits the data voltage on the data line Data to the gate of the driving transistor T1 through the first compensation transistor T2 and the driving transistor T1. At the same time, the threshold voltage of the driving transistor T1 is transmitted to the gate of the driving transistor T1, that is, the data voltage after threshold compensation is transmitted to the gate of the driving transistor T1, so as to facilitate threshold compensation of the driving transistor T1.

[0127] Optionally, refer to Figure 7 and Figure 8 The active layer 120 further includes a first electrode T42 of a data writing transistor T4 and a second electrode T43 of the data writing transistor T4, wherein the first electrode T42 of the data writing transistor T4 is connected to the data line Data, and the second electrode T43 of the data writing transistor T4 is connected to the first electrode T22 of the first compensation transistor T2;

[0128] The active layer 120 further includes a first electrode T22 of the first compensation transistor T2 and a second electrode of the first compensation transistor T2. The active layer 120 further includes a first electrode of the driving transistor T1. The second electrode of the first compensation transistor T2 is connected to the first electrode of the driving transistor T1.

[0129] The active layer 120 further includes a first electrode T32 of a second compensation transistor T3 and a second electrode of the second compensation transistor T3 . The first electrode T32 of the second compensation transistor T3 is connected to the power line VDD, and the second electrode of the second compensation transistor T3 is connected to the first electrode of the driving transistor T1 .

[0130] The active layer 120 further includes the second electrode T12 of the driving transistor T1. The first electrode T42 of the data writing transistor T4 is a source electrode, and the second electrode T43 of the data writing transistor T4 is a drain electrode; or, the first electrode T42 of the data writing transistor T4 is a drain electrode, and the second electrode T43 of the data writing transistor T4 is a source electrode, which is not limited in this embodiment. The first electrode T22 of the first compensation transistor T2 is a source electrode, and the second electrode of the first compensation transistor T2 is a drain electrode; or, the first electrode T22 of the first compensation transistor T2 is a drain electrode, and the second electrode of the first compensation transistor T2 is a source electrode, which is not limited in this embodiment. The first electrode T32 of the second compensation transistor T3 is a source electrode, and the second electrode of the second compensation transistor T3 is a drain electrode; or, the first electrode T32 of the second compensation transistor T3 is a drain electrode, and the second electrode of the second compensation transistor T3 is a source electrode, which is not limited in this embodiment. The first electrode of the driving transistor T1 is a source, and the second electrode T12 of the driving transistor T1 is a drain; or, the first electrode of the driving transistor T1 is a drain, and the second electrode T12 of the driving transistor T1 is a source, which is not limited in this embodiment.

[0131] Specifically, since the first channel region T11 of the driving transistor T1 is connected to the second channel region T21 of the first compensation transistor T2, the second electrode of the first compensation transistor T2 is directly connected to the first electrode of the driving transistor T1, and there is no need to separately set the second electrode of the first compensation transistor T2 and the first electrode of the driving transistor T1, which can reduce the occupied space of the pixel circuit 100. Similarly, there is no need to separately set the second electrode of the second compensation transistor T3, which can further reduce the occupied space of the pixel circuit 100.

[0132] The first electrode T32 of the second compensation transistor T3 is connected to the power line VDD. In the light emitting stage, the power voltage on the power line VDD is transmitted to the driving transistor T1, so that the driving transistor T1 generates current, thereby driving the light emitting element to emit light.

[0133] Optionally, refer to Figure 8 The first electrode T42 of the data writing transistor T4 is connected to the data line Data through the connecting wire L0. The first electrode T42 of the data writing transistor T4 is connected to the connecting wire L0 through a via hole, and the connecting wire L0 is connected to the data line Data through a via hole.

[0134] Fig. 9 yes Figure 8 A cross-sectional view along the direction a1-a2, optionally, referring to Figure 8 and Fig. 9 , the array substrate further comprises:

[0135] The first conductive layer M1 is located on a side of the active layer 120 away from the substrate 110 ; the first scan line S1 is located on the first conductive layer M1 .

[0136] Specifically, the first scan line S1 is disposed in the first conductive layer M1 so that the first scan line S1 overlaps with the fourth channel region T41 on the active layer 120 to form the gate of the data writing transistor T4, thereby facilitating controlling the conduction timing of the data writing transistor T4.

[0137] Optionally, refer to Figure 6 , the pixel circuit 100 further includes a threshold compensation transistor T5.

[0138] Optionally, refer to Figure 7 , the active layer 120 further includes a fifth channel region T51, a first electrode T52 of the threshold compensation transistor T5, and a second electrode T53 of the threshold compensation transistor T5; the active layer 120 further includes a second electrode T12 of the driving transistor T1;

[0139] refer to Figure 8 , the orthographic projection of the first scan line S1 on the substrate 110 partially overlaps with the orthographic projection of the fifth channel region T51 on the substrate 110;

[0140] A first electrode T52 of the threshold compensation transistor T5 is connected to a second electrode T12 of the driving transistor T1 , and a second electrode T53 of the threshold compensation transistor T5 is connected to a gate of the driving transistor T1 .

[0141] Specifically, the orthographic projection of the first scan line S1 on the substrate 110 partially overlaps with the orthographic projection of the fifth channel region T51 on the substrate 110, forming the gate of the threshold compensation transistor T5. The first electrode T52 of the threshold compensation transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T53 of the threshold compensation transistor T5 is connected to the gate of the driving transistor T1, so that the threshold compensation transistor T5 can perform threshold compensation on the driving transistor T1 and transmit the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1.

[0142] Fig.10 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Fig.10 , the array substrate further comprises:

[0143] The first connection line LA1 is located at a side of the first conductive layer M1 away from the substrate 110 . The first connection line LA1 is connected between the second electrode T53 of the threshold compensation transistor T5 and the gate of the driving transistor T1 .

[0144] Specifically, the second electrode T53 of the threshold compensation transistor T5 is connected to the first connection line LA1 through a via, and the first connection line LA1 is connected to the gate of the driving transistor T1 through a via, so that the threshold compensation transistor T5 can perform threshold compensation on the driving transistor T1.

[0145] Optionally, refer to Fig.10 , the first scanning line S1 includes a main body portion S11 and an extension portion S12; the main body portion S11 extends along the second direction X, and the extension portion S12 extends along the first direction Y;

[0146] The portion where the main body S11 overlaps with the active layer 120 forms the first gate T5_1 of the threshold compensation transistor T5, and the portion where the extension S12 overlaps with the active layer 120 forms the second gate T5_2 of the threshold compensation transistor T5. In this way, the formed threshold compensation transistor T5 is a dual-gate transistor, which can reduce the leakage current of the gate of the driving transistor T1, and thus can better maintain the voltage of the gate of the driving transistor T1, thereby maintaining the driving current generated by the driving transistor T1, which is beneficial to improving the display effect of the display panel.

[0147] Optionally, refer to Figure 6 , the pixel circuit 100 further includes a first reset transistor T6.

[0148] Optionally, refer to Figure 7 , the active layer 120 further includes a sixth channel region T61 of the first reset transistor T6 , a first electrode T62 of the first reset transistor T6 , and a second electrode T63 of the first reset transistor T6 .

[0149] Optionally, refer to Fig.10 , the array substrate further comprises:

[0150] The second scan line S2 is located at a side of the active layer 120 away from the substrate 110 and extends along the second direction X; the orthographic projection of the second scan line S2 on the substrate 110 partially overlaps with the orthographic projection of the sixth channel region T61 on the substrate 110;

[0151] A first reset signal line Vref1 is located at a side of the second scan line S2 away from the substrate 110 and extends along the second direction X;

[0152] A first electrode T62 of the first reset transistor T6 is connected to the first reset signal line Vrref1 , and a second electrode T63 of the first reset transistor T6 is connected to the second electrode T53 of the threshold compensation transistor T5 .

[0153] The first electrode T62 of the first reset transistor T6 is the source of the first reset transistor T6, and the second electrode T63 of the first reset transistor T6 is the drain of the first reset transistor T6; or, the first electrode T62 of the first reset transistor T6 is the drain of the first reset transistor T6, and the second electrode T63 of the first reset transistor T6 is the source of the first reset transistor T6.

[0154] Specifically, the first reset transistor T6 is provided, and the orthographic projection of the second scan line S2 on the substrate 110 overlaps with the orthographic projection of the sixth channel region T61 on the substrate 110, thereby forming the gate of the first reset transistor T6. And the second scan line S2 can control the turn-on timing of the first reset transistor T6. When the second scan signal on the second scan line S2 controls the first reset transistor T6 to turn on, the first reset transistor T6 transmits the first reset voltage on the first reset signal line Vref1 to the gate of the driving transistor T1, thereby resetting the gate of the driving transistor T1.

[0155] Optionally, refer to Fig.10 , the array substrate further comprises:

[0156] The second connection line LA2 is located at the first side of the film layer where the first reset signal line Vref1 is located away from the substrate 110 . The second connection line LA2 is connected between the first reset signal line Vref1 and the first electrode T61 of the first reset transistor T6 .

[0157] Specifically, the second connection line LA2 is connected to the first reset signal line Vref1 through a via hole, and the second connection line LA2 is connected to the first electrode T61 of the first reset transistor T6 through a via hole, so that the first electrode T62 of the first reset transistor T6 is connected to the first reset signal line Vref1.

[0158] Optionally, refer to Figure 7 , the sixth channel region T61 includes a first sub-region T611 and a second sub-region T612;

[0159] The first sub-region T611 is connected to the second sub-region T612 and extends along the first direction Y, and is arranged along the second direction X;

[0160] The orthographic projection of the second scan line S2 on the substrate 110 overlaps with the orthographic projection of the first sub-area T611 on the substrate 110 to form the first gate T6_1 of the first reset transistor T6, and the orthographic projection of the second scan line S2 on the substrate 110 overlaps with the orthographic projection of the second sub-area T612 on the substrate 110 to form the second gate T6_2 of the first reset transistor T6. In this way, the first reset transistor T6 formed is a dual-gate transistor, which can reduce the leakage current of the gate of the driving transistor T1, thereby maintaining the voltage of the gate of the driving transistor T1, thereby maintaining the driving current generated by the driving transistor T1, which is beneficial to improving the display effect of the display panel.

[0161] Fig.11 yes Fig.10 A cross-sectional view along the b1-b2 direction, optionally, referring to Fig.10 and Fig.11 , the array substrate further comprises:

[0162] A second conductive layer M2 is located at a side of the first conductive layer M1 away from the substrate 110 , and the first reset signal line Vref1 is located at the second conductive layer M2 ;

[0163] A third conductive layer M3 is located at a side of the second conductive layer M2 away from the substrate 110, and the first connecting line LA1 and the second connecting line LA2 are located in the third conductive layer M3;

[0164] The fourth conductive layer M4 is located at a side of the third conductive layer M3 away from the substrate 110 . The data line Data and the power line VDD are located in the fourth conductive layer M4 .

[0165] Specifically, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 are stacked. By arranging the first connecting line LA1 and the second connecting line LA2 in the third conductive layer M3, it is convenient to perform wire jumping, so that the first reset signal line Vref1 is connected to the first reset transistor T6 through the second connecting line LA2, and the threshold compensation transistor T5 is connected to the driving transistor T1 through the first connecting line LA1.

[0166] Optionally, the active layer 120 includes polysilicon semiconductor material. In this way, it is easy to form a P-type transistor, so that the transistor in the pixel circuit 100 is a P-type transistor, which can reduce the cost, reduce the occupied space of the pixel circuit 100, and facilitate improving the pixel density of the display panel.

[0167] Optionally, refer to Figure 6 The pixel circuit 100 also includes a first light emission control transistor T7 and a second light emission control transistor T8; the active layer 120 also includes a seventh channel region T71 of the first light emission control transistor T7, a first electrode T72 of the first light emission control transistor T7, and a second electrode T73 of the first light emission control transistor T7; the active layer 120 also includes an eighth channel region T81 of the second light emission control transistor T8, a first electrode T82 of the second light emission control transistor T8, and a second electrode T83 of the second light emission control transistor T8.

[0168] like Figure 6 As shown, the first light-emitting control transistor T7, the second compensation transistor T3, the driving transistor T1 and the light-emitting control transistor T8 are connected to form a light-emitting branch. When the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are turned on, and the second compensation transistor T3 and the driving transistor T1 are turned on, the power line VDD, the first light-emitting control transistor T7, the second compensation transistor T3, the driving transistor T1, the second light-emitting control transistor T8 and the light-emitting element OLED form a current path, so that the driving transistor T1 generates a driving current, and the light-emitting element OLED emits light in response to the driving current.

[0169] Optionally, refer to Fig.10, the array substrate further comprises:

[0170] The light emitting control line EM is located on a side of the active layer 120 away from the substrate 110, and the orthographic projection of the light emitting control line EM on the substrate 110 overlaps with the orthographic projection of the seventh channel region T71 on the substrate 110, and the orthographic projection of the light emitting control line EM on the substrate 110 overlaps with the orthographic projection of the eighth channel region T81 on the substrate 110;

[0171] The power line VDD is located at the side of the film layer where the light emitting control line EM is located away from the substrate 110; the first electrode T72 of the first light emitting control transistor T7 is connected to the first electrode T32 of the second compensation transistor T3, and the second electrode T73 of the first light emitting control transistor T7 is connected to the power line VDD;

[0172] The first electrode T82 of the second light emitting control transistor T8 is connected to the second electrode T12 of the driving transistor T1 , and the second electrode T83 of the second light emitting control transistor T8 is connected to the first electrode of the light emitting element OLED.

[0173] Specifically, the first light emission control transistor T7 and the second light emission control transistor T8 can control whether the driving transistor T1 generates a driving current. The orthographic projection of the light emission control line EM on the substrate 110 overlaps with the orthographic projection of the seventh channel region T71 on the substrate 110, forming the gate of the first light emission control transistor T7. The orthographic projection of the light emission control line EM on the substrate 110 overlaps with the orthographic projection of the eighth channel region T81 on the substrate 110, forming the gate of the second light emission control transistor T8. The light emission control signal on the light emission control line EM can control the timing of the first light emission control transistor T7 and the second light emission control transistor T8. When the light emission control signal on the light emission control line EM controls the first light emission control transistor T7 and the second light emission control transistor T8 to turn on, the power line VDD, the first light emission control transistor T7, the second compensation transistor T3, the driving transistor T1, the second light emission control transistor T8 and the light emitting element OLED form a current path, so that the driving transistor T1 generates a driving current, and the light emitting element OLED emits light in response to the driving current.

[0174] The gate of the first light emission control transistor T7 is formed by overlapping the orthographic projection of the light emission control line EM on the substrate 110 with the orthographic projection of the seventh channel region T71 on the substrate 110. The orthographic projection of the light emission control line EM on the substrate 110 overlaps the orthographic projection of the eighth channel region T81 on the substrate 110 to form the gate of the second light emission control transistor T8. It is not necessary to additionally set the gates of the first light emission control transistor T7 and the second light emission control transistor T8, which can reduce the occupied space of the transistors. In addition, the number of light emission control lines can be reduced, which is convenient for improving the pixel density of the display panel.

[0175] Optionally, refer to Figure 6 , Fig.10 and Fig.11 The pixel circuit 100 further includes a storage capacitor Cst, which includes a first capacitor plate C1 and a second capacitor plate C2; ​​the gate T1_1 of the driving transistor T1 is reused as the first capacitor plate C2.

[0176] Specifically, the storage capacitor Cst can maintain the voltage of the gate of the driving transistor T1, thereby maintaining the driving current of the driving transistor T1. By reusing the gate T1_1 of the driving transistor T1 as the first capacitor plate C2, the electrode settings can be reduced, the occupied space of the pixel circuit 100 can be reduced, and the thin and light design of the array substrate can be realized. In addition, the connection wiring between the storage capacitor Cst and the driving transistor T1 can be reduced, which is convenient for improving the pixel density of the display panel.

[0177] Fig.12 yes Fig.10 A cross-sectional view along the direction b3-b4, optionally, referring to Fig.11 and Fig.12 The array substrate further includes a first conductive layer M1 and a second conductive layer M2 which are stacked on the substrate 110; the light emitting control line EM and the first capacitor plate C1 are located on the first conductive layer M1, and the second capacitor plate C2 is located on the second conductive layer M2. In this way, the number of wirings and electrodes on the first conductive layer M1 and the second conductive layer M2 is not large, and the occupied space of the pixel circuit 100 can be reduced.

[0178] Optionally, refer to Fig.10 The array substrate further includes a power connection line VL, and the power connection line VL is connected between the second capacitor plate C2 and the power line VDD.

[0179] Specifically, the power connection line VL can connect a row of second capacitor plates C2, which is convenient for connecting the second capacitor plates C2 to the power line VDD and can reduce the voltage drop of the power line VDD, which is beneficial to ensure the accuracy of power voltage transmission.

[0180] Optionally, the power connection line VL and the second capacitor plate C2 are arranged in the same layer. In this way, it is convenient to connect the power connection line VL with the second capacitor plate C2, and the arrangement of the film layer can be reduced, which is conducive to realizing the light and thin design of the array substrate. In addition, the connection line between the power connection line VL and the second capacitor plate C2 can be reduced, which is conducive to improving the pixel density of the display panel.

[0181] The structure of the array substrate is described below in conjunction with structures that may be included in the pixel circuit, but this is not intended to limit the present application.

[0182] In one embodiment, optionally, reference Figure 6, the pixel circuit 100 further includes a second reset transistor T9.

[0183] Optionally, refer to Figure 7 The active layer 120 further includes a ninth channel region T91 of the second reset transistor T9 , a first electrode T92 of the second reset transistor T9 , and a second electrode T93 of the second reset transistor T9 .

[0184] Optionally, refer to Fig.10 , the array substrate further comprises:

[0185] A third scan line S3 is located at a side of the active layer 120 away from the substrate 110 and extends along the second direction X, and an orthographic projection of the third scan line S3 on the substrate 110 partially overlaps with an orthographic projection of the ninth channel region T91 on the substrate 110;

[0186] The second reset signal line Vref2 is located at the side of the film layer where the third scan line S3 is located away from the substrate 110. The first electrode T92 of the second reset transistor T9 is connected to the second reset signal line Vref2. The second electrode T93 of the second reset transistor T9 is connected to the first electrode of the light emitting element OLED.

[0187] Specifically, the orthographic projection of the third scan line S3 on the substrate 110 partially overlaps with the orthographic projection of the ninth channel region T91 on the substrate 110, forming the gate of the second reset transistor T9, and the third scan signal on the third scan line S3 can control the turn-on timing of the second reset transistor T9. After the third scan signal on the third scan line S3 controls the second reset transistor T9 to turn on, the second reset transistor T9 transmits the second reset voltage on the second reset signal line Vref2 to the first electrode of the light-emitting element OLED, and resets the first electrode of the light-emitting element OLED.

[0188] Alternatively, if Figure 6 As shown, the second electrode of the light emitting element OLED is connected to the second power supply VSS. The first electrode of the light emitting element OLED is an anode, and the second electrode of the light emitting element OLED is a cathode; or the first electrode of the light emitting element OLED is a cathode, and the second electrode of the light emitting element OLED is an anode.

[0189] Optionally, refer to Fig.10 The orthographic projection of the second reset signal line Vref2 on the substrate 110 at least partially overlaps with the orthographic projection of the third scan line S3 on the substrate 110. This arrangement can reduce the space occupied by the array substrate in the first direction Y, which is beneficial to improving the pixel density of the display panel formed by the array substrate.

[0190] Optionally, refer to Fig.10 , the array substrate further comprises:

[0191] The third connection line LA3 is located at a side of the film layer where the third scan line S3 is located away from the substrate 110 . The third connection line LA3 is connected between the first electrode T92 of the second reset transistor T9 and the second reset signal line Vref2 .

[0192] Specifically, the second reset signal line Vref2 is connected to the third connection line LA3, and the third connection line LA3 is connected to the first electrode T92 of the second reset transistor T9 through a via, so that the second reset transistor T9 can be connected to the second reset signal line Vref2 through the third connection line LA3.

[0193] Optionally, refer to Fig.10 and Fig.12 The third connection line LA3 and the second reset signal line Vref2 are arranged on the same layer. In this way, the third connection line LA3 and the second reset signal line Vref2 do not need to be connected through a via hole, which can reduce the number of via holes and the space occupied by the third connection line LA3, which is conducive to improving the pixel density of the display panel formed by the array substrate.

[0194] Optionally, refer to Fig.12 The array substrate further includes a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3 which are stacked on the substrate 110;

[0195] The third scan line S3 is located on the first conductive layer M1, and the second reset signal line Vref2 and the third connection line LA3 are located on the third conductive layer M3. In this way, the number of wirings and electrodes on the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 is not large, and the occupied space of the pixel circuit 100 can be reduced.

[0196] In another embodiment, Fig.13 is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Fig.13 , the pixel circuit 100 further includes a second reset transistor T9 and a third reset transistor T10.

[0197] Optionally, refer to Figure 7 The active layer 120 also includes a ninth channel region T91 of the second reset transistor T9, a first electrode T92 of the second reset transistor T9, and a second electrode T93 of the second reset transistor T9; the active layer 120 also includes a tenth channel region T101 of the third reset transistor T10, a first electrode T102 of the third reset transistor T10, and a second electrode T103 of the third reset transistor T10.

[0198] Fig.14 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Fig.14 , the array substrate further comprises:

[0199] The third scan line S3 is located at a side of the active layer 120 away from the substrate 110 and extends along the second direction X. The orthographic projection of the third scan line S3 on the substrate 110 partially overlaps with the orthographic projection of the ninth channel region T91 on the substrate 110; the orthographic projection of the third scan line S3 on the substrate 110 partially overlaps with the orthographic projection of the tenth channel region T101 on the substrate 101;

[0200] The second reset signal line Vref2 is located at the side of the film layer where the third scan line S3 is located away from the substrate 110, the first electrode T92 of the second reset transistor T9 is connected to the second reset signal line Vref2, and the second electrode T93 of the second reset transistor T9 is connected to the first electrode of the light emitting element OLED;

[0201] The third reset signal line Vref3 is located on the side of the film layer where the second reset signal line Vref2 is located away from the substrate 110. The first electrode T102 of the third reset transistor T10 is connected to the third reset signal line Vref3. The second electrode T103 of the third reset transistor T10 is connected to the first electrode T72 of the first light-emitting control transistor T7.

[0202] Specifically, the orthographic projection of the third scan line S3 on the substrate 110 overlaps with the orthographic projection of the ninth channel region T91 on the substrate 110, and the orthographic projection of the third scan line S3 on the substrate 110 overlaps with the orthographic projection of the tenth channel region T101 on the substrate 101, so that the second reset transistor T9 and the third reset transistor T10 are connected to the same scan line (the third scan line S3), which can reduce the number of signal lines and is conducive to improving the pixel density of the display panel. When the third scan signal on the third scan line S3 controls the second reset transistor T9 and the third reset transistor T10 to turn on, the second reset transistor T9 transmits the second reset voltage on the second reset signal line Vref2 to the first electrode of the light-emitting element OLED, and resets the first electrode of the light-emitting element OLED. The third reset transistor T10 transmits the third reset voltage on the third reset signal line Vref3 to the first electrode T72 of the first light-emitting control transistor T7, and can transmit the third reset voltage to the first electrode of the driving transistor T1 through the second compensation transistor T3, and reset the first electrode of the driving transistor T1.

[0203] By arranging the third reset signal line Vref3 at a side of the film layer where the second reset signal line Vref2 is located away from the substrate 110, the third reset signal line Vref3 and the second reset signal line Vref2 are arranged in different layers, which can reduce the size in the first direction Y and is beneficial to improving the pixel density of the display panel.

[0204] Optionally, refer to Fig.14 , the array substrate further comprises:

[0205] A third connection line LA3 is located at a side of the film layer where the third scan line S3 is located away from the substrate 110 , and the third connection line LA3 is connected between the first electrode of the second reset transistor T9 and the second reset signal line Vref2 ;

[0206] The fourth connection line LA4 is located at a side of the film layer where the third scan line S3 is located away from the substrate 110 . The fourth connection line LA4 is connected between the second electrode of the third reset transistor T10 and the first electrode of the first light emitting control transistor T7 .

[0207] Specifically, the second reset signal line Vref2 is connected to the third connection line LA3 through a via, and the third connection line LA3 is connected to the first electrode T92 of the second reset transistor T9 through a via, so that the second reset transistor T9 can be connected to the second reset signal line Vref2 through the third connection line LA3.

[0208] The second electrode of the third reset transistor T10 is connected to the fourth connection line LA4 through a via, and the fourth connection line LA4 is connected to the first electrode of the first light-emitting control transistor T7 through a via, so that the second electrode of the third reset transistor T10 can be connected to the first electrode of the first light-emitting control transistor T7 through the fourth connection line LA4.

[0209] Optionally, refer to Fig.14 The third connection line LA3 and the fourth connection line LA4 are arranged in the same layer. This arrangement can reduce the film thickness of the array substrate, which is conducive to the lightweight design of the array substrate.

[0210] Optionally, refer to Fig.14 The orthographic projection of the third reset signal line Vref3 on the substrate 110 at least partially overlaps with the orthographic projection of the third scan line S3 on the substrate 110. This arrangement can reduce the space occupied by the array substrate in the first direction Y, which is beneficial to improving the pixel density of the display panel formed by the array substrate.

[0211] Fig.15 yes Fig.14 A cross-sectional view along the direction e1-e2, optionally, referring to Fig.15 The array substrate further includes a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3 which are stacked on the substrate 110;

[0212] The third scan line S3 is located on the first conductive layer M1, the second reset signal line Vref2 is located on the second conductive layer M2, and the third reset signal line Vref3, the third connection line LA3 and the fourth connection line LA4 are located on the third conductive layer M4. In this way, the number of wirings and electrodes on the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 will not be too large, and the occupied space of the pixel circuit 100 can be reduced.

[0213] An embodiment of the present invention further provides a display panel, Fig.16 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.16 As shown, the display panel includes the array substrate provided by any of the above embodiments. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc. The display panel includes the array substrate provided by any embodiment of the present invention, and thus has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here.

[0214] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: At least one pixel circuit is provided in the array substrate, and the pixel circuit includes a driving transistor, a first compensation transistor and a second compensation transistor; wherein the first compensation transistor is located in a data writing branch in the pixel circuit, and the second compensation transistor is located in a light emitting branch in the pixel circuit; The array substrate comprises: substrate; An active layer is located on one side of the substrate; the active layer includes a first channel region of the driving transistor, a second channel region of the first compensation transistor, and a third channel region of the second compensation transistor; the first channel region, the second channel region, and the third channel region are connected; and the width-to-length ratio of the second channel region is the same as the width-to-length ratio of the third channel region.

2. The array substrate according to claim 1, characterized in that: The width of the second channel region is the same as the width of the third channel region, and the length of the second channel region is the same as the length of the third channel region; wherein the second channel region and the third channel region are arranged along a first direction; the first channel region and the second channel region are arranged along a second direction; and the first direction intersects with the second direction; Preferably, the width of the first channel region, the width of the second channel region and the width of the third channel region are the same; The length of the middle line between the first boundary line and the second boundary line of the first channel region is the length of the first channel region, and the width direction of the first channel region is perpendicular to the middle line; wherein the first boundary line and the second boundary line are arranged along the first direction, and the distance between the first boundary line and the middle line is the same as the distance between the second boundary line and the middle line.

3. The array substrate according to claim 1 or 2, characterized in that: The array substrate further includes: A first conductive layer is located on a side of the active layer away from the substrate; the gate of the driving transistor, the gate of the first compensation transistor and the gate of the second compensation transistor are located in the first conductive layer, and the gate of the driving transistor, the gate of the first compensation transistor and the gate of the second compensation transistor are connected.

4. The array substrate according to claim 1, characterized in that: The pixel circuit further includes a data writing transistor; the active layer further includes a fourth channel region of the data writing transistor; The array substrate further includes: A first scanning line is located at a side of the active layer away from the substrate; an orthographic projection of the first scanning line on the substrate overlaps with an orthographic projection of the fourth channel region on the substrate; Preferably, the active layer further comprises a first electrode of the data writing transistor and a second electrode of the data writing transistor, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the first compensation transistor; The active layer further includes a first electrode of the first compensation transistor and a second electrode of the first compensation transistor, and the active layer further includes a first electrode of the driving transistor; the second electrode of the first compensation transistor is connected to the first electrode of the driving transistor; The active layer further includes a first electrode of the second compensation transistor and a second electrode of the second compensation transistor, the first electrode of the second compensation transistor is connected to a power line, and the second electrode of the second compensation transistor is connected to the first electrode of the driving transistor; Preferably, the array substrate further includes: The first conductive layer is located on a side of the active layer away from the substrate; the first scanning line is located on the first conductive layer.

5. The array substrate according to claim 4, characterized in that: The pixel circuit further includes a threshold compensation transistor; the active layer further includes a fifth channel region, a first electrode of the threshold compensation transistor and a second electrode of the threshold compensation transistor; the active layer further includes a second electrode of the driving transistor; The orthographic projection of the first scanning line on the substrate partially overlaps with the orthographic projection of the fifth channel region on the substrate; The first electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the gate of the driving transistor; Preferably, the array substrate further includes: A first connecting line, located at a side of the first conductive layer away from the substrate, the first connecting line being connected between the second electrode of the threshold compensation transistor and the gate of the driving transistor; Preferably, the first scanning line comprises a main body portion and an extension portion; the main body portion extends along the second direction, and the extension portion extends along the first direction; A portion where the main body overlaps with the active layer forms a first gate of the threshold compensation transistor, and a portion where the extension overlaps with the active layer forms a second gate of the threshold compensation transistor.

6. The array substrate according to claim 5, characterized in that: The pixel circuit further includes a first reset transistor; the active layer further includes a sixth channel region of the first reset transistor, a first electrode of the first reset transistor, and a second electrode of the first reset transistor; The array substrate further includes: a second scanning line, located at a side of the active layer away from the substrate and extending along the second direction; an orthographic projection of the second scanning line on the substrate partially overlaps with an orthographic projection of the sixth channel region on the substrate; A first reset signal line, located at a side of the second scan line away from the substrate and extending along the second direction; A first electrode of the first reset transistor is connected to the first reset signal line, and a second electrode of the first reset transistor is connected to a second electrode of the threshold compensation transistor; Preferably, the array substrate further comprises: a second connection line, located at a first side of the film layer where the first reset signal line is located, away from the substrate, the second connection line being connected between the first reset signal line and the first electrode of the first reset transistor; Preferably, the sixth channel region includes a first sub-region and a second sub-region; The first sub-region is connected to the second sub-region and extends along the first direction, and is arranged along the second direction; The orthogonal projection of the second scan line on the substrate overlaps with the orthogonal projection of the first sub-region on the substrate to form a first gate of the first reset transistor, and the orthogonal projection of the second scan line on the substrate overlaps with the orthogonal projection of the second sub-region on the substrate to form a second gate of the first reset transistor; Preferably, the array substrate further includes: A second conductive layer is located on a side of the first conductive layer away from the substrate, and the first reset signal line is located on the second conductive layer; A third conductive layer is located on a side of the second conductive layer away from the substrate, and the first connecting line and the second connecting line are located in the third conductive layer; a fourth conductive layer, located at a side of the third conductive layer away from the substrate, wherein the data line and the power line are located in the fourth conductive layer; Preferably, the active layer comprises polycrystalline silicon semiconductor material.

7. The array substrate according to claim 1, characterized in that: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor; the active layer further includes a seventh channel region of the first light emission control transistor, a first electrode of the first light emission control transistor, and a second electrode of the first light emission control transistor; the active layer further includes an eighth channel region of the second light emission control transistor, a first electrode of the second light emission control transistor, and a second electrode of the second light emission control transistor; The array substrate further includes: a light emitting control line, located on a side of the active layer away from the substrate, wherein the orthographic projection of the light emitting control line on the substrate overlaps with the orthographic projection of the seventh channel region on the substrate, and the orthographic projection of the light emitting control line on the substrate overlaps with the orthographic projection of the eighth channel region on the substrate; a power line, located at a side of the film layer where the light emitting control line is located away from the substrate; a first electrode of the first light emitting control transistor is connected to a first electrode of the second compensation transistor, and a second electrode of the first light emitting control transistor is connected to the power line; The first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is connected to the first electrode of the light emitting element; Preferably, the pixel circuit further includes a storage capacitor, and the storage capacitor includes a first capacitor plate and a second capacitor plate; the gate of the driving transistor is reused as the first capacitor plate; Preferably, the array substrate further comprises a first conductive layer and a second conductive layer which are stacked on the substrate; the light emitting control line and the first capacitor plate are located in the first conductive layer, and the second capacitor plate is located in the second conductive layer; Preferably, the array substrate further comprises a power connection line, wherein the power connection line is connected between the second capacitor plate and the power line; Preferably, the power connection line is arranged on the same layer as the second capacitor plate.

8. The array substrate according to claim 1, characterized in that: The pixel circuit further includes a second reset transistor; the active layer further includes a ninth channel region of the second reset transistor, a first electrode of the second reset transistor, and a second electrode of the second reset transistor; The array substrate further includes: a third scanning line, located at a side of the active layer away from the substrate and extending along the second direction, wherein an orthographic projection of the third scanning line on the substrate partially overlaps an orthographic projection of the ninth channel region on the substrate; A second reset signal line is located at a side of the film layer where the third scan line is located away from the substrate, a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to the first electrode of the light emitting element; Preferably, the orthographic projection of the second reset signal line on the substrate at least partially overlaps with the orthographic projection of the third scan line on the substrate; Preferably, the array substrate further includes: A third connecting line is located at a side of the film layer where the third scanning line is located away from the substrate, and the third connecting line is connected between the first electrode of the second reset transistor and the second reset signal line; Preferably, the third connecting line and the second reset signal line are arranged on the same layer; Preferably, the array substrate further comprises a first conductive layer, a second conductive layer and a third conductive layer which are located on the substrate and are stacked; The third scan line is located in the first conductive layer, and the second reset signal line and the third connection line are located in the third conductive layer.

9. The array substrate according to claim 7, characterized in that: The pixel circuit further includes a second reset transistor and a third reset transistor; the active layer further includes a ninth channel region of the second reset transistor, a first electrode of the second reset transistor, and a second electrode of the second reset transistor; the active layer further includes a tenth channel region of the third reset transistor, a first electrode of the third reset transistor, and a second electrode of the third reset transistor; The array substrate further includes: a third scanning line, located at a side of the active layer away from the substrate and extending along the second direction, wherein an orthographic projection of the third scanning line on the substrate overlaps with an orthographic projection of the ninth channel region on the substrate; and an orthographic projection of the third scanning line on the substrate overlaps with an orthographic projection of the tenth channel region on the substrate; A second reset signal line is located at a side of the film layer where the third scan line is located away from the substrate, a first electrode of the second reset transistor is connected to the second reset signal line, and a second electrode of the second reset transistor is connected to the first electrode of the light emitting element; a third reset signal line, located at a side of the film layer where the second reset signal line is located away from the substrate, a first electrode of the third reset transistor being connected to the third reset signal line, and a second electrode of the third reset transistor being connected to a first electrode of the first light emission control transistor; Preferably, the array substrate further includes: A third connecting line is located at a side of the film layer where the third scanning line is located away from the substrate, and the third connecting line is connected between the first electrode of the second reset transistor and the second reset signal line; a fourth connecting line, located at a side of the film layer where the third scanning line is located away from the substrate, the fourth connecting line being connected between the second electrode of the third reset transistor and the first electrode of the first light emitting control transistor; Preferably, the third connecting line and the fourth connecting line are arranged in the same layer; Preferably, the orthographic projection of the third reset signal line on the substrate at least partially overlaps with the orthographic projection of the third scan line on the substrate; Preferably, the array substrate further comprises a first conductive layer, a second conductive layer and a third conductive layer which are located on the substrate and are stacked; The third scan line is located in the first conductive layer, the second reset signal line is located in the second conductive layer, and the third reset signal line, the third connecting line and the fourth connecting line are located in the third conductive layer.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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