Display panel and display device

Abstract

The invention relates to a display panel and a display device, the display panel comprises a plurality of pixel circuit groups arranged in multiple rows and multiple columns, and each pixel circuit group comprises a plurality of sub-pixel circuits arranged along a first direction. The display panel comprises a first wiring layer and a second wiring layer which are arranged in a stacked mode. The first wiring layer comprises a plurality of first direction signal lines extending in the first direction, the first direction signal lines comprise first direction power lines and first direction initialization lines, and the second wiring layer comprises a plurality of second direction signal lines extending in the second direction. The plurality of second direction signal lines comprise second direction power lines and second direction initialization lines, and the second direction initialization lines and the first direction initialization lines are mutually connected to form net-shaped initialization signal lines; and in the same pixel circuit group, the sub-pixel circuits and the second direction signal lines are arranged in a one-to-one correspondence manner. The display uniformity of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the display panel, each pixel unit includes a plurality of sub-pixels that emit light of multiple colors, and each sub-pixel of each pixel unit needs to be driven by a sub-pixel circuit. The sub-pixel circuit may have a scan line, a data line, a power line, etc. At the same time, when the display panel displays frame by frame, the brightness of the same sub-pixel in different frames needs to be different. In order to prevent the previous frame data from affecting the display of the next frame, it is usually necessary to set an initialization line in the sub-pixel circuit to provide an initialization voltage Vref for the gate of the driving transistor and / or the anode of the light-emitting sub-pixel.

[0003] The initialization voltage Vref is very important for low grayscale display. However, since there is current during initialization, and the initialization line providing the initialization voltage Vref in the related art has a large resistivity, it is easy to generate a voltage drop on the initialization line. Therefore, the initialization voltage Vref in different places is different, which easily leads to obvious differences in the display effect. Summary of the invention

[0004] Based on this, the present application provides a high-quality display panel and a display device capable of improving display uniformity.

[0005] A display panel, comprising:

[0006] A plurality of pixel circuit groups arranged in a plurality of rows and columns, wherein the pixel circuit groups include a plurality of sub-pixel circuits arranged along a first direction;

[0007] A first wiring layer and a second wiring layer are stacked, the first wiring layer includes a plurality of first direction signal lines arranged along a second direction and extending along the first direction for forming a mesh signal line, and the plurality of first direction signal lines include a first direction power line and a first direction initialization line, the second wiring layer includes a plurality of second direction signal lines arranged along the first direction and extending along the second direction for forming a mesh signal line, and the plurality of second direction signal lines include a second direction power line and a second direction initialization line, the second direction power line and the first direction power line are connected to each other to form a mesh power signal line, and the second direction initialization line and the first direction initialization line are connected to each other to form a mesh initialization signal line;

[0008] Furthermore, in the same pixel circuit group, the sub-pixel circuits and the second direction signal lines are arranged in a one-to-one correspondence.

[0009] In one embodiment, the resistivity of the second wiring layer is less than or equal to the resistivity of the first wiring layer.

[0010] In one of the embodiments, in the same pixel circuit group, at least one sub-pixel circuit is arranged in one-to-one correspondence with the second direction initialization line, and the remaining sub-pixel circuits are arranged in one-to-one correspondence with the second direction power supply lines.

[0011] In one embodiment, in different pixel circuit groups, sub-pixel circuits for driving sub-pixels of the same color are arranged corresponding to the second direction signal lines providing the same voltage.

[0012] In one of the embodiments, in the pixel circuit group, a sub-pixel circuit for driving a light-emitting sub-pixel with the highest light-emitting efficiency is arranged corresponding to the second direction initialization line.

[0013] In one embodiment, the pixel circuit group includes a first sub-pixel circuit for driving a first sub-pixel, a second sub-pixel circuit for driving a second sub-pixel, and a third sub-pixel circuit for driving a third sub-pixel, the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit in the same pixel circuit group are arranged in sequence along the first direction, the second sub-pixel circuit is arranged corresponding to the second direction initialization line, and the first sub-pixel circuit and the third sub-pixel circuit are both arranged corresponding to the second direction power supply line;

[0014] Preferably, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0015] In one embodiment, the width of the second-direction power line in the first direction is a first preset width, and the first preset width is greater than 2 μm;

[0016] Preferably, the sum of the widths of all the second-direction power lines corresponding to the same pixel circuit group in the first direction is a second preset width, and the second preset width is greater than 4.5 μm.

[0017] In one embodiment, the display panel further comprises a substrate, the first wiring layer and the second wiring layer are spaced apart in a thickness direction of the substrate, and the second wiring layer is located on a side of the first wiring layer away from the substrate;

[0018] Preferably, the first direction is a row direction, and the second direction is a column direction.

[0019] In one embodiment,

[0020] The first direction power line includes a first direction positive power line for transmitting a positive power voltage, the second direction power line includes a second direction positive power line for transmitting the positive power voltage, and the second direction positive power line and the first direction positive power line are interconnected to form a meshed positive power signal line; and / or,

[0021] The first direction power line includes a first direction negative power line for transmitting a negative power supply voltage, the second direction power line includes a second direction negative power line for transmitting the negative power supply voltage, and the second direction negative power line and the first direction negative power line are interconnected to form a meshed negative power signal line; and / or,

[0022] The first direction initialization line includes a first direction initialization line 1 for transmitting a first initialization voltage, the second direction initialization line includes a second direction initialization line 1 for transmitting the first initialization voltage, and the second direction initialization line 1 and the first direction initialization line 1 are interconnected to form a first mesh initialization signal line; and / or,

[0023] The first direction initialization line includes a first direction initialization line 2 for transmitting a second initialization voltage, the second direction initialization line includes a second direction initialization line 2 for transmitting the second initialization voltage, the second direction initialization line 2 and the first direction initialization line 2 are interconnected to form a second mesh initialization signal line, and the first initialization voltage is different from the second initialization voltage.

[0024] A display device comprises the above-mentioned display panel.

[0025] In the display panel and the display device, the signal lines (second direction power lines and first direction power lines) for providing power supply voltage and the signal lines (second direction initialization lines and first direction initialization lines) for providing initialization voltage are both designed as mesh line structures. The total impedance is reduced after the first direction initialization lines located in the first wiring layer and the second direction initialization lines located in the second wiring layer are connected in parallel, thereby reducing the impedance on the signal lines providing the initialization voltage, which is beneficial to improving display uniformity.

[0026] At the same time, in the present application, in the same pixel circuit group, sub-pixel circuits are arranged in a one-to-one correspondence with the second direction signal lines, and different sub-pixel circuits are arranged in a corresponding manner with different second direction signal lines.

[0027] The special feature of the present application is that a second direction initialization line is designed at a certain sub-pixel circuit position, and the corresponding second direction power line is cancelled. At this time, it can effectively ensure that there is sufficient spacing between the second direction signal lines, thereby effectively preventing line defects from being generated on the second direction signal lines, thereby effectively improving the product yield, and at the same time realizing a low resistance design of the initialized signal line. Therefore, the present application can effectively provide a high-quality display panel with uniform display. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A partial structural plan view of a display panel in the related art;

[0030] Figure 2 is a partial structural plan view of a display panel in an embodiment of the present application;

[0031] Figure 3 Schematic diagram of a 7T1C sub-pixel circuit in an embodiment of the present application;

[0032] Figures 4 to 10 It is a partial structural plan view of a display panel in other different embodiments of the present application.

[0033] Description of reference numerals:

[0034] 100-pixel circuit group, 110-sub-pixel circuit, 210-first direction signal line, 211-first direction power line, 2111-first direction positive power line, 2112-first direction negative power line, 212-first direction initialization line, 2121-first direction initialization line one, 2122-first direction initialization line two, 220-second direction signal line, 221-second direction power line, 2211-second direction positive power line, 2212-second direction negative power line, 222-second direction initialization line, 2221-second direction initialization line one, 2222-second direction initialization line two, 300-connection hole. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0038] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0039] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0040] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0041] When a statement such as "at least one (of)..." is located after a list of elements, it modifies the entire list of elements rather than the individual elements in the list. The term "and / or" as used herein includes any and all combinations of one or more related listed items. As used in the application documents, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0042] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present application concepts described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and an emission driver) can be implemented using any appropriate hardware, firmware (for example, a dedicated integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard storage device (for example, such as a random access memory RAM). The computer program instructions can also be stored in other non-temporary computer-readable media (for example, such as CD-ROMs, flash drives, etc.). Moreover, those skilled in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the concepts of the present application.

[0043] As mentioned in the background art, the initialization line provided in the related art has a large resistivity, so it is easy to generate a voltage drop on the initialization line. Therefore, the initialization voltages in different places are different, which easily leads to obvious differences in display effects.

[0044] For example, see Figure 1In the display panel of the related art, power lines (first direction positive power line 2111, second direction positive power line 2211) extending in different directions for providing positive power voltage VDD are usually provided in two wiring layers (first wiring layer and second wiring layer). At the same time, the positive power lines in the two wiring layers can be connected to each other through the connection holes 300, thereby forming a mesh line structure.

[0045] The initialization line for providing the initialization voltage Vref is arranged in one of the two wiring layers (the first wiring layer), and the resistivity of the wiring layer provided with the initialization line is relatively large, so that a voltage drop is easily generated on the initialization line, resulting in uneven display.

[0046] Understandably, Figure 1 The figure shows the wiring design of a pixel circuit group 100 in the display panel, but the actual display panel may be provided with multiple pixel circuit groups 100 arranged in multiple rows and columns. The pixel circuit groups 100 in the same row share the same initialization line, which may cause uneven display between pixel units driven by pixel circuit groups 100 in different positions in the same row.

[0047] At the same time, in the related art, there is also a method of designing the initialization line that provides the initialization voltage Vref into a mesh line structure. However, at the same time, on the second wiring layer, both the initialization line and the power line are designed for the same sub-pixel circuit, which will cause the distance between the signal lines to decrease and the line defects to increase, thereby affecting the yield of the product. The special feature of this application is that a second direction initialization line is designed at a certain sub-pixel circuit position, and the corresponding second direction power line is cancelled, realizing the mesh structure design of the initialization signal line and the power line, while avoiding the increase of wiring density and improving the yield of the product.

[0048] Based on this, the present application provides a high-quality display panel and a display device that improve display uniformity. In one embodiment, a display panel is provided, comprising a plurality of pixel circuit groups. The plurality of pixel circuit groups are arranged in multiple rows and columns. For example, the pixel circuit groups can be arranged in an array.

[0049] See also Figure 2 , the pixel circuit group 100 includes a plurality of sub-pixel circuits 110 arranged along a first direction.

[0050] The pixel circuit group 100 can be used to drive the light-emitting pixel group. The multiple sub-pixel circuits 110 in the pixel circuit group 100 can be used to drive multiple light-emitting sub-pixels in the light-emitting pixel group that emit light of different colors. As an example, the pixel circuit group 100 may include a sub-pixel circuit R for driving a red sub-pixel that emits red light, a sub-pixel circuit G for driving a green sub-pixel that emits green light, and a sub-pixel circuit B for driving a blue sub-pixel that emits blue light.

[0051] As an example, the sub-pixel circuit may include, but is not limited to, Figure 3 The 7TIC circuit shown.

[0052] As an example, during the preparation of the display panel, a plurality of pixel circuit groups arranged in a plurality of rows and columns may be formed first, and then light-emitting sub-pixels may be formed on the pixel circuit groups.

[0053] Meanwhile, the display panel includes a first wiring layer and a second wiring layer stacked in layers. The materials of the first wiring layer and the second wiring layer may include but are not limited to metal materials. An interlayer dielectric layer may be provided between the second wiring layer and the first wiring layer.

[0054] As an example, the display panel further includes a substrate, the first wiring layer and the second wiring layer are spaced apart in a thickness direction of the substrate, and the second wiring layer is located on a side of the first wiring layer away from the substrate.

[0055] At this time, a first wiring layer may be formed on the substrate first, and then a second wiring layer may be formed on the first wiring layer. Further, the first wiring layer may be, for example, a second metal layer formed on the substrate, and the second wiring layer may be, for example, a third metal layer formed on the substrate.

[0056] See also Figure 2 The first wiring layer includes a plurality of first direction signal lines 210. The plurality of first direction signal lines 210 are arranged along the second direction and extend along the first direction.

[0057] Exemplarily, the first direction may be a row direction, and the second direction may be a column direction. At this time, the same first direction signal line 210 may be shared by the sub-pixel circuits 110 located in the same row. Of course, the first direction may also be a row direction, and the second direction may be a column direction. This is not limited here.

[0058] The first direction signal lines 210 are used to form a mesh signal line. The plurality of first direction signal lines 210 include a first direction power line 211 and a first direction initialization line 212 .

[0059] The first direction power line 211 is used to provide a power voltage Vpow. Figure 4 The first direction power line 211 may include a first direction positive power line 2111, and the first direction positive power line 2111 is used to transmit a positive power voltage VDD. The positive power voltage VDD can power the sub-pixel circuit. Alternatively, refer to Figure 5The first direction power line 211 may also include a first direction negative power line 2112, and the first direction negative power line 2112 is used to transmit a negative power voltage VSS. The negative power voltage VSS can supply power to the cathode of the light-emitting sub-pixel. Alternatively, the first direction power line 211 may also include a first direction positive power line 2111 and a first direction negative power line 2112 at the same time.

[0060] The first direction initialization line 212 is used to provide an initialization voltage Vref. Figure 6 The first direction initialization line 212 may include a first direction initialization line 2121, and the first direction initialization line 2121 is used to transmit a first initialization voltage Vref1. The first initialization voltage Vref1 may be used to initialize the gate of the driving transistor T1. Alternatively, refer to Figure 7 , the first direction initialization line 212 may also include a first direction initialization line 2122, and the first direction initialization line 2122 is used to transmit a second initialization voltage Vref2. The second initialization voltage Vref2 is used to initialize the anode of the light-emitting sub-pixel. The voltage of the second initialization voltage Vref2 may be different from that of the first initialization voltage Vref1. Alternatively, the first direction initialization line 212 may also include a first direction initialization line 1 2121 and a first direction initialization line 2122 at the same time. Alternatively, the first direction initialization line 212 may also only include a first direction initialization line 3 that transmits the same voltage, and the initialization line provides the initialization voltage Vref for the gate of the driving transistor T1 and / or the anode of the light-emitting sub-pixel.

[0061] The resistivity of the second wiring layer is less than or equal to the resistivity of the first wiring layer. Figure 2 The second wiring layer includes a plurality of second direction signal lines 220. The plurality of second direction signal lines 220 are arranged along the first direction and extend along the second direction.

[0062] For example, the first direction may be a row direction, and the second direction may be a column direction. In this case, the same second direction signal line 220 may be shared by the sub-pixel circuits 110 located in the same column.

[0063] The second direction signal lines 220 are used to form a mesh signal line. The plurality of second direction signal lines 220 include a second direction power line 221 and a second direction initialization line 222 .

[0064] The second direction power line 221 is used to provide a power voltage Vpow. Figure 4 The second direction power line 221 may include a second direction positive power line 2211, and the second direction positive power line 2211 is used to transmit a positive power voltage VDD. The positive power voltage VDD can power the sub-pixel circuit. Alternatively, refer to Figure 5The second direction power line 221 may also include a second direction negative power line 2212, and the second direction negative power line 2212 is used to transmit a negative power voltage VSS. The negative power voltage VSS can supply power to the cathode of the light-emitting sub-pixel. Alternatively, the second direction power line 221 may also include a second direction positive power line 2211 and a second direction negative power line 2212 at the same time.

[0065] The second direction initialization line 222 is used to provide an initialization voltage. Figure 6 The second direction initialization line 222 may include a second direction initialization line 2221, and the second direction initialization line 2221 is used to transmit a first initialization voltage Vref1. The first initialization voltage Vref1 may be used to initialize the gate of the driving transistor T1. Alternatively, refer to Figure 7 , the second direction initialization line 222 may also include a second direction initialization line 2222, and the second direction initialization line 2222 is used to transmit a second initialization voltage Vref2. The second initialization voltage Vref2 is used to initialize the anode of the light-emitting sub-pixel. Alternatively, the second direction initialization line 222 may also include a second direction initialization line 1 2221 and a second direction initialization line 2 2222 at the same time. Alternatively, the second direction initialization line 222 may also only include a second direction initialization line 3 that provides the same voltage, and the initialization line may provide the initialization voltage Vref for the gate of the driving transistor T1 and / or the anode of the light-emitting sub-pixel.

[0066] See also Figure 2 The second direction power lines 221 and the first direction power lines 211 for providing the same power voltage are connected to each other to form a mesh power signal line. The second direction power lines 221 and the first direction power lines 211 forming the mesh power signal line can be electrically connected to each other at the intersection of the two through the connection holes 300 that penetrate the interlayer dielectric layer between the two. In addition, the second direction power lines 221 can be connected to each sub-pixel circuit in the corresponding pixel circuit group through interconnection holes and / or routing.

[0067] See also Figure 4 When the first direction power line 211 includes a first direction positive power line 2111 and the second direction power line 221 includes a second direction positive power line 2211, the second direction positive power line 2211 and the first direction positive power line 2111 can form a mesh positive power signal line.

[0068] See also Figure 5 When the first direction power line 211 includes a first direction negative power line 2112 and the second direction power line 221 includes a second direction negative power line 2212, the second direction negative power line 2212 and the first direction negative power line 2112 can form a mesh negative power signal line.

[0069] When the first direction power line 211 includes the first direction negative power line 2112, and the second direction power line 221 includes the second direction negative power line 2212, the conventional circuit design for providing the negative power voltage VSS to the cathode can be changed to a planar design, and the cathode can be supplied with power through the frame area outside the display area. In this case, the cathode can be supplied with power in the display area through the formation of a mesh negative power signal line, thereby reducing the impedance of the circuit for providing the negative power voltage VSS.

[0070] See also Figure 2 The second direction initialization line 222 and the first direction initialization line 212 for providing the same initialization voltage are connected to each other to form a mesh initialization signal line. Specifically, the second direction initialization line 222 and the first direction initialization line 212 forming the mesh initialization signal line can also be electrically connected to each other at the intersection of the two through the connection hole 300 that penetrates the interlayer dielectric layer between the two. In addition, the second direction initialization line 222 can be connected to each sub-pixel circuit in the corresponding pixel circuit group through an interconnection hole and / or a wiring.

[0071] See also Figure 6 When the first direction initialization line 212 includes the first direction initialization line 2121 and the second direction initialization line 222 includes the second direction initialization line 2221, the second direction initialization line 2221 and the first direction initialization line 2121 are interconnected to form a first mesh initialization signal line.

[0072] See also Figure 7 When the first direction initialization line 212 includes the second first direction initialization line 2122 and the second direction initialization line 222 includes the second second direction initialization line 2222, the second second direction initialization line 2222 and the first direction initialization line 2122 are interconnected to form a second mesh initialization signal line.

[0073] At the same time, the second direction signal line 220 and each sub-pixel circuit 110 in the pixel circuit group 100 are arranged along the first direction. In the same pixel circuit group 100, the sub-pixel circuit 110 and the second direction signal line 220 are arranged in a one-to-one correspondence, and different sub-pixel circuits 110 are arranged in correspondence with different second direction signal lines 220. Among them, the second direction signal line 220 includes a second direction power line 221 and a second direction initialization line 222. The second direction power line 221 can, for example, include a second direction positive power line 2211 and / or a second direction negative power line 2212. The second direction initialization line 222 can, for example, include a second direction initialization line 1 2221 and / or a second direction initialization line 2222.

[0074] In this embodiment, the signal lines (second direction power lines 221 and first direction power lines 211) for providing the power supply voltage Vpow and the signal lines (second direction initialization lines 222 and first direction initialization lines 212) for providing the initialization voltage Vref are both designed as mesh line structures. After the first direction initialization lines located in the first wiring layer and the second direction initialization lines located in the second wiring layer are connected in parallel, the total impedance is reduced, thereby reducing the impedance on the signal line providing the initialization voltage Vref, which is beneficial to improving display uniformity.

[0075] At the same time, in the present embodiment, in the same pixel circuit group 100, the sub-pixel circuits 110 are arranged in one-to-one correspondence with the second direction signal lines 220, and different sub-pixel circuits 110 are arranged in correspondence with different second direction signal lines 220. In this case, it can be effectively ensured that there is sufficient spacing between the second direction signal lines 220, so that line defects on the second direction signal lines 220 can be effectively prevented, thereby effectively improving the product yield. Therefore, the present embodiment can effectively provide a high-quality display panel with uniform display.

[0076] It should be noted that, in the same pixel circuit group 100, the sub-pixel circuits 110 and the second direction signal lines 220 are arranged in a one-to-one correspondence, which may mean that in the same pixel circuit group 100, each sub-pixel circuit 110 and each second direction signal line 220 are arranged overlapping in a plan view (or the orthographic projections of the two on the substrate).

[0077] At the same time, it can be understood that when the first direction power line 211 includes the first direction positive power line 2111 and the second direction power line 221 includes the second direction positive power line 2211, since the number of columns of the sub-pixel circuit 110 in the display panel is usually large, even if the present embodiment is relatively Figure 1 The prior art shown has fewer second direction positive power lines 2211, but the impedance of the meshed positive power signal lines formed by the retained second direction positive power lines 2211 and the first direction positive power lines 2111 is still relatively small, and can still provide sufficient display uniformity.

[0078] In one embodiment, the resistivity of the second wiring layer is less than or equal to the resistivity of the first wiring layer. At this time, the first direction initialization line located in the first wiring layer can be connected in parallel with the second direction initialization line with a smaller resistivity, thereby better reducing the impedance on the signal line providing the initialization voltage Vref, which is more conducive to improving display uniformity.

[0079] In one embodiment, among the multiple sub-pixel circuits 110 of the same pixel circuit group 100, at least one sub-pixel circuit 110 is arranged in one-to-one correspondence with the second direction initialization line 222, and the remaining sub-pixel circuits 110 are arranged in one-to-one correspondence with the second direction power supply line 221. That is, among the multiple sub-pixel circuits 110 of the same pixel circuit group 100, each sub-pixel circuit 110 of at least one sub-pixel circuit 110 is arranged to overlap with each second direction initialization line 222 in a plan view (or the orthographic projection of the two on the substrate), and each sub-pixel circuit 110 of the remaining sub-pixel circuits 110 is arranged to overlap with the second direction power supply line 221 in a plan view (or the orthographic projection of the two on the substrate).

[0080] That is, in the multiple sub-pixel circuits 110 of the same pixel circuit group 100, there are both sub-pixel circuits 110 corresponding to the second direction initialization line 222 and sub-pixel circuits 110 corresponding to the second direction power line 221. Therefore, the same pixel circuit group 100 may have both a signal line network for providing a power supply voltage Vpow (such as a positive power supply voltage VDD) and a signal line network for providing an initialization voltage Vref.

[0081] In this case, the display in each pixel circuit group 100 can be made more uniform.

[0082] Of course, in some embodiments, among the multiple sub-pixel circuits 110 in the same pixel circuit group 100, there may be only the sub-pixel circuit 110 corresponding to the second direction initialization line 222, or only the sub-pixel circuit 110 corresponding to the second direction power line 221. For example, the second direction power line 221 and the second direction initialization line 222 may be alternately arranged in each pixel circuit group arranged along the first direction. This application does not limit this.

[0083] In one embodiment, in different pixel circuit groups 100, sub-pixel circuits 110 for driving sub-pixels of the same color are arranged correspondingly to second direction signal lines 220 providing the same voltage. For example, in all pixel circuit groups 100, sub-pixel circuits 110 of the same color are arranged correspondingly to second direction signal lines 220 providing the same voltage.

[0084] As an example, see Figure 8, the pixel circuit group 100 includes a sub-pixel circuit R for driving a red sub-pixel, a sub-pixel circuit G for driving a green sub-pixel, and a sub-pixel circuit B for driving a blue sub-pixel. Then, the sub-pixel circuits R in all pixel circuit groups 100 can be arranged corresponding to the second direction positive power line 2211 providing the positive power voltage VDD; the sub-pixel circuits G in all pixel circuit groups 100 can be arranged corresponding to the second direction initialization line 222 (such as the second direction initialization line 1 2221 or the second direction initialization line 2222 or the second direction initialization line 2223) providing the initialization voltage Vref; and the sub-pixel circuits B in all pixel circuit groups 100 can be arranged corresponding to the second direction positive power line 2211 providing the positive power voltage VDD.

[0085] As another example, the pixel circuit group 100 includes a sub-pixel circuit R for driving a red sub-pixel, a sub-pixel circuit G for driving a green sub-pixel, a sub-pixel circuit B for driving a blue sub-pixel, and a sub-pixel circuit W for driving a white sub-pixel. Then, the sub-pixel circuits R in all pixel circuit groups 100 may be arranged corresponding to the first second direction initialization line 2221 providing the initialization voltage Vref1; the sub-pixel circuits G in all pixel circuit groups 100 may be arranged corresponding to the second direction initialization line 2222 providing the initialization voltage Vref2; the sub-pixel circuits B in all pixel circuit groups 100 may be arranged corresponding to the second direction positive power supply line 2211 providing the positive power supply voltage VDD; and the sub-pixel circuits W in all pixel circuit groups 100 may be arranged corresponding to the second direction negative power supply line 2212 providing the negative power supply voltage VSS.

[0086] At this time, the second direction power line 221 and the second direction initialization line 222 in the second direction signal line 220 can be periodically arranged according to the arrangement period of the sub-pixel circuit 110 in the pixel circuit group 100, so that the sub-pixel circuit 110 in each pixel circuit group 100 corresponds to the second direction power line 221 and the second direction initialization line 222 in the same way, thereby preventing different pixel circuit groups 100 from generating bright and dark dividing lines under low grayscale and low brightness conditions.

[0087] In other embodiments, in different pixel circuit groups 100, sub-pixel circuits 110 of the same color may also be arranged corresponding to second direction signal lines 220 providing different voltages. This application does not limit this.

[0088] In one embodiment, in the pixel circuit group 100 , the sub-pixel circuit 110 for driving the sub-pixel with the highest light-emitting efficiency is disposed corresponding to the second direction initialization line 222 .

[0089] As an example, see Figure 8The pixel circuit group 100 includes a first sub-pixel circuit for driving a first sub-pixel, a second sub-pixel circuit for driving a second sub-pixel, and a third sub-pixel circuit for driving a third sub-pixel. Vegetarian road.

[0090] The first sub-pixel circuit, the second sub-pixel circuit and the third sub-pixel circuit in the same pixel circuit group are arranged in sequence along the first direction.

[0091] The second sub-pixel circuit is a sub-pixel circuit 110 for driving a sub-pixel with the highest luminous efficiency. The second sub-pixel circuit is arranged corresponding to the second direction initialization line, and the first sub-pixel circuit and the third sub-pixel circuit are arranged corresponding to the second direction power supply line.

[0092] As an example, the first sub-pixel can be set as a red sub-pixel, the second sub-pixel can be set as a green sub-pixel, and the third sub-pixel can be set as a blue sub-pixel. Then, the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are respectively sub-pixel circuit R, sub-pixel circuit G, and sub-pixel circuit B. Among them, the green sub-pixel has the highest luminous efficiency. Then, the sub-pixel circuit G can be set to correspond to the second direction initialization line 222. The sub-pixel circuit R and the sub-pixel circuit B are both set to correspond to the second direction power supply line 221.

[0093] For the sub-pixel circuit 110 (such as sub-pixel circuit G) for driving the sub-pixel with the highest luminous efficiency, the current provided on the mesh power signal line that requires the power supply voltage Vpow (such as the positive power supply voltage VDD) is the smallest. Therefore, the sub-pixel circuit 110 is opposite to the second direction initialization line 222 for providing the initialization voltage Vref, but not to the second direction power supply line 221 for providing the power supply voltage Vpow, so that the second direction power supply line 221 has less influence on the display uniformity.

[0094] At the same time, the sub-pixel circuit 110 for driving the sub-pixel with the highest luminous efficiency is more sensitive to the initialization voltage Vref than other sub-pixel circuits 110. Therefore, by placing the sub-pixel circuit 110 opposite to the second direction initialization line 222 instead of the second direction power supply line 221, the initialization voltage Vref can be made more uniform in each pixel circuit group 100, thereby more effectively improving display uniformity.

[0095] Of course, in other embodiments, the sub-pixel circuit 110 with the highest luminous efficiency may be set to correspond to the second direction power supply line 221, and the remaining sub-pixel circuits 110 may be set to correspond to the second direction initialization line 222. Since the number of columns (or rows) of sub-pixel circuits 110 in the display panel is usually tens of thousands. Therefore, no matter which color of the sub-pixel circuit 110 is set to correspond to the second direction initialization line 222, the effect on the display uniformity is not significant and is acceptable. At the same time, in the same pixel circuit group 100, one or more sub-pixel circuits 110 may be set to correspond to the second direction initialization line 222. It can be set specifically according to actual needs.

[0096] For example, see Fig. 9 , the pixel circuit group 100 may also include four sub-pixel circuits arranged in sequence, namely, a sub-pixel circuit R for driving a red sub-pixel, a sub-pixel circuit G for driving a green sub-pixel, a sub-pixel circuit B for driving a blue sub-pixel, and a sub-pixel circuit G for driving a green sub-pixel. In this case, the sub-pixel circuit R or the sub-pixel circuit B may be arranged corresponding to the second direction initialization line 222. The sub-pixel circuit G may be arranged corresponding to the second direction positive power line 2211.

[0097] For example, see Fig.10 , the pixel circuit group 100 includes four sub-pixel circuits, namely, a sub-pixel circuit R for driving a red sub-pixel, a sub-pixel circuit G for driving a green sub-pixel, a sub-pixel circuit B for driving a blue sub-pixel, and a sub-pixel circuit G for driving a green sub-pixel, which are arranged in sequence. At this time, the sub-pixel circuit R for driving a red sub-pixel can be set to correspond to the first second direction initialization line 2221. The sub-pixel circuit B for driving a blue sub-pixel is set to correspond to the second direction initialization line 2222. And the two sub-pixel circuits G for driving a green sub-pixel are set to correspond to the second direction positive power supply line 2211.

[0098] In one embodiment, the width of the second direction power line 221 in the first direction is a first preset width.

[0099] When the second direction power line 221 is a second direction positive power line 2211, the first preset width may be, for example, greater than the width of the second direction positive power line 2211 extending along the second direction in the related art as shown in the figure and used to provide the positive power voltage VDD in the first direction. Figure 1 In the related art shown, each sub-pixel circuit 110 is disposed corresponding to a second direction positive power line 2211 extending along the second direction.

[0100] Exemplarily, the first preset width may be greater than 2 μm. The pixel density of the display panel may be, for example, 300-400 (eg, 350).

[0101] At this time, in the same pixel circuit group 100, at least one sub-pixel circuit 110 is not opposite to the second direction positive power line 2211, and at the same time, the width of the second direction positive power line 2211 for providing the positive power voltage VDD in the first direction can be set to a first preset width, which can reduce the impact of the reduction in the number of second direction positive power lines 2211 on the impedance of the mesh positive power signal line.

[0102] When the second direction power line 221 is the second direction negative power line 2212 , the principle is similar to that when the second direction power line 221 is the second direction positive power line 2211 , and will not be described in detail herein.

[0103] In one embodiment, the sum of the widths of all second-direction power lines 221 corresponding to the same pixel circuit group 100 in the first direction is the second preset width.

[0104] When the second direction power line 221 is a second direction positive power line 2211 , the second preset width may be the sum of the widths of the second direction positive power lines 2211 in the same pixel circuit group 100 in the related art as shown in the figure in the first direction.

[0105] Exemplarily, the second preset width may be greater than 4.5 μm, for example. The pixel density of the display panel may be, for example, 300-400 (eg, 350).

[0106] As an example, the pixel circuit group 100 includes a sub-pixel circuit R for driving a red sub-pixel, a sub-pixel circuit G for driving a green sub-pixel, and a sub-pixel circuit B for driving a blue sub-pixel. One of the sub-pixel circuits 110 is opposite to the second direction initialization line 222, and the other two sub-pixel circuits 110 are opposite to the second direction positive power line 2211. At this time, the width of the second direction positive power line 2211 can be increased by 50% relative to the width of the second direction positive power line 2211 in the related art as shown in the figure.

[0107] At this time, the total width of the second direction positive power lines 2211 in the same pixel circuit group 100 can be maintained unchanged, thereby further improving display uniformity.

[0108] When the second direction power line 221 is the second direction negative power line 2212 , the principle is similar to that when the second direction power line 221 is the second direction positive power line 2211 , and will not be described in detail herein.

[0109] In one embodiment, a typical example, the first direction is the row direction, the second direction is the column direction, and the sub-pixel circuits 110 are arranged in n rows and m columns, where m is greater than n. That is, the number of columns of the sub-pixel circuits 110 is greater than the number of rows. At this time, setting some sub-pixel circuits 110 to correspond to the second direction initialization lines 222 can make the second direction power supply lines 221 have less influence on display uniformity.

[0110] Of course, in other embodiments, m may also be less than or equal to n.

[0111] In one embodiment, the same sub-pixel circuit 110 is disposed corresponding to a first direction power line 211 and a first direction initialization line 212 .

[0112] Exemplarily, the first direction is the row direction, and the second direction is the column direction. At this time, the sub-pixel circuits 110 located in the same row can share the first direction power supply line 211 and the first direction initialization line 212 .

[0113] At this time, the first wiring layer provided with the first direction power line 211 and the first direction initialization line 212 can be the same as the related art shown in the figure, so that the setting of other lines (such as data lines, etc.) of the pixel circuit layer can be compatible with the related art.

[0114] Based on the same inventive concept, an embodiment of the present application further provides a display device (not shown), which includes the display panel in the above embodiment.

[0115] It can be understood that the display device in the embodiments of the present application can be an OLED display device, a QLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, or any other product or component with a display function, and the embodiments disclosed in the present application are not limited to this.

[0116] In the description of this specification, the description with reference to the terms "one embodiment", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0117] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel circuit groups arranged in a plurality of rows and columns, wherein the pixel circuit groups include a plurality of sub-pixel circuits arranged along a first direction; A first wiring layer and a second wiring layer are stacked, the first wiring layer includes a plurality of first direction signal lines arranged along a second direction and extending along the first direction for forming a mesh signal line, and the plurality of first direction signal lines include a first direction power line and a first direction initialization line, the second wiring layer includes a plurality of second direction signal lines arranged along the first direction and extending along the second direction for forming a mesh signal line, and the plurality of second direction signal lines include a second direction power line and a second direction initialization line, the second direction power line and the first direction power line are connected to each other to form a mesh power signal line, and the second direction initialization line and the first direction initialization line are connected to each other to form a mesh initialization signal line; Furthermore, in the same pixel circuit group, the sub-pixel circuits and the second direction signal lines are arranged in a one-to-one correspondence.

2. The display panel according to claim 1, characterized in that: The resistivity of the second wiring layer is less than or equal to the resistivity of the first wiring layer.

3. The display panel according to claim 1, characterized in that: In the same pixel circuit group, at least one sub-pixel circuit is arranged in one-to-one correspondence with the second direction initialization line, and the remaining sub-pixel circuits are arranged in one-to-one correspondence with the second direction power supply lines.

4. The display panel according to claim 3, characterized in that: In different pixel circuit groups, sub-pixel circuits for driving sub-pixels of the same color are arranged corresponding to the second direction signal lines providing the same voltage.

5. The display panel according to claim 3, characterized in that: The sub-pixel circuit corresponding to the light-emitting sub-pixel with the highest light-emitting efficiency in the pixel circuit group is arranged corresponding to the second direction initialization line.

6. The display panel according to claim 5, characterized in that: The pixel circuit group includes a first sub-pixel circuit for driving a first sub-pixel, a second sub-pixel circuit for driving a second sub-pixel, and a third sub-pixel circuit for driving a third sub-pixel. The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit in the same pixel circuit group are arranged in sequence along the first direction. The second sub-pixel circuit is arranged corresponding to the second direction initialization line. The first sub-pixel circuit and the third sub-pixel circuit are both arranged corresponding to the second direction power supply line. Preferably, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

7. The display panel according to claim 3, characterized in that: The width of the second-direction power line in the first direction is a first preset width, and the first preset width is greater than 2 μm; Preferably, the sum of the widths of all the second-direction power lines corresponding to the same pixel circuit group in the first direction is a second preset width, and the second preset width is greater than 4.5 μm.

8. The display panel according to claim 1, characterized in that: The display panel further includes a substrate, the first wiring layer and the second wiring layer are spaced apart in a thickness direction of the substrate, and the second wiring layer is located on a side of the first wiring layer away from the substrate; Preferably, the first direction is a row direction, and the second direction is a column direction.

9. The display panel according to claim 1, characterized in that: The first direction power line includes a first direction positive power line for transmitting a positive power voltage, the second direction power line includes a second direction positive power line for transmitting the positive power voltage, and the second direction positive power line and the first direction positive power line are interconnected to form a meshed positive power signal line; and / or, The first direction power line includes a first direction negative power line for transmitting a negative power supply voltage, the second direction power line includes a second direction negative power line for transmitting the negative power supply voltage, and the second direction negative power line and the first direction negative power line are interconnected to form a meshed negative power signal line; and / or, The first direction initialization line includes a first direction initialization line 1 for transmitting a first initialization voltage, the second direction initialization line includes a second direction initialization line 1 for transmitting the first initialization voltage, and the second direction initialization line 1 and the first direction initialization line 1 are interconnected to form a first mesh initialization signal line; and / or, The first direction initialization line includes a first direction initialization line 2 for transmitting a second initialization voltage, the second direction initialization line includes a second direction initialization line 2 for transmitting the second initialization voltage, the second direction initialization line 2 and the first direction initialization line 2 are interconnected to form a second mesh initialization signal line, and the first initialization voltage is different from the second initialization voltage.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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