Display panel and display device

Abstract

The present application discloses a display panel and a display device; the display panel includes a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel circuit connected to the light-emitting device, the pixel circuit includes a switching transistor, a driving transistor and a reset module connected to each other, the switching transistor is connected to a data signal line, the control end of the reset module is connected to a reset line, the reset line includes an overlapping portion overlapping with the data signal line, and at least two layers of insulating layers are arranged between the overlapping portion and the data signal line; the present application increases the spacing between the reset line and the data signal line by spacing the overlapping portion of the reset line overlapping with the data signal line and the data signal line by at least two layers of insulating layers, reduces the coupling capacitance between the reset line and the data signal line, improves the accuracy of the signal transmitted by the data signal line, and improves the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In related technologies, the pixel circuit of an OLED display panel includes a reset transistor for resetting some nodes, and the reset control line that controls the conduction of the reset transistor is usually overlapped with the data signal line, and the distance between the two in the thickness direction is small, which makes the coupling capacitance between the reset control line and the data signal line large, resulting in abnormal display of the display panel. Summary of the Invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] In a first aspect, the present application provides a display panel comprising a plurality of sub-pixels, each of the sub-pixels comprising a light-emitting device and a pixel circuit connected to the light-emitting device, the pixel circuit comprising:

[0007] a switching transistor connected to the data signal line;

[0008] a driving transistor connected to the switching transistor at a first control node; and

[0009] A reset module is connected to the driving transistor, and a control end of the reset module is connected to a reset line, wherein the reset line includes an overlapping portion overlapping the data signal line, and at least two insulating layers are arranged between the overlapping portion and the data signal line.

[0010] Optionally, the reset module includes a first reset transistor, the reset trace includes a first reset control line, the gates of the first reset transistor and the driving transistor are connected to a first reset node, and the gate of the first reset transistor is connected to the first reset control line;

[0011] Among them, the first reset control line includes a plurality of first line segments and a plurality of second line segments arranged alternately along a first direction, two adjacent first line segments are electrically connected to the second line segments, the first line segments and the second line segments are arranged in different layers, and at least two insulating layers are arranged between the second line segments and the data signal line.

[0012] Optionally, the reset module further includes a second reset transistor, the reset trace further includes a second reset control line, the second reset transistor and the anode of the light-emitting device are connected to a second reset node, and the gate of the second reset transistor is connected to the second reset control line;

[0013] Among them, the second reset control line includes a plurality of third line segments and a plurality of fourth line segments arranged alternately along the first direction, two adjacent third line segments are electrically connected to the fourth line segments, the third line segments and the fourth line segments are arranged in different layers, and at least two insulating layers are arranged between the fourth line segments and the data signal line.

[0014] Optionally, the length of the first line segment is greater than the length of the third line segment, and the length of the second line segment is less than the length of the fourth line segment.

[0015] Optionally, the first line segment and the third line segment are located on the surface of the same insulating film layer, and the second line segment and the fourth line segment are located on the surface of the same insulating film layer.

[0016] Optionally, in the thickness direction of the display panel, the distances between the first line segment and the third line segment and the film layer where the data signal line is located are smaller than the distances between the second line segment and the fourth line segment and the film layer where the data signal line is located.

[0017] Optionally, the display panel includes:

[0018] substrate;

[0019] A first gate layer is provided on one side of the base substrate;

[0020] a second gate layer, disposed on a side of the first gate layer away from the base substrate;

[0021] a first source-drain electrode layer, provided on a side of the second gate layer away from the base substrate;

[0022] a second source-drain electrode layer, provided on a side of the first source-drain electrode layer away from the base substrate;

[0023] The first line segment and the third line segment are located in the first gate layer, the second line segment and the fourth line segment are located in the first source-drain layer, and the data signal line is located in the second source-drain layer.

[0024] Optionally, the display panel includes a plurality of repeating units, each of the repeating units includes two pixel circuits arranged along a first direction, and the two data signal lines connected to the two pixel circuits in the repeating unit are provided on both sides of the repeating unit;

[0025] The display panel further includes a longitudinal potential line corresponding to the repeating unit and transmitting a high potential signal. The longitudinal potential line is electrically connected to the two pixel circuits in the repeating unit and at least partially overlaps with the two pixel circuits in the repeating unit.

[0026] Optionally, in two adjacent sub-pixels in the first direction, patterns of at least part of the film layers in the pixel circuits in the two adjacent sub-pixels are symmetrically arranged in the first direction.

[0027] In a second aspect, the present application also proposes a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0029] Figure 1 A simplified structural diagram of the display panel of this application;

[0030] Figure 2 This is an equivalent circuit diagram of a pixel circuit in the display panel of this application;

[0031] Figure 3 This is a schematic diagram of the film layer in the display panel of this application;

[0032] Figure 4 A diagram showing the film layer stacking of a sub-pixel in the display panel of this application;

[0033] Figure 5 for Figure 4 Structural diagram of the first gate layer;

[0034] Figure 6 for Figure 4 Structural diagram of the active layer in ;

[0035] Figure 7 for Figure 4 A stacking diagram of the first gate layer and the active layer;

[0036] Figure 8 for Figure 4 Structural diagram of the second gate layer;

[0037] Figure 9 for Figure 4 A stacking diagram of the first gate layer, the active layer and the second gate layer;

[0038] Figure 10 for Figure 4 A structural diagram of the first source and drain layer;

[0039] Figure 11 for Figure 4 A stacked diagram of the first gate layer, the active layer, the second gate layer and the first source and drain layer;

[0040] Figure 12 for Figure 4 A structural diagram of the second source and drain layer;

[0041] Figure 13 for Figure 4 A stacked diagram of the first gate layer, the active layer, the second gate layer, the first source and drain layer, and the second source and drain layer;

[0042] Figure 14 for Figure 4 Figure 2. Structure of the anode within a repeating unit. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0044] See also Figures 1 to 14 The present application provides a display panel 100 , which may include a display portion 200 and a gate circuit 300 located on one side of the display portion 200 , wherein the gate circuit 300 is used to input a control signal to the display portion 200 .

[0045] In this example, see Figure 1 The display unit 200 includes a plurality of sub-pixel PX columns 210, each sub-pixel PX column 210 includes a plurality of sub-pixels PX, each sub-pixel PX is provided with a light-emitting device EL and a pixel circuit PC connected to the light-emitting device EL, and the gate circuit 300 is used to input a gate control signal to the transistor in the pixel circuit PC.

[0046] In this embodiment, the display panel 100 also includes multiple data signal lines Data, and one pixel circuit PC is connected to one data signal line Data; for example, multiple pixel circuits PC in a column of sub-pixels PX column 210 can be connected to one or two data signal lines Data, and in this embodiment, multiple pixel circuits PC in a column of sub-pixels PX column 210 can be connected to one data signal line Data.

[0047] In this embodiment, the pixel circuit PC includes a switching transistor T2, a driving transistor T1 and a reset module RS, the switching transistor T2 is connected to the data signal line Data, the driving transistor T1 and the switching transistor T2 are connected to the first control node A, the reset module RS is connected to the driving transistor T1, and the control end of the reset module RS is connected to the reset line VI, the reset line VI includes an overlapping portion overlapping with the data signal line Data, and at least two insulating layers are arranged between the overlapping portion and the data signal line Data.

[0048] The present application increases the spacing between the reset line VI and the data signal line Data by spacing the overlapping portion of the reset line VI with the data signal line Data by at least two insulating layers, reduces the coupling capacitance between the reset line VI and the data signal line Data, improves the accuracy of the signal transmitted by the data signal line Data, and improves the display effect of the display panel 100.

[0049] It should be noted that the light-emitting device EL of the present application can be an organic light-emitting diode, Mini LED, MicroLED, a conventional-sized LED or other light-emitting source.

[0050] The technical solution of this application is now described in conjunction with specific embodiments.

[0051] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display portion 200 is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the region within the display panel 100 used for display functions, and contains a plurality of sub-pixels PX therein to implement these functions. The non-display area NA may be a border region of the display panel 100, and may contain functional components that assist the sub-pixels PX within the display area AA in performing display functions.

[0052] See also Figure 1The lower side of the display area AA is provided with a binding terminal 400. The binding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data line, thereby driving the display panel 100 to display the image. For example, the binding terminal 400 can be bonded to a chip or a chip-on-film to provide power and driving signals to the display panel 100.

[0053] In this embodiment, the gate circuit 300 is arranged in the non-display area NA, and the gate circuit 300 can be arranged on both sides of the display area AA; the gate circuit 300 may include multiple cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0054] In this embodiment, a plurality of light-emitting devices EL and a pixel circuit PC for driving the light-emitting devices EL may be arranged in an array in the display area AA. The pixel circuit PC may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C or other pixel circuit PC. The following embodiment uses a 7T1C pixel circuit PC as an example for description.

[0055] See also Figure 2 The pixel circuit PC may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first light-emitting transistor T5, a second light-emitting transistor T6, and a storage capacitor Cst, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0056] See also Figure 2, the drain of the switching transistor T2 is connected to the data signal line Data, the source of the switching transistor T2 is connected to the first control node A, and the switch gate T2G of the switching transistor T2 is connected to the first control line Scan1; the drain of the driving transistor T1 is connected to the first control node A, the source of the driving transistor T1 is connected to the second control node B, and the drive gate T1G of the driving transistor T1 is connected to the first reset node Q; the drain of the compensation transistor T3 is connected to the first reset node Q, the source of the compensation transistor T3 is connected to the second control node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control line Scan1; the drain of the first reset transistor T4 is connected to the first reset line Vi1, the source of the first reset transistor T4 is connected to the first reset node Q, and the gate T4G of the first reset transistor T4 is connected to the first reset control line Scan2; the drain of the second reset transistor T7 is connected to The first light emitting transistor T5 is connected to the second reset line Vi2, the source of the second reset transistor T7 is connected to the second reset node P, that is, the anode of the light emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the second reset control line Scan3; the drain of the first light emitting transistor T5 is connected to the high potential line VDD, the source of the first light emitting transistor T5 is connected to the first control node A, and the first light emitting gate T5G of the first light emitting transistor T5 is connected to the light emitting control line EM; the drain of the second light emitting transistor T6 is connected to the second control node B, the source of the second light emitting transistor T6 is connected to the anode of the light emitting device EL, and the second light emitting gate T6G of the second light emitting transistor T6 is connected to the light emitting control line EM; the first plate Cst1 of the storage capacitor Cst is connected to the first reset node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; and the cathode of the light emitting device EL is connected to the low potential line VSS.

[0057] It should be noted that the switch transistors T2 in different sub-pixels PX are connected to different data signal lines, and this application only takes one of them as an example for description.

[0058] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel circuit PC, and the low potential line VSS is used to provide a constant low voltage level to the pixel circuit PC.

[0059] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 can be one of P-type transistors or N-type transistors; this application is described as an example in which the switching transistor T2, the driving transistor T1, the second reset transistor T7, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 are all P-type transistors.

[0060] In this embodiment, the source is only the output end of the present application, and the drain is only the input end of the present application, and the two are only distinguished in name.

[0061] In the following embodiments, the first direction is perpendicular to the extending direction of the data signal line Data, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction and the second direction Y is the vertical direction.

[0062] The following is for Figure 2 The structure of the pixel circuit PC of this application is described.

[0063] See also Figure 3 The display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer PDL disposed on the array drive layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE disposed on the pixel definition layer PDL. The following primarily describes the film layer structure within the display area AA.

[0064] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0065] In this embodiment, the base substrate 110 is used to support the various film layers provided thereon. The base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0066] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0067] See also Figure 3The array driving layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, and other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 3 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of the various film layers of the display panel 100 of the present application.

[0068] See also Figure 3 The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, an active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, an inter-insulating layer 128 disposed on the second gate layer 127, a first source-drain electrode layer 129 disposed on the inter-insulating layer 128, a first planarizing layer 130 disposed on the first source-drain electrode layer 129, a second source-drain electrode layer 131 disposed on the first planarizing layer 130, a second planarizing layer 132 disposed on the second source-drain electrode layer 131, a light-emitting device layer and a pixel definition layer PDL disposed on the second planarizing layer 132, and an encapsulation layer TFE disposed on the pixel definition layer PDL.

[0069] See also Figure 3 The light shielding layer 121 is provided on the second barrier layer 114 and is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0070] See also Figure 3 The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0071] In this embodiment, the light shielding layer 121 may also be embedded in the buffer layer 122 .

[0072] See also Figure 3 The material of the active layer 123 may be a silicon semiconductor. For example, in the present application, the material of the active layer 123 may be low-temperature polysilicon.

[0073] See also Figure 3The first gate insulating layer 124, the second gate insulating layer 126, and the inter-insulating layer 128 are respectively arranged on the corresponding metal layer or semiconductor layer, and are separated by different layers of metal layers or semiconductor layers; and the materials of the first gate insulating layer 124, the second gate insulating layer 126, and the inter-insulating layer 128 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0074] See also Figure 3 The first gate layer 125 and the second gate layer 127 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 127 can be copper, molybdenum, or molybdenum-titanium alloy.

[0075] See also Figure 3 The materials of the first source-drain electrode layer 129 and the second source-drain electrode layer 131 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal.

[0076] See also Figure 3 The first flat layer 130 and the second flat layer 132 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 130, the second flat layer 132 and the third flat layer 134 can be composed of inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0077] See also Figure 3 The light emitting device layer may include a plurality of light emitting devices EL, each of which includes an anode AN connected to a pixel circuit, a light emitting unit, and a cathode CA.

[0078] In this embodiment, the data signal line Data is usually arranged in the second source and drain layer 131, and the overlapping part of the reset line VI with the data signal line Data can be arranged in the film layer where the second gate layer 127, the first gate layer 125 or the light-shielding layer 121 is located, that is, the reset line VI of the present application is composed of two layers of wires arranged in different layers.

[0079] In this embodiment, the reset module RS may include only a first reset transistor T4, that is, the reset line VI includes a first reset control line Scan2, the gates of the first reset transistor T4 and the driving transistor T1 are connected to the first reset node Q, and the gate of the first reset transistor T4 is connected to the first reset control line Scan2; at the same time, the first reset control line Scan2 includes a plurality of first line segments LN1 and a plurality of second line segments LN2 alternately arranged along the first direction X, two adjacent first line segments LN1 and second line segments LN2 are electrically connected, the first line segment LN1 and the second line segment LN2 are arranged in different layers, and at least two insulating layers are arranged between the second line segment LN2 and the data signal line Data.

[0080] That is, the present application increases the spacing between the first reset control line Scan2 and the data signal line Data by setting the first reset control line Scan2 as the first line segment LN1 and the second line segment LN2 set in different layers, and sets at least two insulating layers between the second line segment LN2 and the data signal line Data, reduces the coupling capacitance between the first reset control line Scan2 and the data signal line Data, improves the accuracy of the signal transmitted by the data signal line Data, and improves the display effect of the display panel 100.

[0081] In this embodiment, the reset module RS may further include a second reset transistor T7, the reset trace VI also includes a second reset control line Scan3, the second reset transistor T7 and the anode AN of the light-emitting device EL are connected to the second reset node P, and the gate of the second reset transistor T7 is connected to the second reset control line Scan3; at the same time, the second reset control line Scan3 includes a plurality of third line segments LN3 and a plurality of fourth line segments LN4 alternately arranged along the first direction X, two adjacent third line segments LN3 and the fourth line segment LN4 are electrically connected, the third line segment LN3 and the fourth line segment LN4 are arranged in different layers, and at least two insulating layers are arranged between the fourth line segment LN4 and the data signal line Data.

[0082] That is, the present application increases the spacing between the second reset control line Scan3 and the data signal line Data by setting the second reset control line Scan3 as a third line segment LN3 and a fourth line segment LN4 that are set in different layers, and at least two insulating layers are set between the fourth line segment LN4 and the data signal line Data, thereby reducing the coupling capacitance between the second reset control line Scan3 and the data signal line Data, improving the accuracy of the signal transmitted by the data signal line Data, and improving the display effect of the display panel 100.

[0083] In this embodiment, the first line segment LN1 and the third line segment LN3 are located on the surface of the same insulating film layer, and the second line segment LN2 and the fourth line segment LN4 are located on the surface of the same insulating film layer.

[0084] In this embodiment, in the thickness direction of the display panel 100, the distances between the first line segment LN1 and the third line segment LN3 and the film layer where the data signal line Data is located are both smaller than the distances between the second line segment LN2 and the fourth line segment LN4 and the film layer where the data signal line Data is located; that is, the present application can increase the distance between the second line segment LN2 and the fourth line segment LN4 and the data signal line Data, while reducing the distance between the first line segment LN1 and the third line segment LN3 that are arranged non-overlapping with the data signal line Data, so as to facilitate wiring.

[0085] For example, the first line segment LN1 and the third line segment LN3 are located in the first gate layer 125, and the second line segment LN2 and the fourth line segment LN4 are located in the first source-drain layer 129, which is equivalent to the second gate insulation layer 126, the inter-insulation layer 128 and the first flat layer 130 being arranged between the second line segment LN2 and the data signal line Data, and the second gate insulation layer 126, the inter-insulation layer 128 and the first flat layer 130 being arranged between the fourth line segment LN4 and the data signal line Data.

[0086] See also Figure 4 The display panel 100 may include a plurality of repeating units RU, each of the repeating units RU including two pixel circuits PC arranged along a first direction X, and two data signal lines Data connected to the two pixel circuits PC in the repeating unit RU are arranged on both sides of the repeating unit RU; that is, two data signal lines Data are arranged between two adjacent repeating units RU, and no data signal line Data is arranged between two pixel circuits PC in the repeating unit RU, thereby reducing the distance between the two pixel circuits PC in the repeating unit RU.

[0087] In this embodiment, in two adjacent sub-pixels PX in the first direction X, patterns of at least a portion of the film layers in the pixel circuits PC in the two adjacent sub-pixels PX are symmetrically arranged in the first direction X.

[0088] In the following embodiments, the technical solution of the present application is described by taking the structure of each film layer in the first pixel circuit PC1 and the second pixel circuit PC2 in a repeating unit RU as an example.

[0089] See also Figure 4 and Figure 5 , Figure 4 FIG. 1 is a film layer stack diagram of a sub-pixel PX in the display panel 100 of the present application. Figure 5 for Figure 4 FIG. 1 is a structural diagram of the first gate layer 125 .

[0090] See also Figure 5 The patterns of the first pixel circuit PC1 and the second pixel circuit PC2 in the first gate layer 125 are symmetrically arranged in the first direction X.

[0091] See also Figure 5The first gate layer 125 includes a plurality of second line segments LN2, a plurality of fourth line segments LN4, and a plurality of light-emitting control segments EMa extending along the first direction X. The plurality of second line segments LN2 are arranged at intervals, the plurality of fourth line segments LN4 are arranged at intervals, and the plurality of light-emitting control segments EMa are arranged at intervals. The fourth line segments LN4, the second line segments LN2, and the light-emitting control segments EMa are arranged in sequence in the second direction Y. The second line segment LN2 is a partial line segment of the first reset control line Scan2, and the fourth line segment LN4 is a partial line segment of the second reset control line Scan3.

[0092] See also Figure 5 The first gate layer 125 further includes a first reset gate T4G, a switch gate T2G and a compensation gate T3G, the first reset gate T4G is electrically connected to the second line segment LN2, and the switch gate T2G and the compensation gate T3G are located between the light emitting control segment EMa and the second line segment LN2.

[0093] See also Figure 5 The first reset gate T4G includes a first transverse segment T4Ga, a second transverse segment T4Gb, and a first connecting segment CT1 connecting the first transverse segment T4Ga and the second transverse segment T4Gb, wherein the first connecting segment CT1 extends along the second direction Y, the first transverse segment T4Ga and the second transverse segment T4Gb extend along the first direction X, and the first transverse segment T4Ga is connected to the second line segment LN2.

[0094] See also Figure 5 The first gate layer 125 further includes a second connecting segment CT2 extending along the second direction Y, wherein one end of the second connecting segment CT2 away from the first reset gate T4G is connected to the compensation gate T3G and the switch gate T2G, and the compensation gate T3G includes a first compensation segment T3Ga and a second compensation segment T3Gb connected to each other, wherein one end of the first compensation segment T3Ga is connected to the second connecting segment CT2, and the other end of the first compensation segment T3Ga is connected to the second compensation segment T3Gb, and the first compensation segment T3Ga extends along the first direction X, and the second compensation segment T3Gb extends along the second direction Y.

[0095] See also Figure 5 The first gate layer 125 further includes a first plate Cst1 of a storage capacitor Cst, and the first plate Cst1 is located between the light emitting control segment EMa and the compensation gate T3G.

[0096] See also Figure 4 and Figure 6 , Figure 6 for Figure 4FIG. 1 is a structural diagram of the active layer 123 .

[0097] See also Figure 6 The patterns of the first pixel circuit PC1 and the second pixel circuit PC2 in the active layer 123 are symmetrically arranged in the first direction X.

[0098] See also Figure 6 The active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a driving active portion T1A of the driving transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a first reset active portion T4A of the first reset transistor T4, a second reset active portion T7A of the second reset transistor T7, a compensation active portion T3A of the compensation transistor T3, and an extension segment ET.

[0099] See also Figure 6 The switching active portion T2A, the second light emitting active portion T6A and the driving active portion T1A are connected to the first connection point N1, the driving active portion T1A, the extension segment ET and the first light emitting active portion T5A are connected to the second connection point N2, the second light emitting active portion T6A and the second reset active portion T7A are connected to the third connection point N3, the first reset active portion T4A and the compensation active portion T3A are connected to the fourth connection point N4, and the extension segment ET and the compensation active portion T3A are connected to the fifth connection point N5.

[0100] See also Figure 6 The switch active portion T2A, the first light emitting active portion T5A, the second light emitting active portion T6A, the second reset active portion T7A, and the first reset active portion T4A extend along the first direction X and are strip-shaped. The driving active portion T1A may be U-shaped, and the compensation active portion T3A may be L-shaped.

[0101] See also Figure 7 , Figure 7 for Figure 4 FIG. 1 is a stacked diagram of the first gate layer 125 and the active layer 123.

[0102] See also Figure 7 The light-emitting control segment EMa and the first light-emitting active portion T5A have an overlapping portion. The light-emitting control line EM in the overlapping portion is multiplexed as the first light-emitting gate T5G. The first light-emitting active portion T5A in the overlapping portion is the channel of the first light-emitting transistor T5. The end of the first light-emitting active portion T5A away from the second connection point N2 is multiplexed as the drain T5D of the first light-emitting transistor T5, and the end of the first light-emitting active portion T5A close to the second connection point N2 is multiplexed as the source T5S of the first light-emitting transistor T5. That is, the structure in the area where the second connection point N2 is located is the first control node A in the pixel circuit PC.

[0103] See also Figure 7 The light-emitting control segment EMa and the second light-emitting active portion T6A also have an overlapping portion. The light-emitting control line EM in the overlapping portion is multiplexed into the second light-emitting gate T6G. The second light-emitting active portion T6A in the overlapping portion is the channel of the second light-emitting transistor T6. The end of the second light-emitting active portion T6A away from the first connection point N1 is multiplexed into the source T6S of the second light-emitting transistor T6, and the end of the second light-emitting active portion T6A close to the first connection point N1 is multiplexed into the drain T6D of the second light-emitting transistor T6. That is, the structure of the area where the first connection point N1 is located is the second control node B in the pixel circuit PC, and the structure of the area where the third connection point N3 is located is the position connected to the anode AN in the pixel circuit PC, that is, the second reset node P of the present application.

[0104] See also Figure 7 The first reset gate T4G and the first reset active portion T4A have an overlapping portion. The first reset active portion T4A in the overlapping portion is the channel of the first reset transistor T4. An end of the first reset active portion T4A close to the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and an end of the first reset active portion T4A far from the second connection point N2 is multiplexed as the drain T4D of the first reset transistor T4. That is, the structure in the area where the fourth connection point N4 is located is the first reset node Q in the pixel circuit PC.

[0105] It should be noted that both the first transverse segment T4Ga and the second transverse segment T4Gb have overlapping portions with the first reset active portion T4A, which is equivalent to the first reset transistor T4 of the present application having two channels, and both the first transverse segment T4Ga and the second transverse segment T4Gb can serve as the gate of the first reset transistor T4. The first reset transistor T4 is equivalent to being composed of two transistors connected in series, thereby reducing the leakage current of the first reset transistor T4.

[0106] See also Figure 7 The fourth line segment LN4 and the second reset active portion T7A have an overlapping portion. The fourth line segment LN4 in the overlapping portion is multiplexed as the second reset gate T7G. The second reset active portion T7A in the overlapping portion is the channel of the second reset transistor T7. An end of the second reset active portion T7A close to the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7, and an end of the second reset active portion T7A far from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7. That is, the structure in the area where the fourth connection point N4 is located is the second reset node P in the pixel circuit PC.

[0107] See also Figure 7The switch gate T2G and the switch active portion T2A have an overlapping portion. The switch active portion T2A in the overlapping portion is the channel of the switch transistor T2. An end of the switch active portion T2A close to the second connection point N2 is multiplexed as the source T2S of the switch transistor T2, and an end of the switch active portion T2A far from the second connection point N2 is multiplexed as the drain T2D of the switch transistor T2.

[0108] See also Figure 7 The compensation active portion T3A includes a longitudinal segment T3Aa and a transverse segment T3Ab. The first compensation segment T3Ga and the longitudinal segment T3Aa have an overlapping portion, and the second compensation segment T3Gb and the transverse segment T3Ab have an overlapping portion. That is, the first compensation segment T3Ga and the second compensation segment T3Gb can both be the gate T3G of the compensation transistor T3, which is equivalent to the compensation transistor T3 having two channels. The compensation transistor T3 is equivalent to being composed of two series-connected transistors, which reduces the leakage current of the compensation transistor T3; at the same time, the end of the compensation active portion T3A close to the fourth connection point N4 is reused as the drain T3D of the compensation transistor T3, and the end of the compensation active portion T3A close to the second connection point N2 is reused as the source T3S of the compensation transistor T3.

[0109] See also Figure 4 、 Figure 8 and Figure 9 , Figure 8 for Figure 4 The structure diagram of the second gate layer 127, Figure 9 for Figure 4 FIG. 1 is a stacked diagram of the first gate layer 125, the active layer 123 and the second gate layer 127.

[0110] See also Figure 8 The patterns of the first pixel circuit PC1 and the second pixel circuit PC2 in the second gate layer 127 are symmetrically arranged in the first direction X.

[0111] See also Figure 8 The second gate layer 127 includes a second electrode plate Cst2 of the storage capacitor and a third connecting segment CT3, the third connecting segment CT3 extends along the first direction X, the third connecting segment CT3 is arranged on both sides of the second electrode plate Cst2, and two adjacent second electrode plates Cst2 are electrically connected through the third connecting segment CT3.

[0112] In this embodiment, the second electrode plate Cst2 is provided with a through hole HL0 , and the upper transmission line passes through the through hole HL0 and is connected to the first electrode plate Cst1 .

[0113] See also Figure 4 、 Figure 10 and Figure 11 , Figure 10 for Figure 4For a structural diagram of the first source / drain layer 129, please refer to Figure 11 , Figure 11 for Figure 4 FIG. 1 is a stacked diagram of the first gate layer 125 , the active layer 123 , the second gate layer 127 and the first source and drain layer 129 .

[0114] See also Figure 10 The patterns of the first pixel circuit PC1 and the second pixel circuit PC2 in the first source and drain electrode layer 129 are symmetrically arranged in the first direction X.

[0115] See also Figure 10 and Figure 11 The first source-drain layer 129 includes a third line segment LN3, a second reset line Vi2, a first reset line Vi1, a first line segment LN1, a first control line Scan1, a transverse potential line VD1, and a light-emitting control line EM, which are spaced apart and arranged in sequence along the second direction Y. The third line segment LN3, the second reset line Vi2, the first reset line Vi1, the first line segment LN1, the first control line Scan1, the transverse potential line VD1, and the light-emitting control line EM all extend along the first direction X. Two adjacent first line segments LN1 arranged along the first direction X are spaced apart, and two adjacent third line segments LN3 arranged along the first direction X are spaced apart.

[0116] In this embodiment, the light emitting control segment EMa and the light emitting control line EM are at least partially overlapped, and the transverse potential line VD1 and the first connecting segment CT1 are at least partially overlapped.

[0117] See also Figure 11 One end of the third line segment LN3 passes through the first via hole HL1 and is electrically connected to the fourth line segment LN4 of the first pixel circuit PC1, and the other end of the third line segment LN3 passes through the second via hole HL2 and is electrically connected to the fourth line segment LN4 of the second pixel circuit PC2; one end of the first line segment LN1 passes through the third via hole HL3 and is electrically connected to the first reset gate T4G of the first pixel circuit PC1 and the connection point of the second line segment LN2, and the other end of the first line segment LN1 passes through the fourth via hole HL4 and the first reset gate T4G of the second pixel circuit PC2 and is electrically connected to the other A connection point of the second line segment LN2 is electrically connected; an end of the second connection segment CT2 away from the compensation gate T3G passes through the fifth via HL5 and is electrically connected to the first control line Scan1; the horizontal potential line VD1 includes a first potential segment VD1a and a second potential segment VD1b connected to each other, the line width of the first potential segment VD1a is greater than the line width of the second potential segment VD1b, and the first potential segment VD1a passes through the sixth via HL6 and is electrically connected to the second electrode Cst2; the light-emitting control line EM passes through the seventh via HL7 and is electrically connected to the light-emitting control segment EMa.

[0118] See also Figure 11 The first source-drain layer 129 further includes a fourth connection segment CT4 located between the first control line Scan1 and the horizontal potential line VD1, one end of the fourth connection segment CT4 passes through the eighth via HL8 and is electrically connected to the data signal line Data, and the other end of the fourth connection segment CT4 passes through the ninth via HL9 and is electrically connected to an end of the switch active portion T2A away from the second connection point N2.

[0119] See also Figure 11 The first source-drain layer 129 further includes a fifth connection segment CT5 extending along the second direction Y and located between the first control line Scan1 and the horizontal potential line VD1. One end of the fifth connection segment CT5 passes through the tenth via HL10 and is electrically connected to the connection point between the first reset active portion T4A and the compensation active portion T3A. The other end of the fifth connection segment CT5 passes through the eleventh via HL11 and is connected to the first electrode plate Cst1 through the through hole HL.

[0120] See also Figure 11 One end of the first reset active portion T4A away from the fourth connection point N4 passes through the twelfth via HL12 and is electrically connected to the first control line Scan1, and one end of the second reset active portion T7A away from the third connection point N3 passes through the thirteenth via HL13 and is electrically connected to the second reset line Vi2.

[0121] See also Figure 11 The first source-drain layer 129 further includes a sixth connection segment CT6 and a seventh connection segment CT7, which are arranged on the side of the light-emitting control line EM away from the horizontal potential line VD1. The sixth connection segment CT6 connects the high potential line and an end of the first light-emitting active portion T5A away from the second connection point N2. The seventh connection segment CT7 connects the active portion in the area where the third connection point N3 is located and the anode AN of the light-emitting device EL.

[0122] In this embodiment, the first via HL1 and the second via HL2 can be arranged between the second reset active portion T7A in the two pixel circuits PC within the repeating unit RU, and the third via HL3 and the fourth via HL4 can be arranged on both sides of the first reset active portion T4A in the two pixel circuits PC within the repeating unit RU. Therefore, the length of the first line segment LN1 of the present application is greater than the length of the third line segment LN3, and the length of the second line segment LN2 is less than the length of the fourth line segment LN4.

[0123] See also Figure 4 、 Figure 12 and Figure 13 , Figure 12 for Figure 4The structure diagram of the second source and drain layer 131, Figure 13 for Figure 4 FIG. 1 is a stacked diagram of the first gate layer 125 , the active layer 123 , the second gate layer 127 , the first source-drain layer 129 and the second source-drain layer 131 .

[0124] See also Figure 12 The patterns of the first pixel circuit PC1 and the second pixel circuit PC2 in the second source / drain electrode layer 131 are symmetrically arranged in the first direction X.

[0125] See also Figure 12 and Figure 13 The second source-drain layer 131 includes data signal lines Data and longitudinal potential lines VD2 arranged at intervals along the first direction X, and both the data signal lines Data and the longitudinal potential lines VD2 extend along the second direction Y.

[0126] In this embodiment, the data signal line Data is electrically connected to the fourth connection segment CT4 through the eighth via HL8, the longitudinal potential line VD2 is electrically connected to the sixth connection segment CT6 through the fourteenth via HL14, and the longitudinal potential line VD2 is also electrically connected to the first potential segment VD1a through the fifteenth via HL15.

[0127] In this embodiment, the second source-drain layer 131 further includes an eighth connection segment CT8 arranged between the data signal line Data and the longitudinal potential line VD2, one end of the eighth connection segment CT8 is connected to the anode AN of the light-emitting device EL through a via hole, and the other end of the eighth connection segment CT8 is connected to the active part of the area where the seventh connection segment CT7 and the third connection point N3 are located through a via hole.

[0128] In this embodiment, the attached Figure 12 and attached Figure 13 The first pixel circuit PC1 and the second pixel circuit PC2 are each provided with a longitudinal potential line VD2, and each longitudinal potential line VD2 can be electrically connected to a node in the corresponding pixel circuit PC; secondly, the attached Figure 12 and attached Figure 13The two longitudinal potential lines VD2 in the repeating unit RU can be merged into one longitudinal potential line VD2, which is equivalent to setting a longitudinal potential line VD2 in a repeating unit RU, and the longitudinal potential line VD2 can be electrically connected to the two pixel circuits PC in the repeating unit RU, and at least partially overlap with the two pixel circuits PC in the repeating unit RU; for example, the longitudinal potential line VD2 can be set between the first pixel circuit PC1 and the second pixel circuit PC2, and the longitudinal potential line VD2 partially overlaps with the first pixel circuit PC1 and the second pixel circuit PC2. The two pixel circuits PC share one longitudinal potential line VD2, which can reduce the distance between two adjacent pixel circuits PC and improve the setting density of the pixel circuit PC in the unit area.

[0129] It should be noted that the second source-drain layer 131 also includes a reset line arranged vertically. The reset signal line can be located at Figure 12 On both sides of any one of the two data signal lines Data, the longitudinal reset lines can be electrically connected to the first reset line Vi1 or the second reset line Vi2, so that the first reset line Vi1 or the second reset line Vi2 forms a horizontally and vertically staggered mesh structure, thereby reducing the impedance of the reset line.

[0130] It should be noted that the horizontal potential line VD1 and the vertical potential line VD2 of the present application constitute the high potential line VDD of the present application and transmit a high potential signal.

[0131] See also Figure 4 and Figure 14 , Figure 14 for Figure 4 Structural diagram of the middle anode AN.

[0132] See also Figure 4 and Figure 14 In the same repeating unit RU, the display panel 100 may include a first anode AN1 connected to the first pixel circuit PC1 and a second anode AN2 connected to the second pixel circuit PC2, the first anode AN1 and the second anode AN2 are arranged along the second direction Y, and the first anode AN1 and the first pixel circuit PC1 have an overlapping portion, and the second anode AN2 and the second pixel circuit PC2 have an overlapping portion.

[0133] In this embodiment, the first pixel circuit PC1 may be one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the second pixel circuit PC2 may be the other one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0134] It should be noted that the anode area can be adaptively adjusted for sub-pixels of different colors. For example, the anode area of ​​the blue sub-pixel is the largest, and the anode area of ​​the green sub-pixel can be less than or equal to the anode area of ​​the red sub-pixel.

[0135] It should be noted that the signal transmission wires of the present application extend along the first direction X or the second direction Y, which only means that the wires extend in that direction, and does not mean that the wires are straight lines. For example, the wires of the present application may be bent curves or broken lines.

[0136] The present application also provides a display device, comprising the above-mentioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0137] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of sub-pixels, each of which comprises a light-emitting device and a pixel circuit connected to the light-emitting device, wherein the pixel circuit comprises: a switching transistor connected to the data signal line; a driving transistor connected to the switching transistor at a first control node; and A reset module is connected to the driving transistor, and a control end of the reset module is connected to a reset line, wherein the reset line includes an overlapping portion overlapping the data signal line, and at least two insulating layers are arranged between the overlapping portion and the data signal line.

2. The display panel according to claim 1, wherein: The reset module includes a first reset transistor, the reset trace includes a first reset control line, the gates of the first reset transistor and the driving transistor are connected to a first reset node, and the gate of the first reset transistor is connected to the first reset control line; Among them, the first reset control line includes a plurality of first line segments and a plurality of second line segments arranged alternately along a first direction, two adjacent first line segments are electrically connected to the second line segments, the first line segments and the second line segments are arranged in different layers, and at least two insulating layers are arranged between the second line segments and the data signal line.

3. The display panel according to claim 2, wherein: The reset module further includes a second reset transistor, the reset trace further includes a second reset control line, the second reset transistor and the anode of the light-emitting device are connected to a second reset node, and the gate of the second reset transistor is connected to the second reset control line; Among them, the second reset control line includes a plurality of third line segments and a plurality of fourth line segments arranged alternately along the first direction, two adjacent third line segments are electrically connected to the fourth line segments, the third line segments and the fourth line segments are arranged in different layers, and at least two insulating layers are arranged between the fourth line segments and the data signal line.

4. The display panel according to claim 3, wherein: The length of the first line segment is greater than that of the third line segment, and the length of the second line segment is less than that of the fourth line segment.

5. The display panel according to claim 3, wherein: The first line segment and the third line segment are located on the surface of the same insulating film layer, and the second line segment and the fourth line segment are located on the surface of the same insulating film layer.

6. The display panel according to claim 5, wherein: In the thickness direction of the display panel, the distances between the first and third line segments and the film layer where the data signal line is located are smaller than the distances between the second and fourth line segments and the film layer where the data signal line is located.

7. The display panel according to claim 5, wherein: The display panel includes: substrate; A first gate layer is provided on one side of the base substrate; a second gate layer, disposed on a side of the first gate layer away from the base substrate; a first source-drain electrode layer, provided on a side of the second gate layer away from the base substrate; a second source-drain electrode layer, provided on a side of the first source-drain electrode layer away from the base substrate; The first line segment and the third line segment are located in the first gate layer, the second line segment and the fourth line segment are located in the first source-drain layer, and the data signal line is located in the second source-drain layer.

8. The display panel according to any one of claims 1 to 7, characterized in that: The display panel includes a plurality of repeating units, each of the repeating units includes two pixel circuits arranged along a first direction, and two data signal lines connected to the two pixel circuits in the repeating unit are arranged on both sides of the repeating unit; The display panel further includes a longitudinal potential line corresponding to the repeating unit and transmitting a high potential signal. The longitudinal potential line is electrically connected to the two pixel circuits in the repeating unit and at least partially overlaps with the two pixel circuits in the repeating unit.

9. The display panel according to any one of claims 1 to 7, wherein: In two adjacent sub-pixels in the first direction, patterns of at least a portion of the film layers in the pixel circuits in the two adjacent sub-pixels are symmetrically arranged in the first direction.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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