Superconducting quantum circuit and preparation method thereof

Abstract

The invention discloses a superconducting quantum circuit and a preparation method thereof, and relates to the technical field of quantum devices, and the preparation method of the superconducting quantum circuit comprises the steps that an initial structure of a large-structure circuit is formed on the surface of one side of a substrate, and the initial structure is broken by a channel; comprising a first superconducting layer, a barrier layer and a second superconducting layer which are sequentially stacked from one side close to a substrate; defining a first photoresist pattern on the surface of the initial structure, the first photoresist pattern being adjacent to the first channel; etching the second superconducting layer and the barrier layer based on the first photoresist pattern, and removing the first photoresist pattern to form a Josephson junction and a large-structure circuit; an isolation connecting piece is prepared, the superconducting quantum circuit is obtained, the isolation connecting piece comprises a third superconducting layer, and the isolation connecting piece is used for connecting the upper surface of the Josephson junction and the first superconducting layer and blocking electric communication between the first electrode and the second electrode of the Josephson junction. The preparation process of the superconducting quantum circuit is effectively simplified.

Description

Technical Field

[0001] The present application relates to the technical field of quantum devices, and in particular to a superconducting quantum circuit and a preparation method thereof. Background Art

[0002] As a quantum computing solution with great potential, superconducting quantum computing has a core hardware part, the superconducting quantum circuit, which is mainly composed of six parts: Josephson junction, resonant cavity, bit capacitor, control line, read line and air bridge. These components together form the basis of superconducting quantum circuit, enabling it to achieve efficient quantum information processing in an extremely low temperature environment.

[0003] In the manufacturing process of superconducting quantum circuits, a superconducting-insulating-superconducting thin film layer is usually prepared on the substrate first, and then the upper and lower electrode regions of the Josephson junction are defined by etching, and the Josephson junction region is covered with an insulating layer; finally, the upper and lower electrodes are led out by filling superconducting metal and connected to the external circuit. Although this process can improve the uniformity and stability of the Josephson junction performance and is more compatible with traditional semiconductor process equipment, its overall process is relatively cumbersome. Summary of the invention

[0004] The main purpose of the present application is to provide a superconducting quantum circuit and a preparation method thereof, which effectively simplifies the preparation process of the superconducting quantum circuit.

[0005] To achieve the above object, the present invention provides a method for preparing a superconducting quantum circuit, comprising the following steps:

[0006] Providing a substrate, and forming an initial structure of a large structure circuit on a surface of one side of the substrate, wherein the initial structure is divided by a channel, the channel includes a first channel, and the initial structure includes a first superconducting layer, a barrier layer, and a second superconducting layer stacked in sequence from one side close to the substrate;

[0007] defining a first photoresist pattern on a surface of the initial structure, wherein the first photoresist pattern is adjacent to the first channel;

[0008] Etching the second superconducting layer and the barrier layer based on the first photoresist pattern, and removing the first photoresist pattern to form a Josephson junction and a large structure circuit;

[0009] An isolation connector is prepared to obtain a superconducting quantum circuit, wherein the isolation connector includes a third superconducting layer, and the isolation connector is used to connect the upper surface of the Josephson junction and the first superconducting layer and block the electrical connection between the first electrode and the second electrode of the Josephson junction.

[0010] In one embodiment, the step of forming an initial structure of a large structure circuit on a surface of one side of the substrate comprises:

[0011] forming the first superconducting layer, the barrier layer and the second superconducting layer in sequence on one side surface of the substrate;

[0012] defining a second photoresist pattern on a surface of the second superconducting layer;

[0013] The second superconducting layer, the barrier layer and the first superconducting layer are etched based on the second photoresist pattern until the substrate is completely exposed, and the second photoresist pattern is removed to form the initial structure.

[0014] In one embodiment, the step of forming an initial structure of a large structure circuit on a surface of one side of the substrate comprises:

[0015] Defining a third photoresist pattern on a side surface of the substrate;

[0016] sequentially preparing the first superconducting layer, the barrier layer and the second superconducting layer;

[0017] The third photoresist pattern and the first superconducting layer, the barrier layer and the second superconducting layer on the upper surface thereof are peeled off to form the initial structure.

[0018] In one embodiment, the barrier layer is formed by partially oxidizing the first superconducting layer.

[0019] In one embodiment, the thickness of the first superconducting layer is 100-1000 nm;

[0020] and / or, the thickness of the second superconducting layer is 50 to 200 nm;

[0021] and / or, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first superconducting layer and the second superconducting layer, and the thickness of the third superconducting layer is 400-1500 nm;

[0022] The material of the substrate includes: sapphire and / or intrinsic silicon;

[0023] And / or, the material of the first superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material;

[0024] And / or, the material of the second superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material;

[0025] And / or, the material of the third superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material.

[0026] In one embodiment, the step of preparing the isolation connector comprises:

[0027] defining a fourth photoresist pattern;

[0028] preparing the third superconducting layer;

[0029] defining a fifth photoresist pattern on the surface of the third superconducting layer;

[0030] The third superconducting layer is etched based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and the fourth photoresist pattern and the fifth photoresist pattern are removed to form the isolation connector.

[0031] In one embodiment, the isolation connector includes: a first air bridge and / or a superconducting wire;

[0032] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively;

[0033] The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction in contact with the superconducting wire has a natural oxide layer.

[0034] In one embodiment, the channel further includes: a second channel and a third channel, and after the step of etching the third superconducting layer based on the fifth photoresist pattern, further includes:

[0035] A second air bridge spaced apart from the isolation connector is obtained, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.

[0036] To achieve the above object, an embodiment of the present application provides a superconducting quantum circuit, which is prepared by the superconducting quantum circuit preparation method as described above, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer and a third superconducting layer stacked in sequence;

[0037] The first superconducting layer includes a macrostructure circuit interrupted by channels, the channels including a first channel;

[0038] An overlapping region between the first superconducting layer, the barrier layer and the second superconducting layer forms a Josephson junction, and the Josephson junction is adjacent to the first channel;

[0039] The third superconducting layer includes an isolating connector, which is used to connect the upper surface of the Josephson junction and the first superconducting layer and block the electrical connection between the first electrode and the second electrode of the Josephson junction.

[0040] In one embodiment, the isolation connector includes: a first air bridge and / or a superconducting wire;

[0041] The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively;

[0042] The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction contacting the superconducting wire has a natural oxide layer.

[0043] In one embodiment, the channel further includes: a second channel and a third channel;

[0044] The second channel, the third channel, and a first superconducting layer located between the second channel and the third channel constitute a resonant cavity.

[0045] In one embodiment, the third superconducting layer further includes: a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.

[0046] The embodiment of the present application provides a method for preparing a superconducting quantum circuit, which fully integrates the preparation of the Josephson junction into the preparation of the large-structure circuit and air bridge of the superconducting quantum chip, without the need for separate preparation, and realizes the simultaneous preparation of the large-structure circuit, air bridge and Josephson junction, simplifying the overall process flow and steps of chip preparation. The Josephson junction is directly integrated with the large-structure circuit, so there is no need to connect the Josephson junction to the large-structure circuit separately through leads, which effectively reduces the extra steps required in the traditional process. In addition, the direct connection between the Josephson junction and the large-structure circuit in the superconducting quantum circuit is achieved through an isolation connector, and the independence of the first electrode and the second electrode of the Josephson junction ensures the superconducting characteristics and quantum tunneling effect of the Josephson junction; at the same time, it avoids the negative impact on the performance of the quantum bit due to the introduction and residual dielectric insulating materials such as oxides and nitrides, and improves the superconducting quantum bit performance of the superconducting quantum circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a flow chart of a method for preparing a superconducting quantum circuit according to an embodiment of the present application;

[0048] Figure 2The process flow of the superconducting quantum circuit preparation method involved in the embodiment of the present application is as follows Figure 1 ;

[0049] Figure 3 The process flow of the superconducting quantum circuit preparation method involved in the embodiment of the present application is as follows Figure 2 ;

[0050] Figure 4 This is a process flow chart of a relatively complete embodiment 1 of the method for preparing a superconducting quantum circuit involved in the embodiment scheme of the present application;

[0051] Figure 5 This is a process flow chart of a relatively complete embodiment 2 of the method for preparing a superconducting quantum circuit involved in the embodiment scheme of the present application;

[0052] Figure 6 The structure of the superconducting quantum circuit involved in the embodiment of the present application is shown in FIG. Figure 1 ;

[0053] Figure 7 The structure of the superconducting quantum circuit involved in the embodiment of the present application is shown in FIG. Figure 2 .

[0054] Description of reference numerals:

[0055] 100, superconducting quantum circuit; 110, substrate; 120, first superconducting layer;

[0056] 121, first channel; 122, second channel; 123, third channel;

[0057] 130, barrier layer; 140, second superconducting layer; 150, third superconducting layer;

[0058] 151. first air bridge; 152. second air bridge; 153. superconducting wire;

[0059] 160, Josephson knot;

[0060] 171, a first photoresist pattern; 172, a fourth photoresist pattern; 173, a fifth photoresist pattern;

[0061] 174, second photoresist pattern; 175, third photoresist pattern; 176, natural oxide layer;

[0062] 180. Large structure circuit.

[0063] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to the conventional conditions or the conditions recommended by the manufacturer. If the manufacturer is not specified for the reagents or instruments used, they are all conventional products that can be purchased commercially.

[0065] Hereinafter, the superconducting quantum circuit and the method for preparing the same of the present application are specifically disclosed in detail with appropriate reference to the accompanying drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0066] The "range" disclosed in the present application is defined in the form of a lower limit and an upper limit, and a given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundaries of the particular range. The range defined in this way can be inclusive or exclusive of the end values, and can be arbitrarily combined, that is, any lower limit can be combined with any upper limit to form a range. For example, if a range of 60 to 120 and 80 to 110 is listed for a particular parameter, it is understood that a range of 60 to 110 and 80 to 120 is also expected. In addition, if the minimum range values ​​1 and 2 are listed, and if the maximum range values ​​3, 4 and 5 are listed, the following ranges can all be expected: 1 to 3, 1 to 4, 1 to 5, 2 to 3, 2 to 4 and 2 to 5. In the present application, unless otherwise specified, the numerical range "a to b" represents an abbreviation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "0-5" means that all real numbers between "0-5" are listed in this document, and "0-5" is just an abbreviation of these numerical combinations. In addition, when a parameter is expressed as an integer ≥ 2, it is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0067] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0068] Unless otherwise specified, all steps of the present application may be performed sequentially or randomly, preferably sequentially. For example, a method includes steps (a) and (b), which means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, a method may also include step (c), which means that step (c) may be added to the method in any order, for example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0069] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the technical solution of the present application is further described below in conjunction with the accompanying drawings and embodiments. However, the present application is not limited to the listed embodiments, and should also include any other known changes within the scope of the rights claimed in the present application.

[0070] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0071] In conventional technology, superconducting quantum circuits usually first prepare a superconducting-insulating-superconducting thin film layer on a substrate, then define the upper and lower electrode regions of the Josephson junction through an etching process, and use an insulating layer to cover the Josephson junction region; finally, the upper and lower electrodes are led out by filling superconducting metal and connected to the external circuit. Although this process can improve the uniformity and stability of the Josephson junction performance and is more compatible with traditional semiconductor process equipment, each component needs to be prepared separately and then connected, making the overall process more cumbersome. At the same time, the introduction of dielectric insulating layers, such as silicon oxide, silicon nitride, etc., may significantly reduce the performance of superconducting quantum bits.

[0072] The embodiment of the present application provides a method for preparing a superconducting quantum circuit, which fully integrates the preparation of the Josephson junction into the preparation of the large-structure circuit and air bridge of the superconducting quantum chip, without the need for separate preparation, and realizes the simultaneous preparation of the large-structure circuit, air bridge and Josephson junction, simplifying the overall process flow and steps of chip preparation. The Josephson junction is directly integrated with the large-structure circuit, so there is no need to connect the Josephson junction to the large-structure circuit through a lead alone, effectively reducing the extra steps required in the traditional process. In addition, the direct connection between the Josephson junction and the large-structure circuit in the superconducting quantum circuit is achieved through an isolation connector, and the independence between the first electrode and the second electrode of the Josephson junction is ensured, ensuring the superconducting characteristics and quantum tunneling effect of the Josephson junction; at the same time, it avoids the negative impact on the performance of the quantum bit due to the introduction and residual dielectric insulating materials such as oxides and nitrides, and improves the superconducting quantum bit performance of the superconducting quantum circuit.

[0073] The first embodiment of the present application provides a method for preparing a superconducting quantum circuit, referring to Figure 1 , including the following steps:

[0074] Step S10, providing a substrate, and forming an initial structure of a large structure circuit on a surface of one side of the substrate, wherein the initial structure is divided by a channel, the channel includes a first channel, and the initial structure includes a first superconducting layer, a barrier layer, and a second superconducting layer stacked in sequence from one side close to the substrate;

[0075] In a feasible embodiment, a clean substrate is provided, and an initial structure of a large structure circuit separated by a plurality of channels is formed on the surface of the substrate, wherein the initial structure of the large structure circuit includes a first superconducting layer, a barrier layer, and a second superconducting layer stacked in sequence from a side close to the substrate, and the channel includes a first channel. The large structure circuit is a basic structure circuit, which is usually composed of four parts: a resonant cavity, a bit capacitor, a control line, and a read line. Therefore, the initial structure of the large structure circuit composed of a resonant cavity, a bit capacitor, a control line, and a read line can be first formed on the substrate.

[0076] It can be understood that the large structure circuit includes at least one first channel.

[0077] In a feasible implementation, the material of the substrate includes: sapphire and / or intrinsic silicon.

[0078] Sapphire is favored for its low dielectric loss, high mechanical strength, good thermal conductivity, relatively cheap price, good chemical stability, small thermal expansion coefficient and high transmittance to infrared light, all of which help improve the coherence, stability and performance of superconducting quantum circuits.

[0079] With its high resistance and low leakage current characteristics, intrinsic silicon provides excellent insulation properties for superconducting quantum circuits, helping to reduce circuit noise and increase the coherence time of quantum bits.

[0080] In a feasible implementation manner, the material of the first superconducting layer includes at least one of an Al-based superconducting material, a Nb-based superconducting material, a Ta-based superconducting material, and a TiN-based superconducting material.

[0081] In a feasible implementation manner, the material of the second superconducting layer includes at least one of an Al-based superconducting material, a Nb-based superconducting material, a Ta-based superconducting material, and a TiN-based superconducting material.

[0082] Aluminum (Al) has a large coherence length, a low melting point, is easily oxidized on the surface to form an oxide barrier layer, and is more compatible with silicon semiconductor processes. Therefore, it is a commonly used material for preparing Josephson junctions.

[0083] Niobium (Nb) has a high melting point and can be used to prepare large-area dense films through magnetron sputtering. It is suitable for the preparation of larger capacitors, coplanar waveguides, inductors and other devices on quantum chips.

[0084] Tantalum (Ta) has small grains and a rough surface, but quantum bits made from tantalum films have a higher quality factor and a coherence time of more than 0.5ms. Therefore, they have potential application value in superconducting quantum circuits.

[0085] Titanium nitride (TiN) has low surface roughness and good surface flatness, which is crucial for the preparation of high-quality superconducting tunnel junctions.

[0086] In one feasible implementation, the thickness of the first superconducting layer is 100-1000 nm. For example, the thickness of the first superconducting layer is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, etc.

[0087] In one feasible embodiment, the thickness of the second superconducting layer is 50-200 nm. For example, the thickness of the second superconducting layer is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc.

[0088] Step S20, defining a first photoresist pattern on the surface of the initial structure, wherein the first photoresist pattern is adjacent to the first trench;

[0089] In a feasible embodiment, a photoresist layer is prepared on the surface of the second superconducting layer, and the photoresist layer is patterned to obtain a first photoresist pattern adjacent to the first channel.

[0090] Exemplarily, a photoresist is uniformly coated on the surface of the second superconducting layer, the photoresist is exposed, and then developed to prepare a photoresist layer, wherein the exposure can be performed using an ultraviolet contact photolithography machine, a stepper photolithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the photoresist type and photolithography parameters.

[0091] Step S30, etching the second superconducting layer and the barrier layer based on the first photoresist pattern, and removing the first photoresist pattern to form a Josephson junction and a large structure circuit;

[0092] In a feasible embodiment, the first photoresist pattern is used as an anti-etching layer, and the second superconducting layer and the barrier layer are etched until the first superconducting layer is completely exposed, and then the first photoresist pattern remaining on the substrate surface is removed to form a large structure circuit, and a Josephson junction formed by the overlapping area between the first superconducting layer, the barrier layer and the second superconducting layer, wherein the first superconducting layer in the overlapping area constitutes the lower electrode of the Josephson junction and is directly integrated with the large structure circuit. In the preparation process of the superconducting quantum circuit, there is no need to prepare the lower electrode of the Josephson junction separately, or to connect the Josephson junction to the large structure circuit separately through leads, which effectively reduces the extra steps required in the traditional process and simplifies the entire preparation process.

[0093] Step S40, preparing an isolation connector to obtain a superconducting quantum circuit, wherein the isolation connector includes a third superconducting layer, and the isolation connector is used to connect the upper surface of the Josephson junction and the first superconducting layer, and block the electrical connection between the first electrode and the second electrode of the Josephson junction;

[0094] In a feasible embodiment, the lower electrode of the Josephson junction has been connected to the large structure circuit, and in order for the superconducting quantum circuit to work normally, the upper electrode of the Josephson junction needs to be connected to the large structure circuit as well. Therefore, an isolation connector is further prepared to connect the upper surface of the Josephson junction (i.e., the upper electrode of the Josephson junction) and the first superconducting layer to achieve connectivity between the Josephson junction and the large structure circuit. At the same time, the isolation connector can block the electrical connectivity between the first electrode and the second electrode of the Josephson junction, wherein the first electrode and the second electrode of the Josephson junction can be the upper electrode and the lower electrode of the Josephson junction, respectively.

[0095] Exemplarily, the upper surface of the Josephson junction constitutes an upper electrode (ie, a first electrode) of the Josephson junction, and the upper surface of the Josephson junction constitutes a lower electrode (ie, a second electrode) of the Josephson junction.

[0096] In one feasible implementation, step S40, the step of preparing the isolation connector includes:

[0097] S41, defining a fourth photoresist pattern;

[0098] In one feasible embodiment, a photoresist layer is prepared again and patterned to obtain a fourth photoresist pattern, and the fourth photoresist pattern can be used to avoid deposition of the third superconducting layer in some areas, for example, to avoid deposition of the third superconducting layer in the channel part of a large structure circuit.

[0099] Step S42, preparing a third superconducting layer;

[0100] In a feasible embodiment, a third superconducting layer is prepared, wherein the third superconducting layer can be prepared on the surface of the substrate by dual-tilt evaporation, magnetron sputtering, metal organic deposition, electron beam co-evaporation technology, pulsed laser deposition, metal organic chemical vapor deposition, high-rate physical vapor deposition and the like.

[0101] In one feasible implementation, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first superconducting layer and the second superconducting layer, and the thickness of the third superconducting layer is 400-1500 nm. For example, the thickness of the third superconducting layer is 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, etc.

[0102] In a feasible implementation manner, the material of the third superconducting layer includes at least one of an Al-based superconducting material, a Nb-based superconducting material, a Ta-based superconducting material, and a TiN-based superconducting material.

[0103] For example, when the first superconducting layer is easily oxidized, before forming the third superconducting layer on the substrate surface, the oxide layers on the surfaces of the first and second superconducting layers can be pre-cleaned and removed, and then the substrate is placed in a multi-cavity electron beam evaporation device to evaporate the third superconducting layer.

[0104] Step S43, defining a fifth photoresist pattern on the surface of the third superconducting layer;

[0105] In a feasible embodiment, a photoresist layer is again prepared on the surface of the third superconducting layer away from the substrate, and the photoresist layer is patterned to obtain a fifth photoresist pattern.

[0106] Step S44, etching the third superconducting layer based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and removing the fourth photoresist pattern and the fifth photoresist pattern to form an isolation connector.

[0107] In a feasible embodiment, the third superconducting layer is etched with the fifth photoresist pattern as an anti-etching layer until the exposed third superconducting layer is completely etched, and the remaining fourth photoresist pattern and fifth photoresist pattern are removed to form an isolation connector connecting the upper surface of the Josephson junction and the first superconducting layer to achieve connectivity between the Josephson junction and the large structure circuit, and at the same time, the isolation connector can block the electrical connectivity between the first electrode and the second electrode of the Josephson junction.

[0108] Exemplarily, the etching method may be dry etching or wet etching, wherein the dry etching may be inductively coupled plasma etching or reactive ion etching, and the etching gas may be a fluorine-based gas or a chlorine-based gas; the wet etching may be performed using an etching solution.

[0109] In a feasible implementation manner, the channel further includes: a second channel and a third channel, and the second channel, the third channel and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity. After the step of etching the third superconducting layer based on the fifth photoresist pattern in step S44, the method further includes:

[0110] Step S45 , obtaining a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.

[0111] In a feasible embodiment, the fourth photoresist pattern can simultaneously include the first region corresponding to the isolation connector and the region corresponding to the bridge pier of the second air bridge, and the fifth photoresist pattern can also simultaneously include the second region corresponding to the isolation connector and the region corresponding to the bridge surface of the second air bridge; and then the isolation connector and the second air bridge can be obtained at the same time through one etching, wherein the isolation connector is used to connect the upper electrode of the Josephson junction with the large structure circuit, and keep the upper and lower electrodes independent to ensure the superconducting characteristics and quantum tunneling effect of the Josephson junction. The second air bridge spans the second channel and the third channel (i.e., the resonant cavity), and contacts the first superconducting layer located on both sides of the second channel and the third channel, and is used to balance the potential difference, reduce parasitic capacitance, and thus optimize the performance of the resonant cavity.

[0112] By isolating the connector, the adverse effects of introducing dielectric insulating layer materials into the superconducting quantum circuit can be avoided, effectively improving the superconducting quantum bit performance of the superconducting quantum circuit.

[0113] The second air bridge can balance the potential difference and reduce the parasitic capacitance, thereby optimizing the performance of the resonant cavity.

[0114] It can be understood that the large structure circuit includes at least one second channel and at least one third channel.

[0115] In this embodiment, the preparation of the Josephson junction is fully integrated into the preparation of the large structure circuit and air bridge of the superconducting quantum chip, and there is no need to prepare it separately. The large structure circuit, air bridge and Josephson junction are prepared at the same time, which simplifies the overall process flow and steps of chip preparation. The Josephson junction is directly integrated with the large structure circuit, so there is no need to connect the Josephson junction to the large structure circuit through a lead alone, which effectively reduces the extra steps required in the traditional process. In addition, the direct connection between the Josephson junction and the large structure circuit in the superconducting quantum circuit is achieved through an isolation connector, and the independence between the first electrode and the second electrode of the Josephson junction is ensured, ensuring the superconducting characteristics and quantum tunneling effect of the Josephson junction; at the same time, it avoids the negative impact on the performance of the quantum bit due to the introduction and residual dielectric insulating materials such as oxides and nitrides, and improves the superconducting quantum bit performance of the superconducting quantum circuit. The superconducting quantum circuit preparation method provided in the embodiment of the present application is fully compatible with traditional semiconductor equipment and processes, can be prepared on large-size wafers, and can effectively improve the stability and uniformity of the Josephson junction.

[0116] Based on the above first embodiment, a second embodiment of the method for preparing a superconducting quantum circuit of the present application is provided. In this embodiment, step S10, the step of forming an initial structure of a large structure circuit on one side surface of the substrate includes:

[0117] Step A11, forming a first superconducting layer, a barrier layer and a second superconducting layer in sequence on one side surface of the substrate;

[0118] In a feasible embodiment, a first superconducting layer, a barrier layer and a second superconducting layer are sequentially formed on one surface of a clean substrate.

[0119] For example, the first superconducting layer and / or the second superconducting layer can be formed on the surface of the clean substrate by dual-tilt evaporation, magnetron sputtering, metal organic deposition, electron beam co-evaporation technology, pulsed laser deposition, metal organic chemical vapor deposition, high-rate physical vapor deposition, etc.

[0120] In one feasible embodiment, the barrier layer is formed by partial oxidation of the first superconducting layer. After the first superconducting layer is formed on the surface of the substrate, the first superconducting layer located on the surface can be oxidized to form the barrier layer. The barrier layer is located between the first superconducting layer and the second superconducting layer, and can be directly formed on the superconducting layer by oxidation. In this way, the preparation of the barrier layer of the Josephson junction and the large structure circuit can be completed in the same process flow without the need for additional insulating layer materials.

[0121] Exemplarily, the substrate is placed in a multi-cavity electron beam evaporation device to evaporate a first superconducting layer; then transferred to an oxidation chamber to be oxidized with oxygen to prepare a barrier layer; and then transferred again to the multi-cavity electron beam evaporation device to evaporate a second superconducting layer.

[0122] Exemplarily, the oxidation pressure during the barrier layer formation process is 1 to 99 torr, for example, 1 torr, 10 torr, 20 torr, 30 torr, 40 torr, 50 torr, 60 torr, 70 torr, 80 torr, 90 torr, 95 torr, 99 torr, etc.; the oxidation time is 1 to 100 min; for example, 1 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 95 min, 100 min, etc.

[0123] For example, a clean sapphire substrate is placed in a multi-cavity electron beam evaporation device and the vacuum is less than 1×e - 9 In the case of torr, the first layer of aluminum film (i.e., the first superconducting layer) is evaporated, and then transferred into the oxidation chamber to be oxidized by oxygen to prepare the barrier layer; it is transferred into the evaporation chamber again to evaporate the second layer of aluminum film (i.e., the second superconducting layer).

[0124] Step A12, defining a second photoresist pattern on the surface of the second superconducting layer;

[0125] In a feasible embodiment, a photoresist layer is prepared on the surface of the second superconducting layer, and the photoresist layer is patterned to form a second photoresist pattern.

[0126] Exemplarily, a photoresist is uniformly coated on the surface of the second superconducting layer, the photoresist is exposed, and then developed to prepare a photoresist layer, wherein the exposure can be performed using an ultraviolet contact photolithography machine, a stepper photolithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the photoresist type and photolithography parameters.

[0127] Step A13, etching the second superconducting layer, the barrier layer and the first superconducting layer based on the second photoresist pattern until the substrate is completely exposed, and removing the second photoresist pattern to form an initial structure.

[0128] In one feasible embodiment, the second photoresist pattern is used as an anti-etching layer to etch the second superconducting layer, the barrier layer and the first superconducting layer until the substrate is completely exposed, and then the remaining second photoresist pattern is removed to form the initial structure of the large structure circuit.

[0129] Exemplarily, the etching method may be dry etching or wet etching, wherein the dry etching may be inductively coupled plasma etching or reactive ion etching, and the etching gas may be a fluorine-based gas or a chlorine-based gas; the wet etching may be performed using an etching solution.

[0130] For example, refer to Figure 2 . Reference Figure 2(a) A clean substrate 110 is provided, and a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 are sequentially formed on one side surface of the substrate 110. Figure 2 (b) A photoresist layer (not shown in the drawings) is prepared on the surface of the second superconducting layer 140 and patterned to obtain a second photoresist pattern 174. Figure 2 (c) Using the second photoresist pattern 174 as an anti-etching layer, the second superconducting layer 140, the barrier layer 130 and the first superconducting layer 120 are etched until the substrate 110 is completely exposed, and the second photoresist pattern 174 is removed to form an initial structure 180 of a large structure circuit.

[0131] In this embodiment, an initial pattern of a large structure circuit is formed on a substrate through an etching process, achieving high-precision pattern transfer with stable process and strong repeatability.

[0132] In one feasible implementation, step S10, the step of forming an initial structure of a large structure circuit on one side surface of the substrate includes:

[0133] Step B11, defining a third photoresist pattern on one side surface of the substrate;

[0134] In a feasible embodiment, a photoresist layer is prepared on one surface of the substrate in advance, and the photoresist layer is patterned to form a third photoresist pattern.

[0135] Exemplarily, a photoresist is uniformly coated on the surface of a substrate, exposed, and then developed to prepare a photoresist layer, wherein the exposure can be performed using an ultraviolet contact photolithography machine, a stepper photolithography machine, or a laser direct writing device; the development can be performed using a solution corresponding to the photoresist type and photolithography parameters.

[0136] Step B12, sequentially preparing a first superconducting layer, a barrier layer, and a second superconducting layer;

[0137] In a feasible embodiment, a first superconducting layer, a barrier layer and a second superconducting layer are sequentially prepared on a substrate surface having a third photoresist pattern on the surface.

[0138] For example, the first superconducting layer and / or the second superconducting layer can be formed on the surface of the clean substrate by dual-tilt evaporation, magnetron sputtering, metal organic deposition, electron beam co-evaporation technology, pulsed laser deposition, metal organic chemical vapor deposition, high-rate physical vapor deposition, etc.

[0139] In one feasible implementation, the barrier layer is formed by partially oxidizing the first superconducting layer. After the first superconducting layer is formed on the surface of the substrate, the first superconducting layer located on the surface can be oxidized to form the barrier layer.

[0140] Exemplarily, the substrate is placed in a multi-cavity electron beam evaporation device to evaporate a first superconducting layer; then transferred to an oxidation chamber to be oxidized with oxygen to prepare a barrier layer; and then transferred again to the multi-cavity electron beam evaporation device to evaporate a second superconducting layer.

[0141] Exemplarily, a clean sapphire substrate having a third photoresist pattern on its surface is placed in a multi-cavity electron beam evaporation device, and the vacuum degree is less than 1×e -9 In the case of torr, the first layer of aluminum film (i.e., the first superconducting layer) is evaporated, and then transferred into the oxidation chamber to be oxidized by oxygen to prepare the barrier layer; it is transferred into the evaporation chamber again to evaporate the second layer of aluminum film (i.e., the second superconducting layer).

[0142] Step B13, stripping off the third photoresist pattern and the first superconducting layer, the barrier layer and the second superconducting layer on its upper surface to form an initial structure.

[0143] In a feasible embodiment, the third photoresist pattern, as well as the first superconducting layer, the barrier layer, and the second superconducting layer located on the upper surface of the third photoresist pattern are stripped off, thereby obtaining an initial structure of a large structure circuit.

[0144] Exemplarily, the third photoresist pattern and the first superconducting layer, the barrier layer and the second superconducting layer on its upper surface may be stripped by chemical dissolution, thermal decomposition, wet removal, mechanical removal, dry stripping, wet stripping or the like.

[0145] Exemplarily, the third photoresist pattern and the first superconducting layer, the barrier layer, and the second superconducting layer on the upper surface thereof are stripped off by chemical dissolution to form an initial structure.

[0146] For example, refer to Figure 3 . Reference Figure 3 (a) A clean substrate 110 is provided, and a photoresist layer (not shown in the drawings) is prepared on one side of the substrate 110 and patterned to obtain a third photoresist pattern 175. Figure 3 (b) On the surface of the substrate 110 formed with the third photoresist pattern 175, the first superconducting layer 120, the barrier layer 130 and the second superconducting layer 140 are sequentially formed. Figure 3 (c) The third photoresist pattern 175 and the first superconducting layer 120 , the barrier layer 130 , and the second superconducting layer 140 on the upper surface thereof are peeled off to form an initial structure 180 .

[0147] In this embodiment, the initial structure of the large-structure circuit is produced by an evaporation lift-off process; this method can achieve large-area, highly stable and repeatable superconducting junction preparation, and can also avoid damage to the substrate during the etching process.

[0148] Based on the above first and / or second embodiments, a third embodiment of the method for preparing a superconducting quantum circuit of the present application is provided. In this embodiment, the isolation connector includes: a first air bridge and / or a superconducting lead;

[0149] The first air bridge spans the first trench and contacts the upper surface of the Josephson junction and the first superconducting layer respectively;

[0150] The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction contacting the superconducting wire has a natural oxide layer.

[0151] In one feasible embodiment, the isolation connector includes a first air bridge that spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively, and the first channel can constitute a bit capacitor in the large structure circuit. The connection between the Josephson junction and the large structure circuit is achieved through the first air bridge, while avoiding electrical connection between the first electrode and the second electrode of the Josephson junction.

[0152] Exemplarily, a superconducting quantum circuit may include a plurality of Josephson junctions, and each Josephson junction may be connected to a large structure circuit via a first air bridge and a superconducting wire.

[0153] In order to assist in understanding the above technical solution, a relatively complete embodiment of the present application is provided. Figure 4 . Reference Figure 4 (a) A substrate 110 is provided, and an initial structure of a large structure circuit 180 separated by channels is formed on the surface of the substrate 110 (not shown in the drawings), wherein the channels include a first channel 121, a second channel 122, and a third channel 123, and the initial structure includes a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 stacked in sequence from the side close to the substrate. Figure 4 (b) A photoresist layer is prepared on the surface of the second superconducting layer 140 and patterned to obtain a first photoresist pattern 171 adjacent to the first channel 121. Figure 4 (c), using the first photoresist pattern 171 as an anti-etching layer, etching the second superconducting layer 140 and the barrier layer 130 until the first superconducting layer 120 is completely exposed, and removing the first photoresist pattern 171 to form a Josephson junction 160 and a large structure circuit 180. Figure 4 (d), prepare a photoresist layer and pattern it to obtain a fourth photoresist pattern 172. Figure 4 (e) After removing the natural oxide layer on the exposed surfaces of the first superconducting layer 120 and the second superconducting layer 140, the third superconducting layer 150 is deposited. Figure 4 (f) A photoresist layer is prepared on the surface of the third superconducting layer 150 and patterned to obtain a fifth photoresist pattern 173. Figure 4(g) Using the fifth photoresist pattern 173 as an anti-etching layer, the third superconducting layer 150 is etched until the exposed third superconducting layer 150 is completely etched, forming a first air bridge 151 that spans the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120, respectively, to serve as an isolation connector; and a second air bridge 152 that is spaced apart from the first air bridge 151 and spans the second channel 122 and the third channel 123. Figure 4 (h), removing the fourth photoresist pattern 172 and the fifth photoresist pattern 173, and obtaining a superconducting quantum circuit 100, wherein the superconducting quantum circuit 100 comprises: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 which are stacked in sequence; the first superconducting layer 120 comprises a large structure circuit divided by channels, and the channels comprise a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and the channel located in the second channel The first superconducting layer 120 between the first channel 122 and the third channel 123 constitutes a resonant cavity (not shown in the drawings); the overlapping area between the first superconducting layer 120, the barrier layer 130 and the second superconducting layer 140 constitutes a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121; the third superconducting layer 150 includes: a first air bridge 151 and a second air bridge 152 arranged at intervals; the first air bridge 151 spans the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120 respectively. The second air bridge 152 spans the second channel 122 and the third channel 123 and contacts the first superconducting layer 120.

[0154] In a feasible embodiment, if the first superconducting layer and the second superconducting layer are made of materials that are easily oxidized, a natural oxide layer can be formed on the surface of the first superconducting layer and the second superconducting layer during the preparation of the superconducting quantum circuit; and then, before preparing the third superconducting layer, it is usually necessary to pre-clean and remove the oxide layer on the surface of the first superconducting layer and the second superconducting layer. However, at the same time, since the natural oxide layer is generally electrically insulating and cannot achieve electron tunneling, it cannot achieve the Josephson effect at ultra-low temperatures, and then the natural oxide layer can be relied on to block the electrical connection between the first electrode and the second electrode of the Josephson junction. Based on this, the embodiment of the present application can use the superconducting wire as a blocking connector, and before preparing the third superconducting layer, retain the natural oxide layer on the side surface where the Josephson junction contacts the superconducting wire, so as to avoid the superconducting wire connecting the first electrode and the second electrode of the Josephson junction, and remove the remaining natural oxide layer; then prepare the superconducting wire by depositing the third superconducting layer to cover at least part of the upper surface of the Josephson junction and the width range of the first channel adjacent to the Josephson junction, and extend to the first superconducting layer adjacent to the Josephson junction, so as to realize the direct connection between the Josephson junction and the large structure circuit. At this time, since the side surface where the Josephson junction contacts the superconducting wire has a natural oxide layer, the independence of the first electrode and the second electrode of the Josephson junction is ensured.

[0155] It can be understood that the superconducting wire covers the width of the first channel adjacent to the Josephson junction, but does not cover the entire length of the first channel.

[0156] In order to assist in understanding the above technical solution, a relatively complete second embodiment of the present application is provided. Figure 5 . Reference Figure 5 (a) A substrate 110 is provided, and an initial structure of a large structure circuit 180 separated by channels is formed on the surface of the substrate 110 (not shown in the drawings), wherein the channels include a first channel 121, a second channel 122, and a third channel 123, and the initial structure includes a first superconducting layer 120, a barrier layer 130, and a second superconducting layer 140 stacked in sequence from the side close to the substrate. Figure 5 (b) A photoresist layer is prepared on the surface of the second superconducting layer 140 and patterned to obtain a first photoresist pattern 171 adjacent to the first channel 121. Figure 5 (c), using the first photoresist pattern 171 as an anti-etching layer, etching the second superconducting layer 140 and the barrier layer 130 until the first superconducting layer 120 is completely exposed, and removing the first photoresist pattern 171 to form a Josephson junction 160 and a large structure circuit 180. Figure 5 (d) A photoresist layer is prepared and patterned to obtain a fourth photoresist pattern 172. Meanwhile, a natural oxide layer 176 can be formed on the side surface of the Josephson junction exposed to air. Figure 5(e) The natural oxide layer 170 on the side surface where the Josephson junction 160 contacts the superconducting wire 153 is retained, while the oxide layer on the remaining part is removed, and the third superconducting layer 150 is deposited. Figure 5 (f) A photoresist layer is prepared on the surface of the third superconducting layer 150 and patterned to obtain a fifth photoresist pattern 173. Figure 5 (g) Using the fifth photoresist pattern 173 as an anti-etching layer, the third superconducting layer 150 is etched until the exposed third superconducting layer 150 is completely etched away, forming a superconducting wire 153 covering the upper surface of the Josephson junction 160 and the width of the first channel 121 adjacent to the Josephson junction 160, and extending to the first superconducting layer 120 adjacent to the Josephson junction 160, as an isolation connector; and a second air bridge 152 spaced from the superconducting wire 153 and spanning the second channel 122 and the third channel 123. Figure 5 (h), removing the fourth photoresist pattern 172 and the fifth photoresist pattern 173 to obtain a superconducting quantum circuit 100, wherein the superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 stacked in sequence; the first superconducting layer 120 includes a large structure circuit separated by channels, and the channels include a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and a channel located between the second channel 122 and the third channel 123 The first superconducting layer 120 of the embodiment of the present invention constitutes a resonant cavity (not shown in the drawings); the overlapping area between the first superconducting layer 120, the barrier layer 130 and the second superconducting layer 140 constitutes a Josephson junction 160, and the Josephson junction 160 is adjacent to the first channel 121; the third superconducting layer 150 includes: a superconducting wire 153 and a second air bridge 152 arranged at intervals; the superconducting wire 153 covers the upper surface of the Josephson junction 160 and the width range of the first channel 121 adjacent to the Josephson junction 160, and extends to contact the first superconducting layer 120 adjacent to the Josephson junction 160. The second air bridge 152 spans the second channel 122 and the third channel 123, and contacts the first superconducting layer 120.

[0157] The embodiment of the present application provides a superconducting quantum circuit, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer and a third superconducting layer stacked in sequence;

[0158] The first superconducting layer includes a macrostructure circuit interrupted by channels, the channels including a first channel;

[0159] The overlapping region between the first superconducting layer, the barrier layer and the second superconducting layer forms a Josephson junction, and the Josephson junction is adjacent to the first channel;

[0160] The third superconducting layer includes: an isolation connector;

[0161] The isolation connecting element crosses the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively, and the first channel can constitute a bit capacitor in a large structure circuit.

[0162] In a feasible embodiment, the isolation connector includes: a first air bridge and / or a superconducting wire;

[0163] The first air bridge spans the first trench and contacts the upper surface of the Josephson junction and the first superconducting layer respectively;

[0164] The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction contacting the superconducting wire has a natural oxide layer.

[0165] In a feasible implementation, the channel that divides the large structure circuit further includes: a second channel and a third channel, wherein the second channel, the third channel and the first superconducting layer located between the second channel and the third channel constitute a resonant cavity.

[0166] In one feasible embodiment, the third superconducting layer further includes: a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer to balance the potential difference and reduce parasitic capacitance, thereby optimizing the performance of the resonant cavity.

[0167] For example, refer to Figure 6 The superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 which are stacked in sequence;

[0168] The first superconducting layer 120 includes a large structure circuit divided by channels, and the channels include a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and the first superconducting layer 120 located between the second channel 122 and the third channel 123 constitute a resonant cavity (not shown in the drawings);

[0169] The overlapping area between the first superconducting layer 120 , the barrier layer 130 and the second superconducting layer 140 forms a Josephson junction 160 , and the Josephson junction 160 is adjacent to the first channel 121 ;

[0170] The third superconducting layer 150 includes: a first air bridge 151 and a second air bridge 152 arranged at intervals;

[0171] The first air bridge 151 spans across the first channel 121 and contacts the upper surface of the Josephson junction 160 and the first superconducting layer 120 respectively;

[0172] The second air bridge 152 spans the second channel 122 and the third channel 123 and contacts the first superconducting layer 120 .

[0173] For example, refer to Figure 7 The superconducting quantum circuit 100 includes: a substrate 110, a first superconducting layer 120, a barrier layer 130, a second superconducting layer 140 and a third superconducting layer 150 which are stacked in sequence;

[0174] The first superconducting layer 120 includes a large structure circuit divided by channels, and the channels include a first channel 121, a second channel 122 and a third channel 123, wherein the second channel 122, the third channel 123 and the first superconducting layer 120 located between the second channel 122 and the third channel 123 constitute a resonant cavity (not shown in the drawings);

[0175] The overlapping area between the first superconducting layer 120 , the barrier layer 130 and the second superconducting layer 140 forms a Josephson junction 160 , and the Josephson junction 160 is adjacent to the first channel 121 ;

[0176] The third superconducting layer 150 includes: a superconducting wire 153 and a second air bridge 152 arranged at intervals; the superconducting wire 153 covers the upper surface of the Josephson junction 160 and the width range of the first channel 121 adjacent to the Josephson junction 160, and extends to contact the first superconducting layer 120 adjacent to the Josephson junction 160;

[0177] The second air bridge 152 spans the second channel 122 and the third channel 123 and contacts the first superconducting layer 120 .

[0178] In this embodiment, the direct connection between the Josephson junction and the large structure circuit in the superconducting quantum circuit is achieved by isolating the connector, thereby avoiding the adverse effects of the dielectric insulating layer material on the circuit performance, and effectively improving the superconducting quantum bit performance of the superconducting quantum circuit. At the same time, the components of the superconducting quantum circuit provided in the embodiment of the present application are composed of a substrate and a plurality of superconducting layers (a first superconducting layer, a second superconducting layer, a third superconducting layer) and a barrier layer. This stacked structure allows the formation of the Josephson junction and other parts of the large structure circuit to be formed simultaneously in a continuous process flow, for example, by controlling the formation and patterning of each layer of material. Since the preparation of the Josephson junction and the large structure circuit can be completed in the same process flow, this effectively reduces the additional steps required in the traditional process, such as the double-angle evaporation stripping process, thereby simplifying the entire preparation process.

[0179] The above are only preferred embodiments of the present application, and do not limit the scope of the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of patent protection of the present application.

Claims

1. A method for preparing a superconducting quantum circuit, characterized in that: The superconducting quantum circuit preparation method comprises the following steps: Providing a substrate, and forming an initial structure of a large structure circuit on a surface of one side of the substrate, wherein the initial structure is divided by a channel, the channel includes a first channel, and the initial structure includes a first superconducting layer, a barrier layer, and a second superconducting layer stacked in sequence from one side close to the substrate; defining a first photoresist pattern on a surface of the initial structure, wherein the first photoresist pattern is adjacent to the first channel; Etching the second superconducting layer and the barrier layer based on the first photoresist pattern, and removing the first photoresist pattern to form a Josephson junction and a large structure circuit; An isolation connector is prepared to obtain a superconducting quantum circuit, wherein the isolation connector includes a third superconducting layer, and the isolation connector is used to connect the upper surface of the Josephson junction and the first superconducting layer and block the electrical connection between the first electrode and the second electrode of the Josephson junction.

2. The method for preparing a superconducting quantum circuit according to claim 1, characterized in that: The step of forming an initial structure of a large structure circuit on one side surface of the substrate comprises: forming the first superconducting layer, the barrier layer and the second superconducting layer in sequence on one side surface of the substrate; defining a second photoresist pattern on a surface of the second superconducting layer; The second superconducting layer, the barrier layer and the first superconducting layer are etched based on the second photoresist pattern until the substrate is completely exposed, and the second photoresist pattern is removed to form the initial structure.

3. The method for preparing a superconducting quantum circuit according to claim 1, characterized in that: The step of forming an initial structure of a large structure circuit on one side surface of the substrate comprises: Defining a third photoresist pattern on a side surface of the substrate; sequentially preparing the first superconducting layer, the barrier layer and the second superconducting layer; The third photoresist pattern and the first superconducting layer, the barrier layer and the second superconducting layer on the upper surface thereof are peeled off to form the initial structure.

4. The method for preparing a superconducting quantum circuit according to any one of claims 1 to 3, characterized in that: The barrier layer is formed by partially oxidizing the first superconducting layer.

5. The method for preparing a superconducting quantum circuit according to any one of claims 1 to 3, characterized in that: The thickness of the first superconducting layer is 100-1000 nm; and / or, the thickness of the second superconducting layer is 50 to 200 nm; and / or, the thickness of the third superconducting layer is greater than the sum of the thicknesses of the first superconducting layer and the second superconducting layer, and the thickness of the third superconducting layer is 400-1500 nm; The material of the substrate includes: sapphire and / or intrinsic silicon; And / or, the material of the first superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material; And / or, the material of the second superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material; And / or, the material of the third superconducting layer includes: at least one of Al-based superconducting material, Nb-based superconducting material, Ta-based superconducting material and TiN-based superconducting material.

6. The method for preparing a superconducting quantum circuit according to claim 1, characterized in that: The steps of preparing the isolation connector include: defining a fourth photoresist pattern; preparing the third superconducting layer; defining a fifth photoresist pattern on the surface of the third superconducting layer; The third superconducting layer is etched based on the fifth photoresist pattern until the fourth photoresist pattern is exposed, and the fourth photoresist pattern and the fifth photoresist pattern are removed to form the isolation connector.

7. The method for preparing a superconducting quantum circuit according to claim 1 or 6, characterized in that: The isolation connector includes: a first air bridge and / or a superconducting wire; The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively; The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction in contact with the superconducting wire has a natural oxide layer.

8. The method for preparing a superconducting quantum circuit according to claim 6, characterized in that: The channel further includes: a second channel and a third channel, and after the step of etching the third superconducting layer based on the fifth photoresist pattern, further includes: A second air bridge spaced apart from the isolation connector is obtained, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.

9. A superconducting quantum circuit, characterized in that: The superconducting quantum circuit is made by the method according to any one of claims 1 to 8, comprising: a substrate, a first superconducting layer, a barrier layer, a second superconducting layer and a third superconducting layer stacked in sequence; The first superconducting layer includes a macrostructure circuit interrupted by channels, the channels including a first channel; An overlapping region between the first superconducting layer, the barrier layer and the second superconducting layer forms a Josephson junction, and the Josephson junction is adjacent to the first channel; The third superconducting layer includes an isolating connector, which is used to connect the upper surface of the Josephson junction and the first superconducting layer and block the electrical connection between the first electrode and the second electrode of the Josephson junction.

10. The superconducting quantum circuit according to claim 9, characterized in that: The isolation connector includes: a first air bridge and / or a superconducting wire; The first air bridge spans the first channel and contacts the upper surface of the Josephson junction and the first superconducting layer respectively; The superconducting wire covers at least a portion of the upper surface of the Josephson junction and extends to contact the first superconducting layer adjacent to the Josephson junction. The side surface of the Josephson junction contacting the superconducting wire has a natural oxide layer.

11. The superconducting quantum circuit according to claim 9, characterized in that: The channel further includes: a second channel and a third channel; The second channel, the third channel, and a first superconducting layer located between the second channel and the third channel constitute a resonant cavity.

12. The superconducting quantum circuit according to claim 11, characterized in that: The third superconducting layer further includes: a second air bridge spaced apart from the isolation connector, wherein the second air bridge spans the second channel and the third channel and contacts the first superconducting layer.

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