Systems and techniques for fault injection mitigation of tamper-resistant elements

Abstract

Systems and techniques are provided for a method of fault injection mitigation. For example, a process for fault injection mitigation may include receiving a sensor event notification; incrementing an erasable event counter based on the sensor event notification; making a first determination that the number of events of the erasable event counter is below an event threshold; and making a second determination that the permanent event registry is not updated based on the first determination.

Description

Technical Field

[0001] The present disclosure generally relates to tamper-resistant elements. For example, aspects of the present disclosure relate to performing fault injection mitigation on tamper-resistant elements. Background Art

[0002] Devices typically implement various techniques for device security. Device security may involve protecting the device from physical and / or logical attacks that attempt to compromise the security of the device. Device security techniques may include configuring a tamper-resistant element for the device. A tamper-resistant element (TRE) may include any number of sensors for sensing device conditions (e.g., temperature, voltage, signal frequency, etc.). Such sensors may be configured so that when a sensor value exceeding a threshold is reached, the sensor provides a sensor event notification. Sensor event notifications are typically recorded using a memory that may not be erasable. Typically, when the number of sensor event notifications exceeds the maximum number of sensor events, a fault mitigation action (e.g., disabling all or any part of the components of the tamper-resistant element, resetting the TRE, etc.) is performed. However, such fault mitigation actions may not account for the frequency with which sensor events occur, and may therefore result in disabling all or any part of the TRE or resetting the TRE, even when the sensor event is not the result of a security attack. Summary of the invention

[0003] Systems and techniques for performing fault injection mitigation on tamper-resistant elements are described. For example, these systems and techniques can determine when a sensor event is registered, which can help determine when to perform fault mitigation actions on a device that includes one or more tamper-resistant elements.

[0004] According to at least one example, a method for fault injection mitigation is provided. The method includes: receiving a sensor event notification; incrementing an erasable event counter based on the sensor event notification; making a first determination that a number of events of the erasable event counter is below an event threshold; and making a second determination not to update a permanent event register based on the first determination.

[0005] In another illustrative example, an apparatus for fault injection mitigation is provided. The apparatus may include an erasable event counter; a permanent event register; at least one memory; and at least one processor coupled to the at least one memory. The apparatus may be configured to: receive a sensor event notification at the erasable event counter; increment the erasable event counter based on the sensor event notification; make a first determination that the number of events of the erasable event counter is below an event threshold; and make a second determination based on the first determination not to update the permanent event register.

[0006] In another illustrative example, a non-transitory computer-readable medium is provided, on which instructions are stored, which when executed by one or more processors cause the one or more processors to perform the following operations: receive a sensor event notification; increment an erasable event counter based on the sensor event notification; make a first determination that the number of events in the erasable event counter is below an event threshold; and make a second determination not to update a permanent event registry based on the first determination.

[0007] In another illustrative example, a device for identity impersonation is provided, the device including components for performing the following operations: receiving a sensor event notification; incrementing an erasable event counter based on the sensor event notification; making a first determination that the number of events of the erasable event counter is below an event threshold; and making a second determination not to update a permanent event registry based on the first determination.

[0008] In some aspects, one or more of the devices described herein are, are part of, and / or include an extended reality (XR) device or system (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a mobile device (e.g., a mobile phone or other mobile device), a wearable device, a wireless communication device, a camera, a personal computer, a laptop, a vehicle or a computing device or component of a vehicle, a server computer or server device (e.g., an edge or cloud-based server, a personal computer acting as a server device, a mobile device such as a mobile phone acting as a server device, an XR device acting as a server device, a vehicle acting as a server device, a network router, or other device acting as a server device), another device, or a combination thereof. In some aspects, the device includes a camera or cameras for capturing one or more images. In some aspects, the device also includes a display for displaying one or more images, notifications, and / or other displayable data. In some aspects, the above-mentioned device may include one or more sensors (e.g., one or more inertial measurement units (IMUs)), such as one or more gyroscopes, one or more gyrometers, one or more accelerometers, any combination thereof, and / or other sensors.

[0009] This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this patent, any or all drawings, and each claim.

[0010] The foregoing and other features and aspects will become more apparent upon reference to the following description, claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Illustrative examples of the present application are described in detail below with reference to the following drawings:

[0012] Figure 1 is a block diagram illustrating an anti-tamper element according to some examples.

[0013] Figure 2 is a flow diagram illustrating an example of a process for fault injection mitigation according to aspects of the present disclosure.

[0014] Figure 3 is a diagram illustrating an example of a computing system according to aspects of the present disclosure. DETAILED DESCRIPTION

[0015] Certain aspects of the present disclosure are provided below. Some of these aspects may be applied independently, and some of them may be applied in combination, which is obvious to those skilled in the art. In the following description, specific details are set forth for explanation purposes to provide a thorough understanding of various aspects of the application. However, it is apparent that various aspects may be implemented without these specific details. Each of the drawings and descriptions is not intended to be restrictive.

[0016] As used herein, the phrase "operably connected" or "operably connected" means that there is a direct or indirect connection between elements / components / devices, etc. that allows the elements to interact with each other in some way. For example, the phrase "operably connected" can refer to any direct connection (e.g., a wired connection directly between two devices or components) or an indirect connection (e.g., a wired and / or wireless connection between any number of devices, components, circuits, etc. that connect operably connected devices). Therefore, any path through which any type of information can travel can be considered an operational connection. Additionally, operably connected devices and / or components can exchange things other than information (such as, for example, current, radio frequency signals, etc.). Such information can initially be in one form (e.g., an indication that a sensor reading exceeds a configured threshold), and when traversing the operational connection, such information can be converted into different information (e.g., an operation that causes one or more individual components to take action based on one or more sensor readings and / or to take action on one or more individual components based on one or more sensor readings).

[0017] The following description provides only example aspects and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the following description of the example aspects will provide a description that can be used to implement the example aspects to those skilled in the art. It should be understood that various changes may be made to the function and arrangement of elements without departing from the essence and scope of the present application as set forth in the appended claims.

[0018] Security-hardened hardware, such as tamper-resistant elements (TREs), are designed to resist potential attackers. Such attackers are able to inject faults that are designed to interrupt and change the expected hardware and software behavior and modify their overall flow. Mitigating fault injection typically involves an array of sensors that monitor the operating conditions (e.g., voltage and frequency) of the security-hardened hardware (e.g., TREs). Once such one or more sensors are triggered, the security-hardened hardware (e.g., TRE) will typically protect its data, such as by resetting itself and preventing attackers from manipulating the hardware / software functionality.

[0019] Given that the fault injection attack surface can be large and may extend over a long period of time, some sensors may have endpoint limits on how many times they can be triggered. Otherwise, if no limits are placed on certain sensor triggers, an advanced attacker could potentially exploit an unlimited number of sensor events to circumvent fault injection countermeasures (such as when executed over a long period of time and / or across many devices).

[0020] Based on such vulnerabilities, it may be desirable to place hardware (e.g., TRE) lifetime limits on certain sensors to mitigate such attacks. Once this limit has been reached, the security hardening hardware (e.g., TRE) will no longer function as part of the mitigation.

[0021] Given the length of time it takes to write to traditional non-volatile memory (e.g., Flash), a record of these sensor events can be stored in a one-time programmable memory (OTP) such as an eFuse. However, OTP memory may have a very limited size, in which case the number of such events is limited. There is no concept of rate, and by definition, once written, OTP memory cannot be erased.

[0022] Furthermore, despite best design efforts, it may be difficult to prevent certain false sensor events (such as in electrically noisy environments) that are beyond the control of the security hardened hardware (e.g., TRE) designer. This is especially true when considering billions of units and TRE lifetimes that can be measured in years. As a result, a certain percentage of devices may experience false events that, while benign, accumulate over time and exceed the lifetime limits of the security hardened hardware (e.g., TRE). This may cause the security hardened hardware (e.g., TRE) to self-terminate for reasons not related to security.

[0023] Systems and techniques for improving the robustness of fault injection mitigation are described herein, such as for securely hardened hardware (e.g., TRE) that includes one or more of the following features: an always-on (AO) register that persists across TRE startup; reliably detect when the AO register is reset (e.g., if power is disconnected); and the ability to reliably measure elapsed time from startup. By using the systems and techniques described herein, securely hardened hardware (e.g., TRE) can form an additional layer of fault mitigation based on the AO register without relying on limited OTP memory. Such systems and techniques can additionally or alternatively provide rate control and rewritability to securely hardened hardware (e.g., TRE), which is not possible with OTM memory.

[0024] A comparison of a first technique and a second technique provided by the systems and techniques described herein is provided below (where TRE is used as an illustrative example of security hardened hardware):

[0025]

[0026] The systems and techniques described herein can be used to significantly reduce the chances of security-hardened hardware (e.g., TRE) being disabled by false sensor events, which is a concern for TRE designers.

[0027] Various aspects of the systems and techniques described herein are discussed below with respect to the accompanying figures. Figure 1 is a block diagram of an anti-tamper element 102 according to one or more examples described herein. Figure 1 As shown, a tamper-resistant element 102 is included in a computing device 100. The tamper-resistant element 102 may include a processor 104, any number of sensors (e.g., sensor A 106, sensor N 108, etc.), an erasable event counter 110, a permanent event register 112, a time component 106, and a power failure detector 118. Each of these components is described below.

[0028] Computing device 100 is any device, portion of a device, or any collection of devices capable of processing instructions electronically, and may include, but is not limited to, any of the following: one or more processors (e.g., components including integrated circuits, such as processor 104), memory, input and output devices (not shown), non-volatile storage hardware (not shown), one or more physical interfaces (not shown), any number of other hardware components (e.g., sensors 106 and 108, erasable event counter 110, permanent event register 112, etc.), and / or any combination thereof. Examples of computing devices include, but are not limited to, mobile devices (e.g., laptops, smart phones, personal digital assistants, tablet computers, automotive computing systems, and / or any other mobile computing devices), Internet of Things (IoT) devices, servers (e.g., blade servers in blade server chassis, rack-mounted servers in racks, etc.), desktop computers, storage devices (e.g., disk drive arrays, Fibre Channel storage devices, Internet Small Computer System Interface (iSCSI) storage devices, tape storage devices, flash arrays, network attached storage devices, etc.), network devices (e.g., switches, routers, multi-layer switches, etc.), wearable devices (e.g., connected watches or smart watches or other wearable devices), robotic devices, smart TVs, smart appliances, extended reality (XR) devices (e.g., augmented reality, virtual reality, etc.), any device including one or more SoCs, and / or any other type of computing device having the aforementioned requirements. In one or more examples, any or all of the aforementioned examples may be combined to create a system of such devices, which may be collectively referred to as a computing device. Other types of computing devices may be used without departing from the scope of the examples described herein.

[0029] In some examples, the computing device 100 includes an anti-tampering element 102. In one or more embodiments, the anti-tampering element 102 is any security element that includes hardware, software, firmware, middleware, and / or any combination thereof that is configured to provide resistance to logical and / or physical attacks that attempt to damage all or any part of the computing device 100. The anti-tampering element may, for example, be included in one or more subscriber identity modules (SIMs) of any type (e.g., a removable SIM card, an eSIM, an integrated SIM, a payment card chip, etc.) of the computing device 100 and / or operatively connected to one or more subscriber identity modules (SIMs) of any type of the computing device 100. In some examples, the anti-tampering element 102 may be subject to attacks that attempt to damage the anti-tampering element 104 and / or the computing device 100 in some way. As an example, a passive attack may attempt to measure one or more physical aspects of the anti-tampering element (e.g., temperature, electromagnetic radiation, etc.) in order to obtain information about the operation of the anti-tampering element 104. As another example, an active attack may attempt to cause all or any portion of the tamper-resistant element 104 to change its operational behavior (e.g., by increasing temperature, voltage, current, signal frequency, etc.) in order to create a scenario that allows an attack on the security of the tamper-resistant element 104. As an example, such an attack may allow an attacker to gain insight into the operation of one or more aspects of the computing device 100 (e.g., software program flow) and / or the tamper-resistant element 102. As an example, such insight may allow faults to be injected into the operation of the tamper-resistant element to allow an attacker to increase the likelihood of successfully compromising the security of the tamper-resistant element 104 (e.g., by causing an invalid signature to be accepted, etc.).

[0030] In one or more embodiments, the tamper-proof element 102 includes and / or is operatively connected to a processor 104. In some examples, the processor 104 is any component that includes a circuit for executing instructions / operations (e.g., of a computer program). As an example, such circuits may be integrated circuits implemented at least in part using transistors that implement such components as arithmetic logic units, control units, logic gates, registers, etc. In some examples, the processor may include additional components, such as, for example, cache memory. In some examples, in order to perform an operation, the processor retrieves and decodes instructions, which are then executed. The execution of instructions may include operating on data, which operations may include reading data, writing data, converting data, etc. In some examples, the instructions and data used by the processor are stored in a memory and / or other components (e.g., registers) of the computing device 100. The processor may perform various operations for executing software (such as an operating system, an application, etc.). The processor may write data from the memory of the computing device 100 to the storage device of the computing device and / or read data from the storage device via the memory. Examples of processors include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit, a tensor processing unit, a data processing unit (DPU), a digital signal processor (DSP), and the like.

[0031] In some examples, components of tamper-resistant element 102 (such as Figure 1 All or any part of those components shown in Figure 1 104 shown in ). As described above, the processor 104 can be any circuit that implements any type of logic component and is used for any purpose. Therefore, the tamper-resistant element 102 may include a processor as described above and / or a separate set of processing logic components (which may also be referred to as a processor) for implementing all or any portion of the functionality described herein, such as implementing operational connections between all or any portion of the components discussed herein. In other words, the tamper-resistant element 102 may include a set of logic components (e.g., fault injection mitigation logic components) that are at least partially implemented in a circuit, which exists together with any number of other processing elements (e.g., the processor 104). As discussed above, the phrase "operably connected" and / or any connecting arrows or lines shown in any of the figures are not intended to exclusively imply a specific, direct coupling between any elements shown in these figures, but are intended to convey any physical and / or logical operational path through which information, data, etc. can travel, thereby creating a path through which the actions, operations, etc. of a component, element, etc. can affect the actions, operations, etc. of another component or any subcomponent therein. Therefore, although Figure 1Each component is shown as being operatively connected via processor 104, but one of ordinary skill in the relevant art will appreciate that other configurations of tamper-resistant elements may exist (where different logical groupings may exist and where various components, elements, circuits, etc. may exist) and may allow for operative connections between any one or more of the components, elements, etc. As an example, all or any portion of the sensors (e.g., 106, 108), erasable event counters 110, time component 116, power failure detector 118, and / or permanent event register 112 may be operatively connected via processor 104. Figure 1 shown), through Figure 1 In some examples, Figure 1 All or any portion of the components shown in may be logically referred to as a fault injection mitigation logic component. As an example, the erasable event counter 110, the time component 116, the power failure detector, and / or the persistent event register may be considered as logical blocks representing elements of the fault injection mitigation logic component, and all or any portion of such components may be operatively connected to each other (e.g., logically connected to each other) and / or operatively connected to one or more sensors (e.g., 106, 108) such that sensor events and / or events in any other component cause changes in one or more components to which the sensor and / or other component is logically connected. Thus, although Figure 1 The operative connections between various other components are shown via the processor 104, but in some examples, all or any portion of the various other elements may additionally or alternatively be operatively connected in other ways using any other direct and / or indirect circuits, components, etc., in order to perform the various types of functionality described herein. Thus, the examples described herein may be performed using the processor 104, other sets of logic included in the tamper-resistant element 102, or any combination thereof.

[0032] In some examples, the tamper-proof element 102 includes any number of sensors (e.g., sensor A 106, sensor N 108). Such sensors may be operably connected to the processor 104 and / or any other component of the computing device 100. In some examples, the sensors (e.g., 106, 108) may be configured to record, measure, etc. any aspect of the computing device 100 and / or the tamper-proof element 102. Examples of such aspects include temperature, voltage, current, signal frequency, etc. In one or more embodiments, based on the output from a given sensor, a sensor event notification may be generated. In some examples, a sensor event is any aspect or condition of the computing device 100 and / or the tamper-proof element 102 that exceeds a configured threshold. As an example, the temperature may be higher or lower than a temperature range. As another example, the voltage supplied to a given component may be higher or lower than a given voltage range. It will be understood by those of ordinary skill in the art that, without departing from the scope of the examples discussed herein, other values ​​may be measured by one or more sensors and compared with various thresholds to distinguish sensor events.

[0033] In some examples, the tamper-resistant element 102 includes a fault injection mitigation logic component (not shown). In some examples, the fault injection mitigation logic component is any hardware logic component (e.g., circuitry), software, firmware, and / or any combination thereof configured to determine when to update a permanent event register (discussed below) based on sensor event notifications (in some examples, by using the erasable event counter 110). Thus, the fault injection mitigation logic component may include Figure 1 All or any portion of the components shown in , as well as any other circuits, components, etc. that facilitate communication, combined action, etc. between any two or more components of the tamper-proof element 102.

[0034] In some examples, the tamper-resistant element 102 includes an erasable event counter 110. The erasable event counter 110 can be any hardware (e.g., circuitry), software, firmware, and / or any combination thereof configured to record any number of instances of sensor event notifications. As an example, when a sensor (e.g., 106, 108) of the tamper-resistant element 102 measures a value that exceeds (e.g., is higher than, lower than, etc.) a configured threshold value (e.g., five, ten, one hundred, etc.), the erasable event counter 100 can be updated (e.g., via the processor 104, by a separate fault injection mitigation logic component). The erasable event counter 110 can be operably connected to the processor 104 and / or any component of the tamper-resistant element 102 (e.g., sensors 106 and 108). In some examples, the erasable event counter 110 can be considered erasable because data can be erased, altered, etc. after being written to the erasable event counter (e.g., the counter can be reset, decremented, etc. after a certain amount of time has passed).

[0035] The erasable event counter 110 may include and / or be operatively connected to an always-on register. In some examples, the always-on register is a storage element that includes a power source that is separate from other power provided to various components of the computing device 100 (e.g., via a separate power rail). In some examples, updating the erasable event counter 110 may include incrementing a value stored in the always-on register based on a sensor event notification. In some examples, if the value stored by the erasable event counter 110 reaches and / or exceeds a configured value based on the number of sensor event notifications, the permanent event register 112 (discussed below) may be updated. In some examples, the always-on register may be updated based on the occurrence of a sensor event, regardless of whether the sensor is directly coupled to the always-on register or whether the update is performed via an indirect connection via the processor 104 and / or other fault injection mitigation logic components. In some examples, the always-on register is used as the erasable event counter 110. In other examples, an update to the always-on register may cause an update to a separate, operatively connected erasable event counter.

[0036] In some examples, the tamper-resistant element 102 includes a time component 116 (e.g., a counter, a timer, etc.) capable of tracking time. In some examples, the time component 116 is included in the processor 102 and / or is operatively connected to the processor and / or the erasable event counter 110 (e.g., via a fault injection mitigation logic component). In some examples, the time component 116 may be configured with a time value, which may be referred to as a time threshold (e.g., 10 minutes). As an example, the configured time (e.g., the time threshold) may be the time since the computing device 100 and / or the tamper-resistant element 102 has been started and / or restarted. In some examples, if the timer of the time component 116 reaches the configured time limit, an action is performed. As an example, if the timer reaches the configured time limit, the erasable event counter 110 may be reset, thereby restarting the counting of sensor event notifications. As another example, if the timer reaches the configured time limit, the erasable event counter 110 may decrement its count of sensor event notifications by one or more, thereby maintaining a rolling count of sensor event notifications per unit time. In some examples, if the erasable event counter 110 does not reach a configured threshold within a particular amount of time, the permanent event registry 112 is not updated to record the sensor event, which can prevent all or any portion of the tamper-resistant element from being unnecessarily disabled or reset (e.g., based on infrequent, abnormal sensor events that are not caused by an attempted attack on the security of the tamper-resistant element 102).

[0037] In some examples, as discussed above, the erasable event counter 110 is configured to have a consistent power supply. In some examples, in the event that power is disconnected (e.g., from the always-on register), the erasable event counter 110 may lose all or any portion of a certain amount of sensor event notifications, which may cause the number of sensor event notifications to be unreliable. In some examples, such power outages themselves may be part of an attempt to attack (e.g., inject a fault) the tamper-proof element. Therefore, in some examples, the erasable event counter 110 may include a power outage detector 118 or any component operatively connected to the erasable event counter (e.g., the always-on register) and / or operatively connected to the power outage detector or any component (e.g., via the processor 104 and / or via other fault injection mitigation logic components), which provides an indication to the erasable event counter 110 that a power outage has occurred. In some examples, such indications may cause a change in the behavior of the configuration of the tamper-proof element 102. As an example, the configuration of tamper-resistant element 102 may be updated so that sensor event notifications, when sensor events occur (e.g., via processor 104 and / or via other fault injection mitigation logic components), cause updates to values ​​stored by persistent event register 112 (discussed below) rather than updates to erasable event counter 110. In some examples, such changes may be referred to as updating the persistent event register update technique.

[0038] In some examples, the tamper-proof element 102 includes a permanent event register 112. In some examples, the permanent event register 112 is any hardware, software, firmware, and / or any combination thereof configured to store the number of occurrences of sensor event notifications. In some examples, the permanent event register 112 is called permanent because, as the name implies, the information written to the permanent register 112 may not be erasable or otherwise changeable. As an example, the permanent event register 112 may be a one-time programmable memory device configured to allow information to be written but not erased. As an example, the occurrence of an event may be written to the permanent event register 112, but may not be erasable. Therefore, in some examples, the permanent event register 112 may permanently record instances of sensor event notifications that are not erasable. In some examples, the permanent event register 112 may be configured with a threshold number of sensor events, and if the threshold number is reached and / or exceeded, the threshold number causes the tamper-proof element 110 to disable all or any part of the components therein (which may be referred to as an example of a fault injection mitigation action). As an example, the tamper-proof element 110 may be included as part of a SIM card. In such a scenario, if the permanent event registry 112 reaches or exceeds a threshold number of sensor events, portions of the SIM card that allow network connection may be disabled. As another example, the fault injection mitigation action may include resetting all or any portion of the tamper-resistant element 102 and / or the computing device 100. Other actions may be performed as fault injection mitigation actions without departing from the scope of the examples described herein.

[0039] In some examples, disabling parts of the SIM card may reduce user satisfaction. Even in examples where the sensor events recorded by the permanent event registry 112 are not the result of a security attack, such a reduction in user satisfaction may result. Therefore, the examples described herein use the above-mentioned erasable event counter 110 and other components of the tamper-proof element 102 to filter instances of sensor event notifications so as not to cause updates to the permanent event registry 112 unless such sensor events occur within a certain amount of time and / or at a specific frequency. As an example, if the erasable event counter has not been updated to reflect the occurrence of more than four sensor events within ten minutes of startup since the last startup of the tamper-proof element 102, the erasable event counter can be reset to restart the count for another ten minutes. In such scenarios, unless the erasable event counter 110 records a certain number of sensor events within a configured time period, the permanent event registry 112 is not updated, thereby increasing the possibility that the permanent event registry 112 does not reach the threshold number (unless the sensor event occurs at or above a specific frequency level) that causes a fault injection mitigation action.

[0040] Additionally or alternatively, the erasable event counter 110 may be configured to decrement after a configured amount of time, which may allow the erasable event counter to have a rolling count of sensor events per a specific time period. In such a scenario, the persistent event registry 112 may be updated only when the erasable event counter exceeds a configured threshold within a given time period, thereby increasing the likelihood that the persistent event registry 112 does not reach a threshold number that results in a fault injection mitigation action (unless sensor events occur at or above a specific frequency level).

[0041] As an example, consider a mobile device including a SIM card that is sometimes placed on the dashboard of a vehicle in a hot environment (which occasionally raises the device temperature), and is sometimes charged with a charger that provides inconsistent voltage input to the device. The SIM card includes an anti-tampering element that includes at least a temperature sensor and a voltage sensor, and a one-time programmable memory device as a permanent event register. Without using the example described herein including an erasable event counter, the temperature rises, and the inconsistent voltage input causes a sensor event that causes an update to the permanent event register. Over time, repeated temperature rises and inconsistent voltage inputs may cause the number of sensor events recorded by the permanent event register to reach and / or exceed a configured threshold for such events. Once such a threshold is reached, in order to prevent possible fault injection, the anti-tampering element may disable all or any part of the SIM card. Such fault injection mitigation actions may render all or any part of the mobile device inoperable, which may cause the user's satisfaction with the device to decrease because the sensor event is not the result of an actual security attack.

[0042] The examples discussed herein can improve the operation of such mobile devices by including an erasable event counter that is configured to track sensor events for a configured amount of time. Such examples can update a permanent event registry only when the frequency of sensor events reaches or exceeds a configured value. Thus, rather than performing fault injection mitigation actions based on the total number of sensor events regardless of the frequency of such events, fault injection mitigation actions can be performed only when detected sensor events are occurring frequently enough to reach and / or exceed a threshold for such events.

[0043] Figure 2 An example of a process 200 for performing fault injection mitigation according to the techniques described herein is illustrated. The process 200 may be performed by a processor such as Figure 1 The present invention may be executed by a device such as the computing device 100 or a component of the device (eg, a chipset, a processor, a memory, any combination thereof, and / or other components).

[0044] At block 202, a first device (or a component thereof) may receive a sensor event notification. As an example, a sensor event (e.g., based on a reading from a temperature sensor, a voltage sensor, etc.) may indicate a value exceeding a configured threshold, which may trigger a sensor event notification to be provided to an erasable event counter. Such a notification may be provided directly from the sensor, or via any other operational (e.g., logical) connection between the sensor and the erasable event counter (e.g., via a processor, via any other fault injection mitigation logic component, any combination thereof, etc.).

[0045] At block 204 , the first device (or a component thereof) may increment an erasable event counter based on the sensor event notification.

[0046] At block 206, the first device (or a component thereof) may make a first determination that the event count of the erasable event counter is below an event threshold. In some examples, the event threshold refers to a threshold number of sensor event notifications that may be recorded, for example, via the erasable event counter.

[0047] At block 208, the first device (or a component thereof) may make a second determination based on the first determination not to update the persistent event register. Figure 2 , but later, additional sensor event notifications may be received, which may cause the erasable event counter to be incremented again. Such increments may cause the erasable event counter to be above the event threshold, which may cause an update to the persistent event registry. In some examples, the update to the persistent event registry may cause the value stored in the persistent event registry to exceed the maximum sensor event threshold. In some examples, the maximum sensor event threshold is a configurable value that, if reached and / or exceeded, causes the execution of a fault injection mitigation action (e.g., disabling all or any portion of the tamper-resistant element and / or computing device).

[0048] In some cases, a device or apparatus configured to perform the operations of process 200 and / or other processes described herein may include a processor, microprocessor, microcomputer, or other component of a device configured to implement the steps of process 200 and / or other processes. In some examples, such a device or apparatus may include one or more sensors configured to capture image data and / or other sensor measurements. In some examples, such a computing device or apparatus may include one or more sensors and / or cameras configured to capture one or more images or videos. In some cases, such a device or apparatus may include a display for displaying an image. In some examples, one or more sensors and / or cameras are separated from a device or apparatus, in which case the device or apparatus receives sensed data. Such a device or apparatus may also include a network interface configured to convey data.

[0049] Components of a device or apparatus configured to perform one or more operations of process 200 and / or other processes described herein may be implemented in circuits. For example, a component may include an electronic circuit or other electronic hardware, and / or may be implemented using an electronic circuit or other electronic hardware, which may include one or more programmable electronic circuits (e.g., a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), a central processing unit (CPU), and / or other suitable electronic circuits), and / or may include computer software, firmware, or any combination thereof for performing the various operations described herein, and / or may be implemented using computer software, firmware, or any combination thereof for performing the various operations described herein. A computing device may also include a display (as an example of an output device or as a supplement to an output device), a network interface configured to communicate and / or receive data, any combination thereof, and / or other components. A network interface may be configured to communicate and / or receive data based on an Internet Protocol (IP) or other types of data.

[0050] Process 200 is illustrated as a logic flow diagram, the operations of which represent a sequence of operations that can be implemented in hardware, computer instructions, or a combination thereof. In the context of computer instructions, each operation represents a computer-executable instruction stored on one or more computer-readable storage media that, when executed by one or more processors, performs the described operation. Generally speaking, computer-executable instructions include routines, programs, objects, components, and data structures that perform specific functions or implement specific data types. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations may be combined in any order and / or in parallel to implement the process.

[0051] Additionally, the processes described herein (e.g., process 200 and / or other processes) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware on one or more processors or a combination thereof. As noted above, the code may be stored on a computer-readable or machine-readable storage medium, for example, in the form of a computer program that includes a plurality of instructions that can be executed by one or more processors. The computer-readable or machine-readable storage medium may be non-transitory.

[0052] Figure 3 is a diagram illustrating an example of a system for implementing certain aspects of the present technology. Specifically, Figure 3An example of a computing system 300 is illustrated, which may be any computing device, for example, constituting an internal computing system, a remote computing system, a camera, or any components thereof, wherein the components of the system communicate with each other using connection 305. Connection 305 may be a physical connection using a bus, or a direct connection into processor 310, such as in a chipset architecture. Connection 305 may also be a virtual connection, a networked connection, or a logical connection.

[0053] In some aspects, computing system 300 is a distributed system, where the functionality described in the present disclosure may be distributed within a data center, multiple data centers, a peer-to-peer network, etc. In some aspects, one or more of the described system components represent a number of such components that each perform some or all of the functionality for which the component is described. In some aspects, each component may be a physical or virtual device.

[0054] The example system 300 includes at least one processing unit (CPU or processor) 310 and connections 305 that couple various system components including system memory 315, such as read only memory (ROM) 320 and random access memory (RAM) 325, to the processor 310. The computing system 300 may include a cache 311 of high-speed memory directly connected to the processor 310, in close proximity to the processor, or integrated as part of the processor.

[0055] Processor 310 may include any general purpose processor and hardware or software services such as services 332, 334, and 336 stored in storage device 330 configured to control processor 310, as well as special purpose processors where software instructions are incorporated into the actual processor design. Processor 310 may essentially be a completely independent computing system containing multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0056] To enable user interaction, computing system 300 includes input device 345, which may represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphical input, a keyboard, a mouse, motion input, voice, etc. Computing system 300 may also include output device 335, which may be one or more of a plurality of output mechanisms. In some cases, a multimodal system may enable a user to provide multiple types of input / output to communicate with computing system 300. Computing system 300 may include communication interface 340, which may generally govern and manage user input and system output.

[0057] The communication interface can perform or facilitate the reception and / or transmission of wired or wireless communications using wired and / or wireless transceivers, including using audio jacks / plugs, microphone jacks / plugs, Universal Serial Bus (USB) ports / plugs, Apple ® Lightning ® Port / plug, Ethernet port / plug, Optical port / plug, Dedicated wired port / plug, BLUETOOTH ® Wireless signal transmission, BLUETOOTH ® Low power (BLE) wireless signal transmission, IBEACON ® Wireless signal transmission, radio frequency identification (RFID) wireless signal transmission, near field communication (NFC) wireless signal transmission, dedicated short range communication (DSRC) wireless signal transmission, 802.11 Wi-Fi wireless signal transmission, WLAN signal transmission, visible light communication (VLC), Worldwide Interoperability for Microwave Access (WiMAX), infrared (IR) communication wireless signal transmission, public switched telephone network (PSTN) signal transmission, integrated services digital network (ISDN) signal transmission, 3G / 4G / 5G / Long Term Evolution (LTE) cellular data network wireless signal transmission, ad hoc network signal transmission, radio wave signal transmission, microwave signal transmission, infrared signal transmission, visible light signal transmission, ultraviolet light signal transmission, wireless signal transmission along the electromagnetic spectrum, or some combination thereof.

[0058] The communication interface 340 may also include one or more GNSS receivers or transceivers for determining the location of the computing system 300 based on receiving one or more signals from one or more satellites associated with one or more GNSS systems. GNSS systems include, but are not limited to, the Global Positioning System (GPS) of the United States, the Global Navigation Satellite System (GLONASS) of Russia, the BeiDou Navigation Satellite System (BDS) of China, and the Galileo GNSS of Europe. There is no limitation to operating on any particular hardware arrangement, and thus the underlying features herein may be easily replaced to obtain improved hardware or firmware arrangements as they are developed.

[0059] The storage device 330 may be a non-volatile and / or non-transitory and / or computer-readable memory device, and may be a hard disk or other type of computer-readable medium that can store data that can be accessed by a computer, such as a magnetic cassette, a flash memory card, a solid-state memory device, a digital versatile disk, a cassette, a floppy disk, a floppy disk, a hard disk, a magnetic tape, a magnetic stripe / magnetic stripe, any other magnetic storage medium, a flash memory, a memristor memory, any other solid-state memory, a compact disc-read only memory (CD-ROM) disc, a rewritable compact disc (CD) disc, a digital video disc (DVD) disc, a Blu-ray disc (BDD) disc, a holographic disc, another optical medium, a secure digital (SD) card, a micro secure digital (microSD) card, a Memory Stick ® card, a smart card chip, a Europay, MasterCard and Visa (EMV) chip, a Subscriber Identity Module (SIM) card, a mini / micro / nano / pico SIM card, another integrated circuit (IC) chip / card, a RAM, a static RAM (SRAM), a dynamic RAM (DRAM), a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash EPROM (FLASHEPROM), a cache memory (L1 / L2 / L3 / L4 / L5 / L#), a resistive random access memory (RRAM / ReRAM), a phase change memory (PCM), a spin transfer torque RAM (STT-RAM), another memory chip or box, and / or a combination thereof.

[0060] Storage device 330 may include software services, servers, services, etc., which, when the code defining such software is executed by processor 310, causes the system to perform functions. In some aspects, hardware services that perform specific functions may include software components for performing functions stored in a computer-readable medium connected to the necessary hardware components (such as processor 310, connection 305, output device 335, etc.). The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing or carrying instructions and / or data. Computer-readable media may include non-transitory media in which data may be stored and does not include carrier waves and / or transient electronic signals propagated wirelessly or over a wired connection.

[0061] The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing or carrying instructions and / or data. Computer-readable media may include non-transient media in which data may be stored and does not include carrier waves and / or transient electronic signals that are propagated wirelessly or over a wired connection. Examples of non-transient media may include, but are not limited to, disks or tapes, optical storage media (such as compact disks (CDs) or digital versatile disks (DVDs)), flash memory, memory, or memory devices. Computer-readable media may have stored thereon code and / or machine-executable instructions that may represent procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, categories, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, independent variables, parameters, or memory contents. Information, independent variables, parameters, data, etc. may be passed, forwarded, or sent via any suitable means, including memory sharing, message passing, token passing, or network sending, etc.

[0062] In some aspects, computer readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer readable storage media expressly excludes media such as energy, carrier signals, electromagnetic waves, and signals themselves.

[0063] Specific details are provided in the above description to provide a detailed understanding of the various aspects and each example provided herein. However, it will be understood by those skilled in the art that these aspects can also be practiced without these specific details. For the sake of clarity of explanation, in some cases, the present technology may be presented as including a separate functional block, which includes a device, device component, step or routine in a method embodied in a combination of software or hardware and software. Additional components other than those components shown in the accompanying drawings and / or described herein may be used. For example, circuits, systems, networks, processes and other components may be shown as components in block diagram form to avoid confusing these aspects in unnecessary details. In other cases, known circuits, processes, algorithms, structures and techniques may be shown without unnecessary details to avoid confusing various aspects.

[0064] Various aspects may be described above as a process or method, which is depicted as a flow chart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flow chart may describe an operation as a sequential process, many operations in the operation may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. The process is terminated when the operation of the process is completed, but the process may have additional steps not included in the accompanying drawings. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, the termination of the process may correspond to the function returning to the calling function or the main function.

[0065] The processes and methods according to the above examples can be implemented using stored computer executable instructions or otherwise obtained from computer readable media. Such instructions may include, for example, instructions and data that configure a general-purpose computer, a special-purpose computer, or a processing device to perform a certain function or group of functions. Parts of the computer resources used can be accessed through a network. Computer executable instructions can be, for example, binary, intermediate format instructions such as assembly language, firmware, source code. Examples of computer readable media that can be used to store instructions, information used, and / or information created during the method according to the described examples include disks or optical disks, flash memories, USB devices with non-volatile memory, networked storage devices, etc.

[0066] Devices implementing the processes and methods according to these disclosures may include hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and may take any of a variety of form factors. When implemented in software, firmware, middleware, or microcode, program code or code segments (e.g., computer program products) for performing necessary tasks may be stored in a computer-readable or machine-readable medium. The processor may perform the necessary tasks. Typical examples of form factors include laptop computers, smart phones, mobile phones, tablet devices or other small form factor personal computers, personal digital assistants, rack-mounted devices, stand-alone devices, etc. The functionality described herein may also be embodied in peripheral devices or add-in cards. By way of further example, such functionality may also be implemented on circuit boards among different chips or different processes executed on a single device.

[0067] Instructions, media for conveying such instructions, computing resources for executing them, and other structures for supporting such computing resources are example components for providing the functionality described in this disclosure.

[0068] In the above description, various aspects of the present application are described with reference to their specific aspects, but those skilled in the art will recognize that the present application is not limited thereto. Thus, although the exemplary aspects of the present application have been described in detail herein, it should be understood that each inventive concept can be implemented and adopted in various other ways, and the appended claims are not intended to be interpreted as including such variations, unless limited by the prior art. Various features and aspects of the above-mentioned applications can be used individually or in combination. In addition, without departing from the broader essence and scope of this specification, various aspects can be utilized in any number of environments and applications beyond those described herein. Therefore, the description and the accompanying drawings should be considered as illustrative rather than restrictive. For the purpose of illustration, each method is described in a specific order. It should be understood that, in alternative aspects, each method can be performed in a different order than described.

[0069] It should be understood by those skilled in the art that the less than ("<") and greater than (">") symbols or terms used herein may be replaced by less than or equal to (" ”) and greater than or equal to (“ ”) symbol instead.

[0070] Where a component is described as being “configured to” perform certain operations, such configuration may be achieved, for example, by designing electronic circuits or other hardware to perform the operations, by programming programmable electronic circuits (e.g., a microprocessor or other suitable electronic circuits) to perform the operations, or any combination thereof.

[0071] The phrase "coupled to" means that any component is directly or indirectly physically connected to another component, and / or any component is directly or indirectly in communication with another component (eg, connected to another component via a wired or wireless connection and / or other suitable communication interface).

[0072] Claim language or other language in this disclosure that states "at least one of" a set and / or "one or more of" a set indicates that one member of the set or multiple members of the set (in any combination) satisfies the claim. For example, claim language that states "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, claim language that states "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, or A and B and C. The language "at least one of" a set and / or "one or more of" a set does not limit the set to the items listed in the set. For example, claim language that states "at least one of A and B" or "at least one of A or B" may mean A, B, or A and B, and may additionally include items not listed in the set of A and B.

[0073] Various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the examples disclosed herein may be implemented as electronic hardware, computer software, firmware, or a combination thereof. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints proposed for the entire system. The technician may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as departing from the scope of the present application.

[0074] The techniques described herein may also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques may be implemented in any of a variety of devices, such as general-purpose computers, wireless communication devices, or integrated circuit devices with multiple uses, including applications in wireless communication devices, mobile phones, and other devices. Any features described as modules or components may be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the technique may be implemented at least in part by a computer-readable data storage medium including a program code, which includes instructions for executing one or more of the methods, algorithms, and / or operations described above when executed. A computer-readable data storage medium may form part of a computer program product, which may include packaging materials. A computer-readable medium may include a memory or data storage medium, such as a random access memory (RAM) (such as a synchronous dynamic random access memory (SDRAM)), a read-only memory (ROM), a non-volatile random access memory (NVRAM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, and a magnetic or optical data storage medium, etc. Additionally or alternatively, the technology may be implemented at least in part by a computer-readable communication medium that carries or communicates program code in the form of instructions or data structures and that can be accessed, read, and / or executed by a computer, such as a propagated signal or wave.

[0075] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processors may be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Therefore, the term "processor" as used herein may refer to any of the aforementioned structures, any combination of the aforementioned structures, or any other structure or device suitable for implementing the techniques described herein.

[0076] Illustrative aspects of the present disclosure include:

[0077] Aspect 1: A method for fault injection mitigation, the method comprising: receiving a sensor event notification; incrementing an erasable event counter based on the sensor event notification; making a first determination that the number of events of the erasable event counter is below an event threshold; and making a second determination not to update a permanent event register based on the first determination.

[0078] Aspect 2: According to the method described in Aspect 1, the method also includes: receiving additional sensor event notifications; incrementing the erasable event counter based on the additional sensor event notifications; making a third determination that the number of events of the erasable event counter is higher than the event threshold; and updating the permanent event registry based on the third determination.

[0079] Aspect 3: According to the method of any one of Aspects 1 or 2, the method further includes: after updating the permanent event registry, making a fourth determination that a maximum sensor event threshold is reached; and performing a fault injection mitigation action based on the fourth determination.

[0080] Aspect 4: The method according to any one of aspects 1 to 3, wherein the fault injection mitigation action comprises: disabling at least a portion of the tamper-proof element.

[0081] Aspect 5: According to the method described in any one of Aspects 1 to 4, the method further includes: detecting a power-off event of an always-on register operably connected to the erasable event counter; and updating a permanent event registry update technology based on the power-off event to register all sensor events in the permanent event registry.

[0082] Aspect 6: The method according to any one of aspects 1 to 5, further comprising: making a third determination that a time threshold of the erasable event counter has been reached; and resetting the erasable event counter based on the third determination.

[0083] Aspect 7: The method according to any one of aspects 1 to 6, the method further comprising: making a third determination that a time threshold of the erasable event counter has been reached; and decrementing the erasable event counter based on the third determination.

[0084] Aspect 8: The method according to any one of aspects 1 to 7, wherein the sensor event notification is received based on a temperature sensor reading.

[0085] Aspect 9: The method according to any one of aspects 1 to 8, wherein the sensor event notification is received based on a voltage sensor reading.

[0086] Aspect 10: The method according to any one of aspects 1 to 9, wherein the sensor event notification is received based on a signal frequency sensor reading.

[0087] Aspect 11: A device for fault injection mitigation, the device comprising: an erasable event counter; a permanent event registry; at least one memory; and at least one processor, the at least one processor coupled to the at least one memory, wherein the device is configured to: receive a sensor event notification at the erasable event counter; increment the erasable event counter based on the sensor event notification; make a first determination that the number of events of the erasable event counter is lower than an event threshold; and make a second determination not to update the permanent event registry based on the first determination.

[0088] Aspect 12: An apparatus according to Aspect 11, wherein the apparatus is further configured to: receive additional sensor event notifications; increment the erasable event counter based on the additional sensor event notifications; make a third determination that the number of events of the erasable event counter is greater than the event threshold; and update the permanent event registry based on the third determination.

[0089] Aspect 13: The apparatus according to aspect 11 or 12, wherein the apparatus is further configured to: after updating the permanent event registry, make a fourth determination that a maximum sensor event threshold is reached; and perform a fault injection mitigation action based on the fourth determination.

[0090] Aspect 14: The apparatus of any one of Aspects 11 to 13, wherein the fault injection mitigation action comprises: disabling at least a portion of a tamper-resistant element.

[0091] Aspect 15: An apparatus according to any one of Aspects 11 to 14, wherein the apparatus is further configured to: detect a power-off event of an always-on register operably connected to the erasable event counter; and update a permanent event registry update technique based on the power-off event to register all sensor events in the permanent event registry.

[0092] Aspect 16: An apparatus according to any one of aspects 11 to 15, wherein the apparatus is further configured to: make a third determination that a time threshold of the erasable event counter has been reached; and reset the erasable event counter based on the third determination.

[0093] Aspect 17: An apparatus according to any one of aspects 11 to 16, wherein the apparatus is further configured to: make a third determination that a time threshold of the erasable event counter has been reached; and decrement the erasable event counter based on the third determination.

[0094] Aspect 18: The apparatus of any one of aspects 11 to 17, wherein the sensor event notification is received based on a temperature sensor reading.

[0095] Aspect 19: The apparatus of any one of aspects 11 to 18, wherein the sensor event notification is received based on a voltage sensor reading.

[0096] Aspect 20: The apparatus of any one of aspects 11 to 19, wherein the sensor event notification is received based on a signal frequency sensor reading.

[0097] Aspect 21: A non-transitory computer-readable medium having instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to perform the following operations: receive a sensor event notification; increment an erasable event counter based on the sensor event notification; make a first determination that the number of events in the erasable event counter is below an event threshold; and make a second determination not to update a permanent event register based on the first determination.

[0098] Aspect 21: According to the non-transitory computer-readable medium described in Aspect 21, additional instructions are stored on the non-transitory computer-readable medium, and when the additional instructions are executed by the one or more processors, the one or more processors perform the following operations: receive additional sensor event notifications; increment the erasable event counter based on the additional sensor event notifications; make a third determination that the number of events of the erasable event counter is higher than the event threshold; and update the permanent event registry based on the third determination.

[0099] Aspect 23: According to the non-transitory computer-readable medium described in Aspect 21 or 22, the non-transitory computer-readable medium has additional instructions stored thereon, and when the additional instructions are executed by the one or more processors, the one or more processors perform the following operations: after updating the permanent event registry, make a fourth determination that the maximum sensor event threshold is reached; and perform fault injection mitigation actions based on the fourth determination.

[0100] Aspect 24: The non-transitory computer-readable medium of any one of Aspects 21 to 23, wherein the fault injection mitigation action comprises disabling at least a portion of a tamper-resistant element.

[0101] Aspect 25: According to any one of Aspects 21 to 24, the non-transitory computer-readable medium has additional instructions stored thereon, and the additional instructions, when executed by the one or more processors, cause the one or more processors to perform the following operations: detect a power-off event of an always-on register operably connected to the erasable event counter; and update a permanent event registry update technique based on the power-off event to register all sensor events in the permanent event registry.

[0102] Aspect 26: According to any one of Aspects 21 to 25, the non-transitory computer-readable medium has additional instructions stored thereon, and the additional instructions, when executed by the one or more processors, cause the one or more processors to perform the following operations: make a third determination that the time threshold of the erasable event counter has been reached; and reset the erasable event counter based on the third determination.

[0103] Aspect 27: According to any one of Aspects 21 to 26, the non-transitory computer-readable medium has additional instructions stored thereon, and the additional instructions, when executed by the one or more processors, cause the one or more processors to perform the following operations: make a third determination that the time threshold of the erasable event counter has been reached; and decrement the erasable event counter based on the third determination.

[0104] Aspect 28: The non-transitory computer-readable medium of any one of aspects 21 to 27, wherein the sensor event notification is received based on a temperature sensor reading.

[0105] Aspect 29: The non-transitory computer readable medium of any one of aspects 21 to 28, wherein the sensor event notification is received based on a voltage sensor reading.

[0106] Aspect 30: The non-transitory computer-readable medium of any one of aspects 21 to 29, wherein the sensor event notification is received based on a signal frequency sensor reading.

[0107] Aspect 30: An apparatus for fault injection mitigation, the apparatus comprising one or more components for performing the operations according to any one of Aspects 1 to 10.

Claims

1. A method for fault injection mitigation, the method comprising: Receive sensor event notifications; incrementing an erasable event counter based on the sensor event notification; making a first determination that a number of events of the erasable event counter is below an event threshold; as well as A second determination is made based on the first determination not to update the persistent event registry.

2. The method according to claim 1, further comprising: Receive additional sensor event notifications; incrementing the erasable event counter based on the additional sensor event notification; making a third determination that the number of events of the erasable event counter is above the event threshold; as well as The permanent event registry is updated based on the third determination.

3. The method according to claim 2, further comprising: After updating the permanent event registry, making a fourth determination that a maximum sensor event threshold has been reached; as well as A fault injection mitigation action is performed based on the fourth determination.

4. The method of claim 3, wherein the fault injection mitigation action comprises: At least a portion of the tamper-resistant element is disabled.

5. The method according to claim 1, further comprising: detecting a power-off event of an always-on register operatively connected to the erasable event counter; as well as A persistent event registry update technique is updated based on the power off event to register all sensor events in the persistent event registry.

6. The method according to claim 1, further comprising: making a third determination that a time threshold of the erasable event counter has been reached; as well as The erasable event counter is reset based on the third determination.

7. The method according to claim 1, further comprising: making a third determination that a time threshold of the erasable event counter has been reached; as well as The erasable event counter is decremented based on the third determination. The method of claim 1 , wherein the sensor event notification is received based on a temperature sensor reading. 9 . The method of claim 1 , wherein the sensor event notification is received based on a voltage sensor reading.

10. The method of claim 1, wherein the sensor event notification is received based on a signal frequency sensor reading.

11. An apparatus for fault injection mitigation, the apparatus comprising: Erasable event counter; Permanent event registry; at least one memory; and at least one processor coupled to the at least one memory, wherein the apparatus is configured to: receiving a sensor event notification at the erasable event counter; incrementing the erasable event counter based on the sensor event notification; making a first determination that a number of events of the erasable event counter is below an event threshold; as well as A second determination is made based on the first determination not to update the persistent event registry.

12. The apparatus according to claim 11, wherein the apparatus is further configured to: Receive additional sensor event notifications; incrementing the erasable event counter based on the additional sensor event notification; making a third determination that the number of events of the erasable event counter is above the event threshold; as well as The permanent event registry is updated based on the third determination.

13. The apparatus according to claim 12, wherein the apparatus is further configured to: After updating the permanent event registry, making a fourth determination that a maximum sensor event threshold has been reached; and A fault injection mitigation action is performed based on the fourth determination.

14. The apparatus of claim 13, wherein the fault injection mitigation action comprises: At least a portion of the tamper-resistant element is disabled.

15. The apparatus according to claim 11, wherein the apparatus is further configured to: detecting a power-off event of an always-on register operatively connected to the erasable event counter; and A persistent event registry update technique is updated based on the power off event to register all sensor events in the persistent event registry.

16. The apparatus according to claim 11, wherein the apparatus is further configured to: making a third determination that a time threshold of the erasable event counter has been reached; and The erasable event counter is reset based on the third determination.

17. The apparatus according to claim 11, wherein the apparatus is further configured to: making a third determination that a time threshold of the erasable event counter has been reached; and The erasable event counter is decremented based on the third determination.

18. The apparatus of claim 11, wherein the sensor event notification is received based on a temperature sensor reading.

19. The apparatus of claim 11, wherein the sensor event notification is received based on a voltage sensor reading.

20. The apparatus of claim 11, wherein the sensor event notification is received based on a signal frequency sensor reading.

21. A non-transitory computer readable medium having instructions stored thereon, the instructions, when executed by one or more processors, causing the one or more processors to perform the following operations: Receive sensor event notifications; incrementing an erasable event counter based on the sensor event notification; making a first determination that a number of events of the erasable event counter is below an event threshold; as well as A second determination is made based on the first determination not to update the persistent event registry.

22. The non-transitory computer readable medium of claim 21 having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: Receive additional sensor event notifications; incrementing the erasable event counter based on the additional sensor event notification; making a third determination that the number of events of the erasable event counter is above the event threshold; as well as The permanent event registry is updated based on the third determination.

23. The non-transitory computer readable medium of claim 22 having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: After updating the permanent event registry, making a fourth determination that a maximum sensor event threshold has been reached; and A fault injection mitigation action is performed based on the fourth determination.

24. The non-transitory computer readable medium of claim 23, wherein the fault injection mitigation action comprises: At least a portion of the tamper-resistant element is disabled.

25. The non-transitory computer readable medium of claim 21 having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: detecting a power-off event of an always-on register operatively connected to the erasable event counter; and A persistent event registry update technique is updated based on the power off event to register all sensor events in the persistent event registry.

26. The non-transitory computer readable medium of claim 21 having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: making a third determination that a time threshold of the erasable event counter has been reached; and The erasable event counter is reset based on the third determination.

27. The non-transitory computer readable medium of claim 21 having further instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to: making a third determination that a time threshold of the erasable event counter has been reached; and The erasable event counter is decremented based on the third determination.

28. The non-transitory computer readable medium of claim 21, wherein the sensor event notification is received based on a temperature sensor reading.

29. The non-transitory computer readable medium of claim 21, wherein the sensor event notification is received based on a voltage sensor reading.

30. The non-transitory computer readable medium of claim 21, wherein the sensor event notification is received based on a signal frequency sensor reading.

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