Functional circuit block acquisition in integrated circuit

Abstract

An integrated circuit (IC) that can be configured for use in one of several possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable registers. The programmable register, when programmed, enables the corresponding functional circuit block to be fully or partially disabled. Different platforms support different sets of peripheral devices. Thus, a programmable register is used to configure the IC for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform to support its particular set of peripherals.

Description

Background Art Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly, to integrated circuits having configurable functionality.

[0002] Related technical description

[0003] As feature sizes have decreased, the amount of functionality that can be implemented on an integrated circuit (IC) has correspondingly increased. Thus, many functions that were previously placed on multiple IC dies can now be combined into a single IC. Furthermore, the level of integration on an IC has increased to the point where an entire system (referred to as a SoC) can be combined onto a single IC. An SoC can combine various functional circuit blocks such as a processor core, a graphics processor, a memory controller, image system processing circuitry, various types of input / output (I / O) circuitry, including circuit blocks that support various types of wired I / O (e.g., high-speed serial links), and circuit blocks that support radio frequency communications, and the like.

[0004] SoCs are used in a wide variety of systems. Some systems that utilize SoCs include smart watches, mobile devices (e.g., smartphones, tablet computers), TV set-top boxes, desktop computers, servers, etc. These various systems can utilize corresponding SoCs that incorporate functionality levels as required by their specific applications. Summary of the invention

[0005] The present disclosure relates to an IC that can be configured for use in any of several different platforms. In one embodiment, an integrated circuit (IC) includes a set of processing blocks for a computer system, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks. The IC includes a set of programmable registers associated with the processing blocks in the set of processing blocks, wherein the IC is configured to disable a portion of a given processing block in the set of processing blocks when a given programmable register in the set of programmable registers is set. The processing blocks in the set of processing blocks are configured to be at least partially disabled by setting a programmable register in the set of programmable registers, so that the IC can be configured for use in different computing platforms by partially or completely disabling different combinations of the set of processing blocks. At least two of the different computing platforms support different sets of peripheral devices.

[0006] In one embodiment, a method includes: testing an IC having a plurality of functional circuit blocks; and determining, based on the testing, that one or more of the plurality of functional circuit blocks on the IC are unable to perform their intended functions. The method also includes programming one or more of the programmable registers corresponding to the one or more of the plurality of functional circuit blocks that are determined to be unable to perform their intended functions. As a result of the programming, a corresponding power switch of a plurality of power switches may be configured (e.g., disconnected) so that power is not provided to its corresponding functional circuit block of the plurality of functional circuit blocks. Subsequently, the method includes programming an additional programmable register of the programmable registers to prohibit power from being provided to a corresponding functional circuit block of the functional circuit block, thereby disabling these functional circuit blocks according to a selected computing platform.

[0007] The present disclosure also contemplates a computer system having a set of processing blocks, wherein the computer system includes a set of programmable registers, wherein a given one of the programmable registers corresponds to at least one processing block in the set of processing blocks. The computer system is configured to receive an acquisition command to write a disable value to a set of one or more programmable registers in the programmable registers, the set of programmable registers corresponding to a set of processing blocks in the set of processing blocks to be disabled for a selected computing platform among a plurality of different computing platforms for which the computer system can be configured. The computer system also includes one or more hardware circuits configured to perform one or more tasks after a given startup of the computer system, wherein the one or more tasks utilize circuits in at least one processing block in the set of processing blocks in the set of processing blocks. The power control circuit is configured to temporarily disable the set of processing blocks in the set of processing blocks after the one or more tasks have been performed, thereby configuring the computer system for the selected computing platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0009] Figure 1 is a block diagram of one embodiment of an integrated circuit (IC).

[0010] Figure 2 is a block diagram of one embodiment of a system on a chip (SoC).

[0011] Figure 3 is a block diagram of another implementation of an IC.

[0012] Figure 4A is a block diagram of another implementation of an IC.

[0013] Figure 4Bis a block diagram of another embodiment of an IC in which functional circuit blocks are enabled to perform tasks during a cold start prior to being disabled.

[0014] Figure 4C is a diagram illustrating an example mechanism by which a functional circuit block may be disabled based on setting a programmable register.

[0015] Figure 5 is a diagram illustrating a product matrix of a specific design using IC / SoC in different platforms.

[0016] Figure 6 is a block diagram illustrating different platforms upon which embodiments of the IC / SoC may be implemented.

[0017] Figure 7 is a flow chart of one embodiment of a method for configuring an IC for use in a particular platform.

[0018] Figure 8 is a flow chart of another embodiment of a method for configuring an IC for use in a particular platform.

[0019] Fig. 9 is a flow chart of another embodiment of a method for configuring an IC for use in a particular platform.

[0020] Fig.10 is a flow chart of an embodiment of performing a cold boot in a system and subsequently disabling certain functional circuit blocks.

[0021] Fig.11 is a block diagram of one implementation of a test system.

[0022] Fig.12 is a block diagram of one embodiment of a computer readable medium and a manufacturing system for manufacturing a circuit according to the present disclosure. DETAILED DESCRIPTION

[0023] The present disclosure relates to various methods for configuring SoC according to a specific system / computing platform where SoC (and more generally, IC) will be used.SoC can be manufactured to combine various different functions.In addition, companies that manufacture various electronic devices can sometimes adopt public SoC architecture across various platforms.For example, public SoC architecture (including public instruction set architecture or ISA for processing circuits therein) can be adopted on a series of platforms including smart watches, mobile computing devices (e.g., tablets, smart phones), set-top boxes for TV, laptop computers and desktop computers, server systems, etc. Although public SoC architecture is adopted, these different platforms may have different functional requirements.For example, although smart phones can include cameras utilizing image processing systems, the set-top boxes utilizing the SoC of the same architecture may not need to perform any image processing.

[0024] At the end of the manufacturing process, the SoC / IC undergoes testing to verify its functionality. In some cases, some circuit blocks may not pass the test. However, the failure of some circuit blocks does not necessarily make a specific instance of the SoC / IC unavailable. For example, if the image processing system for a camera fails in a specific instance of the SoC, it can still be used in a platform that does not utilize a camera, such as a desktop computer or a TV set-top box. In another example, in a SoC with several processor cores, an instance of the SoC with some failed instances can still be useful in a system that does not require a full complement of processor cores. Therefore, a SoC that is unavailable in a high-power desktop computer due to some failed processor cores is still useful in a smart watch, a tablet computer, or other platforms with lower processing requirements.

[0025] An example of an SoC (and more generally, any IC) that remains usable despite the presence of some failed circuit blocks can use programmable registers to disable the failed circuit blocks. This can prevent these circuit blocks from receiving any power, and can also prevent them from receiving clock signals. By disabling functional circuit blocks so that they cannot receive power and / or clock signals, these functional circuit blocks can be prohibited from inadvertently generating any signals that can adversely affect the operation of other fully functional circuit blocks. In addition, disabling unused functional circuit blocks by prohibiting the supply of power to the functional circuit blocks can reduce the static power consumption of the IC / SoC.

[0026] When a particular instance of a SoC is designated as being capable of use in a particular platform, the SoC has functional circuit blocks on it that are not used but have been tested. Referring again to the example given above, a desktop computer may include a SoC with image processing circuitry that is fully capable of performing its intended functions, although such circuitry is not required. To use another example given above, a SoC designated for implementation in a set-top box may also have functional image processing circuitry without a corresponding requirement for that functional image processing circuitry.

[0027] Thus, the present disclosure contemplates a specifically designed SoC that can be used in a variety of different platforms. The present disclosure also contemplates various methods for acquiring a SoC to be used in a specific platform among those platforms. The specifically designed SoC may include programmable registers for each functional circuit block that is coupled to receive power via a power switch and is therefore capable of being powered off during operation (e.g., to enter a sleep mode). These programmable registers, when programmed, may render the corresponding functional circuit block unable to receive power, thereby effectively disabling the corresponding functional circuit block.

[0028] The present disclosure contemplates programmable registers as one-time programmable devices with limited programmability. For example, the default condition of a programmable register when unprogrammed may be to allow the corresponding functional circuit block to be enabled. However, when programmed, the programmable register may cause the corresponding functional circuit block to be disabled. The limited programmability in various embodiments may prevent the programmable register from being reprogrammed to subsequently enable a previously disabled functional circuit block. In addition, the programmable registers of the present disclosure may be one-time programmable devices because, once programmed to disable a given functional circuit block, these registers remain programmed in that state for at least the remainder of a particular session of the computing platform (where the start of a session may be marked by a cold start).

[0029] In one embodiment, a method includes testing a SoC and determining which of its various functional circuit blocks are able to perform their intended functions. Based on the test, the functional circuit blocks that fail the test (if any) can be disabled by programming their corresponding programmable registers so that the functional circuit blocks cannot receive power. Based on which functional circuit blocks are disabled as a result of the test, the SoC can be specified for use in one or more platforms that do not utilize the capabilities of the disabled circuits. Thus, for example, an instance of a SoC having an image processing circuit disabled by programming corresponding programmable registers can be specified for use in a server, a desktop computer, or a set-top box (assuming that other required capabilities are enabled), and is excluded from use in, for example, a smart phone or a tablet that utilizes the function in conjunction with a camera. In another example, a SoC having multiple (but not all) processor cores disabled can be specified for use in a smart watch, but is excluded from use in a high-power desktop computer.

[0030] The present disclosure also contemplates disabling additional functional circuit blocks of a SoC (or more generally, an IC) by using a programmable register in the programmable registers. The computer system may receive a capture command (e.g., from a cryptographic signature or other source) and program the additional programmable registers to disable the additional functional circuit blocks.

[0031] In light of the foregoing, the present disclosure also contemplates methods for acquiring IC / SoCs based on test results and platform requirements. In one embodiment, a SoC may undergo testing to determine the ability of its various functional circuit blocks to perform their intended operations. After testing, if certain functional circuit blocks fail while other functional circuit blocks are fully functional, the SoC may be designated for one or more platforms that do not require the functional circuit blocks that failed the test. The SoC may then be selected for a particular platform, and configuration registers may be programmed during system startup (e.g., cold boot) to keep any additional, unneeded functional circuit blocks powered off during operation of the SoC.

[0032] With respect to ICs / SoCs according to the present disclosure, at least one programmable register may be provided for each functional circuit block with a dedicated power switch that allows each functional circuit block to be powered down independently of other functional circuit blocks when enabled. In some embodiments, a particular functional circuit block may include a programmable register that enables powering up both power gating and clock gating of the particular functional circuit block when both are programmed.

[0033] The present disclosure contemplates a wide variety of functional circuit blocks that can be powered down independently of other functional circuit blocks. Examples of such functional circuit blocks include (but are not limited to) processor cores, memory controllers, graphics processing cores, image system processors, various input / output (I / O) circuits such as various radio frequency communication circuits (e.g., cellular, WiFi, Bluetooth circuits), serial and parallel communication links for transferring data to / from the SoC / IC, network interface circuits (e.g., Ethernet controllers), and the like.

[0034] The present disclosure also contemplates that some SoC / ICs include an "always on" portion that communicates with other functional circuit blocks. As defined herein, an always-on circuit is a functional circuit block that continues to receive power and operate at any time when the SoC / IC is receiving power (and is therefore never put into a sleep state). An example of a circuit in an always-on functional circuit block is a processor that responds to a touch of a touch screen in a SoC for a smartphone when the rest of the SoC is in a sleep state. The processor can wake up the rest of the SoC to allow operation to resume. Since the functional circuit blocks in the always-on portion of the SoC / IC can be configured to communicate with other functional circuit blocks in the SoC, the signal can be sent to a circuit that is disabled by using a specific programmable register in the programmable registers. Therefore, the present disclosure contemplates additional programmable registers that can be used to cut off communication between a normally-on circuit and a functional circuit block that has been disabled or otherwise not required for a particular platform due to a failed test.

[0035] In some instances, during the startup (e.g., cold start) of the system, it may be necessary for certain functions to be intended to disable a specific functional circuit block. For example, the IC / SoC may include built-in self-test (BIST) functionality, wherein the BIST controller is implemented in various functional circuit blocks in the functional circuit block, including the functional circuit block that will be disabled for a specific computing platform. These BIST controllers can be coupled to each other in a daisy chain configuration, and can perform tests and communicate with the main BIST controller during system startup. If the specific functional circuit block is disabled, the communication link to the main BIST controller via the daisy chain will be cut off. Therefore, the present disclosure contemplates that the selected programmable register in the programming programmable register enables limited functionality during the system startup procedure to allow execution of tasks (such as the aforementioned test using the BIST controller), wherein the corresponding functional circuit block is disabled thereafter. The disabling of these functional circuit blocks can be performed after their specified tasks are completed and before the system software accesses them. The disabled functional circuit block can remain disabled during the entire session until the next cold start, after which the same cycle can be repeated.

[0036] Various embodiments of multi-platform IC / SoC and methods for configuring multi-platform IC / SoC for specific platforms are now discussed in further detail. The description begins with a discussion of various embodiments of IC / SoC, which can be configured for use in various platforms in various different platforms, while implementing a common architecture between all platforms. The product matrix and system diagram of different platforms that illustrate the use of SoCs with a given architecture are then discussed. Thereafter, a description of various methods for testing, configuring, implementing and operating the IC / SoC of the present disclosure is as follows. The description ends with a discussion of a test system and a computer-readable medium for testing IC / SoC, on which the design of the IC / SoC is represented and can be used for the manufacture of the IC / SoC.

[0037] Multi-platform IC / SoC implementation :

[0038] Figure 1 is a block diagram of one embodiment of an IC that may be configured for use in one of a variety of different platforms. IC 100 is shown here by way of example to illustrate a configurable IC, and is not intended to limit the present disclosure to any particular IC embodiment.

[0039] In the illustrated embodiment, IC 100 includes a programmable register file 103 and a plurality of power switches 104. The power switches are coupled to provide various supply voltages (e.g., Vdd1, Vdd2, etc.) to correspondingly coupled functional circuit blocks. In the illustrated embodiment, Vdd1 may be provided to a graphics processing unit (GPU) circuit block 110 (which includes several GPU cores) via switches S1 and S2, Vdd2 may be provided to a central processing unit (CPU) circuit block 105 (including several processor cores) via switches S3, S4, and S5, Vdd3 may be provided to a functional circuit block 115 via switch S6, and Vdd4 may be provided to a functional circuit block 116 via switch S7. Functional circuit blocks 115 and 116 may be one of several different types of circuits such as image processing circuits, network interfaces, radio frequency (RF) circuits (e.g., WiFi transceivers), etc. The various circuit blocks including CPU circuit block 105 and GPU circuit block 110 may represent heterogenous processing blocks that perform various functions of IC 100 .

[0040] In this particular example, the GPU circuit block 110 is at least partially disabled due to S2 being disconnected, which may be the result of programming the corresponding programmable register in the programmable register file 103. Therefore, the supply voltage Vdd1 is only provided to some portions of the GPU circuit block 110, but not all. Similarly, the CPU circuit block 105 is partially disabled due to the disconnected state of S5, while switches S3 and S4 are closed to provide power to its portions. In this example, the functional circuit block 115 is completely disabled due to the disconnection of switch S6, while the functional circuit block 116 is completely enabled due to the closed state of S7. In this example, the disconnected states of these switches are the result of programming the corresponding programmable registers in the programmable register file 103.

[0041] In the illustrated embodiment, disabling of a particular one of the circuit blocks or a portion thereof may be accomplished by programming a programmable register in a corresponding programmable register (PR1-PR) in the programmable register file 103. In one embodiment, a particular programmable register may be programmed such that its corresponding power switch remains open to disable all or a portion of the functional circuit block. In general, a programmable register according to the present disclosure may fully or partially disable a corresponding functional circuit block by prohibiting power and / or clock signals (or both) from being provided to the corresponding functional circuit block.

[0042] Please note that although Figure 1 The programmable registers are shown grouped into a single unit (programmable register file 103), but this configuration is not intended to be limiting. Instead, the programmable registers in these programmable registers can be distributed around IC 100 in any desired manner.

[0043] The programmable registers of the present disclosure have limited programmability in various embodiments. For example, a programmable register may allow power to be provided to a corresponding functional circuit block in its unprogrammed state. When programmed, the same programmable register may cause a corresponding power switch to be disconnected to disable the functional circuit block by preventing the functional circuit block from receiving power. Once programmed to disable its corresponding functional circuit block, a particular programmable register may not be reprogrammed to subsequently enable the same functional circuit block to perform its intended operation.

[0044] In various embodiments, one or more of the programmable registers may be switches with limited programmability (e.g., from enable to disable), and they may further be one-time programmable structures. For example, a switch circuit that cannot be closed again (or vice versa) during a particular session once disconnected may be used to implement the programmable register. It is also envisioned that the programmable register is implemented as an embodiment of a programmable read-only memory (PROM) structure. In some embodiments, fuses may be used to implement at least some of the programmable registers, wherein a given one of the fuses disables a corresponding one of the functional circuit blocks or a portion thereof when it is blown (e.g., prohibiting the supply of power and / or clock signals thereto). In general, a programmable register according to the present disclosure is a device or circuit that, once programmed to a particular state, cannot be reprogrammed to a different state, and further can only be programmed to a particular value. With respect to the functional circuit blocks of a given embodiment, a programmable register according to the present disclosure is limited because the programmable register can be programmed from its default state that allows enabling to disable one of the corresponding functional circuit blocks, but cannot be programmed in the opposite direction.

[0045] It is also noted that different types of programmable registers may be used in a single embodiment. For example, the present disclosure contemplates embodiments in which fuses are used to implement some programmable registers and unidirectionally operable switch circuits are used to implement other of the programmable registers.

[0046] The IC 100 in the illustrated embodiment may be utilized in any of a number of different platforms. Using the programmable registers of the programmable register unit 103 and the power switch 104, an instance of the IC may be configured for use in a particular platform by disabling or keeping enabled various ones of the functional circuit blocks and processing blocks. This may include disabling some peripheral components while keeping other peripheral components enabled, and may also include disabling portions of, for example, the CPU circuit block 105 and the GPU circuit block 110. In some platforms, peripherals are enabled or disabled as needed. For example, for a desktop computer that does not utilize a camera, a corresponding instance of the IC / SoC may disable an image processing circuit block designed to support camera operations.

[0047] In addition, the amount of processing power enabled and disabled can vary from one platform to another. Therefore, an instance of an IC / SoC specified for use in a high-performance desktop computer (e.g., a gaming PC) can utilize a full complement of CPU and GPU cores. On the other hand, an instance of an IC / SoC used in an entry-level smartphone can utilize a reduced complement of CPU and GPU cores, and therefore portions of the corresponding CPU and GPU circuit blocks can be disabled. Using this method, a single design of an IC / SoC can be used for a variety of platforms, including (but not limited to) smart watches, servers, desktop computers, laptop computers, tablets, smartphones, TV set-top boxes, etc., as well as different performance levels (e.g., high-performance desktop computers or medium-performance desktop computers) for a given type of platform. The design of the IC / SoC can implement a common computing architecture in all these systems, with the main difference being the ability to be enabled or disabled.

[0048] Figure 2It is a block diagram of an embodiment of a SoC that can be used in a variety of platforms. In the illustrated embodiment, SoC 200 includes several different functional circuit blocks and can be implemented in a variety of different platforms that operate using a public computing architecture. These platforms include (but are not limited to) smart watches, smart phones, tablet computers, laptop computers, desktop computers, monitors, TV set-top boxes, server computers, Internet of Things (IoT) devices, and various vehicle-based computing systems, etc. Various devices to which SoC 200 is applicable can utilize a public computing architecture that can allow relatively seamless data transmission and communication between these different platforms. However, due to the presence of a large number of different functional circuit blocks in SoC 200, some functional circuit blocks may not be used in certain platforms. The present disclosure describes various methods and mechanisms that can be used to configure an instance of SoC 200 for use in a specific platform while disabling unused or unnecessary functional circuit blocks. This can provide various advantages, such as reducing static power consumption, and reducing parasitic noise that may be generated by originally unused circuits.

[0049] SoC 200 in the illustrated embodiment includes several different functional circuit blocks. Each of these functional circuit blocks can be powered via a corresponding power switch (not shown here) and can be powered on or off independently of other functional circuit blocks in SoC 100.

[0050] The functional circuit blocks of SoC 200 include a CPU block 203 having processor cores 211 and 212. In this embodiment, processor cores 211 and 212 are general-purpose processors optimized for different goals. For example, processor core 211 may be optimized for high performance, with the ability to handle heavy workloads, while processor core 212 is optimized for handling lighter workloads while limiting power consumption. Although Figure 2 Four processor cores are included, but this is not intended to limit the number of cores in a particular embodiment. For example, an embodiment with 16 processor cores is possible and is contemplated within the scope of the present disclosure. In addition, although the illustrated embodiment contemplates heterogeneous multi-core processing, an embodiment utilizing homogeneous multi-core processing is also possible and contemplated. The number of processor cores enabled in a particular platform may vary according to the processing needs of the platform. Therefore, some of the processor cores in the processor cores of SoC 200 may be disabled in some platforms. For example, in a high-end desktop computer system, all processor cores may be enabled, while in an entry-level laptop computer, one of the processor cores in processor core 211 and one of the processor cores in processor core 212 may be disabled.

[0051] Various embodiments of SoC 200 include a neural engine 255 that can be used to perform various machine learning functions. In some embodiments, the neural engine 255 can be a processor circuit that acts as a coprocessor for each processor core 211. In such embodiments, the neural engine 255 can receive instructions from each processor core in the processor core 211, perform operations according to the instructions, and return results to the processor core. In various embodiments, the neural engine 255 can include an array of processing elements, and these processing elements can be independently disabled relative to other processing elements in the processing elements.

[0052] The SoC 200 in the illustrated embodiment also includes a graphics processing unit 214 that includes several different graphics cores 215 as functional circuit blocks. The graphics cores 215 may include circuits for performing various graphics processing functions, but in some embodiments may also perform processing functions with a certain degree of parallelism. The number of graphics cores 215 enabled in the SoC 200 may vary from one platform to the next. For example, a desktop computer optimized for gaming or other graphics-intensive processing may enable all graphics cores, while an application such as a smartwatch may use fewer graphics cores and therefore have fewer graphics cores enabled. In platforms where graphics processing is not required, all graphics cores 215 may be disabled.

[0053] The SoC 200 in this particular embodiment includes two memory controllers 205, but in other embodiments the number of memory controllers may be greater or less than the number shown here. Each of the memory controllers 215 includes circuitry for facilitating communication between system memory and other functional circuit blocks, such as processor cores 211 and 212. Some platforms may utilize more memory controllers 205 than other platforms. For example, a desktop computer may utilize multiple memory controllers 205, while a smartwatch may utilize only a single instance of a memory controller. Thus, in the latter example, all but one memory controller 205 may be disabled.

[0054] In some embodiments, various memory controllers 205 may be associated with corresponding on-chip memories that share a common voltage supply. Since these memories share a common voltage source, they cannot be powered off independently of each other. Therefore, it is desirable to drive various signals such as a reset signal in this case, or conversely to disable a chip select signal to prevent unused memories from generating noise or leakage. Therefore, the present disclosure contemplates providing support logic that will perform the function of controlling a reset signal or a chip select signal when the corresponding memory controller 205 is disabled. For example, the support logic can prevent the reset signal from deasserting the unused memory, thereby keeping the unused memory in a reset state, and preventing it from generating noise that may affect the operation of other circuits. The support logic can be activated, for example, using a programmable register discussed elsewhere herein.

[0055] SoC 200 also includes a display controller 227. Display controller 227 may include circuits that perform various functions related to controlling a display such as a touch screen (e.g., for a smartphone or tablet computer) or a monitor coupled to a desktop computer. Some platforms such as television set-top boxes or servers may not include a dedicated display, or in the latter case, are not coupled to a dedicated display. In such platforms, display controller 227 may be disabled.

[0056] The image system processor (ISP) 225 in the illustrated embodiment includes circuitry to perform image processing in conjunction with a camera included in such platforms, such as a tablet computer or a smart phone. The image processing circuitry may include pixel circuitry, sampling circuitry, analog-to-digital converters, etc. The ISP 225 may be disabled in some platforms that do not utilize a camera, such as a desktop computer, a server computer, or a television set-top box.

[0057] SoC 200 in the illustrated embodiment includes several different input / output (I / O) circuits that enable communication with the outside world. These circuits include radio frequency (RF) circuits 223 and 224, serial interface 231, parallel interface 232, and network interface 233.

[0058] RF circuits 223 and 224 may include transceiver circuits and processing circuits for various RF communication protocols, such as Bluetooth, WiFi, cellular communications (e.g., 4G, 5G), and near field communications (NFC). Thus, the number of RF circuits in a given implementation of SoC 200 may vary from that shown here. However, some RF circuits implemented on SoC 200 may not be used in all possible platforms in which they may be included. For example, when a desktop computer is not used to make contactless payments, NFC communication circuits may be disabled in an implementation of SoC 200 implemented in that particular platform.

[0059] The number of serial interfaces 231 included in the SoC 200 may also vary from one embodiment to the next. For example, multiple serial interfaces 231 having circuitry for universal serial bus communications transmitted over a wired link may be included on the SoC 200. Serial interfaces 231 for other communication protocols, such as inter-IC communication (IC communication), may also be included on the SoC 200. 2 C) interface and serial peripheral interface (SPI), etc. Some platforms may not utilize the entire complement of serial interfaces 231, and may further not utilize a particular serial interface dedicated to a particular communication protocol. For example, a laptop computer may utilize a fewer number of USB ports than a desktop computer, and therefore may have fewer serial interfaces 231 dedicated to that particular protocol. Therefore, serial interfaces 231 that are not used in a particular platform may be disabled.

[0060] One or more instances of parallel interface 232 may be used to facilitate parallel communications with other devices external to SoC 100 according to various parallel communication protocols. Such protocols may include the High Performance Parallel Interface Protocol (HIPPI), the Parallel Peripheral Interface (PPI) protocol, etc. Platforms such as smart watches or television set-top boxes may not utilize parallel communications with external platforms, and therefore at least some instances of parallel interface 232 may be disabled.

[0061] The network interface 233 in the illustrated embodiment may include circuitry for connecting the SoC 200 to a wired network according to a particular network protocol, such as the Ethernet protocol. Other instances of the network interface 233 that use other protocols to facilitate communication with the network are also possible and contemplated. Since some platforms, such as smart watches, do not utilize wired network communications, any instance of the network interface 233 implemented in the SoC may be disabled when used in such platforms.

[0062] Although not explicitly shown here, SoC 200 may also include a plurality of different power supply circuits. Such circuits may include various types of voltage regulators, such as switching regulators (buck converters and boost converters), low dropout voltage regulators, and other types of circuits for generating supply voltages. In some instances, functional circuit blocks coupled to receive power from a particular power supply circuit may be disabled so that the power supply circuit does not have a load to which a supply voltage is provided. Thus, programmable registers according to the present disclosure may be used to disable such power supply circuits.

[0063] The SoC 200 in the illustrated embodiment also includes a power control circuit 265, which is used to perform various functions. According to the present disclosure, these functions include disabling various functional circuit blocks according to the programming of programmable registers. In one embodiment, when the system is started, the power control circuit 265 can read programmable registers from programmable register stacks 230 (in AON circuit 217) and 240, and perform the disabling of the specified functional circuit blocks of SoC 200 according to the programming of the programmable registers. When disabling the functional circuit block, the power control circuit 265 can ensure that power is not provided to it, for example, by keeping the power switch disconnected. The power control circuit 265 can also prohibit the clock signal from being provided to the disabled functional circuit block. In the case of the memory discussed above, the power control circuit 265 can ensure that the corresponding memory controller (which may otherwise be disabled) asserts a reset signal to any unused memory in the system. In addition, any unused power supply on the SoC 200 that is not used due to its various loads being disabled can also be turned off by the power control circuit 265.

[0064] In some embodiments, the circuits to be disabled according to the specified configuration of the SoC 200 may include functionality that may be needed during system initialization during a cold boot (defined herein as a system startup that occurs when power is applied to the system after the system has been in a powered-off state). Such functionality may include BIST functionality, initial memory calibration, memory repair, etc. Therefore, the power control circuit 265 may allow such circuits to be disabled to perform various tasks during the cold boot procedure before they are ultimately disabled. The tasks performed by such functional circuit blocks (or portions thereof) may be performed before the loading of the operating system software is started. Upon completion of these tasks and before the loading of the operating system is started, the power control circuit 265 may then disable these functional circuit blocks or their corresponding portions according to the configuration of the SoC specified by the programming of various programmable registers.

[0065] The SoC 200 in the illustrated embodiment also includes an always-on (AON) circuit 217. As defined herein, an always-on circuit is a circuit in which one or more functional circuit blocks continue to operate at any time when the SoC 200 is receiving power. The types of circuits implemented in the AON circuit 217 may include one or more auxiliary processors that perform various functions (such as responding to touches of a touch screen, movement of a mouse, and the like). For example, in one embodiment, a processor that wakes up other parts of the SoC 200 from a sleep state in response to a touch of a touch screen may be included in the AON circuit 217. In various embodiments, the AON circuit 217 may also include a power management circuit that may perform various operations, such as setting a performance state of a particular functional circuit block or subsystem (where a performance state is defined as a unique combination of an operating supply voltage and a clock frequency). In one embodiment, the power control circuit 265 may be implemented in the same power domain as the AON circuit 217.

[0066] One or more signal connections may exist between circuits in the AON circuit 217 and other ones of the functional circuit blocks of the SoC 200. However, because some of these functional circuit blocks may be disabled in a given platform, the present disclosure contemplates disabling connections between these functional circuit blocks and the AON circuit 217. This isolates the disabled functional circuit blocks from signals output from the AON circuit 217. For example, if the AON circuit 217 includes one or more signal connections to the memory controller 205 that are disabled in a particular instance of the SoC 200, those connections may also be disabled by using the programmable registers of the present disclosure. This prevents signals from being sent to these disabled functional circuit blocks, thereby saving power and preventing unwanted system noise.

[0067] According to the present disclosure, disabling of various functional circuit blocks in SoC 200 and connections to AON circuit 217 may be performed through programmable registers. Additional circuits, such as circuits that may result in tri-stating of unused signal lines, may also be implemented. AON circuit 217 in the illustrated embodiment includes a programmable register file 230 that may be used to disable various functional circuit blocks in the functional circuit blocks of SoC 200. Embodiments in which all programmable registers are incorporated within programmable register file 230 (rather than having a separate programmable register file 240) are possible and contemplated.

[0068] In one embodiment, the various registers of the programmable register files 230 and 240 may be programmed during a system startup routine prior to beginning to load an operating system. This may be performed, for example, by a boot loader, which may read a signature file (such as a cryptographic signature) that specifies the configuration of the SoC according to a specified computing platform of the SoC 200. In indicating which functional circuit blocks are to be disabled during operation, the signature may also indicate that signal lines coupled between the disabled functional circuit blocks and the AON circuit 217 are to be disabled, for example, by tri-stating a circuit configured to drive the signals on those lines. By disabling signal lines coupled between the AON circuit 217 and disabled functional circuit blocks elsewhere on the SoC 200, unwanted signaling that does not contribute to system performance may be prevented.

[0069] Using programmable registers to disable functional circuit blocks of SoC 200 can allow more accurate configuration of instances of SoC for use on specific platforms. Some functional circuit blocks of SoC 200 can be disabled in response to failure during manufacturing test. The failed functional circuit blocks can make the instance of SoC 200 unavailable for some platforms or some performance levels of a specific type of platform, but can be used for other platforms. For example, the failure of a single processing core in processing core 211 or 212 can make the instance of SoC 200 unavailable for high-performance computing systems, while it can still retain its availability to mid-level systems. Therefore, in response to manufacturing test failure, any failed functional circuit blocks can be specified as completely disabled in the signature file. In an embodiment in which at least some of the programmable registers in the programmable registers are implemented using fuses, such fuses can be blown to disable the failed functional circuit blocks when the test is completed.

[0070] In addition, non-failed functional circuit blocks can also be disabled for a given instance of SoC 200 after it has been designated for a specific platform. After a test in which some functional circuit blocks of an instance of SoC 200 fail, the number of possible platforms on which the instance of the SoC can be used can be reduced. However, once an instance of SoC 200 is designated for use in a specific platform, there may be additional functional circuit blocks, which, although fully capable of performing their intended operations, are not required and can therefore be disabled by using programmable registers described elsewhere herein. For example, consider an instance of SoC 200 including a functional circuit block supporting cellular communications, where the block fails during manufacturing testing. This instance of SoC 200 can be eliminated from use in a smartphone, but a full complement of processor cores and GPU cores can still be retained, thereby enabling it to be used in a high-power desktop computing system. An instance of SoC may also have a full-featured image processing system that can be used in a smartphone but not in a desktop computer. Therefore, an instance of SoC 200 may be designated for use in a high-performance desktop computer, and the image processing system may be disabled by programming of the corresponding programmable registers.

[0071] Note that while the components of SoC 200 in the embodiment shown here are indicated as being on the same IC, this embodiment is not intended to be limiting. In some embodiments, the various functional circuit blocks of SoC 200 may be implemented on separate IC dies, which may be combined in or on a single package (e.g., substrate, etc.) that can be mounted on a printed circuit board. Thus, Figure 2 An alternative view of SoC 200 illustrated in FIG. 2 may be one in which various ones of the functional circuit blocks are implemented on different IC dies and then the different IC dies are combined into a single package.

[0072] Figure 3 300 is a block diagram of one embodiment of an IC having a plurality of different functional circuit blocks that operate according to supply voltages provided from different power supplies. In the illustrated embodiment, IC 300 includes a plurality of functional circuit blocks 311 to 314 that are coupled to receive supply voltages Vdd1 to Vdd4, respectively. These supply voltages may be generated by different power supplies, which are collectively shown here as power supply 304. The various power supply circuits implemented in power supply 304 may include various types of voltage regulators, such as buck regulators, boost regulators, LDO regulators, and the like. Each of these regulators may be coupled to its respective load via power switches S1 to S4 (e.g., Vdd1 is provided to FCB311 via power switch S1, etc.).

[0073] In the illustrated embodiment, each of the power switches S1 to S4 is associated with a corresponding one of the programmable registers in the programmable register file 320. More generally, each power switch on a given instance of an IC or system (including the SoC 200 discussed above) according to the present disclosure may be associated with at least one programmable register, such that the corresponding functional circuit may be disabled according to its programming. The actual mechanism for ensuring that power is not provided to the corresponding functional circuit block due to programming may vary from one embodiment to another. For example, in response to the programming of the corresponding register, the power control circuit may cause the corresponding power switch to the specified functional circuit block to remain disconnected, thereby prohibiting the specified functional circuit block from receiving power. In some cases where a given functional circuit block is the only load of the corresponding power supply, the power control circuit may shut down the power supply.

[0074] In the illustrated embodiment, IC 300 also includes an AON circuit 330, which can continue to receive power at any time when IC 300 itself is receiving power. AON circuit 330 may include multiple signal paths coupled to other functional circuit blocks. In this example embodiment, these signal paths are T5 to T8, and each signal path includes a corresponding switch in switches S5 to S8. These are examples of signal paths that can be used to transmit signals between various functional circuit blocks in the functional circuit blocks and AON circuit 330 during operation. However, since some functional circuit blocks of IC 300 can be disabled, the present disclosure also contemplates disabling corresponding coupled signal paths by using programmable registers in programmable register stack 320. In this example, disabling signal paths can be performed by disconnecting corresponding switches, but other mechanisms are also possible and contemplated (e.g., tri-state driver circuits intended to send signals on corresponding signal lines). Disabling signal paths can prevent signals from being transmitted between AON circuit 330 and disabled functional circuit blocks.

[0075] The mechanism used to program configuration registers 320 may vary from one embodiment to another. In one embodiment, configuration registers 320 may be programmed during a cold boot process, prior to beginning to load an operating system. The programming may be performed based on a signature stored elsewhere in the system that indicates a specified configuration for an instance of IC 320. The programming in one embodiment may be performed by a boot loader during a cold boot.

[0076] Similarly, the mechanism by which the configuration register 320 disables a functional circuit block or a signal path coupled from a functional circuit block to the AON circuit 330 may vary from one embodiment to another. In one embodiment, when a particular register is programmed, it may cause the assertion of a signal that forces the corresponding power switch to remain open during operation, thereby preventing the corresponding functional circuit block from receiving power. Similarly, a particular register, when programmed, may cause a signal to be transmitted to a circuit within the AON circuit 330 to prevent the circuit from attempting to send or receive a signal from a corresponding disabled functional circuit block. Other disabling mechanisms based on the programming of the configuration register 320 are also possible and contemplated, including the use of fuses.

[0077] In general, the present disclosure contemplates ICs / SoCs / packages that can be used in a large number of platforms with different functional requirements. The IC / SoC / package may have a plurality of different functional circuit blocks therein to support the functional requirements of each platform in the various platforms in which the IC / SoC / package may be used. In addition, in some embodiments, additional functional circuit blocks of a given type may be implemented to improve manufacturing yield, for example, by providing additional capabilities in the event of a failure of a particular functional circuit block. Thus, if a particular instance of a functional circuit block fails a test, but another instance providing the same functionality passes the test, the corresponding IC does not need to be discarded. In addition, since the IC can be used in a wide variety of different platforms with different functional requirements, functional circuit blocks that are not needed in a particular platform may be disabled. This may occur as a response to a manufacturing test in which a given functional circuit block fails a test and is disabled, thereby narrowing the list of platforms in which the functional circuit block may be appropriately used. If the functional circuit blocks are not needed in a specified platform, additional disabling of these functional circuit blocks may occur thereafter. Thus, the IC / SoC / systems and various methods disclosed herein may allow for improved yield and greater product differentiation utilizing a single IC / SoC / package design (e.g., an IC / SoC / package design having a specific computing architecture that may be used in a variety of platforms).

[0078] Note that the present disclosure contemplates a situation where an instance of an IC passes testing without faulty functional circuit blocks (e.g., all perform as expected). In such a situation, any functional circuit blocks not required for the selected platform can be disabled after testing by programming programmable registers as discussed above.

[0079] With respect to programming of the configuration registers 320, the present disclosure contemplates utilizing a signature file, such as a cryptographic signature, that is read by the boot code during a cold boot routine. The cryptographic signature may indicate the intended system configuration, and therefore indicate which of the functional circuit blocks and any signal path connections to the AON circuit 330 are to be disabled. Note that once the configuration registers are programmed, they may not be modified or cleared without another cold boot.

[0080] Figure 4A 4 is a block diagram of another embodiment of an IC illustrating certain aspects of the present disclosure. In the illustrated embodiment, IC 400 includes AON circuit 417 having a set of programmable registers 430, a boot loader 445, and a cryptographic signature 450. Boot loader 445 and cryptographic signature 450 may be implemented on a read-only memory or other non-volatile storage device. The additional set of programmable registers 440 is shown here as being external to AON circuit 417, but it is noted that embodiments in which all programmable registers are merged into a single register file are possible and contemplated.

[0081] The bootloader 445 in the illustrated embodiment may include startup code for starting the boot process during a cold boot. During the boot process, the bootloader 445 may receive acquisition commands from the cryptographic signature 450 to obtain information about the specified configuration of the IC 400 and the platform in which the configuration is to be implemented. The information accessed from the cryptographic signature includes an indication of any functional circuit blocks that will be prohibited from use in the specified platform. In some embodiments, the bootloader 445 may access an additional external programmable register file 440 when determining which functional circuit blocks will be disabled for the specified configuration.

[0082] Using the information about which functional circuit blocks are to be disabled, the boot loader 445 programs the programmable registers of the register files 430 and 440. This programming operation can be performed by the boot loader 445 before starting to load the operating system software. The information programmed into the various programmable registers is then accessed by the power control circuit (not shown here), which can perform various operations to disable the specified functional circuit blocks. This may include prohibiting the provision of power and clock signals to the disabled functional circuit blocks, and cutting off the communication link to the disabled functional circuit blocks. Thereafter, when the operating system is loaded, the disabled functional circuit blocks are not visible to it. Therefore, the operating system software can configure itself to operate only with those functional circuit blocks that are enabled when loaded. When configuring itself for a specific platform, the operating system can abandon loading some parts that will not be used in a specific computing platform. For example, when the system is a desktop computing system, the operating system software can abandon loading the driver for the image system processor that is disabled by programming.

[0083] Figure 4B 4 is a block diagram illustrating limited use of some functional circuit blocks during a cold start before they are disabled. In the illustrated embodiment, system 460 includes functional circuit blocks 437 and 480. System 460 also includes a main BIST controller 461, a BIST controller 462 (in functional circuit block 470), and a BIST controller 464 (in functional circuit block 480).

[0084] In the daisy-chain configuration shown here, the BIST controller 464 can communicate with the main BIST controller 461 via the BIST controller 480. Therefore, the BIST controller 464 relies on the BIST controller 462 (and therefore the functional circuit block 470) to receive power in order to communicate with the main BIST controller 461. However, the functional circuit block 470 can be designated for disabling in the system 400. When this is the case, the power control circuit configured to perform the disabling of the functional circuit block according to the information stored in the programmable register can delay the disabling of the functional circuit block 470 until the test performed by the BIST controller 464 is completed and the results are transmitted to the main BIST controller 461. This can also enable the main BIST controller 461 to transmit commands to the BIST controller 464. The tests performed by the various BIST controllers in the system 460 can be performed during the cold boot process before starting to load the operating system software. Therefore, when the various BIST controllers complete the tests, the power control circuit can disable the functional circuit block 470 according to the specified configuration of the system 460.

[0085] Generally speaking, during the cold boot process, the disabling of at least some functional circuit blocks that would be disabled according to a specified system configuration can be delayed. This can allow various tasks necessary for system initialization to be performed, such as the examples discussed above. Once these tasks have been completed, power control circuits or other logic components in the system can allow the specified functional circuit blocks to be disabled before loading and initializing the operating system.

[0086] Figure 4C 4 is a diagram illustrating an example mechanism for disabling a functional circuit block based on setting a programmable register. In the illustrated example, a power switch P1 is coupled between a supply voltage Vdd and a functional circuit block 490. The power switch P1 is implemented here as a PMOS transistor and is activated when its gate voltage is at least a threshold voltage less than the voltage on its source coupled to Vdd.

[0087] A second switch S40 is coupled to the gate terminal of P1. The switch S40 in the illustrated embodiment is a single-pole, double-throw switch. In a first position (shown here), S40 can couple the gate terminal of P40 to Vdd. In a second position, S40 couples the gate terminal of P1 to a Pwr Ctrl signal, which can be used to activate and deactivate switch P1 as needed. For example, when S40 is in the second position, the power control circuit can activate P1 to allow the functional circuit block 480 to perform its intended function, and deactivate P1 to cause the functional circuit block 480 to enter a sleep mode.

[0088] In this example, programmable register 491 is set and programmed, thereby indicating the configuration of the system so that functional circuit block 490 will remain disabled. Therefore, as a result of the programming, the power control circuit in this example can cause S40 to remain in the first position during normal operation. Because this causes the gate terminal of P1 to be coupled to Vdd, P1 is prevented from being activated, and therefore functional circuit block 490 does not receive a supply voltage.

[0089] Figure 4C The example of is only one of several possible mechanisms that can be used to disable a functional circuit block based on information stored in a programmable register according to the present disclosure. In general, any suitable mechanism can be used to disable a functional circuit block.

[0090] Platform for Configurable IC / SoC :

[0091] Figure 5 500 is a product matrix illustrating a specific design of an embodiment of the IC / SoC used in different platforms. In the illustrated embodiment, the product matrix 500 illustrates different configurations in which the embodiment of the IC / SoC can be used for the following products: tablet computers, high-end smart phones, mid-range smart phones, entry-level smart phones, high-performance desktop personal computers (PCs), mid-range desktop PCs, TV set-top boxes, monitors / TVs (e.g., smart monitors or smart TVs), and laptop PCs. The functional circuit blocks that can be enabled / disabled in this example include a CPU complex (with one or more processor cores), a GPU complex, an image system processing / camera circuit, an external display circuit, an internal display circuit, and a memory controller circuit (MCC).

[0092] Note that the product matrix is ​​shown here by way of example and not by way of limitation. Thus, embodiments of ICs / SoCs that can be configured for use in a different range of products than those shown here are possible and contemplated. Similarly, embodiments of ICs that have different ranges of functional circuit blocks that can be enabled or disabled are also possible and contemplated.

[0093] In the illustrated example, the implementation scheme of the IC is configured differently for each of the different products in which the IC can be used. For example, in a desktop computer, the full functionality of all functional circuit blocks is utilized, while a high-end phone utilizes most of the functional circuit blocks but does not support an external display. Several products in the product, such as mid-level phones, mid-level desktop PCs, and set-top boxes, only utilize a portion of the CPU complex. Therefore, some of the processor cores are disabled in these products. It should be noted that different processor cores in the processor core can be disabled relative to another one in the product in the matrix. For example, some products can utilize at least one high-performance processor core and at least one processor core optimized for energy efficiency, while other products can only optimize the high-efficiency core.

[0094] Other factors such as thermal distribution may be considered when determining which of a particular processor core, GPU core, and other portions of a particular functional circuit to disable. Figure 2 In the CPU block 203 of FIG. 1 , there are four processor cores 211 and 212 (two columns, one for each of two different types of processor cores) arranged in a square orientation. If a specified system configuration requires that only one of processor core 211 and one of processor core 212 be enabled, and all are fully functional (as determined by manufacturing testing), the cores that remain enabled may be oriented diagonally relative to each other. This in turn may minimize the adjacent size of the two enabled cores, since they are each closest to each other only at one corner. Thus, the heat shared between the two enabled cores during operation may be less than it would be in an arrangement in which, for example, two cores in the same row are selected to remain enabled. This may allow excess heat to be dispersed away from the cores more easily, and thus simplifies overall thermal control on the chip.

[0095] Performance considerations may also be a factor in determining which functional circuit blocks will remain enabled. For example, if certain GPU cores in the GPU core are to be disabled, the remaining enabled cores may be selected based on performance metrics collected during manufacturing testing, thereby selecting the highest performance cores.

[0096] Return to Figure 5 For example, for products that do not utilize cameras (such as desktop PCs, set-top boxes, and monitors / TVs, etc.), the ISP / camera circuitry may be disabled. For tablets and high-end phones, full functionality of the ISP / camera may be provided, while for mid-level and entry-level phones, partial functionality may be provided.

[0097] In general, various embodiments of IC / SoCs according to the present disclosure can be used in a wide variety of different products that implement a common computing architecture. Specific instances of the IC / SoC can be configured according to the desired capabilities of those products, with unneeded capabilities disabled as discussed elsewhere herein. By utilizing a common computing architecture, various products that utilize an instance (or more than one instance) of the IC / SoC can work seamlessly with each other for cross-platform communication.

[0098] Next go to Figure 6 , a diagram illustrating examples of different computing platforms according to the present disclosure is shown. The system 600 in the illustrated embodiment is a computing platform that can combine and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 600 includes at least one instance of a system on a chip (SoC) 606, which can include multiple types of processing units (such as one or more CPU cores, a GPU with several graphics processing cores), a communication structure, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 606 include multiple execution paths and instruction issue queues. The SoC 606 can implement a common computing architecture (e.g., a computing architecture using the same instruction set architecture) across the various different platforms shown here. In various embodiments, the SoC 606 is coupled to an external memory 602, a peripheral device 604, and a power supply 608. In some system embodiments, multiple instances of the SoC 606 can be combined to form a common computing element. It should also be noted that, as an alternative to the SoC, various functional circuit blocks can be implemented on multiple ICs, and these ICs can be combined into a single package as part of a specific implementation of the system.

[0099] A power supply 608 is also provided that supplies a supply voltage to the SoC 606 and one or more supply voltages to the memory 602 and / or the peripherals 604. In various embodiments, the power supply 608 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 606 is included (and more than one external memory 602 is also included).

[0100] The memory 602 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device is mounted with the SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0101] The SoC 606 in the illustrated embodiment may be arranged in accordance with the various other SoC / ICs discussed above. That is, the SoC 606 may implement a processor that may be configured in accordance with the embodiment of the present invention. Figure 6 606. Thus, SoC 606 may also be arranged to disable specific functional circuit blocks therein depending on the specific system in which it is implemented. For example, for an instance of SoC 606 implemented in smartwatch 660, a first set of functional circuit blocks may be disabled, while for another instance of SoC 606 implemented in desktop computer 610, a second set of functional circuit blocks may be disabled.

[0102] According to the above discussion, programmable registers can be used to perform disabling of various functional circuit blocks in a particular instance of SoC 606. Some of the registers can be programmed in response to functional testing of SoC 606 occurring at the end of the production line. Based on any failed functional circuit blocks, a given instance of SoC 606 can be eliminated from possible use in certain embodiments of the system embodiments shown herein. For example, if a functional circuit block including an RF circuit supporting cellular communication fails the test, the corresponding SoC 606 can be eliminated from possible use in some embodiments of mobile phone 640 and tablet computer 630. However, although no cellular communication is possible for this particular instance of SoC 606, it can (depending on the test results of other functional circuit blocks) be used in other system embodiments, such as desktop computer 610, laptop computer 620, monitor 650, etc.

[0103] After eliminating a given instance of SoC 606 for use in some platforms due to a failed functional circuit block, the given instance of the SoC may then be designated for use in a specific one of the systems that are still available for it. However, since there may be additional functional circuit blocks that are not needed, configuration registers may be used to disable these functional circuit blocks. Using the example of a failed RF circuit block for cellular communications given above, an instance of SoC 606 that has encountered this failure may be designated for use in a desktop computer 610. However, since the desktop computer 610 does not perform image system processing to support the onboard camera, the functional circuit blocks including the image system processor may also be disabled. This may be achieved through a boot code or a signature associated therewith that causes the configuration register to be programmed at a cold start. Thus, whenever an implementation of such a desktop computer 610 performs a system boot, the configuration register may be programmed to disable the image system processor. In addition, some connections from normally open circuits to disabled functional circuit blocks may also be disabled. Similarly, the connection for providing a clock signal to a disabled functional circuit may itself be disabled. Thus, the design of the SoC 606 may be adapted to Figure 6 Starting with the architecture of all of the platforms shown in (and other platforms that are possible and contemplated), a given instance of the SoC can be configured for use in a particular system such that it provides the functionality necessary for that platform while disabling functionality not required for the given platform.

[0104] Peripheral devices 604 include any desired circuitry, depending on the type of system 600. For example, in one embodiment, peripheral devices 604 include devices for various types of wireless communications such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 604 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripheral devices 604 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0105] As shown, system 600 is shown to be applicable to a wide range of fields. For example, system 600 can be used as a part of a chip, circuit, component, etc. of a desktop computer 610, a laptop computer 620, a tablet computer 630, a cellular or mobile phone 640, or a TV 650 (or a set-top box coupled to a TV). A smart watch and a health monitoring device 660 are also shown. In some embodiments, smart watch 660 may include various general computing related functions. For example, smart watch 660 may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor the vital signs of a user, track the proximity of a user to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watch may include or may not include some or any health monitoring related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices that can be implanted in the human body, glasses designed to provide enhanced and / or virtual reality experience, etc.

[0106] The system 600 may also be used as part of a cloud-based service 670. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 600 may be used in one or more devices of a home system 680 other than those previously mentioned. For example, a home appliance may monitor and detect situations that warrant attention. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device, and an alert may be provided to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home, and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Figure 6 Also shown in the figure are applications of system 600 to various modes of transportation. For example, system 600 can be used as a vehicle system 690 in a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), etc. In various cases, system 600 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Any of these and many other embodiments are possible and contemplated. Note that Figure 6 The devices and applications shown in are exemplary only and are not intended to be limiting. Other devices are possible and contemplated.

[0107] Methods for configuring and operating the IC :

[0108] Figure 7700 is a flow chart of one embodiment of a method for configuring an IC for use in a particular one of several different platforms in which the IC may be implemented. The various different platforms may share a common architecture, and thus a particular instance of an IC according to the present disclosure may be configured for use in any platform. Thus, method 700 contemplates the use of an IC / SoC as disclosed herein. Embodiments of an IC / SoC that are not explicitly disclosed herein but that may be configured in other ways according to method 700 are also considered to fall within the scope of the present disclosure.

[0109] Method 700 includes configuring an integrated circuit (IC) for use in a particular computing platform among a plurality of different computing platforms, the IC having a set of processing blocks, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks (block 705). The configuring includes programming programmable registers in a set of programmable registers associated with processing blocks in the set of processing blocks (block 710). The configuring also includes disabling at least a portion of corresponding processing blocks in the set of processing blocks in response to programming programmable registers in the set of programmable registers, wherein disabling processing blocks in the set of processing blocks at least partially in response to programming enables the IC to be configured for use in different computing platforms by partially or completely disabling different combinations of the set of processing blocks (block 715). At least two of the different computing platforms support different sets of peripheral devices. In addition, the particular computing platform supports a unique set of peripheral devices relative to other computing platforms in the plurality of computing platforms.

[0110] In one embodiment, the method includes configuring a first instance of the IC for use in a tablet computer having a first set of peripherals, the first set of peripherals including an internal display peripheral and an external display peripheral. The method embodiment also includes configuring a second instance of the IC for use in a media player having a second set of peripherals different from the first set of peripherals, wherein configuring the second instance includes partially disabling a CPU circuit block and completely disabling a display pipeline circuit block dedicated to an external display, and also includes disabling an image signal processing circuit block for a camera. The method embodiment may also include configuring the IC for one of a plurality of different performance levels for a given one of the plurality of computing platforms by selectively disabling portions of a set of heterogeneous processing blocks for one of the plurality of different performance levels.

[0111] In some embodiments, the method includes disabling the provision of a clock signal to a given one of the set of processing blocks in response to programming a corresponding first one of the set of programmable registers. Such embodiments may also include disabling the provision of power to a given one of the set of processing blocks in response to programming a corresponding second one of the set of programmable registers.

[0112] In one embodiment, the IC includes a normally-open circuit configured to remain operational when the IC is receiving power. Embodiments of methods involving an IC having a normally-open circuit include severing at least one communication link between the normally-open circuit and a corresponding one of the set of processing blocks in response to programming a corresponding one of the programmable registers.

[0113] Various method implementations include performing one or more tasks utilizing a given processing block at startup of a computing platform including an IC. These method implementations include disabling at least a portion of the given processing block to prevent access by software upon completion of the one or more tasks and based on a given programmable register being set.

[0114] With respect to the programmable register, a given programmable register is a one-time programmable register such that the given programmable register cannot be cleared once set.

[0115] Figure 8 800 is a flow chart of another embodiment of a method for configuring an IC for use in a particular platform. Method 800 may be performed for any embodiment of an IC / SoC as disclosed herein. Embodiments of an IC / SoC that may be configured according to method 800 are also considered to fall within the scope of the present disclosure.

[0116] Method 800 includes testing an IC having a plurality of functional circuit blocks (block 805). The IC may be designed so that it can be used in a wide variety of platforms having significantly different requirements. For example, the IC may be a SoC having a computing architecture suitable for a variety of platforms, including smart watches, smart phones, desktop computers, servers, etc. At least some of these platforms may utilize different combinations of functional circuit blocks than other platforms, including different sets of peripheral devices and different processing circuit blocks in a set of processing circuit blocks.

[0117] The method also includes determining, based on the testing, that one or more functional circuit blocks on the IC are unable to perform their intended functions (block 810). After making this determination, the method includes programming one or more programmable registers corresponding to the one or more functional circuit blocks of the plurality of functional circuit blocks that are determined to be unable to perform their intended functions (block 815). The programming of the one or more programmable registers causes a corresponding power switch of the plurality of power switches to be unable to provide power to its corresponding functional circuit block of the plurality of functional circuit blocks.

[0118] Programming a programmable register to disable a functional circuit block (or portion thereof) from receiving power is only one possible mechanism for performing disabling. Disabling a functional circuit block according to the present disclosure may include disabling a clock signal from being provided to the functional circuit block, and may also include disabling the functional circuit block from receiving certain signals.

[0119] Because some of the functional circuit blocks that passed the test may not be required for the intended platform of the IC, the method also includes programming one or more additional programmable registers during a subsequent startup of a system including the IC (block 820), and in response to the programming, disabling one or more additional power switches of the plurality of power switches from providing power to their corresponding functional circuit blocks of the plurality of functional circuit blocks (block 825). Thus, the functional circuit blocks that are not required but are otherwise operable are also disabled.

[0120] In general, the present disclosure contemplates that each single power domain and clock domain of an IC includes at least one programmable register (or bit thereof) corresponding thereto to allow disabling of various functional circuits that cannot perform their intended functions and / or are otherwise not required for a particular platform. Since this may include a clock domain, the IC may include a programmable register that causes a clock signal to be disabled or prohibited from being provided to a disabled functional circuit block. The programmable register in various embodiments may be a one-time programmable switch with limited programmability. Thus, the programmable register may be programmed to disable a functional circuit block, but once set, it cannot be reprogrammed to enable the same functional circuit block. In various embodiments, the default state of the various programmable registers will enable its corresponding functional circuit block (or portion thereof), wherein the programmed state is used to disable the functional circuit block.

[0121] The present disclosure also contemplates the case where all functional circuits on an instance of an IC pass testing and are initially still fully enabled thereafter.After a particular platform is selected for an instance of an IC, unneeded functional circuit blocks may be disabled by programming programmable registers as discussed herein.

[0122] Programmable registers can be implemented in various ways. Generally speaking, a programmable register can be a register that, when programmed (or set), causes a corresponding power switch to be disconnected, a clock signal to be disabled, or causes some other action that causes a corresponding functional circuit block to be unable to operate completely or even partially. In some embodiments, at least one programmable register can be implemented using at least one fuse. A programmable register can also be implemented as a device that causes its terminals or nodes to be connected to a specific voltage level or voltage rail when programmed. Various programmable read-only memory circuit structures can also be used to implement programmable registers.

[0123] Fig. 9 900 is a flow chart of one embodiment of a method for configuring a SoC for a particular platform. Method 900 may be performed for any embodiment of an IC / SoC according to the present disclosure. Embodiments of IC / SoCs that may be configured according to method 900 but are not otherwise disclosed herein are also considered to fall within the scope of the present disclosure.

[0124] Method 900 includes testing the SoC and determining any failed functional circuit blocks (block 905). Thereafter, the SoC can be classified together with its other instances based on the test results to determine applicable platforms in which the SoC can be used (block 910). Assuming that the SoC does not have any fatal failures (i.e., failures that would make it unusable in any platform), it is designated for use in a specific platform (block 915). This designation can be made in part based on which functional circuit blocks failed the test, but other factors (e.g., product requirements) can also be considered. After this designation, it is determined whether there are any functional circuit blocks on the SoC that have passed the test (and are therefore fully capable of performing their intended functions) but are not used in a specific platform. If not (block 920, no), the method is complete. Otherwise, if there are additional unused functional circuit blocks in the SoC (block 920, yes), the pre-OS boot code can be set (e.g., via a cryptographic signature or other suitable mechanism) to disable the additional unused functional circuit blocks by programming configuration registers during the system cold boot procedure (block 925).

[0125] Fig.10 1 is a flow chart of an embodiment of a method for allowing limited use of a functional circuit block during a cold start prior to subsequent disabling of the functional circuit block. Method 1000 may be performed by any of the IC / SoC and other hardware embodiments disclosed herein. Embodiments of an IC, SoC, or system capable of performing method 1000 but not otherwise disclosed herein are considered to fall within the scope of the present disclosure.

[0126] Method 1000 includes performing, during a given startup of a computer system, one or more initialization tasks utilizing circuits in a particular one of a set of processing blocks within the computer system (block 1005). In various embodiments, the startup may be a cold startup, wherein the system is powered on from a power-off state. The tasks may be various tasks performed during the initialization of the system from a power-off state. For example, performing tests using various processing blocks implemented by the BIST circuit of the system and transmitting these results to a main BIST controller may occur at this time. The method also includes reading a one-time programmable memory to retrieve a value indicating that access to a particular processing block via software will be prevented as part of a desired configuration of the processing blocks of the computer system (where some of the processing blocks in the set of processing blocks are disabled) (block 1010). The one-time programmable memory may include a plurality of programmable registers, wherein a given programmable register includes at least one storage location for a corresponding processing block in the system. The processing block may include various types of functional circuits, including CPU circuits, GPU circuits, various types of peripheral device circuits, interface circuits, etc. The method also includes temporarily preventing the particular processing block from being accessible after the one or more initialization tasks have been performed (block 1015). Disabling a given processing block may include disabling power to it, disabling clocks to it, and / or disabling various signals to it. In one embodiment, temporarily preventing a particular processing block from being accessible occurs until a subsequent startup of the computer system, after which method 1000 is repeated. The various operations of method 1000 may be performed prior to beginning to load operating system software running on the computer system. Thus, the disabled processing block is not visible to the operating system software.

[0127] Various embodiments of the method include receiving an acquisition command that writes the one-time programmable memory with the value to set the desired configuration to a specified one of a plurality of different computing platforms, at least two of the plurality of different computing platforms supporting different sets of peripheral devices. The acquisition command in various embodiments may be received from a source internal to the computer system. For example, an embodiment is contemplated in which a signature (which may be encrypted) is stored in non-volatile memory indicating the platform and / or specific configuration in which the system will operate.

[0128] Method 1000 can be performed for various different computing platforms. In one embodiment, multiple computing platforms for which method 100 can be performed include a TV set-top box. When the computing platform is a TV set-top box, the method includes disabling the internal display interface circuit for the TV set-top box in response to receiving an acquisition command, because the set-top box does not include an internal display. Other processing blocks (such as the image system processor for the camera) can also be disabled in this embodiment. When the computing platform is a smart phone, the method includes disabling the external display interface circuit in response to receiving an acquisition command, because the smart phone utilizes an internal display.

[0129] IC Test System :

[0130] Fig.11 1 is a block diagram of one embodiment of an IC test system. In the illustrated embodiment, test system 1101 may be used to test IC 1105, which may be an IC according to any of the IC / SoC embodiments discussed elsewhere herein. Test system 1101 may perform end-of-line manufacturing testing of IC 1105 to verify its functionality and further identify any functional circuit blocks that are not operating to specification.

[0131] To test IC 1105, test system 1101 may apply various stimuli in the form of analog and / or digital (logic) signals. IC 1105 may return an output signal, which is then compared to an expected response. A failed functional block may return an output signal that is different from the expected output signal and / or has a value outside of some specified range.

[0132] In some embodiments, the test system 1101 may be configured to place the IC 1105 in a programming mode. When in programming mode, the test system 1101 stores at least some portions of a read-only memory (ROM) indicating a signature of its expected system configuration in the programmable IC 1105. The programming may indicate which functional circuit blocks (if any) of the IC 1105 have not passed the test and are therefore unavailable. In doing so, this may prevent the IC 1105 from being considered for some computing platforms, although it may be suitable for other computing platforms. It should be noted that programming may not be completed at this time because it may only consider the failed functional circuit blocks, without considering any additional circuit blocks to be disabled for the computing platform that ultimately implements it. It should be noted that in some embodiments, the IC 1105 may include a fuse, and therefore performing programming in programming mode may include blowing the fuse. In embodiments that do not utilize a fuse, other mechanisms such as the ROM discussed above may be used.

[0133] Computer readable medium and manufacturing system :

[0134] Fig.12 a is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1220 is configured to process design information 1215 stored on a non-transitory computer-readable storage medium 1210 and manufacture an integrated circuit 1230 based on the design information 1215. Such a system can be used to manufacture ICs / SoCs according to the present disclosure.

[0135] The non-transitory computer-readable storage medium 1210 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1210 may be an installation medium, for example, a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, RambusRAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1210 may also include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1210 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0136] Design information 1215 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1215 may be used by semiconductor manufacturing system 1220 to manufacture at least a portion of integrated circuit 1230. The format of design information 1215 may be recognizable by at least one semiconductor manufacturing system such as semiconductor manufacturing system 1220. In some embodiments, design information 1215 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1230 may also be included in design information 1215. Such cell libraries may include information indicating device or transistor level netlists, mask design data, characterization data, etc. of cells included in the cell library.

[0137] In various embodiments, integrated circuit 1230 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1215 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0138] Semiconductor manufacturing system 1220 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or modifying the dielectric constant using ultraviolet treatment), etc. Semiconductor manufacturing system 1220 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0139] In various embodiments, integrated circuit 1230 is configured to operate according to the circuit design specified by design information 1215, which may include performing any of the functionality described herein. For example, integrated circuit 1230 may include any of the various elements shown or described herein. In addition, integrated circuit 1230 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0140] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0141] ***

[0142] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0143] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0144] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0145] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0146] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features consistent with the dependent claims of this disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0147] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0148] ***

[0149] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0150] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0151] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0152] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0153] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0154] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0155] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0156] The phrase "based on" is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on specified factors or on specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0157] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0158] ***

[0159] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0160] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0161] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform a particular function.

[0162] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0163] Different "circuits" may be described in the present disclosure. These circuits constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits.

[0164] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0165] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to transform the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0166] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0167] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0168] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. A device, comprising: An integrated circuit (IC) having a set of processing blocks for a computer system, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks, wherein the IC comprises: a set of programmable registers associated with processing blocks in the set of processing blocks, wherein the IC is configured to disable a portion of a given one of the processing blocks in the set of processing blocks when a given one of the programmable registers in the set of programmable registers is set; and wherein the processing blocks in the set of processing blocks are configured to be at least partially disabled by setting programmable registers in the set of programmable registers, so that the IC can be configured for use in different computing platforms by partially or completely disabling different combinations of the set of processing blocks; and At least two of the different computing platforms support different sets of peripheral devices. 2 . The apparatus of claim 1 , wherein the different computing platforms comprise a tablet computing platform for a tablet computer having a first set of peripherals, the first set of peripherals comprising an internal display peripheral and an external display peripheral.

3. An apparatus according to claim 2, wherein the different computing platforms include a media player computing platform for a media player device having a second set of peripheral devices different from the first set of peripheral devices, and wherein the IC is capable of being configured for use in the media player by partially disabling the CPU circuit block and completely disabling a display pipeline circuit block dedicated to an internal display and an image signal processing (ISP) circuit block for a camera.

4. The device of claim 1, wherein the one or more other circuit blocks include one or more of the following types of circuit blocks: an image signal processing (ISP) circuit block, a neural engine circuit block, an audio / video codec circuit block, and a display pipeline circuit block.

5. The apparatus of claim 1, wherein the IC is configurable for use in different performance levels of a given one of the different computing platforms by selectively disabling portions of the set of processing blocks for different performance levels.

6. An apparatus according to claim 5, wherein the given one of the different computing platforms is a mobile phone platform, and wherein the IC is configurable for use in the first performance level and the second performance level by partially disabling the GPU circuit block for the second performance level of the mobile phone platform but not the first performance level.

7. The apparatus of claim 1 , wherein a programmable register in the set of programmable registers is configured to cause one or more of the following when programmed: prohibiting the clock signal from being provided to a corresponding one of the processing blocks in the set of processing blocks; Supply of power to the corresponding one of the processing blocks in the set of processing blocks is prohibited.

8. An apparatus according to claim 1, wherein the IC includes a normally-open circuit configured to remain operational while the IC is receiving power, and wherein a given one of the programmable registers is configured to sever at least one communication link between the normally-open circuit and a corresponding one of the processing blocks in the processing block set when programmed.

9. The apparatus of claim 1, wherein the different computing platforms include: Desktop computer; Laptop; Mobile phone; Tablet computers; Smart watches; Display unit; Internet of Things (IoT) devices; and Vehicle-based computing systems.

10. The apparatus of claim 1, wherein the IC is configured to, after each boot of the computer system: executing one or more tasks utilizing a given processing block; and Based on a given programmable register being set, the portion of the given processing block is disabled to prevent access by software.

11. The apparatus of claim 10, wherein the given programmable register is a one-time programmable register such that the given programmable register cannot be cleared once set.

12. A method comprising: An integrated circuit (IC) configured for use in a particular computing platform among a plurality of different computing platforms, the IC having a set of processing blocks, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks, wherein the configuration comprises: programming programmable registers of the set of programmable registers associated with processing blocks of the set of processing blocks; and disabling at least a portion of corresponding ones of the set of processing blocks in response to programming the programmable registers of the set of programmable registers, wherein processing blocks of the set of processing blocks are at least partially disabled in response to the programming, such that the IC can be configured for use in different computing platforms by partially or completely disabling different combinations of the set of processing blocks; and At least two of the different computing platforms support different sets of peripheral devices. Wherein the particular computing platform supports a unique set of peripheral devices relative to other computing platforms in the plurality of different computing platforms.

13. The method according to claim 12, further comprising: configuring a first instance of the IC for use in a tablet computer having a first set of peripherals, the first set of peripherals comprising an internal display peripheral and an external display peripheral; and Configuring a second instance of the IC for use in a media player having a second set of peripheral devices that is different from the first set of peripheral devices, wherein configuring the second instance includes partially disabling the CPU circuit block and completely disabling a display pipeline circuit block dedicated to an external display, and also includes disabling an image signal processing circuit block for a camera.

14. The method of claim 12 further comprising configuring the IC for use in one of a plurality of different performance levels by selectively disabling a portion of a set of heterogeneous processing blocks for a given one of a plurality of computing platforms.

15. The method according to claim 12, further comprising: disabling provision of a clock signal to a given one of the set of processing blocks in response to programming a corresponding first one of the set of programmable registers; as well as Power is disabled from being provided to the given one of the set of processing blocks in response to programming a corresponding second one of the set of programmable registers.

16. The method of claim 12, wherein the IC includes a normally-on circuit configured to remain operational while the IC is receiving power, and wherein the method further comprises: At least one communication link between the normally-open circuit and a corresponding one of the set of processing blocks is severed in response to programming a corresponding one of the programmable registers.

17. The method according to claim 12, further comprising: upon startup of a computing platform including the IC, executing one or more tasks utilizing a given processing block; as well as Upon completion of the one or more tasks and based on a given programmable register being set, at least a portion of the given processing block is disabled to prevent access by software.

18. The method of claim 17, wherein the given programmable register is a one-time programmable register such that the given programmable register cannot be cleared once set.

19. A device, comprising: An integrated circuit (IC) configurable for use in one of a plurality of computing platforms, the IC having a set of processing blocks, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks implemented in a corresponding power domain of a plurality of power domains, wherein the integrated circuit further comprises: a plurality of power switches associated with corresponding power domains of the plurality of power domains; and a plurality of programmable registers, wherein a programmable register of the plurality of programmable registers is associated with a corresponding power switch of the plurality of power switches, and wherein the programmable register of the plurality of programmable registers, when programmed, is configured to cause the corresponding power switch of the plurality of power switches to remain open such that a corresponding one of the set of processing blocks is disabled; A given one of the plurality of programmable registers is a one-time programmable register, and once the one-time programmable register is set, cannot be removed; and The IC is configurable for use in different computing platforms among the plurality of computing platforms by partially or completely disabling different combinations of the sets of processing blocks, wherein at least two of the different computing platforms support different sets of peripheral devices.

20. The apparatus of claim 19, wherein the plurality of computing platforms comprises: Desktop computer; Laptop; Mobile phone; Tablet computers; Smart watches; Display unit; TV set-top boxes; Internet of Things (IoT) devices; and Vehicle-based computing systems.

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